From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ivan Gorinov Date: Fri, 20 Apr 2018 10:47:57 -0700 Subject: [U-Boot] [PATCH] x86: Use microcode update from device tree for all processors In-Reply-To: References: <20180404230700.GA57192@intel.com> <20180417182956.GA57575@intel.com> <20180419001146.GA18420@intel.com> Message-ID: <20180420174757.GA2940@intel.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Bin, On Wed, Apr 18, 2018 at 07:05:28PM -0600, Bin Meng wrote: > >> > > >> > If there is no ROM image, ucode_base and ucode_size are not initialized and > >> > the microcode update data from DTB applied by microcode_update_intel() to the > >> > bootstrap CPU is not used by the multiprocessing code. > >> > >> Correct. If it's not a ROM image, which means U-Boot is probably not > >> the 1st stage bootloader, which means updating microcode is not > >> necessary. So is there any issue with current implementation? > > > > If the 1st stage bootloader is running from the on-chip SRAM, there may be > > not enough space to include the microcode update data. In this case, U-Boot > > is a secondary boot loader but still has to update the microcode. > > Thanks for the information. Correct, if that's the case, then we > should tune our codes to support that. > > But I guess the "1st stage" bootloader is loaded by some on-chip > BOOTROM to the internal SRAM? Correct. > Is the "1st stage" bootloader running from SRAM the U-Boot SPL? Or > some proprietary implementation? It's usually a proprietary implementation.