From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ivan Gorinov <ivan.gorinov@intel.com>
Date: Fri, 20 Apr 2018 11:00:47 -0700
Subject: [U-Boot] [PATCH v6 1/2] x86: Add TSC-specific timer functions
In-Reply-To: <1524227108.21176.462.camel@linux.intel.com>
References: <cover.1523570597.git.ivan.gorinov@intel.com>
 <269698c303c3da454b34f149d4a3562fc57091f2.1523570597.git.ivan.gorinov@intel.com>
 <1524227108.21176.462.camel@linux.intel.com>
Message-ID: <20180420180047.GB2940@intel.com>
List-Id: <u-boot.lists.denx.de>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
To: u-boot@lists.denx.de

On Fri, Apr 20, 2018 at 06:25:08AM -0600, Andy Shevchenko wrote:
> > Coreboot timestamp functions and Quark memory reference code use
> > get_tbclk() to get TSC frequency. This will not work if another
> > early timer is selected.
> > 
> > Add tsc_rate_mhz() function and use it in the code that specifically
> > needs to get TSC rate regardless of currently selected early timer.
> 
> 
> >  void delay_n(uint32_t ns)
> >  {
> >  	/* 1000 MHz clock has 1ns period --> no conversion required
> > */
> > -	uint64_t final_tsc = rdtsc();
> > +	uint64_t start_tsc = rdtsc();
> > +	uint64_t ticks;
> >  
> > -	final_tsc += ((get_tbclk_mhz() * ns) / 1000);
> > -
> > -	while (rdtsc() < final_tsc)
> > -		;
> > +	ticks = (tsc_rate_mhz() * ns) / 1000;
> 
> > +	while (rdtsc() - start_tsc < ticks);
> 
> I would rather preserve existing style.

OK. Existing style does not correctly handle overflow,
but for a 64-bit counter it's a very unlikely event.