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* [U-Boot] [PATCH 1/3] ARM: dts: sun8i: Sync r40 dtsi from Linux
@ 2018-04-25  9:50 Jagan Teki
  2018-04-25  9:50 ` [U-Boot] [PATCH 2/3] sunxi: sun8i: Add Allwinner V40 support Jagan Teki
  2018-04-25  9:50 ` [U-Boot] [PATCH 3/3] board: sunxi: sun8i-v4: Add Bananapi M2 Berry support Jagan Teki
  0 siblings, 2 replies; 5+ messages in thread
From: Jagan Teki @ 2018-04-25  9:50 UTC (permalink / raw)
  To: u-boot

Sync sun8i-r40.dtsi changes from Linux with

Merge: a406778618d0 088345fc3553
Author: Stephen Rothwell <sfr@canb.auug.org.au>
Date:   Tue Apr 24 14:15:02 2018 +1000

    Merge branch 'akpm/master'

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 arch/arm/dts/sun8i-r40.dtsi               |  43 +++++++
 include/dt-bindings/clock/sun8i-r40-ccu.h | 187 ++++++++++++++++++++++++++++++
 include/dt-bindings/reset/sun8i-r40-ccu.h | 130 +++++++++++++++++++++
 3 files changed, 360 insertions(+)
 create mode 100644 include/dt-bindings/clock/sun8i-r40-ccu.h
 create mode 100644 include/dt-bindings/reset/sun8i-r40-ccu.h

diff --git a/arch/arm/dts/sun8i-r40.dtsi b/arch/arm/dts/sun8i-r40.dtsi
index 48ec2e855a..0aa76a2f10 100644
--- a/arch/arm/dts/sun8i-r40.dtsi
+++ b/arch/arm/dts/sun8i-r40.dtsi
@@ -43,6 +43,8 @@
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/sun8i-r40-ccu.h>
+#include <dt-bindings/reset/sun8i-r40-ccu.h>
 
 / {
 	#address-cells = <1>;
@@ -114,6 +116,39 @@
 		#size-cells = <1>;
 		ranges;
 
+		nmi_intc: interrupt-controller at 1c00030 {
+			compatible = "allwinner,sun7i-a20-sc-nmi";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			reg = <0x01c00030 0x0c>;
+			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		mmc0: mmc at 1c0f000 {
+			compatible = "allwinner,sun8i-r40-mmc",
+				     "allwinner,sun50i-a64-mmc";
+			reg = <0x01c0f000 0x1000>;
+			clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
+			clock-names = "ahb", "mmc";
+			resets = <&ccu RST_BUS_MMC0>;
+			reset-names = "ahb";
+			pinctrl-0 = <&mmc0_pins>;
+			pinctrl-names = "default";
+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		ccu: clock at 1c20000 {
+			compatible = "allwinner,sun8i-r40-ccu";
+			reg = <0x01c20000 0x400>;
+			clocks = <&osc24M>, <&osc32k>;
+			clock-names = "hosc", "losc";
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
 		pio: pinctrl at 1c20800 {
 			compatible = "allwinner,sun8i-r40-pinctrl";
 			reg = <0x01c20800 0x400>;
@@ -132,6 +167,14 @@
 				bias-pull-up;
 			};
 
+			mmc0_pins: mmc0-pins {
+				pins = "PF0", "PF1", "PF2",
+				       "PF3", "PF4", "PF5";
+				function = "mmc0";
+				drive-strength = <30>;
+				bias-pull-up;
+			};
+
 			uart0_pb_pins: uart0_pb_pins {
 				pins = "PB22", "PB23";
 				function = "uart0";
diff --git a/include/dt-bindings/clock/sun8i-r40-ccu.h b/include/dt-bindings/clock/sun8i-r40-ccu.h
new file mode 100644
index 0000000000..4fa5f69fc2
--- /dev/null
+++ b/include/dt-bindings/clock/sun8i-r40-ccu.h
@@ -0,0 +1,187 @@
+/*
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN8I_R40_H_
+#define _DT_BINDINGS_CLK_SUN8I_R40_H_
+
+#define CLK_CPU			24
+
+#define CLK_BUS_MIPI_DSI	29
+#define CLK_BUS_CE		30
+#define CLK_BUS_DMA		31
+#define CLK_BUS_MMC0		32
+#define CLK_BUS_MMC1		33
+#define CLK_BUS_MMC2		34
+#define CLK_BUS_MMC3		35
+#define CLK_BUS_NAND		36
+#define CLK_BUS_DRAM		37
+#define CLK_BUS_EMAC		38
+#define CLK_BUS_TS		39
+#define CLK_BUS_HSTIMER		40
+#define CLK_BUS_SPI0		41
+#define CLK_BUS_SPI1		42
+#define CLK_BUS_SPI2		43
+#define CLK_BUS_SPI3		44
+#define CLK_BUS_SATA		45
+#define CLK_BUS_OTG		46
+#define CLK_BUS_EHCI0		47
+#define CLK_BUS_EHCI1		48
+#define CLK_BUS_EHCI2		49
+#define CLK_BUS_OHCI0		50
+#define CLK_BUS_OHCI1		51
+#define CLK_BUS_OHCI2		52
+#define CLK_BUS_VE		53
+#define CLK_BUS_MP		54
+#define CLK_BUS_DEINTERLACE	55
+#define CLK_BUS_CSI0		56
+#define CLK_BUS_CSI1		57
+#define CLK_BUS_HDMI1		58
+#define CLK_BUS_HDMI0		59
+#define CLK_BUS_DE		60
+#define CLK_BUS_TVE0		61
+#define CLK_BUS_TVE1		62
+#define CLK_BUS_TVE_TOP		63
+#define CLK_BUS_GMAC		64
+#define CLK_BUS_GPU		65
+#define CLK_BUS_TVD0		66
+#define CLK_BUS_TVD1		67
+#define CLK_BUS_TVD2		68
+#define CLK_BUS_TVD3		69
+#define CLK_BUS_TVD_TOP		70
+#define CLK_BUS_TCON_LCD0	71
+#define CLK_BUS_TCON_LCD1	72
+#define CLK_BUS_TCON_TV0	73
+#define CLK_BUS_TCON_TV1	74
+#define CLK_BUS_TCON_TOP	75
+#define CLK_BUS_CODEC		76
+#define CLK_BUS_SPDIF		77
+#define CLK_BUS_AC97		78
+#define CLK_BUS_PIO		79
+#define CLK_BUS_IR0		80
+#define CLK_BUS_IR1		81
+#define CLK_BUS_THS		82
+#define CLK_BUS_KEYPAD		83
+#define CLK_BUS_I2S0		84
+#define CLK_BUS_I2S1		85
+#define CLK_BUS_I2S2		86
+#define CLK_BUS_I2C0		87
+#define CLK_BUS_I2C1		88
+#define CLK_BUS_I2C2		89
+#define CLK_BUS_I2C3		90
+#define CLK_BUS_CAN		91
+#define CLK_BUS_SCR		92
+#define CLK_BUS_PS20		93
+#define CLK_BUS_PS21		94
+#define CLK_BUS_I2C4		95
+#define CLK_BUS_UART0		96
+#define CLK_BUS_UART1		97
+#define CLK_BUS_UART2		98
+#define CLK_BUS_UART3		99
+#define CLK_BUS_UART4		100
+#define CLK_BUS_UART5		101
+#define CLK_BUS_UART6		102
+#define CLK_BUS_UART7		103
+#define CLK_BUS_DBG		104
+
+#define CLK_THS			105
+#define CLK_NAND		106
+#define CLK_MMC0		107
+#define CLK_MMC1		108
+#define CLK_MMC2		109
+#define CLK_MMC3		110
+#define CLK_TS			111
+#define CLK_CE			112
+#define CLK_SPI0		113
+#define CLK_SPI1		114
+#define CLK_SPI2		115
+#define CLK_SPI3		116
+#define CLK_I2S0		117
+#define CLK_I2S1		118
+#define CLK_I2S2		119
+#define CLK_AC97		120
+#define CLK_SPDIF		121
+#define CLK_KEYPAD		122
+#define CLK_SATA		123
+#define CLK_USB_PHY0		124
+#define CLK_USB_PHY1		125
+#define CLK_USB_PHY2		126
+#define CLK_USB_OHCI0		127
+#define CLK_USB_OHCI1		128
+#define CLK_USB_OHCI2		129
+#define CLK_IR0			130
+#define CLK_IR1			131
+
+#define CLK_DRAM_VE		133
+#define CLK_DRAM_CSI0		134
+#define CLK_DRAM_CSI1		135
+#define CLK_DRAM_TS		136
+#define CLK_DRAM_TVD		137
+#define CLK_DRAM_MP		138
+#define CLK_DRAM_DEINTERLACE	139
+#define CLK_DE			140
+#define CLK_MP			141
+#define CLK_TCON_LCD0		142
+#define CLK_TCON_LCD1		143
+#define CLK_TCON_TV0		144
+#define CLK_TCON_TV1		145
+#define CLK_DEINTERLACE		146
+#define CLK_CSI1_MCLK		147
+#define CLK_CSI_SCLK		148
+#define CLK_CSI0_MCLK		149
+#define CLK_VE			150
+#define CLK_CODEC		151
+#define CLK_AVS			152
+#define CLK_HDMI		153
+#define CLK_HDMI_SLOW		154
+
+#define CLK_DSI_DPHY		156
+#define CLK_TVE0		157
+#define CLK_TVE1		158
+#define CLK_TVD0		159
+#define CLK_TVD1		160
+#define CLK_TVD2		161
+#define CLK_TVD3		162
+#define CLK_GPU			163
+#define CLK_OUTA		164
+#define CLK_OUTB		165
+
+#endif /* _DT_BINDINGS_CLK_SUN8I_R40_H_ */
diff --git a/include/dt-bindings/reset/sun8i-r40-ccu.h b/include/dt-bindings/reset/sun8i-r40-ccu.h
new file mode 100644
index 0000000000..c5ebcf6672
--- /dev/null
+++ b/include/dt-bindings/reset/sun8i-r40-ccu.h
@@ -0,0 +1,130 @@
+/*
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_RST_SUN8I_R40_H_
+#define _DT_BINDINGS_RST_SUN8I_R40_H_
+
+#define RST_USB_PHY0		0
+#define RST_USB_PHY1		1
+#define RST_USB_PHY2		2
+
+#define RST_DRAM		3
+#define RST_MBUS		4
+
+#define RST_BUS_MIPI_DSI	5
+#define RST_BUS_CE		6
+#define RST_BUS_DMA		7
+#define RST_BUS_MMC0		8
+#define RST_BUS_MMC1		9
+#define RST_BUS_MMC2		10
+#define RST_BUS_MMC3		11
+#define RST_BUS_NAND		12
+#define RST_BUS_DRAM		13
+#define RST_BUS_EMAC		14
+#define RST_BUS_TS		15
+#define RST_BUS_HSTIMER		16
+#define RST_BUS_SPI0		17
+#define RST_BUS_SPI1		18
+#define RST_BUS_SPI2		19
+#define RST_BUS_SPI3		20
+#define RST_BUS_SATA		21
+#define RST_BUS_OTG		22
+#define RST_BUS_EHCI0		23
+#define RST_BUS_EHCI1		24
+#define RST_BUS_EHCI2		25
+#define RST_BUS_OHCI0		26
+#define RST_BUS_OHCI1		27
+#define RST_BUS_OHCI2		28
+#define RST_BUS_VE		29
+#define RST_BUS_MP		30
+#define RST_BUS_DEINTERLACE	31
+#define RST_BUS_CSI0		32
+#define RST_BUS_CSI1		33
+#define RST_BUS_HDMI0		34
+#define RST_BUS_HDMI1		35
+#define RST_BUS_DE		36
+#define RST_BUS_TVE0		37
+#define RST_BUS_TVE1		38
+#define RST_BUS_TVE_TOP		39
+#define RST_BUS_GMAC		40
+#define RST_BUS_GPU		41
+#define RST_BUS_TVD0		42
+#define RST_BUS_TVD1		43
+#define RST_BUS_TVD2		44
+#define RST_BUS_TVD3		45
+#define RST_BUS_TVD_TOP		46
+#define RST_BUS_TCON_LCD0	47
+#define RST_BUS_TCON_LCD1	48
+#define RST_BUS_TCON_TV0	49
+#define RST_BUS_TCON_TV1	50
+#define RST_BUS_TCON_TOP	51
+#define RST_BUS_DBG		52
+#define RST_BUS_LVDS		53
+#define RST_BUS_CODEC		54
+#define RST_BUS_SPDIF		55
+#define RST_BUS_AC97		56
+#define RST_BUS_IR0		57
+#define RST_BUS_IR1		58
+#define RST_BUS_THS		59
+#define RST_BUS_KEYPAD		60
+#define RST_BUS_I2S0		61
+#define RST_BUS_I2S1		62
+#define RST_BUS_I2S2		63
+#define RST_BUS_I2C0		64
+#define RST_BUS_I2C1		65
+#define RST_BUS_I2C2		66
+#define RST_BUS_I2C3		67
+#define RST_BUS_CAN		68
+#define RST_BUS_SCR		69
+#define RST_BUS_PS20		70
+#define RST_BUS_PS21		71
+#define RST_BUS_I2C4		72
+#define RST_BUS_UART0		73
+#define RST_BUS_UART1		74
+#define RST_BUS_UART2		75
+#define RST_BUS_UART3		76
+#define RST_BUS_UART4		77
+#define RST_BUS_UART5		78
+#define RST_BUS_UART6		79
+#define RST_BUS_UART7		80
+
+#endif /* _DT_BINDINGS_RST_SUN8I_R40_H_ */
-- 
2.14.3

^ permalink raw reply related	[flat|nested] 5+ messages in thread
* [U-Boot] [PATCH 2/3] sunxi: sun8i: Add Allwinner V40 support
  2018-04-25  9:50 [U-Boot] [PATCH 1/3] ARM: dts: sun8i: Sync r40 dtsi from Linux Jagan Teki
@ 2018-04-25  9:50 ` Jagan Teki
  2018-04-25 17:24   ` Maxime Ripard
  2018-04-25  9:50 ` [U-Boot] [PATCH 3/3] board: sunxi: sun8i-v4: Add Bananapi M2 Berry support Jagan Teki
  1 sibling, 1 reply; 5+ messages in thread
From: Jagan Teki @ 2018-04-25  9:50 UTC (permalink / raw)
  To: u-boot

Allwinner V40 (sun8i) SoC features a Quad-Core Cortex-A7 ARM CPU,
and a Mali400 MP2 GPU from ARM. It is the automotive version of R40.

This patch add support for V40 by reusing R40 configurations.

MACH_SUN8I_R40_V40 is the common config option for both.

Also fixed checkpatch warnings while making these changes.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 arch/arm/cpu/armv7/sunxi/psci.c               | 10 ++++----
 arch/arm/include/asm/arch-sunxi/clock_sun6i.h |  4 +--
 arch/arm/include/asm/arch-sunxi/cpu_sun4i.h   |  6 ++---
 arch/arm/include/asm/arch-sunxi/timer.h       |  2 +-
 arch/arm/include/asm/arch-sunxi/watchdog.h    |  6 ++---
 arch/arm/mach-sunxi/Kconfig                   | 36 ++++++++++++++++-----------
 arch/arm/mach-sunxi/board.c                   | 11 ++++----
 arch/arm/mach-sunxi/clock_sun6i.c             |  9 +++----
 arch/arm/mach-sunxi/cpu_info.c                |  2 ++
 arch/arm/mach-sunxi/dram_sunxi_dw.c           |  6 ++---
 arch/arm/mach-sunxi/pmic_bus.c                |  8 +++---
 board/sunxi/board.c                           | 26 ++++++++-----------
 drivers/power/Kconfig                         | 18 +++++++-------
 13 files changed, 74 insertions(+), 70 deletions(-)

diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c
index 18da9cb864..39195b6313 100644
--- a/arch/arm/cpu/armv7/sunxi/psci.c
+++ b/arch/arm/cpu/armv7/sunxi/psci.c
@@ -80,7 +80,7 @@ static void __secure clamp_release(u32 __maybe_unused *clamp)
 {
 #if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || \
 	defined(CONFIG_MACH_SUN8I_H3) || \
-	defined(CONFIG_MACH_SUN8I_R40)
+	defined(CONFIG_MACH_SUN8I_R40_V40)
 	u32 tmp = 0x1ff;
 	do {
 		tmp >>= 1;
@@ -95,7 +95,7 @@ static void __secure clamp_set(u32 __maybe_unused *clamp)
 {
 #if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || \
 	defined(CONFIG_MACH_SUN8I_H3) || \
-	defined(CONFIG_MACH_SUN8I_R40)
+	defined(CONFIG_MACH_SUN8I_R40_V40)
 	writel(0xff, clamp);
 #endif
 }
@@ -118,7 +118,7 @@ static void __secure sunxi_power_switch(u32 *clamp, u32 *pwroff, bool on,
 	}
 }
 
-#ifdef CONFIG_MACH_SUN8I_R40
+#ifdef CONFIG_MACH_SUN8I_R40_V40
 /* secondary core entry address is programmed differently on R40 */
 static void __secure sunxi_set_entry_address(void *entry)
 {
@@ -145,7 +145,7 @@ static void __secure sunxi_cpu_set_power(int __always_unused cpu, bool on)
 	sunxi_power_switch(&cpucfg->cpu1_pwr_clamp, &cpucfg->cpu1_pwroff,
 			   on, 0);
 }
-#elif defined CONFIG_MACH_SUN8I_R40
+#elif defined CONFIG_MACH_SUN8I_R40_V40
 static void __secure sunxi_cpu_set_power(int cpu, bool on)
 {
 	struct sunxi_cpucfg_reg *cpucfg =
@@ -155,7 +155,7 @@ static void __secure sunxi_cpu_set_power(int cpu, bool on)
 			   (void *)cpucfg + SUN8I_R40_PWROFF,
 			   on, 0);
 }
-#else /* ! CONFIG_MACH_SUN7I && ! CONFIG_MACH_SUN8I_R40 */
+#else /* ! CONFIG_MACH_SUN7I && ! CONFIG_MACH_SUN8I_R40_V40 */
 static void __secure sunxi_cpu_set_power(int cpu, bool on)
 {
 	struct sunxi_prcm_reg *prcm =
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index d35aa479f7..c4d8c58716 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -285,7 +285,7 @@ struct sunxi_ccm_reg {
 #define AHB_GATE_OFFSET_USB_EHCI1	27
 #define AHB_GATE_OFFSET_USB_EHCI0	26
 #endif
-#ifndef CONFIG_MACH_SUN8I_R40
+#ifndef CONFIG_MACH_SUN8I_R40_V40
 #define AHB_GATE_OFFSET_USB0		24
 #else
 #define AHB_GATE_OFFSET_USB0		25
@@ -439,7 +439,7 @@ struct sunxi_ccm_reg {
 #define CCM_PLL11_PATTERN		0xf5860000
 
 /* ahb_reset0 offsets */
-#ifdef CONFIG_MACH_SUN8I_R40
+#ifdef CONFIG_MACH_SUN8I_R40_V40
 #define AHB_RESET_OFFSET_SATA		24
 #endif
 #define AHB_RESET_OFFSET_GMAC		17
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
index 2419062d45..89300064e1 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -114,7 +114,7 @@ defined(CONFIG_MACH_SUN50I)
 #define SUNXI_TP_BASE			0x01c25000
 #define SUNXI_PMU_BASE			0x01c25400
 
-#if defined CONFIG_MACH_SUN7I || defined CONFIG_MACH_SUN8I_R40
+#if defined CONFIG_MACH_SUN7I || defined CONFIG_MACH_SUN8I_R40_V40
 #define SUNXI_CPUCFG_BASE		0x01c25c00
 #endif
 
@@ -186,8 +186,8 @@ defined(CONFIG_MACH_SUN50I)
 #define SUNXI_PRCM_BASE			0x01f01400
 
 #if defined CONFIG_SUNXI_GEN_SUN6I && \
-    !defined CONFIG_MACH_SUN8I_A83T && \
-    !defined CONFIG_MACH_SUN8I_R40
+	!defined CONFIG_MACH_SUN8I_A83T && \
+	!defined CONFIG_MACH_SUN8I_R40_V40
 #define SUNXI_CPUCFG_BASE		0x01f01c00
 #endif
 
diff --git a/arch/arm/include/asm/arch-sunxi/timer.h b/arch/arm/include/asm/arch-sunxi/timer.h
index ccdf942534..de1a5c1e83 100644
--- a/arch/arm/include/asm/arch-sunxi/timer.h
+++ b/arch/arm/include/asm/arch-sunxi/timer.h
@@ -67,7 +67,7 @@ struct sunxi_timer_reg {
 	struct sunxi_timer timer[6];	/* We have 6 timers */
 	u8 res2[16];
 	struct sunxi_avs avs;
-#if defined(CONFIG_SUNXI_GEN_SUN4I) || defined(CONFIG_MACH_SUN8I_R40)
+#if defined(CONFIG_SUNXI_GEN_SUN4I) || defined(CONFIG_MACH_SUN8I_R40_V40)
 	struct sunxi_wdog wdog;	/* 0x90 */
 	/* XXX the following is not accurate for sun5i/sun7i */
 	struct sunxi_64cnt cnt64;	/* 0xa0 */
diff --git a/arch/arm/include/asm/arch-sunxi/watchdog.h b/arch/arm/include/asm/arch-sunxi/watchdog.h
index ce6d664856..a1041c00c8 100644
--- a/arch/arm/include/asm/arch-sunxi/watchdog.h
+++ b/arch/arm/include/asm/arch-sunxi/watchdog.h
@@ -14,9 +14,9 @@
 #define WDT_CTRL_KEY		(0x0a57 << 1)
 
 #if defined(CONFIG_MACH_SUN4I) || \
-    defined(CONFIG_MACH_SUN5I) || \
-    defined(CONFIG_MACH_SUN7I) || \
-    defined(CONFIG_MACH_SUN8I_R40)
+	defined(CONFIG_MACH_SUN5I) || \
+	defined(CONFIG_MACH_SUN7I) || \
+	defined(CONFIG_MACH_SUN8I_R40_V40)
 
 #define WDT_MODE_EN		(0x1 << 0)
 #define WDT_MODE_RESET_EN	(0x1 << 1)
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index b868f0e350..c50642e1b4 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -121,6 +121,17 @@ config SUNXI_DRAM_DW_32BIT
 	32-bit memory buswidth.
 endif
 
+config MACH_SUN8I_R40_V40
+	bool
+	select CPU_V7
+	select CPU_V7_HAS_NONSEC
+	select CPU_V7_HAS_VIRT
+	select ARCH_SUPPORT_PSCI
+	select SUNXI_GEN_SUN6I
+	select SUPPORT_SPL
+	select SUNXI_DRAM_DW
+	select SUNXI_DRAM_DW_32BIT
+
 config MACH_SUNXI_H3_H5
 	bool
 	select DM_I2C
@@ -218,14 +229,7 @@ config MACH_SUN8I_H3
 
 config MACH_SUN8I_R40
 	bool "sun8i (Allwinner R40)"
-	select CPU_V7
-	select CPU_V7_HAS_NONSEC
-	select CPU_V7_HAS_VIRT
-	select ARCH_SUPPORT_PSCI
-	select SUNXI_GEN_SUN6I
-	select SUPPORT_SPL
-	select SUNXI_DRAM_DW
-	select SUNXI_DRAM_DW_32BIT
+	select MACH_SUN8I_R40_V40
 
 config MACH_SUN8I_V3S
 	bool "sun8i (Allwinner V3s)"
@@ -239,6 +243,10 @@ config MACH_SUN8I_V3S
 	select SUPPORT_SPL
 	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
 
+config MACH_SUN8I_V40
+	bool "sun8i (Allwinner V40)"
+	select MACH_SUN8I_R40_V40
+
 config MACH_SUN9I
 	bool "sun9i (Allwinner A80)"
 	select CPU_V7
@@ -281,7 +289,7 @@ config MACH_SUN8I
 	default y if MACH_SUN8I_A33
 	default y if MACH_SUN8I_A83T
 	default y if MACH_SUNXI_H3_H5
-	default y if MACH_SUN8I_R40
+	default y if MACH_SUN8I_R40_V40
 	default y if MACH_SUN8I_V3S
 
 config RESERVE_ALLWINNER_BOOT0_HEADER
@@ -358,7 +366,7 @@ config DRAM_TYPE
 config DRAM_CLK
 	int "sunxi dram clock speed"
 	default 792 if MACH_SUN9I
-	default 648 if MACH_SUN8I_R40
+	default 648 if MACH_SUN8I_R40_V40
 	default 312 if MACH_SUN6I || MACH_SUN8I
 	default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
 		       MACH_SUN8I_V3S
@@ -382,7 +390,7 @@ config DRAM_ZQ
 	default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
 	default 127 if MACH_SUN7I
 	default 14779 if MACH_SUN8I_V3S
-	default 3881979 if MACH_SUN8I_R40
+	default 3881979 if MACH_SUN8I_R40_V40
 	default 4145117 if MACH_SUN9I
 	default 3881915 if MACH_SUN50I
 	---help---
@@ -392,7 +400,7 @@ config DRAM_ODT_EN
 	bool "sunxi dram odt enable"
 	default n if !MACH_SUN8I_A23
 	default y if MACH_SUN8I_A23
-	default y if MACH_SUN8I_R40
+	default y if MACH_SUN8I_R40_V40
 	default y if MACH_SUN50I
 	---help---
 	Select this to enable dram odt (on die termination).
@@ -633,7 +641,7 @@ config USB3_VBUS_PIN
 
 config I2C0_ENABLE
 	bool "Enable I2C/TWI controller 0"
-	default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
+	default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40_V40
 	default n if MACH_SUN6I || MACH_SUN8I
 	select CMD_I2C
 	---help---
@@ -694,7 +702,7 @@ config VIDEO_SUNXI
 	bool "Enable graphical uboot console on HDMI, LCD or VGA"
 	depends on !MACH_SUN8I_A83T
 	depends on !MACH_SUNXI_H3_H5
-	depends on !MACH_SUN8I_R40
+	depends on !MACH_SUN8I_R40_V40
 	depends on !MACH_SUN8I_V3S
 	depends on !MACH_SUN9I
 	depends on !MACH_SUN50I
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 1753faec1d..8e097d67e6 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -67,14 +67,13 @@ struct mm_region *mem_map = sunxi_mem_map;
 static int gpio_init(void)
 {
 #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
-#if defined(CONFIG_MACH_SUN4I) || \
-    defined(CONFIG_MACH_SUN7I) || \
-    defined(CONFIG_MACH_SUN8I_R40)
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
+		defined(CONFIG_MACH_SUN8I_R40_V40)
 	/* disable GPB22,23 as uart0 tx,rx to avoid conflict */
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
 #endif
-#if defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40)
+#if defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40_V40)
 	sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
 	sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
 #else
@@ -84,7 +83,7 @@ static int gpio_init(void)
 	sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
 #elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || \
 				 defined(CONFIG_MACH_SUN7I) || \
-				 defined(CONFIG_MACH_SUN8I_R40))
+				 defined(CONFIG_MACH_SUN8I_R40_V40))
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
 	sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
@@ -275,7 +274,7 @@ void board_init_f(ulong dummy)
 
 void reset_cpu(ulong addr)
 {
-#if defined(CONFIG_SUNXI_GEN_SUN4I) || defined(CONFIG_MACH_SUN8I_R40)
+#if defined(CONFIG_SUNXI_GEN_SUN4I) || defined(CONFIG_MACH_SUN8I_R40_V40)
 	static const struct sunxi_wdog *wdog =
 		 &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
 
diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c
index 870ff5b1e0..6347085a76 100644
--- a/arch/arm/mach-sunxi/clock_sun6i.c
+++ b/arch/arm/mach-sunxi/clock_sun6i.c
@@ -35,7 +35,7 @@ void clock_init_safe(void)
 	clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);
 #endif
 
-#if defined(CONFIG_MACH_SUN8I_R40) || defined(CONFIG_MACH_SUN50I)
+#if defined(CONFIG_MACH_SUN8I_R40_V40) || defined(CONFIG_MACH_SUN50I)
 	/* Set PLL lock enable bits and switch to old lock mode */
 	writel(GENMASK(12, 0), &ccm->pll_lock_ctrl);
 #endif
@@ -52,7 +52,7 @@ void clock_init_safe(void)
 	if (IS_ENABLED(CONFIG_MACH_SUN6I))
 		writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);
 
-#if defined(CONFIG_MACH_SUN8I_R40) && defined(CONFIG_SUNXI_AHCI)
+#if defined(CONFIG_MACH_SUN8I_R40_V40) && defined(CONFIG_SUNXI_AHCI)
 	setbits_le32(&ccm->sata_pll_cfg, CCM_SATA_PLL_DEFAULT);
 	setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_GATE_OFFSET_SATA);
 	setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA);
@@ -273,9 +273,8 @@ void clock_set_pll10(unsigned int clk)
 }
 #endif
 
-#if defined(CONFIG_MACH_SUN8I_A33) || \
-    defined(CONFIG_MACH_SUN8I_R40) || \
-    defined(CONFIG_MACH_SUN50I)
+#if defined(CONFIG_MACH_SUN8I_A33) || defined(CONFIG_MACH_SUN8I_R40_V40) || \
+	defined(CONFIG_MACH_SUN50I)
 void clock_set_pll11(unsigned int clk, bool sigma_delta_enable)
 {
 	struct sunxi_ccm_reg * const ccm =
diff --git a/arch/arm/mach-sunxi/cpu_info.c b/arch/arm/mach-sunxi/cpu_info.c
index 25a5ec26a0..6f1386b2d0 100644
--- a/arch/arm/mach-sunxi/cpu_info.c
+++ b/arch/arm/mach-sunxi/cpu_info.c
@@ -89,6 +89,8 @@ int print_cpuinfo(void)
 	printf("CPU:   Allwinner H3 (SUN8I %04x)\n", sunxi_get_sram_id());
 #elif defined CONFIG_MACH_SUN8I_R40
 	printf("CPU:   Allwinner R40 (SUN8I %04x)\n", sunxi_get_sram_id());
+#elif defined CONFIG_MACH_SUN8I_V40
+	printf("CPU:   Allwinner V40 (SUN8I %04x)\n", sunxi_get_sram_id());
 #elif defined CONFIG_MACH_SUN8I_V3S
 	printf("CPU:   Allwinner V3s (SUN8I %04x)\n", sunxi_get_sram_id());
 #elif defined CONFIG_MACH_SUN9I
diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c
index 78b4ffb9c3..ffe39216c7 100644
--- a/arch/arm/mach-sunxi/dram_sunxi_dw.c
+++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c
@@ -43,7 +43,7 @@ static void mctl_set_bit_delays(struct dram_para *para)
 		writel(ACBDLR_WRITE_DELAY(para->ac_delays[i]),
 		       &mctl_ctl->acbdlr[i]);
 
-#ifdef CONFIG_MACH_SUN8I_R40
+#ifdef CONFIG_MACH_SUN8I_R40_V40
 	/* DQSn, DMn, DQn output enable bit delay */
 	for (i = 0; i < 4; i++)
 		writel(0x6 << 24, &mctl_ctl->dx[i].sdlr);
@@ -700,7 +700,7 @@ unsigned long sunxi_dram_init(void)
 		.dx_read_delays  = SUN8I_H3_DX_READ_DELAYS,
 		.dx_write_delays = SUN8I_H3_DX_WRITE_DELAYS,
 		.ac_delays	 = SUN8I_H3_AC_DELAYS,
-#elif defined(CONFIG_MACH_SUN8I_R40)
+#elif defined(CONFIG_MACH_SUN8I_R40_V40)
 		.dx_read_delays  = SUN8I_R40_DX_READ_DELAYS,
 		.dx_write_delays = SUN8I_R40_DX_WRITE_DELAYS,
 		.ac_delays	 = SUN8I_R40_AC_DELAYS,
@@ -721,7 +721,7 @@ unsigned long sunxi_dram_init(void)
  */
 #if defined(CONFIG_MACH_SUN8I_H3)
 	uint16_t socid = SOCID_H3;
-#elif defined(CONFIG_MACH_SUN8I_R40)
+#elif defined(CONFIG_MACH_SUN8I_R40_V40)
 	uint16_t socid = SOCID_R40;
 	/* Currently we cannot support R40 with dual rank memory */
 	para.dual_rank = 0;
diff --git a/arch/arm/mach-sunxi/pmic_bus.c b/arch/arm/mach-sunxi/pmic_bus.c
index f917c3e070..5f48bb1942 100644
--- a/arch/arm/mach-sunxi/pmic_bus.c
+++ b/arch/arm/mach-sunxi/pmic_bus.c
@@ -41,8 +41,8 @@ int pmic_bus_init(void)
 	p2wi_init();
 	ret = p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR, AXP221_CTRL_ADDR,
 				       AXP221_INIT_DATA);
-# elif defined CONFIG_MACH_SUN8I_R40
-	/* Nothing. R40 uses the AXP221s in I2C mode */
+# elif defined CONFIG_MACH_SUN8I_R40_V40
+	/* Nothing. R40_V40 uses the AXP221s in I2C mode */
 	ret = 0;
 # else
 	ret = rsb_init();
@@ -68,7 +68,7 @@ int pmic_bus_read(u8 reg, u8 *data)
 #elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
 # ifdef CONFIG_MACH_SUN6I
 	return p2wi_read(reg, data);
-# elif defined CONFIG_MACH_SUN8I_R40
+# elif defined CONFIG_MACH_SUN8I_R40_V40
 	return i2c_read(AXP209_I2C_ADDR, reg, 1, data, 1);
 # else
 	return rsb_read(AXP223_RUNTIME_ADDR, reg, data);
@@ -85,7 +85,7 @@ int pmic_bus_write(u8 reg, u8 data)
 #elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
 # ifdef CONFIG_MACH_SUN6I
 	return p2wi_write(reg, data);
-# elif defined CONFIG_MACH_SUN8I_R40
+# elif defined CONFIG_MACH_SUN8I_R40_V40
 	return i2c_write(AXP209_I2C_ADDR, reg, 1, &data, 1);
 # else
 	return rsb_write(AXP223_RUNTIME_ADDR, reg, data);
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 322dd9e23a..13fedc29f5 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -82,10 +82,8 @@ DECLARE_GLOBAL_DATA_PTR;
 void i2c_init_board(void)
 {
 #ifdef CONFIG_I2C0_ENABLE
-#if defined(CONFIG_MACH_SUN4I) || \
-    defined(CONFIG_MACH_SUN5I) || \
-    defined(CONFIG_MACH_SUN7I) || \
-    defined(CONFIG_MACH_SUN8I_R40)
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || \
+		defined(CONFIG_MACH_SUN7I) || defined(CONFIG_MACH_SUN8I_R40_V40)
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
 	clock_twi_onoff(0, 1);
@@ -101,9 +99,8 @@ void i2c_init_board(void)
 #endif
 
 #ifdef CONFIG_I2C1_ENABLE
-#if defined(CONFIG_MACH_SUN4I) || \
-    defined(CONFIG_MACH_SUN7I) || \
-    defined(CONFIG_MACH_SUN8I_R40)
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
+		defined(CONFIG_MACH_SUN8I_R40_V40)
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
 	clock_twi_onoff(1, 1);
@@ -123,9 +120,8 @@ void i2c_init_board(void)
 #endif
 
 #ifdef CONFIG_I2C2_ENABLE
-#if defined(CONFIG_MACH_SUN4I) || \
-    defined(CONFIG_MACH_SUN7I) || \
-    defined(CONFIG_MACH_SUN8I_R40)
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
+		defined(CONFIG_MACH_SUN8I_R40_V40)
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
 	clock_twi_onoff(2, 1);
@@ -150,7 +146,7 @@ void i2c_init_board(void)
 	sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
 	clock_twi_onoff(3, 1);
 #elif defined(CONFIG_MACH_SUN7I) || \
-      defined(CONFIG_MACH_SUN8I_R40)
+		defined(CONFIG_MACH_SUN8I_R40_V40)
 	sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
 	sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
 	clock_twi_onoff(3, 1);
@@ -159,7 +155,7 @@ void i2c_init_board(void)
 
 #ifdef CONFIG_I2C4_ENABLE
 #if defined(CONFIG_MACH_SUN7I) || \
-    defined(CONFIG_MACH_SUN8I_R40)
+		defined(CONFIG_MACH_SUN8I_R40_V40)
 	sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
 	sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
 	clock_twi_onoff(4, 1);
@@ -323,7 +319,7 @@ static void mmc_pinmux_setup(int sdc)
 		pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
 
 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
-    defined(CONFIG_MACH_SUN8I_R40)
+			defined(CONFIG_MACH_SUN8I_R40_V40)
 		if (pins == SUNXI_GPIO_H) {
 			/* SDC1: PH22-PH-27 */
 			for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
@@ -418,7 +414,7 @@ static void mmc_pinmux_setup(int sdc)
 			sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
 			sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
 		}
-#elif defined(CONFIG_MACH_SUN8I_R40)
+#elif defined(CONFIG_MACH_SUN8I_R40_V40)
 		/* SDC2: PC6-PC15, PC24 */
 		for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
 			sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
@@ -456,7 +452,7 @@ static void mmc_pinmux_setup(int sdc)
 		pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
 
 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
-    defined(CONFIG_MACH_SUN8I_R40)
+			defined(CONFIG_MACH_SUN8I_R40_V40)
 		/* SDC3: PI4-PI9 */
 		for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
 			sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index 1a3852442a..4494075394 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -10,7 +10,7 @@ choice
 	prompt "Select Sunxi PMIC Variant"
 	depends on ARCH_SUNXI
 	default AXP209_POWER if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
-	default AXP221_POWER if MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_R40
+	default AXP221_POWER if MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_R40_V40
 	default AXP818_POWER if MACH_SUN8I_A83T
 	default SUNXI_NO_PMIC if MACH_SUNXI_H3_H5 || MACH_SUN50I
 
@@ -39,7 +39,7 @@ config AXP209_POWER
 
 config AXP221_POWER
 	bool "axp221 / axp223 pmic support"
-	depends on MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_R40
+	depends on MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_R40_V40
 	select AXP_PMIC_BUS
 	select CMD_POWEROFF
 	---help---
@@ -75,7 +75,7 @@ endchoice
 config AXP_DCDC1_VOLT
 	int "axp pmic dcdc1 voltage"
 	depends on AXP221_POWER || AXP809_POWER || AXP818_POWER
-	default 3300 if AXP818_POWER || MACH_SUN8I_R40
+	default 3300 if AXP818_POWER || MACH_SUN8I_R40_V40
 	default 3000 if MACH_SUN6I || MACH_SUN8I || MACH_SUN9I
 	---help---
 	Set the voltage (mV) to program the axp pmic dcdc1 at, set to 0 to
@@ -102,7 +102,7 @@ config AXP_DCDC2_VOLT
 	On A23/A33 boards dcdc2 is used for VDD-SYS and should be 1.1V.
 	On A80 boards dcdc2 powers the GPU and can be left off.
 	On A83T boards dcdc2 is used for VDD-CPUA(cluster 0) and should be 0.9V.
-	On R40 boards dcdc2 is VDD-CPU and should be 1.1V
+	On R40_V40 boards dcdc2 is VDD-CPU and should be 1.1V
 
 config AXP_DCDC3_VOLT
 	int "axp pmic dcdc3 voltage"
@@ -110,7 +110,7 @@ config AXP_DCDC3_VOLT
 	default 900 if AXP809_POWER || AXP818_POWER
 	default 1500 if AXP152_POWER
 	default 1250 if AXP209_POWER
-	default 1100 if MACH_SUN8I_R40
+	default 1100 if MACH_SUN8I_R40_V40
 	default 1200 if MACH_SUN6I || MACH_SUN8I
 	---help---
 	Set the voltage (mV) to program the axp pmic dcdc3 at, set to 0 to
@@ -121,7 +121,7 @@ config AXP_DCDC3_VOLT
 	On A23 / A31 / A33 boards dcdc3 is VDD-CPU and should be 1.2V.
 	On A80 boards dcdc3 is used for VDD-CPUA(cluster 0) and should be 0.9V.
 	On A83T boards dcdc3 is used for VDD-CPUB(cluster 1) and should be 0.9V.
-	On R40 boards dcdc3 is VDD-SYS and VDD-GPU and should be 1.1V.
+	On R40_V40 boards dcdc3 is VDD-SYS and VDD-GPU and should be 1.1V.
 
 config AXP_DCDC4_VOLT
 	int "axp pmic dcdc4 voltage"
@@ -146,13 +146,13 @@ config AXP_DCDC5_VOLT
 	---help---
 	Set the voltage (mV) to program the axp pmic dcdc5 at, set to 0 to
 	disable dcdc5.
-	On A23 / A31 / A33 / A80 / A83T / R40 boards dcdc5 is VCC-DRAM and
+	On A23 / A31 / A33 / A80 / A83T / R40_V40 boards dcdc5 is VCC-DRAM and
 	should be 1.5V, 1.35V if DDR3L is used.
 
 config AXP_ALDO1_VOLT
 	int "axp pmic (a)ldo1 voltage"
 	depends on AXP221_POWER || AXP809_POWER || AXP818_POWER
-	default 0 if MACH_SUN6I || MACH_SUN8I_R40
+	default 0 if MACH_SUN6I || MACH_SUN8I_R40_V40
 	default 1800 if MACH_SUN8I_A83T
 	default 3000 if MACH_SUN8I || MACH_SUN9I
 	---help---
@@ -191,7 +191,7 @@ config AXP_ALDO3_VOLT
 	Set the voltage (mV) to program the axp pmic aldo3 at, set to 0 to
 	disable aldo3.
 	On A10(s) / A13 / A20 boards aldo3 should be 2.8V.
-	On A23 / A31 / A33 / R40 boards aldo3 is VCC-PLL and AVCC and should
+	On A23 / A31 / A33 / R40_V40 boards aldo3 is VCC-PLL and AVCC and should
 	be 3.0V.
 	On A80 boards aldo3 is normally not used.
 	On A83T / H8 boards aldo3 is AVCC, VCC-PL, and VCC-LED, and should be
-- 
2.14.3

^ permalink raw reply related	[flat|nested] 5+ messages in thread
* [U-Boot] [PATCH 3/3] board: sunxi: sun8i-v4: Add Bananapi M2 Berry support
  2018-04-25  9:50 [U-Boot] [PATCH 1/3] ARM: dts: sun8i: Sync r40 dtsi from Linux Jagan Teki
  2018-04-25  9:50 ` [U-Boot] [PATCH 2/3] sunxi: sun8i: Add Allwinner V40 support Jagan Teki
@ 2018-04-25  9:50 ` Jagan Teki
  1 sibling, 0 replies; 5+ messages in thread
From: Jagan Teki @ 2018-04-25  9:50 UTC (permalink / raw)
  To: u-boot

Banana Pi BPI-M2 Berry is a quad-core mini single board computer
built with Allwinner V40 SoC. It features
- Quad Core ARM Cortex A7 CPU V40
- 1GB of RAM .
- microSD/SATA port..
- onboard WiFi and BT
- 4 USB A 2.0 ports
- 1 USB OTG port
- 1 HDMI port
- 1 audio jack
- DC power port

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 arch/arm/dts/Makefile                        |   2 +
 arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts | 132 +++++++++++++++++++++++++++
 board/sunxi/MAINTAINERS                      |   5 +
 configs/bananapi_m2_berry_defconfig          |  14 +++
 4 files changed, 153 insertions(+)
 create mode 100644 arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts
 create mode 100644 configs/bananapi_m2_berry_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ac7667b1e8..de6103602c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -369,6 +369,8 @@ dtb-$(CONFIG_MACH_SUN8I_R40) += \
 	sun8i-r40-bananapi-m2-ultra.dtb
 dtb-$(CONFIG_MACH_SUN8I_V3S) += \
 	sun8i-v3s-licheepi-zero.dtb
+dtb-$(CONFIG_MACH_SUN8I_V40) += \
+	sun8i-v40-bananapi-m2-berry.dtb
 dtb-$(CONFIG_MACH_SUN50I_H5) += \
 	sun50i-h5-nanopi-neo2.dtb \
 	sun50i-h5-nanopi-neo-plus2.dtb \
diff --git a/arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts b/arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts
new file mode 100644
index 0000000000..193d9b29ec
--- /dev/null
+++ b/arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts
@@ -0,0 +1,132 @@
+/*
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-r40.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "Banana Pi M2 Berry";
+	compatible = "sinovoip,bpi-m2-berry", "allwinner,sun8i-r40";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&i2c0 {
+	status = "okay";
+
+	axp22x: pmic at 68 {
+		compatible = "x-powers,axp221";
+		reg = <0x34>;
+		interrupt-parent = <&nmi_intc>;
+		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+	};
+};
+
+#include "axp22x.dtsi"
+
+&reg_aldo3 {
+	regulator-always-on;
+	regulator-min-microvolt = <2700000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "avcc";
+};
+
+&reg_dcdc1 {
+	regulator-always-on;
+	regulator-min-microvolt = <3000000>;
+	regulator-max-microvolt = <3000000>;
+	regulator-name = "vcc-3v0";
+};
+
+&reg_dcdc2 {
+	regulator-always-on;
+	regulator-min-microvolt = <1000000>;
+	regulator-max-microvolt = <1300000>;
+	regulator-name = "vdd-cpu";
+};
+
+&reg_dcdc3 {
+	regulator-always-on;
+	regulator-min-microvolt = <1000000>;
+	regulator-max-microvolt = <1300000>;
+	regulator-name = "vdd-sys";
+};
+
+&reg_dcdc5 {
+	regulator-always-on;
+	regulator-min-microvolt = <1500000>;
+	regulator-max-microvolt = <1500000>;
+	regulator-name = "vcc-dram";
+};
+
+&reg_dldo1 {
+	regulator-min-microvolt = <1800000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-wifi-io";
+};
+
+&reg_dldo2 {
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-wifi";
+};
+
+&mmc0 {
+	vmmc-supply = <&reg_dcdc1>;
+	bus-width = <4>;
+	cd-gpios = <&pio 7 13 GPIO_ACTIVE_LOW>; /* PH13 */
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pb_pins>;
+	status = "okay";
+};
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index 6dd48c0265..5d31bcbdcd 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -126,6 +126,11 @@ M:	Jagan Teki <jagan@amarulasolutions.com>
 S:	Maintained
 F:	configs/bananapi_m1_plus_defconfig
 
+BANANAPI M2 BERRY
+M:	Jagan Teki <jagan@amarulasolutions.com>
+S:	Maintained
+F:	configs/bananapi_m2_berry_defconfig
+
 BANANAPI M2 ULTRA BOARD
 M:	Chen-Yu Tsai <wens@csie.org>
 S:	Maintained
diff --git a/configs/bananapi_m2_berry_defconfig b/configs/bananapi_m2_berry_defconfig
new file mode 100644
index 0000000000..7dc9190d7f
--- /dev/null
+++ b/configs/bananapi_m2_berry_defconfig
@@ -0,0 +1,14 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_SPL=y
+CONFIG_MACH_SUN8I_V40=y
+CONFIG_DRAM_CLK=576
+CONFIG_DRAM_ZQ=3881979
+CONFIG_DRAM_ODT_EN=y
+CONFIG_MMC0_CD_PIN="PH13"
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-v40-bananapi-m2-berry"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_I2C_SUPPORT=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_AXP_DLDO4_VOLT=2500
+CONFIG_AXP_ELDO3_VOLT=1200
-- 
2.14.3

^ permalink raw reply related	[flat|nested] 5+ messages in thread
* [U-Boot] [PATCH 2/3] sunxi: sun8i: Add Allwinner V40 support
  2018-04-25  9:50 ` [U-Boot] [PATCH 2/3] sunxi: sun8i: Add Allwinner V40 support Jagan Teki
@ 2018-04-25 17:24   ` Maxime Ripard
  2018-04-25 17:46     ` Jagan Teki
  0 siblings, 1 reply; 5+ messages in thread
From: Maxime Ripard @ 2018-04-25 17:24 UTC (permalink / raw)
  To: u-boot

On Wed, Apr 25, 2018 at 03:20:14PM +0530, Jagan Teki wrote:
> Allwinner V40 (sun8i) SoC features a Quad-Core Cortex-A7 ARM CPU,
> and a Mali400 MP2 GPU from ARM. It is the automotive version of R40.
> 
> This patch add support for V40 by reusing R40 configurations.
> 
> MACH_SUN8I_R40_V40 is the common config option for both.
> 
> Also fixed checkpatch warnings while making these changes.
> 
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>

Is there any difference between the R40 and V40?

If not, then there's no point in doing this. We already support the R8
and R16 that are exactly the same SoCs than the A13 and A33,
respectively, without having to rewrite the whole thing.

And if there's some minor differences, you can just add a V40 option
that selects the R40. In both cases, the diff is not necessary.

Maxime

-- 
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com

^ permalink raw reply	[flat|nested] 5+ messages in thread
* [U-Boot] [PATCH 2/3] sunxi: sun8i: Add Allwinner V40 support
  2018-04-25 17:24   ` Maxime Ripard
@ 2018-04-25 17:46     ` Jagan Teki
  0 siblings, 0 replies; 5+ messages in thread
From: Jagan Teki @ 2018-04-25 17:46 UTC (permalink / raw)
  To: u-boot

On Wed, Apr 25, 2018 at 10:54 PM, Maxime Ripard
<maxime.ripard@bootlin.com> wrote:
> On Wed, Apr 25, 2018 at 03:20:14PM +0530, Jagan Teki wrote:
>> Allwinner V40 (sun8i) SoC features a Quad-Core Cortex-A7 ARM CPU,
>> and a Mali400 MP2 GPU from ARM. It is the automotive version of R40.
>>
>> This patch add support for V40 by reusing R40 configurations.
>>
>> MACH_SUN8I_R40_V40 is the common config option for both.
>>
>> Also fixed checkpatch warnings while making these changes.
>>
>> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
>
> Is there any difference between the R40 and V40?

As of now I didn't see any diff.

>
> If not, then there's no point in doing this. We already support the R8
> and R16 that are exactly the same SoCs than the A13 and A33,
> respectively, without having to rewrite the whole thing.

What about cpu_info we can simply notify R40 for V40 SOC?

>
> And if there's some minor differences, you can just add a V40 option
> that selects the R40. In both cases, the diff is not necessary.

This I've tried and fired with Kbuild recursive definition issue.

-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.

^ permalink raw reply	[flat|nested] 5+ messages in thread
end of thread, other threads:[~2018-04-25 17:46 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2018-04-25  9:50 [U-Boot] [PATCH 1/3] ARM: dts: sun8i: Sync r40 dtsi from Linux Jagan Teki
2018-04-25  9:50 ` [U-Boot] [PATCH 2/3] sunxi: sun8i: Add Allwinner V40 support Jagan Teki
2018-04-25 17:24   ` Maxime Ripard
2018-04-25 17:46     ` Jagan Teki
2018-04-25  9:50 ` [U-Boot] [PATCH 3/3] board: sunxi: sun8i-v4: Add Bananapi M2 Berry support Jagan Teki

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