From: Tom Rini <trini@konsulko.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [U-Boot, 1/4] ARM: Introduce ability to enable ACR::IBE on Cortex-A8 for CVE-2017-5715
Date: Fri, 29 Jun 2018 16:53:06 -0400 [thread overview]
Message-ID: <20180629205306.GI18596@bill-the-cat> (raw)
In-Reply-To: <20180612202411.29798-2-nm@ti.com>
On Tue, Jun 12, 2018 at 03:24:08PM -0500, Nishanth Menon wrote:
> As recommended by Arm in [1], IBE[2] has to be enabled unconditionally
> for BPIALL to be functional on Cortex-A8 processors. Provide a config
> option for platforms to enable this option based on impact analysis
> for products.
>
> NOTE: This patch in itself is NOT the final solution, this requires:
> a) Implementation of v7_arch_cp15_set_acr on SoCs which may not
> provide direct access to ACR register.
> b) Operating Systems such as Linux to provide adequate workaround in the right
> locations.
> c) This workaround applies to only the boot processor. It is important
> to apply workaround as necessary (context-save-restore) around low
> power context loss OR additional processors as necessary in either
> firmware support OR elsewhere in OS.
>
> [1] https://developer.arm.com/support/security-update
> [2] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0344k/Bgbffjhh.html
>
> Cc: Marc Zyngier <marc.zyngier@arm.com>
> Cc: Russell King <linux@arm.linux.org.uk>
> Cc: Tony Lindgren <tony@atomide.com>
> Cc: Robin Murphy <robin.murphy@arm.com>
> Cc: Florian Fainelli <f.fainelli@gmail.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will.deacon@arm.com>
> Cc: Christoffer Dall <christoffer.dall@linaro.org>
> Cc: Andre Przywara <Andre.Przywara@arm.com>
> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> Cc: Tom Rini <trini@konsulko.com>
> Cc: Michael Nazzareno Trimarchi <michael@amarulasolutions.com>
>
> Signed-off-by: Nishanth Menon <nm@ti.com>
> Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
Applied to u-boot/master, thanks!
--
Tom
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next prev parent reply other threads:[~2018-06-29 20:53 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-12 20:24 [U-Boot] [PATCH 0/4] ARM: Provide workaround setup bits for CVE-2017-5715 (A8/A15) Nishanth Menon
2018-06-12 20:24 ` [U-Boot] [PATCH 1/4] ARM: Introduce ability to enable ACR::IBE on Cortex-A8 for CVE-2017-5715 Nishanth Menon
2018-06-20 14:13 ` Fabio Estevam
2018-06-29 20:53 ` Tom Rini [this message]
2018-06-12 20:24 ` [U-Boot] [PATCH 2/4] ARM: Introduce ability to enable invalidate of BTB with ICIALLU on Cortex-A15 " Nishanth Menon
2018-06-12 23:05 ` Marek Vasut
2018-06-13 13:32 ` Nishanth Menon
2018-06-13 15:46 ` Tom Rini
2018-06-13 21:32 ` Nishanth Menon
2018-06-13 23:06 ` Marek Vasut
2018-06-13 0:30 ` Florian Fainelli
2018-06-13 13:37 ` Nishanth Menon
2018-06-13 21:36 ` Florian Fainelli
2018-06-14 12:46 ` Nishanth Menon
2018-06-20 14:14 ` Fabio Estevam
2018-06-29 20:53 ` [U-Boot] [U-Boot, " Tom Rini
2018-06-12 20:24 ` [U-Boot] [PATCH 3/4] ARM: mach-omap2: omap5/dra7: Enable ACTLR[0] (Enable invalidates of BTB) to facilitate CVE_2017-5715 WA in OS Nishanth Menon
2018-06-12 23:06 ` Marek Vasut
2018-06-13 13:40 ` Nishanth Menon
2018-06-13 17:36 ` Russell King - ARM Linux
2018-06-13 20:36 ` Marek Vasut
2018-06-13 21:31 ` Nishanth Menon
2018-06-13 21:47 ` Russell King - ARM Linux
2018-06-29 20:53 ` [U-Boot] [U-Boot, " Tom Rini
2018-06-12 20:24 ` [U-Boot] [PATCH 4/4] ARM: mach-omap2: omap3/am335x: Enable ACR::IBE on Cortex-A8 SoCs for CVE-2017-5715 Nishanth Menon
2018-06-29 20:53 ` [U-Boot] [U-Boot, " Tom Rini
2018-06-12 23:06 ` [U-Boot] [PATCH 0/4] ARM: Provide workaround setup bits for CVE-2017-5715 (A8/A15) Marek Vasut
2018-06-18 18:48 ` Tom Rini
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