From mboxrd@z Thu Jan 1 00:00:00 1970 From: Shreenidhi Shedi Date: Sat, 30 Jun 2018 03:21:43 +0530 Subject: [U-Boot] [PATCH v1 6/6] watchdog: Convert Xilinx Axi watchdog driver to driver model In-Reply-To: <20180629215143.3975-1-yesshedi@gmail.com> References: <20180629215143.3975-1-yesshedi@gmail.com> Message-ID: <20180629215143.3975-7-yesshedi@gmail.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable To: u-boot@lists.denx.de Signed-off-by: Shreenidhi Shedi --- Changes in v1: None drivers/watchdog/Kconfig | 8 +++ drivers/watchdog/xilinx_tb_wdt.c | 107 ++++++++++++++++++++++++------- 2 files changed, 91 insertions(+), 24 deletions(-) diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 148c6a0d68..351d2af8d9 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -103,4 +103,12 @@ config WDT_CDNS Select this to enable Cadence watchdog timer, which can be found on so= me Xilinx Microzed Platform. =20 +config XILINX_TB_WATCHDOG + bool "Xilinx Axi watchdog timer support" + depends on WDT + imply WATCHDOG + help + Select this to enable Xilinx Axi watchdog timer, which can be found on= some + Xilinx Microblaze Platform. + endmenu diff --git a/drivers/watchdog/xilinx_tb_wdt.c b/drivers/watchdog/xilinx_tb_= wdt.c index 2274123e49..7f20c2ce2f 100644 --- a/drivers/watchdog/xilinx_tb_wdt.c +++ b/drivers/watchdog/xilinx_tb_wdt.c @@ -1,13 +1,17 @@ // SPDX-License-Identifier: GPL-2.0+ /* + * Xilinx Axi platforms watchdog timer driver. + * + * Author(s): Michal =C5=A0imek + * Shreenidhi Shedi + * * Copyright (c) 2011-2013 Xilinx Inc. */ =20 #include -#include -#include -#include -#include +#include +#include +#include =20 #define XWT_CSR0_WRS_MASK 0x00000008 /* Reset status Mask */ #define XWT_CSR0_WDS_MASK 0x00000004 /* Timer state Mask */ @@ -20,49 +24,104 @@ struct watchdog_regs { u32 tbr; /* 0x8 */ }; =20 -static struct watchdog_regs *watchdog_base =3D - (struct watchdog_regs *)CONFIG_WATCHDOG_BASEADDR; +struct xlnx_wdt_priv { + bool enable_once; + struct watchdog_regs *regs; +}; =20 -void hw_watchdog_reset(void) +static int xlnx_wdt_reset(struct udevice *dev) { u32 reg; + struct xlnx_wdt_priv *priv =3D dev_get_priv(dev); + + debug("%s\n", __func__); =20 /* Read the current contents of TCSR0 */ - reg =3D readl(&watchdog_base->twcsr0); + reg =3D readl(&priv->regs->twcsr0); =20 /* Clear the watchdog WDS bit */ if (reg & (XWT_CSR0_EWDT1_MASK | XWT_CSRX_EWDT2_MASK)) - writel(reg | XWT_CSR0_WDS_MASK, &watchdog_base->twcsr0); + writel(reg | XWT_CSR0_WDS_MASK, &priv->regs->twcsr0); + + return 0; } =20 -void hw_watchdog_disable(void) +static int xlnx_wdt_stop(struct udevice *dev) { u32 reg; + struct xlnx_wdt_priv *priv =3D dev_get_priv(dev); + + if (priv->enable_once) { + puts("Can't stop Xilinux Axi watchdog.\n"); + return -1; + } =20 /* Read the current contents of TCSR0 */ - reg =3D readl(&watchdog_base->twcsr0); + reg =3D readl(&priv->regs->twcsr0); =20 - writel(reg & ~XWT_CSR0_EWDT1_MASK, &watchdog_base->twcsr0); - writel(~XWT_CSRX_EWDT2_MASK, &watchdog_base->twcsr1); + writel(reg & ~XWT_CSR0_EWDT1_MASK, &priv->regs->twcsr0); + writel(~XWT_CSRX_EWDT2_MASK, &priv->regs->twcsr1); =20 puts("Watchdog disabled!\n"); + + return 0; } =20 -static void hw_watchdog_isr(void *arg) +static int xlnx_wdt_start(struct udevice *dev, u64 timeout, ulong flags) { - hw_watchdog_reset(); + struct xlnx_wdt_priv *priv =3D dev_get_priv(dev); + + writel((XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK | XWT_CSR0_EWDT1_MASK), + &priv->regs->twcsr0); + + writel(XWT_CSRX_EWDT2_MASK, &priv->regs->twcsr1); + + return 0; } =20 -void hw_watchdog_init(void) +static int xlnx_wdt_probe(struct udevice *dev) { - int ret; + debug("%s: Probing wdt%u\n", __func__, dev->seq); =20 - writel((XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK | XWT_CSR0_EWDT1_MASK), - &watchdog_base->twcsr0); - writel(XWT_CSRX_EWDT2_MASK, &watchdog_base->twcsr1); + xlnx_wdt_stop(dev); =20 - ret =3D install_interrupt_handler(CONFIG_WATCHDOG_IRQ, - hw_watchdog_isr, NULL); - if (ret) - puts("Watchdog IRQ registration failed."); + return 0; } + +static int xlnx_wdt_ofdata_to_platdata(struct udevice *dev) +{ + struct xlnx_wdt_priv *priv =3D dev_get_priv(dev); + + priv->regs =3D (struct watchdog_regs *)dev_read_addr(dev); + if (IS_ERR(priv->regs)) + return PTR_ERR(priv->regs); + + priv->enable_once =3D dev_read_u32_default(dev, "xlnx,wdt-enable-once", + 0); + + debug("%s: wdt-enable-once %d\n", __func__, priv->enable_once); + + return 0; +} + +static const struct wdt_ops xlnx_wdt_ops =3D { + .start =3D xlnx_wdt_start, + .reset =3D xlnx_wdt_reset, + .stop =3D xlnx_wdt_stop, +}; + +static const struct udevice_id xlnx_wdt_ids[] =3D { + { .compatible =3D "xlnx,xps-timebase-wdt-1.00.a", }, + { .compatible =3D "xlnx,xps-timebase-wdt-1.01.a", }, + {}, +}; + +U_BOOT_DRIVER(xlnx_wdt) =3D { + .name =3D "xlnx_wdt", + .id =3D UCLASS_WDT, + .of_match =3D xlnx_wdt_ids, + .probe =3D xlnx_wdt_probe, + .priv_auto_alloc_size =3D sizeof(struct xlnx_wdt_priv), + .ofdata_to_platdata =3D xlnx_wdt_ofdata_to_platdata, + .ops =3D &xlnx_wdt_ops, +}; --=20 2.17.1