From mboxrd@z Thu Jan 1 00:00:00 1970 From: Miquel Raynal Date: Thu, 12 Jul 2018 14:29:13 +0200 Subject: [U-Boot] [PATCH v2 21/21] dt-bindings: Add bindings for SPI NAND devices In-Reply-To: <20180712004444.38f6f9b3@bbrezillon> References: <20180711152529.24547-1-miquel.raynal@bootlin.com> <20180711152529.24547-22-miquel.raynal@bootlin.com> <20180712004444.38f6f9b3@bbrezillon> Message-ID: <20180712142913.133ada6b@xps13> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable To: u-boot@lists.denx.de Hi Boris, Boris Brezillon wrote on Thu, 12 Jul 2018 00:44:44 +0200: > On Wed, 11 Jul 2018 17:25:29 +0200 > Miquel Raynal wrote: >=20 > > From: Boris Brezillon > >=20 > > Add bindings for SPI NAND chips. > >=20 > > Signed-off-by: Boris Brezillon > > Signed-off-by: Miquel Raynal > > --- > > doc/device-tree-bindings/mtd/spi-nand.txt | 27 +++++++++++++++++++++++= ++++ > > 1 file changed, 27 insertions(+) > > create mode 100644 doc/device-tree-bindings/mtd/spi-nand.txt > >=20 > > diff --git a/doc/device-tree-bindings/mtd/spi-nand.txt b/doc/device-tre= e-bindings/mtd/spi-nand.txt > > new file mode 100644 > > index 0000000000..d55f80196c > > --- /dev/null > > +++ b/doc/device-tree-bindings/mtd/spi-nand.txt > > @@ -0,0 +1,27 @@ > > +SPI NAND flash > > + > > +Required properties: > > +- compatible: should be "spi-nand" > > +- reg: should encode the chip-select line used to access the NAND chip > > + > > +Optional properties > > +- spi-max-frequency: maximum frequency of the SPI bus the chip can ope= rate at. > > + This should encode board limitations (i.e. max freq can't > > + be achieved due to crosstalk on IO lines). > > + When unspecified, the driver assumes the chip can run at > > + the max frequency defined in the spec (information > > + extracted chip detection time). > > +- spi-tx-bus-width: The bus width (number of data wires) that is used = for MOSI. > > + Only encodes the board constraints (i.e. when not all IO > > + signals are routed on the board). Device constraints are > > + extracted when detecting the chip, and controller > > + constraints are exposed by the SPI mem controller. If this > > + property is missing that means no constraint at the board > > + level. > > +- spi-rx-bus-width: The bus width (number of data wires) that is used = for MISO. > > + Only encodes the board constraints (i.e. when not all IO > > + signals are routed on the board). Device constraints are > > + extracted when detecting the chip, and controller > > + constraints are exposed by the SPI mem controller. If this > > + property is missing that means no constraint at the board > > + level. =20 >=20 > This section has been dropped from the Linux doc. Removed. Thanks, Miqu=C3=A8l