[U-Boot] sunxi: support multiple memory banks

[Siarhei Siamashka <siarhei.siamashka@gmail.com>]

On Wed, 18 Jul 2018 23:42:07 +0200
michael vogt <michu@neophob.com> wrote:

> Hi
> 
> I would like to support 4 memory chips for a sunxi board (a20). 
> 
> the current configuration in the sunxi-common.h looks like this:
> 
> #define CONFIG_NR_DRAM_BANKS		1
> #define PHYS_SDRAM_0			CONFIG_SYS_SDRAM_BASE
> #define PHYS_SDRAM_0_SIZE		0x80000000 /* 2 GiB */
> 
> which seems to match the memory map for the a20. 
> 
> Question:
> While addressing 2gb ram works using one dram bank - will it work if there are two dram banks needed?

These defines in U-Boot are not directly related to the DRAM
controller setup. They just allow to have multiple disconnected
DRAM areas in the physical address space, but on Allwinner
hardware the DRAM is typically (or even always?) represented
as a single contiguous chunk of memory in the address space.

Did you actually mean support for multiple ranks?
    https://en.wikipedia.org/wiki/Memory_rank

To the best of my knowledge the A20 SoC has one chip select
pin (SCS), so it might support more than one rank. That said,
I'm not aware of any existing A10 or A20 board with a
double rank DRAM configuration. And the DRAM init code in
U-Boot for the A10/A13/A20 SoCs does not support multiple
ranks at the moment (since it was not possible to test
such configuration on real hardware).

If somebody wants to use 2GB on an A20 board in a two ranks
configuration, then it's probably best to design such board
using the boot0 bootloader from the Allwinner's BSP for the
initial testing. And then after everything works correctly,
add the necessary changes to the DRAM init code in U-boot.
I could provide some help with getting this done.

-- 
Best regards,
Siarhei Siamashka