From: Tom Rini <trini@konsulko.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH] ARM: tegra: align carveout size
Date: Wed, 1 Aug 2018 19:46:32 -0400 [thread overview]
Message-ID: <20180801234632.GZ32145@bill-the-cat> (raw)
In-Reply-To: <763c36c7-dc06-81dc-59fa-093255e2f7de@wwwdotorg.org>
On Wed, Aug 01, 2018 at 05:26:10PM -0600, Stephen Warren wrote:
> On 07/31/2018 12:38 PM, Stephen Warren wrote:
> >From: Stephen Warren <swarren@nvidia.com>
> >
> >Align the size of the carveout region to 2M. This ensures that the size
> >can be accurately represented by an LPAE page table that uses sections.
> >
> >This solves a bug (hang at boot time soon after printing the DRAM size)
> >that only shows up when the following two commits are merged together:
> >d32e86bde8a3 ARM: HYP/non-sec: enable ARMV7_LPAE if HYP mode is supported
> >6e584e633d10 ARM: tegra: avoid using secure carveout RAM
> >
> >Cc: Mark Kettenis <kettenis@openbsd.org>
> >Cc: Alexander Graf <agraf@suse.de>
> >Signed-off-by: Stephen Warren <swarren@nvidia.com>
> >---
> >This should be applied quickly since it fixes a regression that causes
> >all boots to fail, which in turn causes test/py to reset and "reflash" the
> >target board for each test, which causes the test to take eons.
>
> Could we apply this please? My Jenkins system will love you because of it:-)
I'm looking for one more person to Ack this, thanks!
--
Tom
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next prev parent reply other threads:[~2018-08-01 23:46 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-31 18:38 [U-Boot] [PATCH] ARM: tegra: align carveout size Stephen Warren
2018-08-01 23:26 ` Stephen Warren
2018-08-01 23:46 ` Tom Rini [this message]
2018-08-01 23:52 ` Tom Warren
2018-08-02 0:06 ` Tom Rini
2018-08-02 17:03 ` Stephen Warren
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