* [U-Boot] [PATCH] ARM: tegra: align carveout size
@ 2018-07-31 18:38 Stephen Warren
2018-08-01 23:26 ` Stephen Warren
0 siblings, 1 reply; 6+ messages in thread
From: Stephen Warren @ 2018-07-31 18:38 UTC (permalink / raw)
To: u-boot
From: Stephen Warren <swarren@nvidia.com>
Align the size of the carveout region to 2M. This ensures that the size
can be accurately represented by an LPAE page table that uses sections.
This solves a bug (hang at boot time soon after printing the DRAM size)
that only shows up when the following two commits are merged together:
d32e86bde8a3 ARM: HYP/non-sec: enable ARMV7_LPAE if HYP mode is supported
6e584e633d10 ARM: tegra: avoid using secure carveout RAM
Cc: Mark Kettenis <kettenis@openbsd.org>
Cc: Alexander Graf <agraf@suse.de>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
This should be applied quickly since it fixes a regression that causes
all boots to fail, which in turn causes test/py to reset and "reflash" the
target board for each test, which causes the test to take eons.
arch/arm/mach-tegra/board2.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c
index 5ecadf705e7e..421a71b3014d 100644
--- a/arch/arm/mach-tegra/board2.c
+++ b/arch/arm/mach-tegra/board2.c
@@ -252,7 +252,7 @@ static ulong carveout_size(void)
#elif defined(CONFIG_ARMV7_SECURE_RESERVE_SIZE)
// BASE+SIZE might not == 4GB. If so, we want the carveout to cover
// from BASE to 4GB, not BASE to BASE+SIZE.
- return (0 - CONFIG_ARMV7_SECURE_BASE);
+ return (0 - CONFIG_ARMV7_SECURE_BASE) & ~(SZ_2M - 1);
#else
return 0;
#endif
--
2.18.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH] ARM: tegra: align carveout size
2018-07-31 18:38 [U-Boot] [PATCH] ARM: tegra: align carveout size Stephen Warren
@ 2018-08-01 23:26 ` Stephen Warren
2018-08-01 23:46 ` Tom Rini
0 siblings, 1 reply; 6+ messages in thread
From: Stephen Warren @ 2018-08-01 23:26 UTC (permalink / raw)
To: u-boot
On 07/31/2018 12:38 PM, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
>
> Align the size of the carveout region to 2M. This ensures that the size
> can be accurately represented by an LPAE page table that uses sections.
>
> This solves a bug (hang at boot time soon after printing the DRAM size)
> that only shows up when the following two commits are merged together:
> d32e86bde8a3 ARM: HYP/non-sec: enable ARMV7_LPAE if HYP mode is supported
> 6e584e633d10 ARM: tegra: avoid using secure carveout RAM
>
> Cc: Mark Kettenis <kettenis@openbsd.org>
> Cc: Alexander Graf <agraf@suse.de>
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
> ---
> This should be applied quickly since it fixes a regression that causes
> all boots to fail, which in turn causes test/py to reset and "reflash" the
> target board for each test, which causes the test to take eons.
Could we apply this please? My Jenkins system will love you because of it:-)
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH] ARM: tegra: align carveout size
2018-08-01 23:26 ` Stephen Warren
@ 2018-08-01 23:46 ` Tom Rini
2018-08-01 23:52 ` Tom Warren
0 siblings, 1 reply; 6+ messages in thread
From: Tom Rini @ 2018-08-01 23:46 UTC (permalink / raw)
To: u-boot
On Wed, Aug 01, 2018 at 05:26:10PM -0600, Stephen Warren wrote:
> On 07/31/2018 12:38 PM, Stephen Warren wrote:
> >From: Stephen Warren <swarren@nvidia.com>
> >
> >Align the size of the carveout region to 2M. This ensures that the size
> >can be accurately represented by an LPAE page table that uses sections.
> >
> >This solves a bug (hang at boot time soon after printing the DRAM size)
> >that only shows up when the following two commits are merged together:
> >d32e86bde8a3 ARM: HYP/non-sec: enable ARMV7_LPAE if HYP mode is supported
> >6e584e633d10 ARM: tegra: avoid using secure carveout RAM
> >
> >Cc: Mark Kettenis <kettenis@openbsd.org>
> >Cc: Alexander Graf <agraf@suse.de>
> >Signed-off-by: Stephen Warren <swarren@nvidia.com>
> >---
> >This should be applied quickly since it fixes a regression that causes
> >all boots to fail, which in turn causes test/py to reset and "reflash" the
> >target board for each test, which causes the test to take eons.
>
> Could we apply this please? My Jenkins system will love you because of it:-)
I'm looking for one more person to Ack this, thanks!
--
Tom
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* [U-Boot] [PATCH] ARM: tegra: align carveout size
2018-08-01 23:46 ` Tom Rini
@ 2018-08-01 23:52 ` Tom Warren
2018-08-02 0:06 ` Tom Rini
0 siblings, 1 reply; 6+ messages in thread
From: Tom Warren @ 2018-08-01 23:52 UTC (permalink / raw)
To: u-boot
I can add this to my PR list (but probably won't get one out until tomorrow morning), or:
Acked-by: Tom Warren <twarren@nvidia.com>
If that'll get it in sooner.
Tom
-----Original Message-----
From: Tom Rini <trini@konsulko.com>
Sent: Wednesday, August 1, 2018 4:47 PM
To: Stephen Warren <swarren@wwwdotorg.org>
Cc: Tom Warren <TWarren@nvidia.com>; u-boot at lists.denx.de; Simon Glass <sjg@chromium.org>; Stephen Warren <swarren@nvidia.com>; Mark Kettenis <kettenis@openbsd.org>; Alexander Graf <agraf@suse.de>
Subject: Re: [U-Boot] [PATCH] ARM: tegra: align carveout size
On Wed, Aug 01, 2018 at 05:26:10PM -0600, Stephen Warren wrote:
> On 07/31/2018 12:38 PM, Stephen Warren wrote:
> >From: Stephen Warren <swarren@nvidia.com>
> >
> >Align the size of the carveout region to 2M. This ensures that the
> >size can be accurately represented by an LPAE page table that uses sections.
> >
> >This solves a bug (hang at boot time soon after printing the DRAM
> >size) that only shows up when the following two commits are merged together:
> >d32e86bde8a3 ARM: HYP/non-sec: enable ARMV7_LPAE if HYP mode is
> >supported
> >6e584e633d10 ARM: tegra: avoid using secure carveout RAM
> >
> >Cc: Mark Kettenis <kettenis@openbsd.org>
> >Cc: Alexander Graf <agraf@suse.de>
> >Signed-off-by: Stephen Warren <swarren@nvidia.com>
> >---
> >This should be applied quickly since it fixes a regression that
> >causes all boots to fail, which in turn causes test/py to reset and
> >"reflash" the target board for each test, which causes the test to take eons.
>
> Could we apply this please? My Jenkins system will love you because of
> it:-)
I'm looking for one more person to Ack this, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH] ARM: tegra: align carveout size
2018-08-01 23:52 ` Tom Warren
@ 2018-08-02 0:06 ` Tom Rini
2018-08-02 17:03 ` Stephen Warren
0 siblings, 1 reply; 6+ messages in thread
From: Tom Rini @ 2018-08-02 0:06 UTC (permalink / raw)
To: u-boot
On Wed, Aug 01, 2018 at 11:52:36PM +0000, Tom Warren wrote:
> I can add this to my PR list (but probably won't get one out until tomorrow morning), or:
>
> Acked-by: Tom Warren <twarren@nvidia.com>
>
> If that'll get it in sooner.
Applied, thanks!
>
> Tom
>
> -----Original Message-----
> From: Tom Rini <trini@konsulko.com>
> Sent: Wednesday, August 1, 2018 4:47 PM
> To: Stephen Warren <swarren@wwwdotorg.org>
> Cc: Tom Warren <TWarren@nvidia.com>; u-boot at lists.denx.de; Simon Glass <sjg@chromium.org>; Stephen Warren <swarren@nvidia.com>; Mark Kettenis <kettenis@openbsd.org>; Alexander Graf <agraf@suse.de>
> Subject: Re: [U-Boot] [PATCH] ARM: tegra: align carveout size
>
> On Wed, Aug 01, 2018 at 05:26:10PM -0600, Stephen Warren wrote:
> > On 07/31/2018 12:38 PM, Stephen Warren wrote:
> > >From: Stephen Warren <swarren@nvidia.com>
> > >
> > >Align the size of the carveout region to 2M. This ensures that the
> > >size can be accurately represented by an LPAE page table that uses sections.
> > >
> > >This solves a bug (hang at boot time soon after printing the DRAM
> > >size) that only shows up when the following two commits are merged together:
> > >d32e86bde8a3 ARM: HYP/non-sec: enable ARMV7_LPAE if HYP mode is
> > >supported
> > >6e584e633d10 ARM: tegra: avoid using secure carveout RAM
> > >
> > >Cc: Mark Kettenis <kettenis@openbsd.org>
> > >Cc: Alexander Graf <agraf@suse.de>
> > >Signed-off-by: Stephen Warren <swarren@nvidia.com>
> > >---
> > >This should be applied quickly since it fixes a regression that
> > >causes all boots to fail, which in turn causes test/py to reset and
> > >"reflash" the target board for each test, which causes the test to take eons.
> >
> > Could we apply this please? My Jenkins system will love you because of
> > it:-)
>
> I'm looking for one more person to Ack this, thanks!
>
> --
> Tom
> -----------------------------------------------------------------------------------
> This email message is for the sole use of the intended recipient(s) and may contain
> confidential information. Any unauthorized review, use, disclosure or distribution
> is prohibited. If you are not the intended recipient, please contact the sender by
> reply email and destroy all copies of the original message.
> -----------------------------------------------------------------------------------
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot
--
Tom
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^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH] ARM: tegra: align carveout size
2018-08-02 0:06 ` Tom Rini
@ 2018-08-02 17:03 ` Stephen Warren
0 siblings, 0 replies; 6+ messages in thread
From: Stephen Warren @ 2018-08-02 17:03 UTC (permalink / raw)
To: u-boot
On 08/01/2018 06:06 PM, Tom Rini wrote:
> On Wed, Aug 01, 2018 at 11:52:36PM +0000, Tom Warren wrote:
>
>> I can add this to my PR list (but probably won't get one out until tomorrow morning), or:
>>
>> Acked-by: Tom Warren <twarren@nvidia.com>
>>
>> If that'll get it in sooner.
>
> Applied, thanks!
Thanks. The Jetson TK1 tests all look good again.
>>
>> Tom
>>
>> -----Original Message-----
>> From: Tom Rini <trini@konsulko.com>
>> Sent: Wednesday, August 1, 2018 4:47 PM
>> To: Stephen Warren <swarren@wwwdotorg.org>
>> Cc: Tom Warren <TWarren@nvidia.com>; u-boot at lists.denx.de; Simon Glass <sjg@chromium.org>; Stephen Warren <swarren@nvidia.com>; Mark Kettenis <kettenis@openbsd.org>; Alexander Graf <agraf@suse.de>
>> Subject: Re: [U-Boot] [PATCH] ARM: tegra: align carveout size
>>
>> On Wed, Aug 01, 2018 at 05:26:10PM -0600, Stephen Warren wrote:
>>> On 07/31/2018 12:38 PM, Stephen Warren wrote:
>>>> From: Stephen Warren <swarren@nvidia.com>
>>>>
>>>> Align the size of the carveout region to 2M. This ensures that the
>>>> size can be accurately represented by an LPAE page table that uses sections.
>>>>
>>>> This solves a bug (hang at boot time soon after printing the DRAM
>>>> size) that only shows up when the following two commits are merged together:
>>>> d32e86bde8a3 ARM: HYP/non-sec: enable ARMV7_LPAE if HYP mode is
>>>> supported
>>>> 6e584e633d10 ARM: tegra: avoid using secure carveout RAM
>>>>
>>>> Cc: Mark Kettenis <kettenis@openbsd.org>
>>>> Cc: Alexander Graf <agraf@suse.de>
>>>> Signed-off-by: Stephen Warren <swarren@nvidia.com>
>>>> ---
>>>> This should be applied quickly since it fixes a regression that
>>>> causes all boots to fail, which in turn causes test/py to reset and
>>>> "reflash" the target board for each test, which causes the test to take eons.
>>>
>>> Could we apply this please? My Jenkins system will love you because of
>>> it:-)
>>
>> I'm looking for one more person to Ack this, thanks!
>>
>> --
>> Tom
>> -----------------------------------------------------------------------------------
>> This email message is for the sole use of the intended recipient(s) and may contain
>> confidential information. Any unauthorized review, use, disclosure or distribution
>> is prohibited. If you are not the intended recipient, please contact the sender by
>> reply email and destroy all copies of the original message.
>> -----------------------------------------------------------------------------------
>> _______________________________________________
>> U-Boot mailing list
>> U-Boot at lists.denx.de
>> https://lists.denx.de/listinfo/u-boot
>
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2018-08-01 23:26 ` Stephen Warren
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2018-08-01 23:52 ` Tom Warren
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