From: Marek Vasut <marex@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH V2 2/3] ARM: socfpga: clk: Make L4SP and MMC clock calculation Gen5 only
Date: Thu, 9 Aug 2018 11:41:33 +0200 [thread overview]
Message-ID: <20180809094134.22566-2-marex@denx.de> (raw)
In-Reply-To: <20180809094134.22566-1-marex@denx.de>
The L4SP and MMC clock precalculation is specific to Gen5, it is not
needed on Arria10/Stratix10. Isolate it to Gen5 until there is a proper
clock driver for Gen5, at which point this will go away completely.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
---
arch/arm/mach-socfpga/clock_manager.c | 2 ++
1 file changed, 2 insertions(+)
---
V2: No change
diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c
index 59ede59b59..9f3c643df8 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -42,9 +42,11 @@ int cm_wait_for_fsm(void)
int set_cpu_clk_info(void)
{
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
/* Calculate the clock frequencies required for drivers */
cm_get_l4_sp_clk_hz();
cm_get_mmc_controller_clk_hz();
+#endif
gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 1000000;
gd->bd->bi_dsp_freq = 0;
--
2.16.2
next prev parent reply other threads:[~2018-08-09 9:41 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-09 9:41 [U-Boot] [PATCH V2 1/3] ARM: socfpga: clk: Obtain handoff base clock via DM Marek Vasut
2018-08-09 9:41 ` Marek Vasut [this message]
2018-08-09 9:41 ` [U-Boot] [PATCH V2 3/3] ARM: socfpga: clk: Drop unused variables on Arria10 Marek Vasut
2018-08-09 9:45 ` [U-Boot] [PATCH V2 1/3] ARM: socfpga: clk: Obtain handoff base clock via DM Ley Foon Tan
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