[U-Boot] [PATCH v2 37/53] clk: sunxi: Implement SPI clocks

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From: Jagan Teki <jagan@amarulasolutions.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v2 37/53] clk: sunxi: Implement SPI clocks
Date: Fri, 10 Aug 2018 11:36:55 +0530	[thread overview]
Message-ID: <20180810060711.6547-38-jagan@amarulasolutions.com> (raw)
In-Reply-To: <20180810060711.6547-1-jagan@amarulasolutions.com>

Implement SPI AHB and MOD clocks for all Allwinner SoC
clock drivers via clock map descriptor table.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/clk/sunxi/clk_a10.c  | 9 +++++++++
 drivers/clk/sunxi/clk_a10s.c | 7 +++++++
 drivers/clk/sunxi/clk_a31.c  | 9 +++++++++
 drivers/clk/sunxi/clk_a64.c  | 5 +++++
 drivers/clk/sunxi/clk_h3.c   | 5 +++++
 drivers/clk/sunxi/clk_v3s.c  | 3 +++
 6 files changed, 38 insertions(+)

diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c
index 55176bc174..ee499c402a 100644
--- a/drivers/clk/sunxi/clk_a10.c
+++ b/drivers/clk/sunxi/clk_a10.c
@@ -22,12 +22,21 @@ static struct ccu_clk_map a10_clks[] = {
 	[CLK_AHB_MMC1]		= { 0x060, BIT(9), NULL },
 	[CLK_AHB_MMC2]		= { 0x060, BIT(10), NULL },
 	[CLK_AHB_MMC3]		= { 0x060, BIT(11), NULL },
+	[CLK_AHB_SPI0]		= { 0x060, BIT(20), NULL },
+	[CLK_AHB_SPI1]		= { 0x060, BIT(21), NULL },
+	[CLK_AHB_SPI2]		= { 0x060, BIT(22), NULL },
+	[CLK_AHB_SPI3]		= { 0x060, BIT(23), NULL },
 
 	[CLK_MMC0]		= { 0x088, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC1]		= { 0x08c, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC3]		= { 0x094, BIT(31), &mmc_clk_set_rate },
 
+	[CLK_SPI0]		= { 0x0a0, BIT(31), NULL },
+	[CLK_SPI1]		= { 0x0a4, BIT(31), NULL },
+	[CLK_SPI2]		= { 0x0a8, BIT(31), NULL },
+	[CLK_SPI3]		= { 0x0d4, BIT(31), NULL },
+
 	[CLK_USB_OHCI0]		= { 0x0cc, BIT(6), NULL },
 	[CLK_USB_OHCI1]		= { 0x0cc, BIT(7), NULL },
 	[CLK_USB_PHY]		= { 0x0cc, BIT(8), NULL },
diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c
index fbac0ad751..bca248f59f 100644
--- a/drivers/clk/sunxi/clk_a10s.c
+++ b/drivers/clk/sunxi/clk_a10s.c
@@ -19,6 +19,9 @@ static struct ccu_clk_map a10s_clks[] = {
 	[CLK_AHB_MMC0]		= { 0x060, BIT(8), NULL },
 	[CLK_AHB_MMC1]		= { 0x060, BIT(9), NULL },
 	[CLK_AHB_MMC2]		= { 0x060, BIT(10), NULL },
+	[CLK_AHB_SPI0]		= { 0x060, BIT(20), NULL },
+	[CLK_AHB_SPI1]		= { 0x060, BIT(21), NULL },
+	[CLK_AHB_SPI2]		= { 0x060, BIT(22), NULL },
 
 #ifdef CONFIG_MMC
 	[CLK_MMC0]		= { 0x088, BIT(31), &mmc_clk_set_rate },
@@ -26,6 +29,10 @@ static struct ccu_clk_map a10s_clks[] = {
 	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },
 #endif
 
+	[CLK_SPI0]		= { 0x0a0, BIT(31), NULL },
+	[CLK_SPI1]		= { 0x0a4, BIT(31), NULL },
+	[CLK_SPI2]		= { 0x0a8, BIT(31), NULL },
+
 	[CLK_USB_OHCI]		= { 0x0cc, BIT(6), NULL },
 	[CLK_USB_PHY0]		= { 0x0cc, BIT(8), NULL },
 	[CLK_USB_PHY1]		= { 0x0cc, BIT(9), NULL },
diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c
index 15076d0e72..1fa77e1272 100644
--- a/drivers/clk/sunxi/clk_a31.c
+++ b/drivers/clk/sunxi/clk_a31.c
@@ -17,6 +17,10 @@ static struct ccu_clk_map a31_clks[] = {
 	[CLK_AHB1_MMC1]		= { 0x060, BIT(9), NULL },
 	[CLK_AHB1_MMC2]		= { 0x060, BIT(10), NULL },
 	[CLK_AHB1_MMC3]		= { 0x060, BIT(12), NULL },
+	[CLK_AHB1_SPI0]		= { 0x060, BIT(20), NULL },
+	[CLK_AHB1_SPI1]		= { 0x060, BIT(21), NULL },
+	[CLK_AHB1_SPI2]		= { 0x060, BIT(22), NULL },
+	[CLK_AHB1_SPI3]		= { 0x060, BIT(23), NULL },
 	[CLK_AHB1_OTG]		= { 0x060, BIT(24), NULL },
 	[CLK_AHB1_EHCI0]	= { 0x060, BIT(26), NULL },
 	[CLK_AHB1_EHCI1]	= { 0x060, BIT(27), NULL },
@@ -29,6 +33,11 @@ static struct ccu_clk_map a31_clks[] = {
 	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC3]		= { 0x094, BIT(31), &mmc_clk_set_rate },
 
+	[CLK_SPI0]		= { 0x0a0, BIT(31), NULL },
+	[CLK_SPI1]		= { 0x0a4, BIT(31), NULL },
+	[CLK_SPI2]		= { 0x0a8, BIT(31), NULL },
+	[CLK_SPI3]		= { 0x0ac, BIT(31), NULL },
+
 	[CLK_USB_PHY0]		= { 0x0cc, BIT(8), NULL },
 	[CLK_USB_PHY1]		= { 0x0cc, BIT(9), NULL },
 	[CLK_USB_PHY2]		= { 0x0cc, BIT(10), NULL },
diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c
index 9ef9b606d2..aa2e69d0a3 100644
--- a/drivers/clk/sunxi/clk_a64.c
+++ b/drivers/clk/sunxi/clk_a64.c
@@ -16,6 +16,8 @@ static struct ccu_clk_map a64_clks[] = {
 	[CLK_BUS_MMC0]		= { 0x060, BIT(8), NULL },
 	[CLK_BUS_MMC1]		= { 0x060, BIT(9), NULL },
 	[CLK_BUS_MMC2]		= { 0x060, BIT(10), NULL },
+	[CLK_BUS_SPI0]		= { 0x060, BIT(20), NULL },
+	[CLK_BUS_SPI1]		= { 0x060, BIT(21), NULL },
 	[CLK_BUS_OTG]		= { 0x060, BIT(23), NULL },
 	[CLK_BUS_EHCI0]		= { 0x060, BIT(24), NULL },
 	[CLK_BUS_EHCI1]		= { 0x060, BIT(25), NULL },
@@ -26,6 +28,9 @@ static struct ccu_clk_map a64_clks[] = {
 	[CLK_MMC1]		= { 0x08c, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },
 
+	[CLK_SPI0]		= { 0x0a0, BIT(31), NULL },
+	[CLK_SPI1]		= { 0x0a4, BIT(31), NULL },
+
 	[CLK_USB_PHY0]		= { 0x0cc, BIT(8), NULL },
 	[CLK_USB_PHY1]		= { 0x0cc, BIT(9), NULL },
 	[CLK_USB_HSIC]		= { 0x0cc, BIT(10), NULL },
diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c
index ad15aaae67..386289b654 100644
--- a/drivers/clk/sunxi/clk_h3.c
+++ b/drivers/clk/sunxi/clk_h3.c
@@ -16,6 +16,8 @@ static struct ccu_clk_map h3_clks[] = {
 	[CLK_BUS_MMC0]		= { 0x060, BIT(8), NULL },
 	[CLK_BUS_MMC1]		= { 0x060, BIT(9), NULL },
 	[CLK_BUS_MMC2]		= { 0x060, BIT(10), NULL },
+	[CLK_BUS_SPI0]		= { 0x060, BIT(20), NULL },
+	[CLK_BUS_SPI1]		= { 0x060, BIT(21), NULL },
 	[CLK_BUS_OTG]		= { 0x060, BIT(23), NULL },
 	[CLK_BUS_EHCI0]		= { 0x060, BIT(24), NULL },
 	[CLK_BUS_EHCI1]		= { 0x060, BIT(25), NULL },
@@ -30,6 +32,9 @@ static struct ccu_clk_map h3_clks[] = {
 	[CLK_MMC1]		= { 0x08c, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },
 
+	[CLK_SPI0]		= { 0x0a0, BIT(31), NULL },
+	[CLK_SPI1]		= { 0x0a4, BIT(31), NULL },
+
 	[CLK_USB_PHY0]		= { 0x0cc, BIT(8), NULL },
 	[CLK_USB_PHY1]		= { 0x0cc, BIT(9), NULL },
 	[CLK_USB_PHY2]		= { 0x0cc, BIT(10), NULL },
diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c
index 6eeec201a2..1cca57e065 100644
--- a/drivers/clk/sunxi/clk_v3s.c
+++ b/drivers/clk/sunxi/clk_v3s.c
@@ -16,12 +16,15 @@ static struct ccu_clk_map v3s_clks[] = {
 	[CLK_BUS_MMC0]		= { 0x060, BIT(8), NULL },
 	[CLK_BUS_MMC1]		= { 0x060, BIT(9), NULL },
 	[CLK_BUS_MMC2]		= { 0x060, BIT(10), NULL },
+	[CLK_BUS_SPI0]		= { 0x060, BIT(20), NULL },
 	[CLK_BUS_OTG]		= { 0x060, BIT(24), NULL },
 
 	[CLK_MMC0]		= { 0x088, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC1]		= { 0x08c, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },
 
+	[CLK_SPI0]		= { 0x0a0, BIT(31), NULL },
+
 	[CLK_USB_PHY0]          = { 0x0cc, BIT(8), NULL },
 };
 
-- 
2.18.0.321.gffc6fa0e3

next prev parent reply	other threads:[~2018-08-10  6:06 UTC|newest]

Thread overview: 56+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-08-10  6:06 [U-Boot] [PATCH v2 00/53] clk: Add Allwinner CLK, RESET support Jagan Teki
2018-08-10  6:06 ` [U-Boot] [PATCH v2 01/53] clk: Kconfig: Ascending order to sub directiory kconfigs Jagan Teki
2018-08-13 10:34   ` Jagan Teki
2018-08-10  6:06 ` [U-Boot] [PATCH v2 02/53] clk: Add Allwinner A64 CLK driver Jagan Teki
2018-08-10  6:06 ` [U-Boot] [PATCH v2 03/53] reset: Add default request ops Jagan Teki
2018-08-10  6:06 ` [U-Boot] [PATCH v2 04/53] reset: Add Allwinner RESET driver Jagan Teki
2018-08-10  6:06 ` [U-Boot] [PATCH v2 05/53] clk: sunxi: Add Allwinner H3/H5 CLK driver Jagan Teki
2018-08-10  6:06 ` [U-Boot] [PATCH v2 06/53] clk: sunxi: Add Allwinner A10/A20 " Jagan Teki
2018-08-10  6:06 ` [U-Boot] [PATCH v2 07/53] clk: sunxi: Add Allwinner A10s/A13 " Jagan Teki
2018-08-10  6:06 ` [U-Boot] [PATCH v2 08/53] clk: sunxi: Add Allwinner A31 " Jagan Teki
2018-08-10  6:06 ` [U-Boot] [PATCH v2 09/53] clk: sunxi: Add Allwinner A23 " Jagan Teki
2018-08-10  6:06 ` [U-Boot] [PATCH v2 10/53] clk: sunxi: a23: Add CLK support for A33 Jagan Teki
2018-08-10  6:06 ` [U-Boot] [PATCH v2 11/53] clk: sunxi: Add Allwinner A83T CLK driver Jagan Teki
2018-08-10  6:06 ` [U-Boot] [PATCH v2 12/53] clk: sunxi: Add Allwinner R40 " Jagan Teki
2018-08-10  6:06 ` [U-Boot] [PATCH v2 13/53] clk: sunxi: Add Allwinner V3S " Jagan Teki
2018-08-10  6:06 ` [U-Boot] [PATCH v2 14/53] sunxi: Enable CLK Jagan Teki
2018-08-10  6:06 ` [U-Boot] [PATCH v2 15/53] musb-new: sunxi: Use CLK and RESET support Jagan Teki
2018-08-10  6:06 ` [U-Boot] [PATCH v2 16/53] phy: sun4i-usb: " Jagan Teki
2018-08-10  6:06 ` [U-Boot] [PATCH v2 17/53] sunxi: usb: Switch to Generic host controllers Jagan Teki
2018-08-10  6:06 ` [U-Boot] [PATCH v2 18/53] usb: host: Drop [e-o]hci-sunxi drivers Jagan Teki
2018-08-10  6:06 ` [U-Boot] [PATCH v2 19/53] clk: sunxi: Implement AHB bus MMC clocks Jagan Teki
2018-08-10  6:06 ` [U-Boot] [PATCH v2 20/53] clk: sunxi: Implement direct " Jagan Teki
2018-08-10  6:06 ` [U-Boot] [PATCH v2 21/53] clk: sunxi: Implement AHB bus MMC resets Jagan Teki
2018-08-10  6:06 ` [U-Boot] [PATCH v2 22/53] reset: Add get reset by name optionally Jagan Teki
2018-08-10  6:06 ` [U-Boot] [PATCH v2 23/53] reset: Add reset valid Jagan Teki
2018-08-10  6:06 ` [U-Boot] [PATCH v2 24/53] dm: mmc: sunxi: Add CLK and RESET support Jagan Teki
2018-08-10  6:06 ` [U-Boot] [PATCH v2 25/53] fastboot: sunxi: Update fastboot mmc default device Jagan Teki
2018-08-10  6:06 ` [U-Boot] [PATCH v2 26/53] env: sunxi: Update default env fat device Jagan Teki
2018-08-10  6:06 ` [U-Boot] [PATCH v2 27/53] sunxi: Use mmc_bootdev=2 for MMC2 boot Jagan Teki
2018-08-10  6:06 ` [U-Boot] [PATCH v2 28/53] sunxi: A20: Enable DM_MMC Jagan Teki
2018-08-10  6:06 ` [U-Boot] [PATCH v2 29/53] mmc: sunxi: Add mmc, emmc H5/A64 compatible Jagan Teki
2018-08-10  6:06 ` [U-Boot] [PATCH v2 30/53] sunxi: H3_H5: Enable DM_MMC Jagan Teki
2018-08-10  6:06 ` [U-Boot] [PATCH v2 31/53] sunxi: A64: " Jagan Teki
2018-08-10  6:06 ` [U-Boot] [PATCH v2 32/53] mmc: sunxi: Add A83T emmc compatible Jagan Teki
2018-08-10  6:06 ` [U-Boot] [PATCH v2 33/53] sunxi: A83T: Enable DM_MMC Jagan Teki
2018-08-10  6:06 ` [U-Boot] [PATCH v2 34/53] sunxi: V40: " Jagan Teki
2018-08-10  6:06 ` [U-Boot] [PATCH v2 35/53] sunxi: A13/A31: " Jagan Teki
2018-08-10  6:06 ` [U-Boot] [PATCH v2 36/53] sunxi: A23/A33/V3S: " Jagan Teki
2018-08-10  6:06 ` Jagan Teki [this message]
2018-08-10  6:06 ` [U-Boot] [PATCH v2 38/53] clk: sunxi: Implement SPI resets Jagan Teki
2018-08-10  6:06 ` [U-Boot] [PATCH v2 39/53] spi: sun4i: Add CLK support Jagan Teki
2018-08-10  6:06 ` [U-Boot] [PATCH v2 40/53] spi: Add Allwinner A31 SPI driver Jagan Teki
2018-08-11  0:38   ` Fahad Sadah
2018-08-10  6:06 ` [U-Boot] [PATCH v2 41/53] clk: sunxi: Implement UART clocks Jagan Teki
2018-08-10  6:07 ` [U-Boot] [PATCH v2 42/53] clk: sunxi: Implement UART resets Jagan Teki
2018-08-10  6:07 ` [U-Boot] [PATCH v2 43/53] clk: sunxi: Implement Ethernet clocks Jagan Teki
2018-08-10  6:07 ` [U-Boot] [PATCH v2 44/53] clk: sunxi: Implement Ethernet resets Jagan Teki
2018-08-10  6:07 ` [U-Boot] [PATCH v2 45/53] net: sunxi_emac: Add CLK support Jagan Teki
2018-08-10  6:07 ` [U-Boot] [PATCH v2 46/53] net: sun8i_emac: Retrieve GMAC clock via 'syscon' phandle Jagan Teki
2018-08-10  6:07 ` [U-Boot] [PATCH v2 47/53] net: sun8i_emac: Add CLK and RESET support Jagan Teki
2018-08-10  6:07 ` [U-Boot] [PATCH v2 48/53] clk: Get the CLK by index without device Jagan Teki
2018-08-10  6:07 ` [U-Boot] [PATCH v2 49/53] clk: Use clk_get_by_index_tail() Jagan Teki
2018-08-10  6:07 ` [U-Boot] [PATCH v2 50/53] reset: Get the RESET by index without device Jagan Teki
2018-08-10  6:07 ` [U-Boot] [PATCH v2 51/53] clk: sunxi: h3: Implement EPHY CLK and RESET Jagan Teki
2018-08-10  6:07 ` [U-Boot] [PATCH v2 52/53] net: sun8i_emac: Add EPHY CLK and RESET support Jagan Teki
2018-08-10  6:07 ` [U-Boot] [PATCH v2 53/53] board: sunxi: gmac: Remove Ethernet clock and reset Jagan Teki

find likely ancestor, descendant, or conflicting patches for this message:
( dfblob:55176bc17 dfblob:ee499c402 dfblob:fbac0ad75 dfblob:bca248f59
dfblob:15076d0e7 dfblob:1fa77e127 dfblob:9ef9b606d dfblob:aa2e69d0a
dfblob:ad15aaae6 dfblob:386289b65 dfblob:6eeec201a dfblob:1cca57e06 )
 OR (
bs:"[U-Boot] [PATCH v2 37/53] clk: sunxi: Implement SPI clocks" )
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