From: Jagan Teki <jagan@amarulasolutions.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v2 41/53] clk: sunxi: Implement UART clocks
Date: Fri, 10 Aug 2018 11:36:59 +0530 [thread overview]
Message-ID: <20180810060711.6547-42-jagan@amarulasolutions.com> (raw)
In-Reply-To: <20180810060711.6547-1-jagan@amarulasolutions.com>
Implement UART clocks for all Allwinner SoC
clock drivers via clock map descriptor table.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
drivers/clk/sunxi/clk_a10.c | 9 +++++++++
drivers/clk/sunxi/clk_a10s.c | 5 +++++
drivers/clk/sunxi/clk_a23.c | 6 ++++++
drivers/clk/sunxi/clk_a31.c | 7 +++++++
drivers/clk/sunxi/clk_a64.c | 6 ++++++
drivers/clk/sunxi/clk_a83t.c | 6 ++++++
drivers/clk/sunxi/clk_h3.c | 5 +++++
drivers/clk/sunxi/clk_r40.c | 9 +++++++++
drivers/clk/sunxi/clk_v3s.c | 4 ++++
9 files changed, 57 insertions(+)
diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c
index ee499c402a..d145d37217 100644
--- a/drivers/clk/sunxi/clk_a10.c
+++ b/drivers/clk/sunxi/clk_a10.c
@@ -27,6 +27,15 @@ static struct ccu_clk_map a10_clks[] = {
[CLK_AHB_SPI2] = { 0x060, BIT(22), NULL },
[CLK_AHB_SPI3] = { 0x060, BIT(23), NULL },
+ [CLK_APB1_UART0] = { 0x06c, BIT(16), NULL },
+ [CLK_APB1_UART1] = { 0x06c, BIT(17), NULL },
+ [CLK_APB1_UART2] = { 0x06c, BIT(18), NULL },
+ [CLK_APB1_UART3] = { 0x06c, BIT(19), NULL },
+ [CLK_APB1_UART4] = { 0x06c, BIT(20), NULL },
+ [CLK_APB1_UART5] = { 0x06c, BIT(21), NULL },
+ [CLK_APB1_UART6] = { 0x06c, BIT(22), NULL },
+ [CLK_APB1_UART7] = { 0x06c, BIT(23), NULL },
+
[CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate },
[CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate },
[CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate },
diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c
index bca248f59f..5912043f19 100644
--- a/drivers/clk/sunxi/clk_a10s.c
+++ b/drivers/clk/sunxi/clk_a10s.c
@@ -23,6 +23,11 @@ static struct ccu_clk_map a10s_clks[] = {
[CLK_AHB_SPI1] = { 0x060, BIT(21), NULL },
[CLK_AHB_SPI2] = { 0x060, BIT(22), NULL },
+ [CLK_APB1_UART0] = { 0x06c, BIT(16), NULL },
+ [CLK_APB1_UART1] = { 0x06c, BIT(17), NULL },
+ [CLK_APB1_UART2] = { 0x06c, BIT(18), NULL },
+ [CLK_APB1_UART3] = { 0x06c, BIT(19), NULL },
+
#ifdef CONFIG_MMC
[CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate },
[CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate },
diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c
index 183c6275f3..331c79af81 100644
--- a/drivers/clk/sunxi/clk_a23.c
+++ b/drivers/clk/sunxi/clk_a23.c
@@ -20,6 +20,12 @@ static struct ccu_clk_map a23_clks[] = {
[CLK_BUS_EHCI] = { 0x060, BIT(26), NULL },
[CLK_BUS_OHCI] = { 0x060, BIT(29), NULL },
+ [CLK_BUS_UART0] = { 0x06c, BIT(16), NULL },
+ [CLK_BUS_UART1] = { 0x06c, BIT(17), NULL },
+ [CLK_BUS_UART2] = { 0x06c, BIT(18), NULL },
+ [CLK_BUS_UART3] = { 0x06c, BIT(19), NULL },
+ [CLK_BUS_UART4] = { 0x06c, BIT(20), NULL },
+
#ifdef CONFIG_MMC
[CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate },
[CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate },
diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c
index a5c6628c63..40803a1d64 100644
--- a/drivers/clk/sunxi/clk_a31.c
+++ b/drivers/clk/sunxi/clk_a31.c
@@ -28,6 +28,13 @@ static struct ccu_clk_map a31_clks[] = {
[CLK_AHB1_OHCI1] = { 0x060, BIT(30), NULL },
[CLK_AHB1_OHCI2] = { 0x060, BIT(31), NULL },
+ [CLK_APB2_UART0] = { 0x06c, BIT(16), NULL },
+ [CLK_APB2_UART1] = { 0x06c, BIT(17), NULL },
+ [CLK_APB2_UART2] = { 0x06c, BIT(18), NULL },
+ [CLK_APB2_UART3] = { 0x06c, BIT(19), NULL },
+ [CLK_APB2_UART4] = { 0x06c, BIT(20), NULL },
+ [CLK_APB2_UART5] = { 0x06c, BIT(21), NULL },
+
[CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate },
[CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate },
[CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate },
diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c
index 218d4f09ea..13b506f983 100644
--- a/drivers/clk/sunxi/clk_a64.c
+++ b/drivers/clk/sunxi/clk_a64.c
@@ -24,6 +24,12 @@ static struct ccu_clk_map a64_clks[] = {
[CLK_BUS_OHCI0] = { 0x060, BIT(28), NULL },
[CLK_BUS_OHCI1] = { 0x060, BIT(29), NULL },
+ [CLK_BUS_UART0] = { 0x06c, BIT(16), NULL },
+ [CLK_BUS_UART1] = { 0x06c, BIT(17), NULL },
+ [CLK_BUS_UART2] = { 0x06c, BIT(18), NULL },
+ [CLK_BUS_UART3] = { 0x06c, BIT(19), NULL },
+ [CLK_BUS_UART4] = { 0x06c, BIT(20), NULL },
+
[CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate },
[CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate },
[CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate },
diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c
index 47b7672e7f..5c1235fa7b 100644
--- a/drivers/clk/sunxi/clk_a83t.c
+++ b/drivers/clk/sunxi/clk_a83t.c
@@ -21,6 +21,12 @@ static struct ccu_clk_map a83t_clks[] = {
[CLK_BUS_EHCI1] = { 0x060, BIT(27), NULL },
[CLK_BUS_OHCI0] = { 0x060, BIT(29), NULL },
+ [CLK_BUS_UART0] = { 0x06c, BIT(16), NULL },
+ [CLK_BUS_UART1] = { 0x06c, BIT(17), NULL },
+ [CLK_BUS_UART2] = { 0x06c, BIT(18), NULL },
+ [CLK_BUS_UART3] = { 0x06c, BIT(19), NULL },
+ [CLK_BUS_UART4] = { 0x06c, BIT(20), NULL },
+
[CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate },
[CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate },
[CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate },
diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c
index f610cee745..b132ae0a0d 100644
--- a/drivers/clk/sunxi/clk_h3.c
+++ b/drivers/clk/sunxi/clk_h3.c
@@ -28,6 +28,11 @@ static struct ccu_clk_map h3_clks[] = {
[CLK_BUS_OHCI2] = { 0x060, BIT(30), NULL },
[CLK_BUS_OHCI3] = { 0x060, BIT(31), NULL },
+ [CLK_BUS_UART0] = { 0x06c, BIT(16), NULL },
+ [CLK_BUS_UART1] = { 0x06c, BIT(17), NULL },
+ [CLK_BUS_UART2] = { 0x06c, BIT(18), NULL },
+ [CLK_BUS_UART3] = { 0x06c, BIT(19), NULL },
+
[CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate },
[CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate },
[CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate },
diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c
index 24c26ad3be..1e5b1d10f7 100644
--- a/drivers/clk/sunxi/clk_r40.c
+++ b/drivers/clk/sunxi/clk_r40.c
@@ -25,6 +25,15 @@ static struct ccu_clk_map r40_clks[] = {
[CLK_BUS_OHCI1] = { 0x060, BIT(30), NULL },
[CLK_BUS_OHCI2] = { 0x060, BIT(31), NULL },
+ [CLK_BUS_UART0] = { 0x06c, BIT(16), NULL },
+ [CLK_BUS_UART1] = { 0x06c, BIT(17), NULL },
+ [CLK_BUS_UART2] = { 0x06c, BIT(18), NULL },
+ [CLK_BUS_UART3] = { 0x06c, BIT(19), NULL },
+ [CLK_BUS_UART4] = { 0x06c, BIT(20), NULL },
+ [CLK_BUS_UART5] = { 0x06c, BIT(21), NULL },
+ [CLK_BUS_UART6] = { 0x06c, BIT(22), NULL },
+ [CLK_BUS_UART7] = { 0x06c, BIT(23), NULL },
+
[CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate },
[CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate },
[CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate },
diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c
index ae4f6ee066..c6e57147ee 100644
--- a/drivers/clk/sunxi/clk_v3s.c
+++ b/drivers/clk/sunxi/clk_v3s.c
@@ -19,6 +19,10 @@ static struct ccu_clk_map v3s_clks[] = {
[CLK_BUS_SPI0] = { 0x060, BIT(20), NULL },
[CLK_BUS_OTG] = { 0x060, BIT(24), NULL },
+ [CLK_BUS_UART0] = { 0x06c, BIT(16), NULL },
+ [CLK_BUS_UART1] = { 0x06c, BIT(17), NULL },
+ [CLK_BUS_UART2] = { 0x06c, BIT(18), NULL },
+
[CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate },
[CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate },
[CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate },
--
2.18.0.321.gffc6fa0e3
next prev parent reply other threads:[~2018-08-10 6:06 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-10 6:06 [U-Boot] [PATCH v2 00/53] clk: Add Allwinner CLK, RESET support Jagan Teki
2018-08-10 6:06 ` [U-Boot] [PATCH v2 01/53] clk: Kconfig: Ascending order to sub directiory kconfigs Jagan Teki
2018-08-13 10:34 ` Jagan Teki
2018-08-10 6:06 ` [U-Boot] [PATCH v2 02/53] clk: Add Allwinner A64 CLK driver Jagan Teki
2018-08-10 6:06 ` [U-Boot] [PATCH v2 03/53] reset: Add default request ops Jagan Teki
2018-08-10 6:06 ` [U-Boot] [PATCH v2 04/53] reset: Add Allwinner RESET driver Jagan Teki
2018-08-10 6:06 ` [U-Boot] [PATCH v2 05/53] clk: sunxi: Add Allwinner H3/H5 CLK driver Jagan Teki
2018-08-10 6:06 ` [U-Boot] [PATCH v2 06/53] clk: sunxi: Add Allwinner A10/A20 " Jagan Teki
2018-08-10 6:06 ` [U-Boot] [PATCH v2 07/53] clk: sunxi: Add Allwinner A10s/A13 " Jagan Teki
2018-08-10 6:06 ` [U-Boot] [PATCH v2 08/53] clk: sunxi: Add Allwinner A31 " Jagan Teki
2018-08-10 6:06 ` [U-Boot] [PATCH v2 09/53] clk: sunxi: Add Allwinner A23 " Jagan Teki
2018-08-10 6:06 ` [U-Boot] [PATCH v2 10/53] clk: sunxi: a23: Add CLK support for A33 Jagan Teki
2018-08-10 6:06 ` [U-Boot] [PATCH v2 11/53] clk: sunxi: Add Allwinner A83T CLK driver Jagan Teki
2018-08-10 6:06 ` [U-Boot] [PATCH v2 12/53] clk: sunxi: Add Allwinner R40 " Jagan Teki
2018-08-10 6:06 ` [U-Boot] [PATCH v2 13/53] clk: sunxi: Add Allwinner V3S " Jagan Teki
2018-08-10 6:06 ` [U-Boot] [PATCH v2 14/53] sunxi: Enable CLK Jagan Teki
2018-08-10 6:06 ` [U-Boot] [PATCH v2 15/53] musb-new: sunxi: Use CLK and RESET support Jagan Teki
2018-08-10 6:06 ` [U-Boot] [PATCH v2 16/53] phy: sun4i-usb: " Jagan Teki
2018-08-10 6:06 ` [U-Boot] [PATCH v2 17/53] sunxi: usb: Switch to Generic host controllers Jagan Teki
2018-08-10 6:06 ` [U-Boot] [PATCH v2 18/53] usb: host: Drop [e-o]hci-sunxi drivers Jagan Teki
2018-08-10 6:06 ` [U-Boot] [PATCH v2 19/53] clk: sunxi: Implement AHB bus MMC clocks Jagan Teki
2018-08-10 6:06 ` [U-Boot] [PATCH v2 20/53] clk: sunxi: Implement direct " Jagan Teki
2018-08-10 6:06 ` [U-Boot] [PATCH v2 21/53] clk: sunxi: Implement AHB bus MMC resets Jagan Teki
2018-08-10 6:06 ` [U-Boot] [PATCH v2 22/53] reset: Add get reset by name optionally Jagan Teki
2018-08-10 6:06 ` [U-Boot] [PATCH v2 23/53] reset: Add reset valid Jagan Teki
2018-08-10 6:06 ` [U-Boot] [PATCH v2 24/53] dm: mmc: sunxi: Add CLK and RESET support Jagan Teki
2018-08-10 6:06 ` [U-Boot] [PATCH v2 25/53] fastboot: sunxi: Update fastboot mmc default device Jagan Teki
2018-08-10 6:06 ` [U-Boot] [PATCH v2 26/53] env: sunxi: Update default env fat device Jagan Teki
2018-08-10 6:06 ` [U-Boot] [PATCH v2 27/53] sunxi: Use mmc_bootdev=2 for MMC2 boot Jagan Teki
2018-08-10 6:06 ` [U-Boot] [PATCH v2 28/53] sunxi: A20: Enable DM_MMC Jagan Teki
2018-08-10 6:06 ` [U-Boot] [PATCH v2 29/53] mmc: sunxi: Add mmc, emmc H5/A64 compatible Jagan Teki
2018-08-10 6:06 ` [U-Boot] [PATCH v2 30/53] sunxi: H3_H5: Enable DM_MMC Jagan Teki
2018-08-10 6:06 ` [U-Boot] [PATCH v2 31/53] sunxi: A64: " Jagan Teki
2018-08-10 6:06 ` [U-Boot] [PATCH v2 32/53] mmc: sunxi: Add A83T emmc compatible Jagan Teki
2018-08-10 6:06 ` [U-Boot] [PATCH v2 33/53] sunxi: A83T: Enable DM_MMC Jagan Teki
2018-08-10 6:06 ` [U-Boot] [PATCH v2 34/53] sunxi: V40: " Jagan Teki
2018-08-10 6:06 ` [U-Boot] [PATCH v2 35/53] sunxi: A13/A31: " Jagan Teki
2018-08-10 6:06 ` [U-Boot] [PATCH v2 36/53] sunxi: A23/A33/V3S: " Jagan Teki
2018-08-10 6:06 ` [U-Boot] [PATCH v2 37/53] clk: sunxi: Implement SPI clocks Jagan Teki
2018-08-10 6:06 ` [U-Boot] [PATCH v2 38/53] clk: sunxi: Implement SPI resets Jagan Teki
2018-08-10 6:06 ` [U-Boot] [PATCH v2 39/53] spi: sun4i: Add CLK support Jagan Teki
2018-08-10 6:06 ` [U-Boot] [PATCH v2 40/53] spi: Add Allwinner A31 SPI driver Jagan Teki
2018-08-11 0:38 ` Fahad Sadah
2018-08-10 6:06 ` Jagan Teki [this message]
2018-08-10 6:07 ` [U-Boot] [PATCH v2 42/53] clk: sunxi: Implement UART resets Jagan Teki
2018-08-10 6:07 ` [U-Boot] [PATCH v2 43/53] clk: sunxi: Implement Ethernet clocks Jagan Teki
2018-08-10 6:07 ` [U-Boot] [PATCH v2 44/53] clk: sunxi: Implement Ethernet resets Jagan Teki
2018-08-10 6:07 ` [U-Boot] [PATCH v2 45/53] net: sunxi_emac: Add CLK support Jagan Teki
2018-08-10 6:07 ` [U-Boot] [PATCH v2 46/53] net: sun8i_emac: Retrieve GMAC clock via 'syscon' phandle Jagan Teki
2018-08-10 6:07 ` [U-Boot] [PATCH v2 47/53] net: sun8i_emac: Add CLK and RESET support Jagan Teki
2018-08-10 6:07 ` [U-Boot] [PATCH v2 48/53] clk: Get the CLK by index without device Jagan Teki
2018-08-10 6:07 ` [U-Boot] [PATCH v2 49/53] clk: Use clk_get_by_index_tail() Jagan Teki
2018-08-10 6:07 ` [U-Boot] [PATCH v2 50/53] reset: Get the RESET by index without device Jagan Teki
2018-08-10 6:07 ` [U-Boot] [PATCH v2 51/53] clk: sunxi: h3: Implement EPHY CLK and RESET Jagan Teki
2018-08-10 6:07 ` [U-Boot] [PATCH v2 52/53] net: sun8i_emac: Add EPHY CLK and RESET support Jagan Teki
2018-08-10 6:07 ` [U-Boot] [PATCH v2 53/53] board: sunxi: gmac: Remove Ethernet clock and reset Jagan Teki
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