From: Lokesh Vutla <lokeshvutla@ti.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 4/6] arm64: dts: k3: Add Support for AM654 SoC
Date: Tue, 21 Aug 2018 20:03:14 +0530 [thread overview]
Message-ID: <20180821143316.29329-5-lokeshvutla@ti.com> (raw)
In-Reply-To: <20180821143316.29329-1-lokeshvutla@ti.com>
Add initial DT support for AM654 EVM that runs on A53.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
- Fetched from Linux next that are in queue for 4.19-rc1
arch/arm/dts/Makefile | 2 +
arch/arm/dts/k3-am65-main.dtsi | 31 ++++++++
arch/arm/dts/k3-am65.dtsi | 87 ++++++++++++++++++++
arch/arm/dts/k3-am654-base-board.dts | 36 +++++++++
arch/arm/dts/k3-am654.dtsi | 115 +++++++++++++++++++++++++++
board/ti/am65x/evm.c | 12 +++
6 files changed, 283 insertions(+)
create mode 100644 arch/arm/dts/k3-am65-main.dtsi
create mode 100644 arch/arm/dts/k3-am65.dtsi
create mode 100644 arch/arm/dts/k3-am654-base-board.dts
create mode 100644 arch/arm/dts/k3-am654.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ebfa227262..150e1d4090 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -549,6 +549,8 @@ dtb-$(CONFIG_TARGET_STM32MP1) += \
stm32mp157c-ed1.dtb \
stm32mp157c-ev1.dtb
+dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb
+
targets += $(dtb-y)
# Add any required device tree compiler flags here
diff --git a/arch/arm/dts/k3-am65-main.dtsi b/arch/arm/dts/k3-am65-main.dtsi
new file mode 100644
index 0000000000..2409344df4
--- /dev/null
+++ b/arch/arm/dts/k3-am65-main.dtsi
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for AM6 SoC Family Main Domain peripherals
+ *
+ * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+&cbass_main {
+ gic500: interrupt-controller at 1800000 {
+ compatible = "arm,gic-v3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x01800000 0x10000>, /* GICD */
+ <0x01880000 0x90000>; /* GICR */
+ /*
+ * vcpumntirq:
+ * virtual CPU interface maintenance interrupt
+ */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ gic_its: gic-its at 18200000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x01820000 0x10000>;
+ msi-controller;
+ #msi-cells = <1>;
+ };
+ };
+};
diff --git a/arch/arm/dts/k3-am65.dtsi b/arch/arm/dts/k3-am65.dtsi
new file mode 100644
index 0000000000..cede1fa098
--- /dev/null
+++ b/arch/arm/dts/k3-am65.dtsi
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for AM6 SoC Family
+ *
+ * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ model = "Texas Instruments K3 AM654 SoC";
+ compatible = "ti,am654";
+ interrupt-parent = <&gic500>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ chosen { };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+
+ psci: psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+ };
+
+ a53_timer0: timer-cl0-cpu0 {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
+ };
+
+ pmu: pmu {
+ compatible = "arm,armv8-pmuv3";
+ /* Recommendation from GIC500 TRM Table A.3 */
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ cbass_main: interconnect at 100000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00100000 0x00 0x00100000 0x00020000>, /* ctrl mmr */
+ <0x00600000 0x00 0x00600000 0x00001100>, /* GPIO */
+ <0x00900000 0x00 0x00900000 0x00012000>, /* serdes */
+ <0x01000000 0x00 0x01000000 0x0af02400>, /* Most peripherals */
+ <0x30800000 0x00 0x30800000 0x0bc00000>, /* MAIN NAVSS */
+ /* MCUSS Range */
+ <0x28380000 0x00 0x28380000 0x03880000>,
+ <0x40200000 0x00 0x40200000 0x00900100>,
+ <0x42040000 0x00 0x42040000 0x03ac2400>,
+ <0x45100000 0x00 0x45100000 0x00c24000>,
+ <0x46000000 0x00 0x46000000 0x00200000>,
+ <0x47000000 0x00 0x47000000 0x00068400>;
+
+ cbass_mcu: interconnect at 28380000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x28380000 0x28380000 0x03880000>, /* MCU NAVSS*/
+ <0x40200000 0x40200000 0x00900100>, /* First peripheral window */
+ <0x42040000 0x42040000 0x03ac2400>, /* WKUP */
+ <0x45100000 0x45100000 0x00c24000>, /* MMRs, remaining NAVSS */
+ <0x46000000 0x46000000 0x00200000>, /* CPSW */
+ <0x47000000 0x47000000 0x00068400>; /* OSPI space 1 */
+
+ cbass_wakeup: interconnect at 42040000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ /* WKUP Basic peripherals */
+ ranges = <0x42040000 0x42040000 0x03ac2400>;
+ };
+ };
+ };
+};
+
+/* Now include the peripherals for each bus segments */
+#include "k3-am65-main.dtsi"
diff --git a/arch/arm/dts/k3-am654-base-board.dts b/arch/arm/dts/k3-am654-base-board.dts
new file mode 100644
index 0000000000..af6956fdc1
--- /dev/null
+++ b/arch/arm/dts/k3-am654-base-board.dts
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include "k3-am654.dtsi"
+
+/ {
+ compatible = "ti,am654-evm", "ti,am654";
+ model = "Texas Instruments AM654 Base Board";
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ bootargs = "earlycon=ns16550a,mmio32,0x02800000";
+ };
+
+ memory at 80000000 {
+ device_type = "memory";
+ /* 4G RAM */
+ reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
+ <0x00000008 0x80000000 0x00000000 0x80000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ secure_ddr: secure_ddr at 9e800000 {
+ reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */
+ alignment = <0x1000>;
+ no-map;
+ };
+ };
+};
diff --git a/arch/arm/dts/k3-am654.dtsi b/arch/arm/dts/k3-am654.dtsi
new file mode 100644
index 0000000000..2affa6f661
--- /dev/null
+++ b/arch/arm/dts/k3-am654.dtsi
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for AM6 SoC family in Quad core configuration
+ *
+ * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#include "k3-am65.dtsi"
+
+/ {
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu-map {
+ cluster0: cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+
+ core1 {
+ cpu = <&cpu1>;
+ };
+ };
+
+ cluster1: cluster1 {
+ core0 {
+ cpu = <&cpu2>;
+ };
+
+ core1 {
+ cpu = <&cpu3>;
+ };
+ };
+ };
+
+ cpu0: cpu at 0 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x000>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&L2_0>;
+ };
+
+ cpu1: cpu at 1 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x001>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&L2_0>;
+ };
+
+ cpu2: cpu at 100 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x100>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&L2_1>;
+ };
+
+ cpu3: cpu at 101 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x101>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&L2_1>;
+ };
+ };
+
+ L2_0: l2-cache0 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <0x80000>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ next-level-cache = <&msmc_l3>;
+ };
+
+ L2_1: l2-cache1 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <0x80000>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ next-level-cache = <&msmc_l3>;
+ };
+
+ msmc_l3: l3-cache0 {
+ compatible = "cache";
+ cache-level = <3>;
+ };
+};
diff --git a/board/ti/am65x/evm.c b/board/ti/am65x/evm.c
index db2c90e948..747cd58958 100644
--- a/board/ti/am65x/evm.c
+++ b/board/ti/am65x/evm.c
@@ -54,3 +54,15 @@ int dram_init_banksize(void)
return 0;
}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+#ifdef CONFIG_TARGET_AM654_A53_EVM
+ if (!strcmp(name, "k3-am654-base-board"))
+ return 0;
+#endif
+
+ return -1;
+}
+#endif
--
2.18.0
next prev parent reply other threads:[~2018-08-21 14:33 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-21 14:33 [U-Boot] [PATCH 0/6] [3/3] Initial support Texas Instrument's AM654 Platform Lokesh Vutla
2018-08-21 14:33 ` [U-Boot] [PATCH 1/6] board: ti: am654: a53: Add initial support for am654 Lokesh Vutla
2018-08-24 14:13 ` Tom Rini
2018-08-21 14:33 ` [U-Boot] [PATCH 2/6] board: ti: am65x: Add README Lokesh Vutla
2018-08-24 14:13 ` Tom Rini
2018-08-21 14:33 ` [U-Boot] [PATCH 3/6] include: am654_evm: Establish initial environment for SD card boot Lokesh Vutla
2018-08-24 14:13 ` Tom Rini
2018-08-21 14:33 ` Lokesh Vutla [this message]
2018-08-24 14:13 ` [U-Boot] [PATCH 4/6] arm64: dts: k3: Add Support for AM654 SoC Tom Rini
2018-08-21 14:33 ` [U-Boot] [PATCH 5/6] arm64: dts: k3: Add u-boot specific nodes Lokesh Vutla
2018-08-24 14:13 ` Tom Rini
2018-08-21 14:33 ` [U-Boot] [PATCH 6/6] configs: am65x_evm_a53: Add initial support Lokesh Vutla
2018-08-24 14:13 ` Tom Rini
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