From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dalon Westergreen Date: Mon, 10 Sep 2018 10:28:48 -0700 Subject: [U-Boot] [PATCH 2/3] arm: socfpga: stratix10: add CONFIG_SPL_TARGET In-Reply-To: <20180910172849.16420-1-dwesterg@gmail.com> References: <20180910172849.16420-1-dwesterg@gmail.com> Message-ID: <20180910172849.16420-3-dwesterg@gmail.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Stratix10 combines the u-boot-spl image into the fpga configuration bitstream so that the SDM can load the processors memory. This process requires a hex format of the u-boot-spl image. CONFIG_SPL_TARGET is set to "spl/u-boot-spl.hex" Signed-off-by: Dalon Westergreen --- include/configs/socfpga_stratix10_socdk.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/socfpga_stratix10_socdk.h b/include/configs/socfpga_stratix10_socdk.h index b58f478004..91315a0031 100644 --- a/include/configs/socfpga_stratix10_socdk.h +++ b/include/configs/socfpga_stratix10_socdk.h @@ -202,6 +202,7 @@ unsigned int cm_get_l4_sys_free_clk_hz(void); * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB) * */ +#define CONFIG_SPL_TARGET "spl/u-boot-spl.hex" #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR -- 2.17.1