[U-Boot] [PATCH V4 32/32] imx: add i.MX8QXP MEK board support

["Lothar Waßmann" <LW@KARO-electronics.de>]

Hi,

On Wed,  5 Sep 2018 10:12:19 +0800 Peng Fan wrote:
> Add i.MX8QXP MEK board support
> Enabled pinctrl/clk/power domain/mmc/i2c driver.
> Added README file.
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> Cc: Stefano Babic <sbabic@denx.de>
> Cc: Fabio Estevam <fabio.estevam@nxp.com>
> Cc: Anatolij Gustschin <agust@denx.de>
> ---
>  arch/arm/dts/Makefile                     |   2 +
>  arch/arm/dts/fsl-imx8qxp-mek.dts          | 136 ++++++++++++++++++++++++++
>  arch/arm/mach-imx/imx8/Kconfig            |  13 +++
>  board/freescale/imx8qxp_mek/Kconfig       |  14 +++
>  board/freescale/imx8qxp_mek/MAINTAINERS   |   6 ++
>  board/freescale/imx8qxp_mek/Makefile      |   7 ++
>  board/freescale/imx8qxp_mek/README        |  72 ++++++++++++++
>  board/freescale/imx8qxp_mek/imx8qxp_mek.c | 152 +++++++++++++++++++++++++++++
>  board/freescale/mx8mq_evk/README          |  81 ++++++++++++++++
>  configs/imx8qxp_mek_defconfig             |  38 ++++++++
>  include/configs/imx8qxp_mek.h             | 156 ++++++++++++++++++++++++++++++
>  11 files changed, 677 insertions(+)
>  create mode 100644 arch/arm/dts/fsl-imx8qxp-mek.dts
>  create mode 100644 board/freescale/imx8qxp_mek/Kconfig
>  create mode 100644 board/freescale/imx8qxp_mek/MAINTAINERS
>  create mode 100644 board/freescale/imx8qxp_mek/Makefile
>  create mode 100644 board/freescale/imx8qxp_mek/README
>  create mode 100644 board/freescale/imx8qxp_mek/imx8qxp_mek.c
>  create mode 100644 board/freescale/mx8mq_evk/README
>  create mode 100644 configs/imx8qxp_mek_defconfig
>  create mode 100644 include/configs/imx8qxp_mek.h
> 
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index ebfa227262..8df85f3987 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -449,6 +449,8 @@ dtb-$(CONFIG_MX7) += imx7-colibri.dtb \
>  
>  dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
>  
> +dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qxp-mek.dtb
> +
>  dtb-$(CONFIG_RCAR_GEN3) += \
>  	r8a7795-h3ulcb.dtb \
>  	r8a7795-salvator-x.dtb \
> diff --git a/arch/arm/dts/fsl-imx8qxp-mek.dts b/arch/arm/dts/fsl-imx8qxp-mek.dts
> new file mode 100644
> index 0000000000..5443ef7e4e
> --- /dev/null
> +++ b/arch/arm/dts/fsl-imx8qxp-mek.dts
> @@ -0,0 +1,136 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2017-2018 NXP
> + */
> +
> +/dts-v1/;
> +
> +#include "fsl-imx8qxp.dtsi"
> +
> +/ {
> +	model = "Freescale i.MX8QXP MEK";
> +	compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp";
> +
> +	chosen {
> +		bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200";
> +		stdout-path = &lpuart0;
> +	};
> +
> +	regulators {
> +		compatible = "simple-bus";
> +
> +		reg_usdhc2_vmmc: usdhc2_vmmc {
>
Node names should have '-' rather than '_'.

> +			compatible = "regulator-fixed";
> +			regulator-name = "SD1_SPWR";
> +			regulator-min-microvolt = <3000000>;
> +			regulator-max-microvolt = <3000000>;
> +			gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>;
> +			off-on-delay = <3480>;
> +			enable-active-high;
> +		};
>
regulators should not have a 'simple-bus' container.

When keeping the simple-bus container the individual regulator nodes
require node addresses and 'reg' properties, and the enclosing
simple-bus container requires #address-cells and #size-cells properties.

> +
> +&iomuxc {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_hog>;
> +
> +	imx8qxp-mek {
> +		pinctrl_hog: hoggrp {
> +			fsl,pins = <
> +				SC_P_MCLK_OUT0_ADMA_ACM_MCLK_OUT0	0x0600004c
> +				SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD	0x000514a0
> +			>;
> +		};
> +
> +		pinctrl_ioexp_rst: ioexp_rst_grp {
>
Node names should have '-' rather than '_'.

> +			fsl,pins = <
> +				SC_P_SPI2_SDO_LSIO_GPIO1_IO01	0x06000021
> +			>;
> +		};
> +
> +		pinctrl_lpi2c1: lpi1cgrp {
> +			fsl,pins = <
> +				SC_P_USB_SS3_TC1_ADMA_I2C1_SCL	0x06000021
> +				SC_P_USB_SS3_TC3_ADMA_I2C1_SDA	0x06000021
> +			>;
> +		};
> +
> +		pinctrl_lpuart0: lpuart0grp {
> +			fsl,pins = <
> +				SC_P_UART0_RX_ADMA_UART0_RX	0x06000020
> +				SC_P_UART0_TX_ADMA_UART0_TX	0x06000020
> +			>;
> +		};
> +
> +		pinctrl_usdhc1: usdhc1grp {
> +			fsl,pins = <
> +				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
> +				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021
> +				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
> +				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
> +				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
> +				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
> +				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
> +				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
> +				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
> +				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
> +				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041
> +			>;
> +		};
> +
> +		pinctrl_usdhc2_gpio: usdhc2gpiogrp {
> +			fsl,pins = <
> +				SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19	0x00000021
> +				SC_P_USDHC1_WP_LSIO_GPIO4_IO21		0x00000021
> +				SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22	0x00000021
> +			>;
> +		};
> +
> +		pinctrl_usdhc2: usdhc2grp {
> +			fsl,pins = <
> +				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041
> +				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000021
> +				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000021
> +				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000021
> +				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000021
> +				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000021
> +				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000021
> +			>;
> +		};
> +	};
> +};
> +
> +&lpuart0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_lpuart0>;
> +	status = "okay";
> +};
> +
> +&i2c1 {
> +	#address-cells = <1>;
> +	#size-cells = <0>;
>
These should be defined in the dtsi file where the i2c1 node is defined,
rather than having each user define those properties.



Lothar Waßmann