[U-Boot] (no subject)

[U-Boot] (no subject)

[Angelo Dureghello]

This patch adds an initial fdt support to the m68k architecture.

It has been tested on stmark2 board, with a devicetree and
CONFIG_DM_SERIAL=y + CONFIG_DM_SPI=y.

----- test log -----

U-Boot 2018.09-00137-g1be43784f1 (Sep 20 2018 - 22:34:42 +0200)

CPU:   Freescale MCF54415 (Mask:a0 Version:2)
       CPU CLK 240 MHz BUS CLK 120 MHz FLB CLK 60 MHz
       INP CLK 30 MHz VCO CLK 480 MHz
SPI:   ready
DRAM:  128 MiB
Loading Environment from SPI Flash... SF: Detected is25lp128 with page size 256 Bytes, erase size 64 KiB, total 16 MiB
*** Warning - bad CRC, using default environment

In:    uart at fc060000
Out:   uart at fc060000
Err:   uart at fc060000
Hit any key to stop autoboot:  0 
SF: Detected is25lp128 with page size 256 Bytes, erase size 64 KiB, total 16 MiB
device 0 offset 0x100000, size 0x700000
SF: 7340032 bytes @ 0x100000 Read: OK
## Booting kernel from Legacy Image at 40001000 ...
   Image Name:   mainline kernel
   Created:      2018-09-14  19:06:13 UTC
   Image Type:   M68K Linux Kernel Image (uncompressed)
   Data Size:    2184848 Bytes = 2.1 MiB
   Load Address: 40001000
   Entry Point:  40001000
   Verifying Checksum ... OK
   Loading Kernel Image ... OK

[U-Boot] [PATCH 1/7] m68k: add basic set of devicetrees

[Angelo Dureghello]

This patch adds a basic group of devicetrees, one for each
cpu, including actually just uart and dspi devices, since
these are the drivers supporting devicetree (support added
in this patch).

Signed-off-by: Angelo Dureghello <angelo@sysam.it>
---
 arch/m68k/dts/mcf5208.dtsi                    | 36 ++++++++
 arch/m68k/dts/mcf5227x.dtsi                   | 48 ++++++++++
 arch/m68k/dts/mcf523x.dtsi                    | 44 ++++++++++
 arch/m68k/dts/mcf5249.dtsi                    | 38 ++++++++
 arch/m68k/dts/mcf5253.dtsi                    | 44 ++++++++++
 arch/m68k/dts/mcf5271.dtsi                    | 44 ++++++++++
 arch/m68k/dts/mcf5272.dtsi                    | 38 ++++++++
 arch/m68k/dts/mcf5275.dtsi                    | 44 ++++++++++
 arch/m68k/dts/mcf5282.dtsi                    | 44 ++++++++++
 arch/m68k/dts/mcf5301x.dtsi                   | 48 ++++++++++
 arch/m68k/dts/mcf5307.dtsi                    | 39 +++++++++
 arch/m68k/dts/mcf5329.dtsi                    | 36 ++++++++
 arch/m68k/dts/mcf5441x.dtsi                   | 87 +++++++++++++++++++
 arch/m68k/dts/mcf5445x.dtsi                   | 48 ++++++++++
 doc/device-tree-bindings/serial/mcf-uart.txt  | 19 ++++
 doc/device-tree-bindings/spi/spi-mcf-dspi.txt | 22 +++++
 16 files changed, 679 insertions(+)
 create mode 100644 arch/m68k/dts/mcf5208.dtsi
 create mode 100644 arch/m68k/dts/mcf5227x.dtsi
 create mode 100644 arch/m68k/dts/mcf523x.dtsi
 create mode 100644 arch/m68k/dts/mcf5249.dtsi
 create mode 100644 arch/m68k/dts/mcf5253.dtsi
 create mode 100644 arch/m68k/dts/mcf5271.dtsi
 create mode 100644 arch/m68k/dts/mcf5272.dtsi
 create mode 100644 arch/m68k/dts/mcf5275.dtsi
 create mode 100644 arch/m68k/dts/mcf5282.dtsi
 create mode 100644 arch/m68k/dts/mcf5301x.dtsi
 create mode 100644 arch/m68k/dts/mcf5307.dtsi
 create mode 100644 arch/m68k/dts/mcf5329.dtsi
 create mode 100644 arch/m68k/dts/mcf5441x.dtsi
 create mode 100644 arch/m68k/dts/mcf5445x.dtsi
 create mode 100644 doc/device-tree-bindings/serial/mcf-uart.txt
 create mode 100644 doc/device-tree-bindings/spi/spi-mcf-dspi.txt

diff --git a/arch/m68k/dts/mcf5208.dtsi b/arch/m68k/dts/mcf5208.dtsi
new file mode 100644
index 0000000000..558d8bf41a
--- /dev/null
+++ b/arch/m68k/dts/mcf5208.dtsi
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+	compatible = "fsl,mcf5208";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		uart0: uart at fc060000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc060000 0x40>;
+			status = "disabled";
+		};
+
+		uart1: uart at fc064000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc064000 0x40>;
+			status = "disabled";
+		};
+
+		uart2: uart at fc068000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc068000 0x40>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/m68k/dts/mcf5227x.dtsi b/arch/m68k/dts/mcf5227x.dtsi
new file mode 100644
index 0000000000..8c95edddb6
--- /dev/null
+++ b/arch/m68k/dts/mcf5227x.dtsi
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+	compatible = "fsl,mcf5227x";
+
+	aliases {
+		serial0 = &uart0;
+		spi0 = &dspi0;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		uart0: uart at fc060000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc060000 0x40>;
+			status = "disabled";
+		};
+
+		uart1: uart at fc064000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc064000 0x40>;
+			status = "disabled";
+		};
+
+		uart2: uart at fc068000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc068000 0x40>;
+			status = "disabled";
+		};
+
+		dspi0: dspi at fc05c000 {
+			compatible = "fsl,mcf-dspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xfc05c000 0x100>;
+			spi-max-frequency = <50000000>;
+			num-cs = <4>;
+			spi-mode = <0>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/m68k/dts/mcf523x.dtsi b/arch/m68k/dts/mcf523x.dtsi
new file mode 100644
index 0000000000..9e79d472ec
--- /dev/null
+++ b/arch/m68k/dts/mcf523x.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+	compatible = "fsl,mcf523x";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		ipsbar: ipsbar at 4000000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x00000000 0x40000000 0x40000000>;
+			reg = <0x40000000 0x40000000>;
+
+			uart0: uart at 200 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x200 0x40>;
+				status = "disabled";
+			};
+
+			uart1: uart at 240 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x240 0x40>;
+				status = "disabled";
+			};
+
+			uart2: uart at 280 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x280 0x40>;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/arch/m68k/dts/mcf5249.dtsi b/arch/m68k/dts/mcf5249.dtsi
new file mode 100644
index 0000000000..248b3dc68b
--- /dev/null
+++ b/arch/m68k/dts/mcf5249.dtsi
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+	compatible = "fsl,mcf5249";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		mbar: mbar at 10000000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x00000000 0x10000000 0x10000>;
+			reg = <0x10000000 0x10000>;
+
+			uart0: uart at 1c0 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x1c0 0x40>;
+				status = "disabled";
+			};
+
+			uart1: uart at 200 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x200 0x40>;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/arch/m68k/dts/mcf5253.dtsi b/arch/m68k/dts/mcf5253.dtsi
new file mode 100644
index 0000000000..3bde2d6202
--- /dev/null
+++ b/arch/m68k/dts/mcf5253.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+	compatible = "fsl,mcf5253";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		mbar: mbar at 10000000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x00000000 0x10000000 0x10000>;
+			reg = <0x10000000 0x10000>;
+
+			uart0: uart at 1c0 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x1c0 0x40>;
+				status = "disabled";
+			};
+
+			uart1: uart at 200 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x200 0x40>;
+				status = "disabled";
+			};
+
+			uart3: uart at c00 {
+				compatible = "fsl,mcf-uart";
+				reg = <0xc00 0x40>;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/arch/m68k/dts/mcf5271.dtsi b/arch/m68k/dts/mcf5271.dtsi
new file mode 100644
index 0000000000..29355528d0
--- /dev/null
+++ b/arch/m68k/dts/mcf5271.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+	compatible = "fsl,mcf5271";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		ipsbar: ipsbar at 4000000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x00000000 0x40000000 0x40000000>;
+			reg = <0x40000000 0x40000000>;
+
+			uart0: uart at 200 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x200 0x40>;
+				status = "disabled";
+			};
+
+			uart1: uart at 240 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x240 0x40>;
+				status = "disabled";
+			};
+
+			uart2: uart at 280 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x280 0x40>;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/arch/m68k/dts/mcf5272.dtsi b/arch/m68k/dts/mcf5272.dtsi
new file mode 100644
index 0000000000..a56117728b
--- /dev/null
+++ b/arch/m68k/dts/mcf5272.dtsi
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+	compatible = "fsl,mcf5272";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		mbar: mbar at 10000000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x00000000 0x10000000 0x10000>;
+			reg = <0x10000000 0x10000>;
+
+			uart0: uart at 100 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x100 0x40>;
+				status = "disabled";
+			};
+
+			uart1: uart at 140 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x140 0x40>;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/arch/m68k/dts/mcf5275.dtsi b/arch/m68k/dts/mcf5275.dtsi
new file mode 100644
index 0000000000..b375609d4a
--- /dev/null
+++ b/arch/m68k/dts/mcf5275.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+	compatible = "fsl,mcf5275";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		ipsbar: ipsbar at 4000000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x00000000 0x40000000 0x40000000>;
+			reg = <0x40000000 0x40000000>;
+
+			uart0: uart at 200 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x200 0x40>;
+				status = "disabled";
+			};
+
+			uart1: uart at 240 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x240 0x40>;
+				status = "disabled";
+			};
+
+			uart2: uart at 280 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x280 0x40>;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/arch/m68k/dts/mcf5282.dtsi b/arch/m68k/dts/mcf5282.dtsi
new file mode 100644
index 0000000000..3ad1be7bb5
--- /dev/null
+++ b/arch/m68k/dts/mcf5282.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+	compatible = "fsl,mcf5282";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		ipsbar: ipsbar at 4000000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x00000000 0x40000000 0x40000000>;
+			reg = <0x40000000 0x40000000>;
+
+			uart0: uart at 200 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x200 0x40>;
+				status = "disabled";
+			};
+
+			uart1: uart at 240 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x240 0x40>;
+				status = "disabled";
+			};
+
+			uart2: uart at 280 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x280 0x40>;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/arch/m68k/dts/mcf5301x.dtsi b/arch/m68k/dts/mcf5301x.dtsi
new file mode 100644
index 0000000000..0891e4dfd5
--- /dev/null
+++ b/arch/m68k/dts/mcf5301x.dtsi
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+	compatible = "fsl,mcf5301x";
+
+	aliases {
+		serial0 = &uart0;
+		spi0 = &dspi0;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		uart0: uart at fc060000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc060000 0x40>;
+			status = "disabled";
+		};
+
+		uart1: uart at fc064000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc064000 0x40>;
+			status = "disabled";
+		};
+
+		uart2: uart at fc068000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc068000 0x40>;
+			status = "disabled";
+		};
+
+		dspi0: dspi at fc05c000 {
+			compatible = "fsl,mcf-dspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xfc05c000 0x100>;
+			spi-max-frequency = <50000000>;
+			num-cs = <4>;
+			spi-mode = <0>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/m68k/dts/mcf5307.dtsi b/arch/m68k/dts/mcf5307.dtsi
new file mode 100644
index 0000000000..e199cf9991
--- /dev/null
+++ b/arch/m68k/dts/mcf5307.dtsi
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+	compatible = "fsl,mcf5307";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/* MBAR */
+		mbar: mbar at 10000000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x00000000 0x10000000 0x10000>;
+			reg = <0x10000000 0x10000>;
+
+			uart0: uart at 1c0 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x1c0 0x40>;
+				status = "disabled";
+			};
+
+			uart1: uart at 200 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x200 0x40>;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/arch/m68k/dts/mcf5329.dtsi b/arch/m68k/dts/mcf5329.dtsi
new file mode 100644
index 0000000000..aeaa6430af
--- /dev/null
+++ b/arch/m68k/dts/mcf5329.dtsi
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+	compatible = "fsl,mcf5329";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		uart0: uart at fc060000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc060000 0x40>;
+			status = "disabled";
+		};
+
+		uart1: uart at fc064000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc064000 0x40>;
+			status = "disabled";
+		};
+
+		uart2: uart at fc068000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc068000 0x40>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/m68k/dts/mcf5441x.dtsi b/arch/m68k/dts/mcf5441x.dtsi
new file mode 100644
index 0000000000..71b392adc3
--- /dev/null
+++ b/arch/m68k/dts/mcf5441x.dtsi
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+	compatible = "fsl,mcf5441x";
+
+	aliases {
+		serial0 = &uart0;
+		spi0 = &dspi0;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		uart0: uart at fc060000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc060000 0x40>;
+			status = "disabled";
+		};
+
+		uart1: uart at fc064000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc064000 0x40>;
+			status = "disabled";
+		};
+
+		uart2: uart at fc068000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc068000 0x40>;
+			status = "disabled";
+		};
+
+		uart3: uart at fc06c000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc06c000 0x40>;
+			status = "disabled";
+		};
+
+		dspi0: dspi at fc05c000 {
+			compatible = "fsl,mcf-dspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xfc05c000 0x100>;
+			spi-max-frequency = <50000000>;
+			num-cs = <4>;
+			spi-mode = <0>;
+			status = "disabled";
+		};
+
+		dspi1: dspi at fc03c000 {
+			compatible = "fsl,mcf-dspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xfc03c000 0x100>;
+			spi-max-frequency = <50000000>;
+			num-cs = <4>;
+			spi-mode = <0>;
+			status = "disabled";
+		};
+
+		dspi2: dspi at ec038000 {
+			compatible = "fsl,mcf-dspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xec038000 0x100>;
+			spi-max-frequency = <50000000>;
+			num-cs = <4>;
+			spi-mode = <0>;
+			status = "disabled";
+		};
+
+		dspi3: dspi at ec03c000 {
+			compatible = "fsl,mcf-dspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xec03c00 0x100>;
+			spi-max-frequency = <50000000>;
+			num-cs = <4>;
+			spi-mode = <0>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/m68k/dts/mcf5445x.dtsi b/arch/m68k/dts/mcf5445x.dtsi
new file mode 100644
index 0000000000..ccbee29a6c
--- /dev/null
+++ b/arch/m68k/dts/mcf5445x.dtsi
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+	compatible = "fsl,mcf5445x";
+
+	aliases {
+		serial0 = &uart0;
+		spi0 = &dspi0;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		uart0: uart at fc060000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc060000 0x40>;
+			status = "disabled";
+		};
+
+		uart1: uart at fc064000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc064000 0x40>;
+			status = "disabled";
+		};
+
+		uart2: uart at fc068000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc068000 0x40>;
+			status = "disabled";
+		};
+
+		dspi0: dspi at fc05c000 {
+			compatible = "fsl,mcf-dspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xfc05c000 0x100>;
+			spi-max-frequency = <50000000>;
+			num-cs = <4>;
+			spi-mode = <0>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/doc/device-tree-bindings/serial/mcf-uart.txt b/doc/device-tree-bindings/serial/mcf-uart.txt
new file mode 100644
index 0000000000..d73f764c01
--- /dev/null
+++ b/doc/device-tree-bindings/serial/mcf-uart.txt
@@ -0,0 +1,19 @@
+Freescale ColdFire UART
+
+Required properties:
+- compatible : should be "fsl,mcf-uart"
+- reg: start address and size of the registers
+
+Example:
+
+soc {
+	compatible = "simple-bus";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	uart0: uart at fc060000 {
+		compatible = "fsl,mcf-uart";
+		reg = <0xfc060000 0x40>;
+		status = "disabled";
+	};
+};
diff --git a/doc/device-tree-bindings/spi/spi-mcf-dspi.txt b/doc/device-tree-bindings/spi/spi-mcf-dspi.txt
new file mode 100644
index 0000000000..1a02e674af
--- /dev/null
+++ b/doc/device-tree-bindings/spi/spi-mcf-dspi.txt
@@ -0,0 +1,22 @@
+Freescale ColdFire DSPI controller
+
+Required properties:
+- compatible : "fsl,mcf-dspi",
+- #address-cells: <1>, as required by generic SPI binding,
+- #size-cells: <0>, also as required by generic SPI binding,
+- reg : offset and length of the register set for the device,
+- spi-max-frequency : max supported spi frequency,
+- num-cs : the number of the chipselect signals,
+- spi-mode: spi motorola mode, 0 to 3,
+
+Example:
+
+dspi0: dspi at fc05c000 {
+	compatible = "fsl,mcf-dspi";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	reg = <0xfc05c000 0x100>;
+	spi-max-frequency = <50000000>;
+	num-cs = <4>;
+	spi-mode = <0>;
+};
-- 
2.19.0

[U-Boot] [PATCH 2/7] drivers: spi: cf_spi: migrate to DM and DT

[Angelo Dureghello]

This patch converts cf_spi.c to DM and to read driver
platform data from flat devicetree.

---
Changes from v1:
- split into 2 patches

Signed-off-by: Angelo Dureghello <angelo@sysam.it>
---
 drivers/spi/Kconfig                     |  18 +-
 drivers/spi/cf_spi.c                    | 495 ++++++++++++++++--------
 include/dm/platform_data/spi_coldfire.h |  25 ++
 3 files changed, 369 insertions(+), 169 deletions(-)
 create mode 100644 include/dm/platform_data/spi_coldfire.h

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index dcd719ff0a..974c5bbed8 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -80,6 +80,12 @@ config CADENCE_QSPI
 	  used to access the SPI NOR flash on platforms embedding this
 	  Cadence IP core.
 
+config CF_SPI
+        bool "ColdFire SPI driver"
+        help
+          Enable the ColdFire SPI driver. This driver can be used on
+          some m68k SoCs.
+
 config DESIGNWARE_SPI
 	bool "Designware SPI driver"
 	help
@@ -244,18 +250,18 @@ config ZYNQMP_GQSPI
 
 endif # if DM_SPI
 
-config SOFT_SPI
-	bool "Soft SPI driver"
-	help
-	 Enable Soft SPI driver. This driver is to use GPIO simulate
-	 the SPI protocol.
-
 config CF_SPI
 	bool "ColdFire SPI driver"
 	help
 	  Enable the ColdFire SPI driver. This driver can be used on
 	  some m68k SoCs.
 
+config SOFT_SPI
+	bool "Soft SPI driver"
+	help
+	 Enable Soft SPI driver. This driver is to use GPIO simulate
+	 the SPI protocol.
+
 config FSL_ESPI
 	bool "Freescale eSPI driver"
 	help
diff --git a/drivers/spi/cf_spi.c b/drivers/spi/cf_spi.c
index 522631cbbf..11a11f79c4 100644
--- a/drivers/spi/cf_spi.c
+++ b/drivers/spi/cf_spi.c
@@ -6,16 +6,27 @@
  *
  * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew at freescale.com)
+ *
+ * Support for device model:
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ *
  */
 
 #include <common.h>
+#include <dm.h>
+#include <dm/platform_data/spi_coldfire.h>
 #include <spi.h>
 #include <malloc.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 
-struct cf_spi_slave {
+struct coldfire_spi_priv {
+#ifndef CONFIG_DM_SPI
 	struct spi_slave slave;
+#endif
+	struct dspi *regs;
 	uint baudrate;
+	int mode;
 	int charbit;
 };
 
@@ -38,14 +49,14 @@ DECLARE_GLOBAL_DATA_PTR;
 #define SPI_MODE_MOD	0x00200000
 #define SPI_DBLRATE	0x00100000
 
-static inline struct cf_spi_slave *to_cf_spi_slave(struct spi_slave *slave)
-{
-	return container_of(slave, struct cf_spi_slave, slave);
-}
+/* Default values */
+#define MCF_DSPI_DEFAULT_SCK_FREQ	10000000
+#define MCF_DSPI_MAX_CHIPSELECTS	4
+#define MCF_DSPI_MODE			0
 
-static void cfspi_init(void)
+static void __spi_init(struct coldfire_spi_priv *cfspi)
 {
-	volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+	struct dspi *dspi = cfspi->regs;
 
 	cfspi_port_conf();	/* port configuration */
 
@@ -56,125 +67,32 @@ static void cfspi_init(void)
 
 	/* Default setting in platform configuration */
 #ifdef CONFIG_SYS_DSPI_CTAR0
-	dspi->ctar[0] = CONFIG_SYS_DSPI_CTAR0;
+	writel(CONFIG_SYS_DSPI_CTAR0, &dspi->ctar[0]);
 #endif
 #ifdef CONFIG_SYS_DSPI_CTAR1
-	dspi->ctar[1] = CONFIG_SYS_DSPI_CTAR1;
+	writel(CONFIG_SYS_DSPI_CTAR1, &dspi->ctar[1]);
 #endif
 #ifdef CONFIG_SYS_DSPI_CTAR2
-	dspi->ctar[2] = CONFIG_SYS_DSPI_CTAR2;
+	writel(CONFIG_SYS_DSPI_CTAR2, &dspi->ctar[2]);
 #endif
 #ifdef CONFIG_SYS_DSPI_CTAR3
-	dspi->ctar[3] = CONFIG_SYS_DSPI_CTAR3;
+	writel(CONFIG_SYS_DSPI_CTAR3, &dspi->ctar[3]);
 #endif
 #ifdef CONFIG_SYS_DSPI_CTAR4
-	dspi->ctar[4] = CONFIG_SYS_DSPI_CTAR4;
+	writel(CONFIG_SYS_DSPI_CTAR4, &dspi->ctar[4]);
 #endif
 #ifdef CONFIG_SYS_DSPI_CTAR5
-	dspi->ctar[5] = CONFIG_SYS_DSPI_CTAR5;
+	writel(CONFIG_SYS_DSPI_CTAR5, &dspi->ctar[5]);
 #endif
 #ifdef CONFIG_SYS_DSPI_CTAR6
-	dspi->ctar[6] = CONFIG_SYS_DSPI_CTAR6;
+	writel(CONFIG_SYS_DSPI_CTAR6, &dspi->ctar[6]);
 #endif
 #ifdef CONFIG_SYS_DSPI_CTAR7
-	dspi->ctar[7] = CONFIG_SYS_DSPI_CTAR7;
+	writel(CONFIG_SYS_DSPI_CTAR7, &dspi->ctar[7]);
 #endif
 }
 
-static void cfspi_tx(u32 ctrl, u16 data)
-{
-	volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
-
-	while ((dspi->sr & 0x0000F000) >= 4) ;
-
-	dspi->tfr = (ctrl | data);
-}
-
-static u16 cfspi_rx(void)
-{
-	volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
-
-	while ((dspi->sr & 0x000000F0) == 0) ;
-
-	return (dspi->rfr & 0xFFFF);
-}
-
-static int cfspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout,
-		      void *din, ulong flags)
-{
-	struct cf_spi_slave *cfslave = to_cf_spi_slave(slave);
-	u16 *spi_rd16 = NULL, *spi_wr16 = NULL;
-	u8 *spi_rd = NULL, *spi_wr = NULL;
-	static u32 ctrl = 0;
-	uint len = bitlen >> 3;
-
-	if (cfslave->charbit == 16) {
-		bitlen >>= 1;
-		spi_wr16 = (u16 *) dout;
-		spi_rd16 = (u16 *) din;
-	} else {
-		spi_wr = (u8 *) dout;
-		spi_rd = (u8 *) din;
-	}
-
-	if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN)
-		ctrl |= DSPI_TFR_CONT;
-
-	ctrl = (ctrl & 0xFF000000) | ((1 << slave->cs) << 16);
-
-	if (len > 1) {
-		int tmp_len = len - 1;
-		while (tmp_len--) {
-			if (dout != NULL) {
-				if (cfslave->charbit == 16)
-					cfspi_tx(ctrl, *spi_wr16++);
-				else
-					cfspi_tx(ctrl, *spi_wr++);
-				cfspi_rx();
-			}
-
-			if (din != NULL) {
-				cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL);
-				if (cfslave->charbit == 16)
-					*spi_rd16++ = cfspi_rx();
-				else
-					*spi_rd++ = cfspi_rx();
-			}
-		}
-
-		len = 1;	/* remaining byte */
-	}
-
-	if ((flags & SPI_XFER_END) == SPI_XFER_END)
-		ctrl &= ~DSPI_TFR_CONT;
-
-	if (len) {
-		if (dout != NULL) {
-			if (cfslave->charbit == 16)
-				cfspi_tx(ctrl, *spi_wr16);
-			else
-				cfspi_tx(ctrl, *spi_wr);
-			cfspi_rx();
-		}
-
-		if (din != NULL) {
-			cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL);
-			if (cfslave->charbit == 16)
-				*spi_rd16 = cfspi_rx();
-			else
-				*spi_rd = cfspi_rx();
-		}
-	} else {
-		/* dummy read */
-		cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL);
-		cfspi_rx();
-	}
-
-	return 0;
-}
-
-static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave,
-					   uint mode)
+int __spi_set_speed(struct coldfire_spi_priv *cfspi, uint bus)
 {
 	/*
 	 * bit definition for mode:
@@ -189,7 +107,7 @@ static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave,
 	 *     11 -  8: Delay after transfer scaler
 	 *      7 -  0: SPI_CPHA, SPI_CPOL, SPI_LSB_FIRST
 	 */
-	volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+	struct dspi *dspi = cfspi->regs;
 	int prescaler[] = { 2, 3, 5, 7 };
 	int scaler[] = {
 		2, 4, 6, 8,
@@ -199,56 +117,38 @@ static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave,
 	};
 	int i, j, pbrcnt, brcnt, diff, tmp, dbr = 0;
 	int best_i, best_j, bestmatch = 0x7FFFFFFF, baud_speed;
-	u32 bus_setup = 0;
+	u32 bus_setup;
+
+	/* Read current setup */
+	bus_setup = readl(&dspi->ctar[bus]);
 
 	tmp = (prescaler[3] * scaler[15]);
 	/* Maximum and minimum baudrate it can handle */
-	if ((cfslave->baudrate > (gd->bus_clk >> 1)) ||
-	    (cfslave->baudrate < (gd->bus_clk / tmp))) {
+	if ((cfspi->baudrate > (gd->bus_clk >> 1)) ||
+	    (cfspi->baudrate < (gd->bus_clk / tmp))) {
 		printf("Exceed baudrate limitation: Max %d - Min %d\n",
 		       (int)(gd->bus_clk >> 1), (int)(gd->bus_clk / tmp));
-		return NULL;
+		return -1;
 	}
 
 	/* Activate Double Baud when it exceed 1/4 the bus clk */
 	if ((CONFIG_SYS_DSPI_CTAR0 & DSPI_CTAR_DBR) ||
-	    (cfslave->baudrate > (gd->bus_clk / (prescaler[0] * scaler[0])))) {
+	    (cfspi->baudrate > (gd->bus_clk / (prescaler[0] * scaler[0])))) {
 		bus_setup |= DSPI_CTAR_DBR;
 		dbr = 1;
 	}
 
-	if (mode & SPI_CPOL)
-		bus_setup |= DSPI_CTAR_CPOL;
-	if (mode & SPI_CPHA)
-		bus_setup |= DSPI_CTAR_CPHA;
-	if (mode & SPI_LSB_FIRST)
-		bus_setup |= DSPI_CTAR_LSBFE;
-
 	/* Overwrite default value set in platform configuration file */
-	if (mode & SPI_MODE_MOD) {
-
-		if ((mode & 0xF0000000) == 0)
-			bus_setup |=
-			    dspi->ctar[cfslave->slave.bus] & 0x78000000;
-		else
-			bus_setup |= ((mode & 0xF0000000) >> 1);
-
+	if (cfspi->mode & SPI_MODE_MOD) {
 		/*
 		 * Check to see if it is enabled by default in platform
 		 * config, or manual setting passed by mode parameter
 		 */
-		if (mode & SPI_DBLRATE) {
+		if (cfspi->mode & SPI_DBLRATE) {
 			bus_setup |= DSPI_CTAR_DBR;
 			dbr = 1;
 		}
-		bus_setup |= (mode & 0x0FC00000) >> 4;	/* PSCSCK, PASC, PDT */
-		bus_setup |= (mode & 0x000FFF00) >> 4;	/* CSSCK, ASC, DT */
-	} else
-		bus_setup |= (dspi->ctar[cfslave->slave.bus] & 0x78FCFFF0);
-
-	cfslave->charbit =
-	    ((dspi->ctar[cfslave->slave.bus] & 0x78000000) ==
-	     0x78000000) ? 16 : 8;
+	}
 
 	pbrcnt = sizeof(prescaler) / sizeof(int);
 	brcnt = sizeof(scaler) / sizeof(int);
@@ -259,10 +159,10 @@ static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave,
 		for (j = 0; j < brcnt; j++) {
 			tmp = (baud_speed / scaler[j]) * (1 + dbr);
 
-			if (tmp > cfslave->baudrate)
-				diff = tmp - cfslave->baudrate;
+			if (tmp > cfspi->baudrate)
+				diff = tmp - cfspi->baudrate;
 			else
-				diff = cfslave->baudrate - tmp;
+				diff = cfspi->baudrate - tmp;
 
 			if (diff < bestmatch) {
 				bestmatch = diff;
@@ -271,50 +171,193 @@ static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave,
 			}
 		}
 	}
+
+	bus_setup &= ~(DSPI_CTAR_PBR(0x03) | DSPI_CTAR_BR(0x0f));
 	bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j));
-	dspi->ctar[cfslave->slave.bus] = bus_setup;
+	writel(bus_setup, &dspi->ctar[bus]);
 
-	return &cfslave->slave;
+	return 0;
 }
-#endif				/* CONFIG_CF_DSPI */
 
-#ifdef CONFIG_CMD_SPI
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+static int __spi_set_mode(struct coldfire_spi_priv *cfspi, uint bus)
 {
-	if (((cs >= 0) && (cs < 8)) && ((bus >= 0) && (bus < 8)))
-		return 1;
-	else
-		return 0;
+	struct dspi *dspi = cfspi->regs;
+	u32 bus_setup = 0;
+
+	if (cfspi->mode & SPI_CPOL)
+		bus_setup |= DSPI_CTAR_CPOL;
+	if (cfspi->mode & SPI_CPHA)
+		bus_setup |= DSPI_CTAR_CPHA;
+	if (cfspi->mode & SPI_LSB_FIRST)
+		bus_setup |= DSPI_CTAR_LSBFE;
+
+	/* Overwrite default value set in platform configuration file */
+	if (cfspi->mode & SPI_MODE_MOD) {
+		if ((cfspi->mode & 0xF0000000) == 0)
+			bus_setup |=
+			    readl(&dspi->ctar[bus]) & 0x78000000;
+		else
+			bus_setup |= ((cfspi->mode & 0xF0000000) >> 1);
+
+		/* PSCSCK, PASC, PDT */
+		bus_setup |= (cfspi->mode & 0x0FC00000) >> 4;
+		/* CSSCK, ASC, DT */
+		bus_setup |= (cfspi->mode & 0x000FFF00) >> 4;
+	} else {
+		bus_setup |= (readl(&dspi->ctar[bus]) & 0x78FCFFF0);
+	}
+
+	cfspi->charbit =
+		((readl(&dspi->ctar[bus]) & 0x78000000) == 0x78000000) ? 16 : 8;
+
+	setbits_be32(&dspi->ctar[bus], bus_setup);
+
+	return 0;
 }
 
-void spi_init(void)
+static inline void __cfspi_tx(struct coldfire_spi_priv *cfspi,
+			      u32 ctrl, u16 data)
+{
+	while ((readl(&cfspi->regs->sr) & 0x0000F000) >= 4)
+		;
+
+	writel(ctrl | data, &cfspi->regs->tfr);
+}
+
+static inline u16 __cfspi_rx(struct coldfire_spi_priv *cfspi)
+{
+	while ((readl(&cfspi->regs->sr) & 0x000000F0) == 0)
+		;
+
+	return readw(&cfspi->regs->rfr);
+}
+
+static int __spi_xfer(struct coldfire_spi_priv *cfspi, uint cs, uint bitlen,
+		      const void *dout, void *din, ulong flags)
+{
+	u16 *spi_rd16 = NULL, *spi_wr16 = NULL;
+	u8 *spi_rd = NULL, *spi_wr = NULL;
+	static u32 ctrl;
+	uint len = bitlen >> 3;
+
+	if (cfspi->charbit == 16) {
+		bitlen >>= 1;
+		spi_wr16 = (u16 *)dout;
+		spi_rd16 = (u16 *)din;
+	} else {
+		spi_wr = (u8 *)dout;
+		spi_rd = (u8 *)din;
+	}
+
+	if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN)
+		ctrl |= DSPI_TFR_CONT;
+
+	ctrl = (ctrl & 0xFF000000) | ((1 << cs) << 16);
+
+	if (len > 1) {
+		int tmp_len = len - 1;
+
+		while (tmp_len--) {
+			if (dout) {
+				if (cfspi->charbit == 16)
+					__cfspi_tx(cfspi, ctrl, *spi_wr16++);
+				else
+					__cfspi_tx(cfspi, ctrl, *spi_wr++);
+				__cfspi_rx(cfspi);
+			}
+
+			if (din) {
+				__cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
+				if (cfspi->charbit == 16)
+					*spi_rd16++ = __cfspi_rx(cfspi);
+				else
+					*spi_rd++ = __cfspi_rx(cfspi);
+			}
+		}
+
+		len = 1;	/* remaining byte */
+	}
+
+	if ((flags & SPI_XFER_END) == SPI_XFER_END)
+		ctrl &= ~DSPI_TFR_CONT;
+
+	if (len) {
+		if (dout) {
+			if (cfspi->charbit == 16)
+				__cfspi_tx(cfspi, ctrl, *spi_wr16);
+			else
+				__cfspi_tx(cfspi, ctrl, *spi_wr);
+			__cfspi_rx(cfspi);
+		}
+
+		if (din) {
+			__cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
+			if (cfspi->charbit == 16)
+				*spi_rd16 = __cfspi_rx(cfspi);
+			else
+				*spi_rd = __cfspi_rx(cfspi);
+		}
+	} else {
+		/* dummy read */
+		__cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
+		__cfspi_rx(cfspi);
+	}
+
+	return 0;
+}
+
+#ifndef CONFIG_DM_SPI
+
+static inline struct coldfire_spi_priv *to_coldfire_spi_slave
+		(struct spi_slave *slave)
 {
-	cfspi_init();
+	return container_of(slave, struct coldfire_spi_priv, slave);
 }
 
 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 				  unsigned int max_hz, unsigned int mode)
 {
-	struct cf_spi_slave *cfslave;
+	struct coldfire_spi_priv *cfspi;
 
 	if (!spi_cs_is_valid(bus, cs))
 		return NULL;
 
-	cfslave = spi_alloc_slave(struct cf_spi_slave, bus, cs);
-	if (!cfslave)
+	cfspi = spi_alloc_slave(struct coldfire_spi_priv, bus, cs);
+	if (!cfspi)
 		return NULL;
 
-	cfslave->baudrate = max_hz;
+	cfspi->regs = (dspi_t *)MMAP_DSPI;
+	cfspi->baudrate = max_hz;
+	cfspi->mode = mode;
+
+	__spi_init(cfspi);
+
+	if (__spi_set_speed(cfspi, bus))
+		return NULL;
+
+	if (__spi_set_mode(cfspi, bus))
+		return NULL;
 
-	/* specific setup */
-	return cfspi_setup_slave(cfslave, mode);
+	return &cfspi->slave;
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	if ((cs >= 0 && cs < 8) && (bus >= 0 && bus < 8))
+		return 1;
+	else
+		return 0;
+}
+
+void spi_init(void)
+{
 }
 
 void spi_free_slave(struct spi_slave *slave)
 {
-	struct cf_spi_slave *cfslave = to_cf_spi_slave(slave);
+	struct coldfire_spi_priv *cfspi = to_coldfire_spi_slave(slave);
 
-	free(cfslave);
+	free(cfspi);
 }
 
 int spi_claim_bus(struct spi_slave *slave)
@@ -330,6 +373,132 @@ void spi_release_bus(struct spi_slave *slave)
 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 	     void *din, unsigned long flags)
 {
-	return cfspi_xfer(slave, bitlen, dout, din, flags);
+	struct coldfire_spi_priv *cfspi = to_coldfire_spi_slave(slave);
+
+	return __spi_xfer(cfspi, slave->cs, bitlen, dout, din, flags);
 }
-#endif				/* CONFIG_CMD_SPI */
+
+#else
+
+void spi_init(void)
+{
+}
+
+static int coldfire_spi_claim_bus(struct udevice *dev)
+{
+	struct udevice *bus = dev->parent;
+	struct dm_spi_slave_platdata *slave_plat =
+		dev_get_parent_platdata(dev);
+
+	return cfspi_claim_bus(bus->seq, slave_plat->cs);
+}
+
+static int coldfire_spi_release_bus(struct udevice *dev)
+{
+	struct udevice *bus = dev->parent;
+	struct dm_spi_slave_platdata *slave_plat =
+		dev_get_parent_platdata(dev);
+
+	cfspi_release_bus(bus->seq, slave_plat->cs);
+
+	return 0;
+}
+
+static int coldfire_spi_xfer(struct udevice *dev, unsigned int bitlen,
+			     const void *dout, void *din,
+			     unsigned long flags)
+{
+	struct udevice *bus = dev_get_parent(dev);
+	struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
+	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+
+	return __spi_xfer(cfspi, slave_plat->cs, bitlen, dout, din, flags);
+}
+
+static int coldfire_spi_set_speed(struct udevice *bus, uint max_hz)
+{
+	struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
+
+	cfspi->baudrate = max_hz;
+
+	return __spi_set_speed(cfspi, bus->seq);
+}
+
+static int coldfire_spi_set_mode(struct udevice *bus, uint mode)
+{
+	struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
+
+	cfspi->mode = mode;
+
+	return __spi_set_mode(cfspi, bus->seq);
+}
+
+static int coldfire_spi_probe(struct udevice *bus)
+{
+	struct coldfire_spi_platdata *plat = dev_get_platdata(bus);
+	struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
+
+	cfspi->regs = (struct dspi *)plat->regs_addr;
+
+	cfspi->baudrate = plat->speed_hz;
+	cfspi->mode = plat->mode;
+
+	__spi_init(cfspi);
+
+	return 0;
+}
+
+static int coldfire_dspi_ofdata_to_platdata(struct udevice *bus)
+{
+	fdt_addr_t addr;
+	struct coldfire_spi_platdata *plat = bus->platdata;
+	const void *blob = gd->fdt_blob;
+	int node = dev_of_offset(bus);
+
+	addr = devfdt_get_addr(bus);
+	if (addr == FDT_ADDR_T_NONE) {
+		debug("DSPI: Can't get base address or size\n");
+		return -ENOMEM;
+	}
+	plat->regs_addr = addr;
+
+	plat->num_cs = fdtdec_get_int(blob, node, "num-cs",
+				      MCF_DSPI_MAX_CHIPSELECTS);
+
+	plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
+					MCF_DSPI_DEFAULT_SCK_FREQ);
+
+	plat->mode = fdtdec_get_int(blob, node, "spi-mode", MCF_DSPI_MODE);
+
+	debug("DSPI: regs=%pa, max-frequency=%d, num-cs=%d, mode=%d\n",
+	      (void *)plat->regs_addr,
+	       plat->speed_hz, plat->num_cs, plat->mode);
+
+	return 0;
+}
+
+static const struct dm_spi_ops coldfire_spi_ops = {
+	.claim_bus	= coldfire_spi_claim_bus,
+	.release_bus	= coldfire_spi_release_bus,
+	.xfer		= coldfire_spi_xfer,
+	.set_speed	= coldfire_spi_set_speed,
+	.set_mode	= coldfire_spi_set_mode,
+};
+
+static const struct udevice_id coldfire_spi_ids[] = {
+	{ .compatible = "fsl,mcf-dspi" },
+	{ }
+};
+
+U_BOOT_DRIVER(coldfire_spi) = {
+	.name = "spi_coldfire",
+	.id = UCLASS_SPI,
+	.of_match = coldfire_spi_ids,
+	.probe = coldfire_spi_probe,
+	.ops = &coldfire_spi_ops,
+	.platdata_auto_alloc_size = sizeof(struct coldfire_spi_platdata),
+	.ofdata_to_platdata = coldfire_dspi_ofdata_to_platdata,
+	.priv_auto_alloc_size = sizeof(struct coldfire_spi_priv),
+};
+#endif				/* CONFIG_DM_SPI */
+#endif				/* CONFIG_CF_DSPI */
diff --git a/include/dm/platform_data/spi_coldfire.h b/include/dm/platform_data/spi_coldfire.h
new file mode 100644
index 0000000000..ee8726ad51
--- /dev/null
+++ b/include/dm/platform_data/spi_coldfire.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2018  Angelo Dureghello <angelo@sysam.it>
+ */
+
+#ifndef __spi_coldfire_h
+#define __spi_coldfire_h
+
+/*
+ * struct coldfire_spi_platdata - information about a coldfire spi module
+ *
+ * @regs_addr: base address for module registers
+ * @speed_hz: default SCK frequency
+ * @mode: default SPI mode
+ * @num_cs: number of DSPI chipselect signals
+ */
+struct coldfire_spi_platdata {
+	fdt_addr_t regs_addr;
+	uint speed_hz;
+	uint mode;
+	uint num_cs;
+};
+
+#endif /* __spi_coldfire_h */
+
-- 
2.19.0

[U-Boot] [PATCH 3/7] drivers: serial: mcfuart: add DT support

[Angelo Dureghello]

This patch adds devicetree support to the mcfuart.c driver.

Signed-off-by: Angelo Dureghello <angelo@sysam.it>
---
 drivers/serial/mcfuart.c | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/drivers/serial/mcfuart.c b/drivers/serial/mcfuart.c
index 1371049de2..5896a19805 100644
--- a/drivers/serial/mcfuart.c
+++ b/drivers/serial/mcfuart.c
@@ -5,6 +5,9 @@
  *
  * Modified to add device model (DM) support
  * (C) Copyright 2015  Angelo Dureghello <angelo@sysam.it>
+ *
+ * Modified to add fdt support
+ * (C) Copyright 2018  Angelo Dureghello <angelo@sysam.it>
  */
 
 /*
@@ -212,6 +215,23 @@ static int coldfire_serial_pending(struct udevice *dev, bool input)
 	return 0;
 }
 
+static int coldfire_ofdata_to_platdata(struct udevice *dev)
+{
+	struct coldfire_serial_platdata *plat = dev_get_platdata(dev);
+	fdt_addr_t addr_base;
+
+	addr_base = devfdt_get_addr(dev);
+	if (addr_base == FDT_ADDR_T_NONE)
+		return -ENODEV;
+
+	plat->base = (uint32_t)addr_base;
+
+	plat->port = dev->seq;
+	plat->baudrate = gd->baudrate;
+
+	return 0;
+}
+
 static const struct dm_serial_ops coldfire_serial_ops = {
 	.putc = coldfire_serial_putc,
 	.pending = coldfire_serial_pending,
@@ -219,9 +239,17 @@ static const struct dm_serial_ops coldfire_serial_ops = {
 	.setbrg = coldfire_serial_setbrg,
 };
 
+static const struct udevice_id coldfire_serial_ids[] = {
+	{ .compatible = "fsl,mcf-uart" },
+	{ }
+};
+
 U_BOOT_DRIVER(serial_coldfire) = {
 	.name = "serial_coldfire",
 	.id = UCLASS_SERIAL,
+	.of_match = coldfire_serial_ids,
+	.ofdata_to_platdata = coldfire_ofdata_to_platdata,
+	.platdata_auto_alloc_size = sizeof(struct coldfire_serial_platdata),
 	.probe = coldfire_serial_probe,
 	.ops = &coldfire_serial_ops,
 	.flags = DM_FLAG_PRE_RELOC,
-- 
2.19.0

[U-Boot] [PATCH 4/7] drivers: serial: mcfuart: add Kconfig option

[Angelo Dureghello]

This patch adds missing CONFIG_MCFUART to Kconfig.

Signed-off-by: Angelo Dureghello <angelo@sysam.it>
---
 drivers/serial/Kconfig | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 5fa27254e3..dcbe999776 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -499,6 +499,13 @@ config MVEBU_A3700_UART
 	  Choose this option to add support for UART driver on the Marvell
 	  Armada 3700 SoC. The base address is configured via DT.
 
+config MCFUART
+	bool "Freescale ColdFire UART support"
+        default n
+        help
+          Choose this option to add support for UART driver on the ColFfire
+          SoC's family.
+
 config MXC_UART
 	bool "IMX serial port support"
 	depends on MX5 || MX6
-- 
2.19.0

[U-Boot] [PATCH 5/7] m68k: architecture changes to support fdt

[Angelo Dureghello]

This patch adds ftd support to the m68k architecture.

Signed-off-by: Angelo Dureghello <angelo@sysam.it>
---
 arch/Kconfig             | 1 +
 arch/m68k/Kconfig        | 2 ++
 arch/m68k/cpu/u-boot.lds | 2 ++
 3 files changed, 5 insertions(+)

diff --git a/arch/Kconfig b/arch/Kconfig
index bf1b4a9afa..d1917f91e1 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -28,6 +28,7 @@ config M68K
 	select HAVE_PRIVATE_LIBGCC
 	select SYS_BOOT_GET_CMDLINE
 	select SYS_BOOT_GET_KBD
+	select SUPPORT_OF_CONTROL
 
 config MICROBLAZE
 	bool "MicroBlaze architecture"
diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig
index 1f6df5c870..60cb9411ed 100644
--- a/arch/m68k/Kconfig
+++ b/arch/m68k/Kconfig
@@ -199,6 +199,8 @@ config TARGET_AMCORE
 config TARGET_STMARK2
         bool "Support stmark2"
         select M54418
+	select OF_CONTROL
+	select DM
 
 endchoice
 
diff --git a/arch/m68k/cpu/u-boot.lds b/arch/m68k/cpu/u-boot.lds
index 96451208e5..e61630db20 100644
--- a/arch/m68k/cpu/u-boot.lds
+++ b/arch/m68k/cpu/u-boot.lds
@@ -75,6 +75,8 @@ SECTIONS
 	. = ALIGN(256);
 	__init_end = .;
 
+	_end = .;
+
 	__bss_start = .;
 	.bss (NOLOAD)       :
 	{
-- 
2.19.0

[U-Boot] [PATCH 6/7] m68k: add stmark2 fdt support

[Angelo Dureghello]

This patch adds stmark2 board fdt support to the m68k arch.

Signed-off-by: Angelo Dureghello <angelo@sysam.it>
---
 arch/m68k/dts/Makefile    | 12 ++++++++++++
 arch/m68k/dts/stmark2.dts | 34 ++++++++++++++++++++++++++++++++++
 2 files changed, 46 insertions(+)
 create mode 100644 arch/m68k/dts/Makefile
 create mode 100644 arch/m68k/dts/stmark2.dts

diff --git a/arch/m68k/dts/Makefile b/arch/m68k/dts/Makefile
new file mode 100644
index 0000000000..9d2e17abf3
--- /dev/null
+++ b/arch/m68k/dts/Makefile
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+dtb-$(CONFIG_TARGET_STMARK2) += stmark2.dtb
+targets += $(dtb-y)
+
+DTC_FLAGS += -R 4 -p 0x1000
+
+PHONY += dtbs
+dtbs: $(addprefix $(obj)/, $(dtb-y))
+	@:
+
+clean-files := *.dtb
diff --git a/arch/m68k/dts/stmark2.dts b/arch/m68k/dts/stmark2.dts
new file mode 100644
index 0000000000..fd8ce4fa35
--- /dev/null
+++ b/arch/m68k/dts/stmark2.dts
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5441x.dtsi"
+
+/ {
+	model = "Sysam stmark2";
+	compatible = "sysam,stmark2";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&dspi0 {
+	spi-mode = <3>;
+	status = "okay";
+
+	flash: is25lp128 at 1 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <60000000>;
+		reg = <1>;
+	};
+};
-- 
2.19.0

[U-Boot] [PATCH 7/7] board: stmark2: updates for DM and DT

[Angelo Dureghello]

This patch enables fdt, and enables DM uart and spi.

Signed-off-by: Angelo Dureghello <angelo@sysam.it>
---
 configs/stmark2_defconfig | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/configs/stmark2_defconfig b/configs/stmark2_defconfig
index 48e851d4a4..7b05b2e20b 100644
--- a/configs/stmark2_defconfig
+++ b/configs/stmark2_defconfig
@@ -2,6 +2,7 @@ CONFIG_M68K=y
 CONFIG_SYS_TEXT_BASE=0x47E00000
 CONFIG_TARGET_STMARK2=y
 CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=30000000"
+CONFIG_DEFAULT_FDT_FILE="stmark2"
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMDLINE_EDITING is not set
@@ -19,12 +20,17 @@ CONFIG_CMD_CACHE=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nor0=spi-flash.0"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=spi-flash.0:1m(u-boot),7m(kernel),-(rootfs)"
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="stmark2"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 # CONFIG_NET is not set
 CONFIG_MTD_DEVICE=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ISSI=y
+CONFIG_DM_SERIAL=y
 CONFIG_SPI_FLASH_MTD=y
 CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_CF_SPI=y
 CONFIG_REGEX=y
-- 
2.19.0

[U-Boot] [PATCH 1/7] m68k: add basic set of devicetrees

[Simon Glass]

On 20 September 2018 at 15:07, Angelo Dureghello <angelo@sysam.it> wrote:
> This patch adds a basic group of devicetrees, one for each
> cpu, including actually just uart and dspi devices, since
> these are the drivers supporting devicetree (support added
> in this patch).
>
> Signed-off-by: Angelo Dureghello <angelo@sysam.it>
> ---
>  arch/m68k/dts/mcf5208.dtsi                    | 36 ++++++++
>  arch/m68k/dts/mcf5227x.dtsi                   | 48 ++++++++++
>  arch/m68k/dts/mcf523x.dtsi                    | 44 ++++++++++
>  arch/m68k/dts/mcf5249.dtsi                    | 38 ++++++++
>  arch/m68k/dts/mcf5253.dtsi                    | 44 ++++++++++
>  arch/m68k/dts/mcf5271.dtsi                    | 44 ++++++++++
>  arch/m68k/dts/mcf5272.dtsi                    | 38 ++++++++
>  arch/m68k/dts/mcf5275.dtsi                    | 44 ++++++++++
>  arch/m68k/dts/mcf5282.dtsi                    | 44 ++++++++++
>  arch/m68k/dts/mcf5301x.dtsi                   | 48 ++++++++++
>  arch/m68k/dts/mcf5307.dtsi                    | 39 +++++++++
>  arch/m68k/dts/mcf5329.dtsi                    | 36 ++++++++
>  arch/m68k/dts/mcf5441x.dtsi                   | 87 +++++++++++++++++++
>  arch/m68k/dts/mcf5445x.dtsi                   | 48 ++++++++++
>  doc/device-tree-bindings/serial/mcf-uart.txt  | 19 ++++
>  doc/device-tree-bindings/spi/spi-mcf-dspi.txt | 22 +++++
>  16 files changed, 679 insertions(+)
>  create mode 100644 arch/m68k/dts/mcf5208.dtsi
>  create mode 100644 arch/m68k/dts/mcf5227x.dtsi
>  create mode 100644 arch/m68k/dts/mcf523x.dtsi
>  create mode 100644 arch/m68k/dts/mcf5249.dtsi
>  create mode 100644 arch/m68k/dts/mcf5253.dtsi
>  create mode 100644 arch/m68k/dts/mcf5271.dtsi
>  create mode 100644 arch/m68k/dts/mcf5272.dtsi
>  create mode 100644 arch/m68k/dts/mcf5275.dtsi
>  create mode 100644 arch/m68k/dts/mcf5282.dtsi
>  create mode 100644 arch/m68k/dts/mcf5301x.dtsi
>  create mode 100644 arch/m68k/dts/mcf5307.dtsi
>  create mode 100644 arch/m68k/dts/mcf5329.dtsi
>  create mode 100644 arch/m68k/dts/mcf5441x.dtsi
>  create mode 100644 arch/m68k/dts/mcf5445x.dtsi
>  create mode 100644 doc/device-tree-bindings/serial/mcf-uart.txt
>  create mode 100644 doc/device-tree-bindings/spi/spi-mcf-dspi.txt

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 2/7] drivers: spi: cf_spi: migrate to DM and DT

[Simon Glass]

Hi Angelo,

On 20 September 2018 at 15:07, Angelo Dureghello <angelo@sysam.it> wrote:
> This patch converts cf_spi.c to DM and to read driver
> platform data from flat devicetree.
>
> ---
> Changes from v1:
> - split into 2 patches
>
> Signed-off-by: Angelo Dureghello <angelo@sysam.it>
> ---
>  drivers/spi/Kconfig                     |  18 +-
>  drivers/spi/cf_spi.c                    | 495 ++++++++++++++++--------
>  include/dm/platform_data/spi_coldfire.h |  25 ++
>  3 files changed, 369 insertions(+), 169 deletions(-)
>  create mode 100644 include/dm/platform_data/spi_coldfire.h
>

Good to see this.

> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index dcd719ff0a..974c5bbed8 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -80,6 +80,12 @@ config CADENCE_QSPI
>           used to access the SPI NOR flash on platforms embedding this
>           Cadence IP core.
>
> +config CF_SPI
> +        bool "ColdFire SPI driver"
> +        help
> +          Enable the ColdFire SPI driver. This driver can be used on
> +          some m68k SoCs.
> +
>  config DESIGNWARE_SPI
>         bool "Designware SPI driver"
>         help
> @@ -244,18 +250,18 @@ config ZYNQMP_GQSPI
>
>  endif # if DM_SPI
>
> -config SOFT_SPI
> -       bool "Soft SPI driver"
> -       help
> -        Enable Soft SPI driver. This driver is to use GPIO simulate
> -        the SPI protocol.

How come this is changing? That should be a separate patch.

> -
>  config CF_SPI
>         bool "ColdFire SPI driver"
>         help
>           Enable the ColdFire SPI driver. This driver can be used on
>           some m68k SoCs.
>
> +config SOFT_SPI
> +       bool "Soft SPI driver"
> +       help
> +        Enable Soft SPI driver. This driver is to use GPIO simulate
> +        the SPI protocol.
> +
>  config FSL_ESPI
>         bool "Freescale eSPI driver"
>         help
> diff --git a/drivers/spi/cf_spi.c b/drivers/spi/cf_spi.c
> index 522631cbbf..11a11f79c4 100644
> --- a/drivers/spi/cf_spi.c
> +++ b/drivers/spi/cf_spi.c
> @@ -6,16 +6,27 @@
>   *
>   * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
>   * TsiChung Liew (Tsi-Chung.Liew at freescale.com)
> + *
> + * Support for device model:
> + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
> + *
>   */
>
>  #include <common.h>
> +#include <dm.h>
> +#include <dm/platform_data/spi_coldfire.h>
>  #include <spi.h>
>  #include <malloc.h>
>  #include <asm/immap.h>
> +#include <asm/io.h>
>
> -struct cf_spi_slave {
> +struct coldfire_spi_priv {
> +#ifndef CONFIG_DM_SPI
>         struct spi_slave slave;
> +#endif
> +       struct dspi *regs;
>         uint baudrate;
> +       int mode;
>         int charbit;
>  };
>
> @@ -38,14 +49,14 @@ DECLARE_GLOBAL_DATA_PTR;
>  #define SPI_MODE_MOD   0x00200000
>  #define SPI_DBLRATE    0x00100000
>
> -static inline struct cf_spi_slave *to_cf_spi_slave(struct spi_slave *slave)
> -{
> -       return container_of(slave, struct cf_spi_slave, slave);
> -}
> +/* Default values */
> +#define MCF_DSPI_DEFAULT_SCK_FREQ      10000000
> +#define MCF_DSPI_MAX_CHIPSELECTS       4
> +#define MCF_DSPI_MODE                  0
>
> -static void cfspi_init(void)
> +static void __spi_init(struct coldfire_spi_priv *cfspi)
>  {
> -       volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
> +       struct dspi *dspi = cfspi->regs;
>
>         cfspi_port_conf();      /* port configuration */
>
> @@ -56,125 +67,32 @@ static void cfspi_init(void)
>
>         /* Default setting in platform configuration */
>  #ifdef CONFIG_SYS_DSPI_CTAR0
> -       dspi->ctar[0] = CONFIG_SYS_DSPI_CTAR0;
> +       writel(CONFIG_SYS_DSPI_CTAR0, &dspi->ctar[0]);

What is going on here? I think these CONFIG options are addresses? If
so, they should be read from the DT, not a CONFIG.

>  #endif
>  #ifdef CONFIG_SYS_DSPI_CTAR1
> -       dspi->ctar[1] = CONFIG_SYS_DSPI_CTAR1;
> +       writel(CONFIG_SYS_DSPI_CTAR1, &dspi->ctar[1]);
>  #endif
>  #ifdef CONFIG_SYS_DSPI_CTAR2
> -       dspi->ctar[2] = CONFIG_SYS_DSPI_CTAR2;
> +       writel(CONFIG_SYS_DSPI_CTAR2, &dspi->ctar[2]);
>  #endif
>  #ifdef CONFIG_SYS_DSPI_CTAR3
> -       dspi->ctar[3] = CONFIG_SYS_DSPI_CTAR3;
> +       writel(CONFIG_SYS_DSPI_CTAR3, &dspi->ctar[3]);
>  #endif
>  #ifdef CONFIG_SYS_DSPI_CTAR4
> -       dspi->ctar[4] = CONFIG_SYS_DSPI_CTAR4;
> +       writel(CONFIG_SYS_DSPI_CTAR4, &dspi->ctar[4]);
>  #endif
>  #ifdef CONFIG_SYS_DSPI_CTAR5
> -       dspi->ctar[5] = CONFIG_SYS_DSPI_CTAR5;
> +       writel(CONFIG_SYS_DSPI_CTAR5, &dspi->ctar[5]);
>  #endif
>  #ifdef CONFIG_SYS_DSPI_CTAR6
> -       dspi->ctar[6] = CONFIG_SYS_DSPI_CTAR6;
> +       writel(CONFIG_SYS_DSPI_CTAR6, &dspi->ctar[6]);
>  #endif
>  #ifdef CONFIG_SYS_DSPI_CTAR7
> -       dspi->ctar[7] = CONFIG_SYS_DSPI_CTAR7;
> +       writel(CONFIG_SYS_DSPI_CTAR7, &dspi->ctar[7]);
>  #endif
>  }
>

[..]

Regards,
Simon

[U-Boot] [PATCH 3/7] drivers: serial: mcfuart: add DT support

[Simon Glass]

On 20 September 2018 at 15:07, Angelo Dureghello <angelo@sysam.it> wrote:
> This patch adds devicetree support to the mcfuart.c driver.
>
> Signed-off-by: Angelo Dureghello <angelo@sysam.it>
> ---
>  drivers/serial/mcfuart.c | 28 ++++++++++++++++++++++++++++
>  1 file changed, 28 insertions(+)

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 4/7] drivers: serial: mcfuart: add Kconfig option

[Simon Glass]

On 20 September 2018 at 15:07, Angelo Dureghello <angelo@sysam.it> wrote:
> This patch adds missing CONFIG_MCFUART to Kconfig.
>
> Signed-off-by: Angelo Dureghello <angelo@sysam.it>
> ---
>  drivers/serial/Kconfig | 7 +++++++
>  1 file changed, 7 insertions(+)
>

Reviewed-by: Simon Glass <sjg@chromium.org>

Suggest you expand the help to mention what features the driver
supports (baud rates, serial format?)

> diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
> index 5fa27254e3..dcbe999776 100644
> --- a/drivers/serial/Kconfig
> +++ b/drivers/serial/Kconfig
> @@ -499,6 +499,13 @@ config MVEBU_A3700_UART
>           Choose this option to add support for UART driver on the Marvell
>           Armada 3700 SoC. The base address is configured via DT.
>
> +config MCFUART
> +       bool "Freescale ColdFire UART support"
> +        default n
> +        help
> +          Choose this option to add support for UART driver on the ColFfire
> +          SoC's family.
> +
>  config MXC_UART
>         bool "IMX serial port support"
>         depends on MX5 || MX6
> --
> 2.19.0
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH 5/7] m68k: architecture changes to support fdt

[Simon Glass]

On 20 September 2018 at 15:07, Angelo Dureghello <angelo@sysam.it> wrote:
> This patch adds ftd support to the m68k architecture.
>
> Signed-off-by: Angelo Dureghello <angelo@sysam.it>
> ---
>  arch/Kconfig             | 1 +
>  arch/m68k/Kconfig        | 2 ++
>  arch/m68k/cpu/u-boot.lds | 2 ++
>  3 files changed, 5 insertions(+)

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 6/7] m68k: add stmark2 fdt support

[Simon Glass]

On 20 September 2018 at 15:07, Angelo Dureghello <angelo@sysam.it> wrote:
> This patch adds stmark2 board fdt support to the m68k arch.
>
> Signed-off-by: Angelo Dureghello <angelo@sysam.it>
> ---
>  arch/m68k/dts/Makefile    | 12 ++++++++++++
>  arch/m68k/dts/stmark2.dts | 34 ++++++++++++++++++++++++++++++++++
>  2 files changed, 46 insertions(+)
>  create mode 100644 arch/m68k/dts/Makefile
>  create mode 100644 arch/m68k/dts/stmark2.dts

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 2/7] drivers: spi: cf_spi: migrate to DM and DT

[Angelo Dureghello]

Hi Simon,

thanks for the review.

On Tue, Sep 25, 2018 at 10:42:08PM -0700, Simon Glass wrote:
> Hi Angelo,
> 
> On 20 September 2018 at 15:07, Angelo Dureghello <angelo@sysam.it> wrote:
> > This patch converts cf_spi.c to DM and to read driver
> > platform data from flat devicetree.
> >
> > ---
> > Changes from v1:
> > - split into 2 patches
> >
> > Signed-off-by: Angelo Dureghello <angelo@sysam.it>
> > ---
> >  drivers/spi/Kconfig                     |  18 +-
> >  drivers/spi/cf_spi.c                    | 495 ++++++++++++++++--------
> >  include/dm/platform_data/spi_coldfire.h |  25 ++
> >  3 files changed, 369 insertions(+), 169 deletions(-)
> >  create mode 100644 include/dm/platform_data/spi_coldfire.h
> >
> 
> Good to see this.
> 
> > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> > index dcd719ff0a..974c5bbed8 100644
> > --- a/drivers/spi/Kconfig
> > +++ b/drivers/spi/Kconfig
> > @@ -80,6 +80,12 @@ config CADENCE_QSPI
> >           used to access the SPI NOR flash on platforms embedding this
> >           Cadence IP core.
> >
> > +config CF_SPI
> > +        bool "ColdFire SPI driver"
> > +        help
> > +          Enable the ColdFire SPI driver. This driver can be used on
> > +          some m68k SoCs.
> > +
> >  config DESIGNWARE_SPI
> >         bool "Designware SPI driver"
> >         help
> > @@ -244,18 +250,18 @@ config ZYNQMP_GQSPI
> >
> >  endif # if DM_SPI
> >
> > -config SOFT_SPI
> > -       bool "Soft SPI driver"
> > -       help
> > -        Enable Soft SPI driver. This driver is to use GPIO simulate
> > -        the SPI protocol.
> 
> How come this is changing? That should be a separate patch.
>
I just respected Kconfig alphabetical order, SOFT_SPI is just moved after.
 
> > -
> >  config CF_SPI
> >         bool "ColdFire SPI driver"
> >         help
> >           Enable the ColdFire SPI driver. This driver can be used on
> >           some m68k SoCs.
> >
> > +config SOFT_SPI
> > +       bool "Soft SPI driver"
> > +       help
> > +        Enable Soft SPI driver. This driver is to use GPIO simulate
> > +        the SPI protocol.
> > +
> >  config FSL_ESPI
> >         bool "Freescale eSPI driver"
> >         help
> > diff --git a/drivers/spi/cf_spi.c b/drivers/spi/cf_spi.c
> > index 522631cbbf..11a11f79c4 100644
> > --- a/drivers/spi/cf_spi.c
> > +++ b/drivers/spi/cf_spi.c
> > @@ -6,16 +6,27 @@
> >   *
> >   * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
> >   * TsiChung Liew (Tsi-Chung.Liew at freescale.com)
> > + *
> > + * Support for device model:
> > + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
> > + *
> >   */
> >
> >  #include <common.h>
> > +#include <dm.h>
> > +#include <dm/platform_data/spi_coldfire.h>
> >  #include <spi.h>
> >  #include <malloc.h>
> >  #include <asm/immap.h>
> > +#include <asm/io.h>
> >
> > -struct cf_spi_slave {
> > +struct coldfire_spi_priv {
> > +#ifndef CONFIG_DM_SPI
> >         struct spi_slave slave;
> > +#endif
> > +       struct dspi *regs;
> >         uint baudrate;
> > +       int mode;
> >         int charbit;
> >  };
> >
> > @@ -38,14 +49,14 @@ DECLARE_GLOBAL_DATA_PTR;
> >  #define SPI_MODE_MOD   0x00200000
> >  #define SPI_DBLRATE    0x00100000
> >
> > -static inline struct cf_spi_slave *to_cf_spi_slave(struct spi_slave *slave)
> > -{
> > -       return container_of(slave, struct cf_spi_slave, slave);
> > -}
> > +/* Default values */
> > +#define MCF_DSPI_DEFAULT_SCK_FREQ      10000000
> > +#define MCF_DSPI_MAX_CHIPSELECTS       4
> > +#define MCF_DSPI_MODE                  0
> >
> > -static void cfspi_init(void)
> > +static void __spi_init(struct coldfire_spi_priv *cfspi)
> >  {
> > -       volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
> > +       struct dspi *dspi = cfspi->regs;
> >
> >         cfspi_port_conf();      /* port configuration */
> >
> > @@ -56,125 +67,32 @@ static void cfspi_init(void)
> >
> >         /* Default setting in platform configuration */
> >  #ifdef CONFIG_SYS_DSPI_CTAR0
> > -       dspi->ctar[0] = CONFIG_SYS_DSPI_CTAR0;
> > +       writel(CONFIG_SYS_DSPI_CTAR0, &dspi->ctar[0]);
> 
> What is going on here? I think these CONFIG options are addresses? If
> so, they should be read from the DT, not a CONFIG.
> 

These are just default settings for each channel (bus), actually coming 
from the include/configs/boardxxx.h. Their speed an mode bitfields are
rewritten later, with values coming from devicetree.
Some driver #define the default value inside the driver itself, in case
i may change in this way. No one seems reading them from device tree.

> >  #endif
> >  #ifdef CONFIG_SYS_DSPI_CTAR1
> > -       dspi->ctar[1] = CONFIG_SYS_DSPI_CTAR1;
> > +       writel(CONFIG_SYS_DSPI_CTAR1, &dspi->ctar[1]);
> >  #endif
> >  #ifdef CONFIG_SYS_DSPI_CTAR2
> > -       dspi->ctar[2] = CONFIG_SYS_DSPI_CTAR2;
> > +       writel(CONFIG_SYS_DSPI_CTAR2, &dspi->ctar[2]);
> >  #endif
> >  #ifdef CONFIG_SYS_DSPI_CTAR3
> > -       dspi->ctar[3] = CONFIG_SYS_DSPI_CTAR3;
> > +       writel(CONFIG_SYS_DSPI_CTAR3, &dspi->ctar[3]);
> >  #endif
> >  #ifdef CONFIG_SYS_DSPI_CTAR4
> > -       dspi->ctar[4] = CONFIG_SYS_DSPI_CTAR4;
> > +       writel(CONFIG_SYS_DSPI_CTAR4, &dspi->ctar[4]);
> >  #endif
> >  #ifdef CONFIG_SYS_DSPI_CTAR5
> > -       dspi->ctar[5] = CONFIG_SYS_DSPI_CTAR5;
> > +       writel(CONFIG_SYS_DSPI_CTAR5, &dspi->ctar[5]);
> >  #endif
> >  #ifdef CONFIG_SYS_DSPI_CTAR6
> > -       dspi->ctar[6] = CONFIG_SYS_DSPI_CTAR6;
> > +       writel(CONFIG_SYS_DSPI_CTAR6, &dspi->ctar[6]);
> >  #endif
> >  #ifdef CONFIG_SYS_DSPI_CTAR7
> > -       dspi->ctar[7] = CONFIG_SYS_DSPI_CTAR7;
> > +       writel(CONFIG_SYS_DSPI_CTAR7, &dspi->ctar[7]);
> >  #endif
> >  }
> >
> 
> [..]
> 
> Regards,
> Simon

Regards,
Angelo

[U-Boot] [PATCH 2/7] drivers: spi: cf_spi: migrate to DM and DT

[Simon Glass]

Hi Angelo,

On 26 September 2018 at 11:53, Angelo Dureghello <angelo@sysam.it> wrote:
> Hi Simon,
>
> thanks for the review.
>
> On Tue, Sep 25, 2018 at 10:42:08PM -0700, Simon Glass wrote:
>> Hi Angelo,
>>
>> On 20 September 2018 at 15:07, Angelo Dureghello <angelo@sysam.it> wrote:
>> > This patch converts cf_spi.c to DM and to read driver
>> > platform data from flat devicetree.
>> >
>> > ---
>> > Changes from v1:
>> > - split into 2 patches
>> >
>> > Signed-off-by: Angelo Dureghello <angelo@sysam.it>
>> > ---
>> >  drivers/spi/Kconfig                     |  18 +-
>> >  drivers/spi/cf_spi.c                    | 495 ++++++++++++++++--------
>> >  include/dm/platform_data/spi_coldfire.h |  25 ++
>> >  3 files changed, 369 insertions(+), 169 deletions(-)
>> >  create mode 100644 include/dm/platform_data/spi_coldfire.h
>> >
>>
>> Good to see this.
>>
>> > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
>> > index dcd719ff0a..974c5bbed8 100644
>> > --- a/drivers/spi/Kconfig
>> > +++ b/drivers/spi/Kconfig
>> > @@ -80,6 +80,12 @@ config CADENCE_QSPI
>> >           used to access the SPI NOR flash on platforms embedding this
>> >           Cadence IP core.
>> >
>> > +config CF_SPI
>> > +        bool "ColdFire SPI driver"
>> > +        help
>> > +          Enable the ColdFire SPI driver. This driver can be used on
>> > +          some m68k SoCs.
>> > +
>> >  config DESIGNWARE_SPI
>> >         bool "Designware SPI driver"
>> >         help
>> > @@ -244,18 +250,18 @@ config ZYNQMP_GQSPI
>> >
>> >  endif # if DM_SPI
>> >
>> > -config SOFT_SPI
>> > -       bool "Soft SPI driver"
>> > -       help
>> > -        Enable Soft SPI driver. This driver is to use GPIO simulate
>> > -        the SPI protocol.
>>
>> How come this is changing? That should be a separate patch.
>>
> I just respected Kconfig alphabetical order, SOFT_SPI is just moved after.

OK, well I do think this should be in a separate patch.

>
>> > -
>> >  config CF_SPI
>> >         bool "ColdFire SPI driver"
>> >         help
>> >           Enable the ColdFire SPI driver. This driver can be used on
>> >           some m68k SoCs.
>> >
>> > +config SOFT_SPI
>> > +       bool "Soft SPI driver"
>> > +       help
>> > +        Enable Soft SPI driver. This driver is to use GPIO simulate
>> > +        the SPI protocol.
>> > +
>> >  config FSL_ESPI
>> >         bool "Freescale eSPI driver"
>> >         help
>> > diff --git a/drivers/spi/cf_spi.c b/drivers/spi/cf_spi.c
>> > index 522631cbbf..11a11f79c4 100644
>> > --- a/drivers/spi/cf_spi.c
>> > +++ b/drivers/spi/cf_spi.c
>> > @@ -6,16 +6,27 @@
>> >   *
>> >   * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
>> >   * TsiChung Liew (Tsi-Chung.Liew at freescale.com)
>> > + *
>> > + * Support for device model:
>> > + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
>> > + *
>> >   */
>> >
>> >  #include <common.h>
>> > +#include <dm.h>
>> > +#include <dm/platform_data/spi_coldfire.h>
>> >  #include <spi.h>
>> >  #include <malloc.h>
>> >  #include <asm/immap.h>
>> > +#include <asm/io.h>
>> >
>> > -struct cf_spi_slave {
>> > +struct coldfire_spi_priv {
>> > +#ifndef CONFIG_DM_SPI
>> >         struct spi_slave slave;
>> > +#endif
>> > +       struct dspi *regs;
>> >         uint baudrate;
>> > +       int mode;
>> >         int charbit;
>> >  };
>> >
>> > @@ -38,14 +49,14 @@ DECLARE_GLOBAL_DATA_PTR;
>> >  #define SPI_MODE_MOD   0x00200000
>> >  #define SPI_DBLRATE    0x00100000
>> >
>> > -static inline struct cf_spi_slave *to_cf_spi_slave(struct spi_slave *slave)
>> > -{
>> > -       return container_of(slave, struct cf_spi_slave, slave);
>> > -}
>> > +/* Default values */
>> > +#define MCF_DSPI_DEFAULT_SCK_FREQ      10000000
>> > +#define MCF_DSPI_MAX_CHIPSELECTS       4
>> > +#define MCF_DSPI_MODE                  0
>> >
>> > -static void cfspi_init(void)
>> > +static void __spi_init(struct coldfire_spi_priv *cfspi)
>> >  {
>> > -       volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
>> > +       struct dspi *dspi = cfspi->regs;
>> >
>> >         cfspi_port_conf();      /* port configuration */
>> >
>> > @@ -56,125 +67,32 @@ static void cfspi_init(void)
>> >
>> >         /* Default setting in platform configuration */
>> >  #ifdef CONFIG_SYS_DSPI_CTAR0
>> > -       dspi->ctar[0] = CONFIG_SYS_DSPI_CTAR0;
>> > +       writel(CONFIG_SYS_DSPI_CTAR0, &dspi->ctar[0]);
>>
>> What is going on here? I think these CONFIG options are addresses? If
>> so, they should be read from the DT, not a CONFIG.
>>
>
> These are just default settings for each channel (bus), actually coming
> from the include/configs/boardxxx.h. Their speed an mode bitfields are
> rewritten later, with values coming from devicetree.
> Some driver #define the default value inside the driver itself, in case
> i may change in this way. No one seems reading them from device tree.

OK, can we remove these? At least they should not have a CONFIG_
prefix, so we can remove them from the whitelist.

Regards,
Simon

[U-Boot] [PATCH 2/7] drivers: spi: cf_spi: migrate to DM and DT

[Angelo Dureghello]

Hi Simon, 

On Thu, Sep 27, 2018 at 06:41:37AM -0700, Simon Glass wrote:
> Hi Angelo,
> 
> On 26 September 2018 at 11:53, Angelo Dureghello <angelo@sysam.it> wrote:
> > Hi Simon,
> >
> > thanks for the review.
> >
> > On Tue, Sep 25, 2018 at 10:42:08PM -0700, Simon Glass wrote:
> >> Hi Angelo,
> >>
> >> On 20 September 2018 at 15:07, Angelo Dureghello <angelo@sysam.it> wrote:
> >> > This patch converts cf_spi.c to DM and to read driver
> >> > platform data from flat devicetree.
> >> >
> >> > ---
> >> > Changes from v1:
> >> > - split into 2 patches
> >> >
> >> > Signed-off-by: Angelo Dureghello <angelo@sysam.it>
> >> > ---
> >> >  drivers/spi/Kconfig                     |  18 +-
> >> >  drivers/spi/cf_spi.c                    | 495 ++++++++++++++++--------
> >> >  include/dm/platform_data/spi_coldfire.h |  25 ++
> >> >  3 files changed, 369 insertions(+), 169 deletions(-)
> >> >  create mode 100644 include/dm/platform_data/spi_coldfire.h
> >> >
> >>
> >> Good to see this.
> >>
> >> > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> >> > index dcd719ff0a..974c5bbed8 100644
> >> > --- a/drivers/spi/Kconfig
> >> > +++ b/drivers/spi/Kconfig
> >> > @@ -80,6 +80,12 @@ config CADENCE_QSPI
> >> >           used to access the SPI NOR flash on platforms embedding this
> >> >           Cadence IP core.
> >> >
> >> > +config CF_SPI
> >> > +        bool "ColdFire SPI driver"
> >> > +        help
> >> > +          Enable the ColdFire SPI driver. This driver can be used on
> >> > +          some m68k SoCs.
> >> > +
> >> >  config DESIGNWARE_SPI
> >> >         bool "Designware SPI driver"
> >> >         help
> >> > @@ -244,18 +250,18 @@ config ZYNQMP_GQSPI
> >> >
> >> >  endif # if DM_SPI
> >> >
> >> > -config SOFT_SPI
> >> > -       bool "Soft SPI driver"
> >> > -       help
> >> > -        Enable Soft SPI driver. This driver is to use GPIO simulate
> >> > -        the SPI protocol.
> >>
> >> How come this is changing? That should be a separate patch.
> >>
> > I just respected Kconfig alphabetical order, SOFT_SPI is just moved after.
> 
> OK, well I do think this should be in a separate patch.
>
Ah, ok. Will do. 
> >
> >> > -
> >> >  config CF_SPI
> >> >         bool "ColdFire SPI driver"
> >> >         help
> >> >           Enable the ColdFire SPI driver. This driver can be used on
> >> >           some m68k SoCs.
> >> >
> >> > +config SOFT_SPI
> >> > +       bool "Soft SPI driver"
> >> > +       help
> >> > +        Enable Soft SPI driver. This driver is to use GPIO simulate
> >> > +        the SPI protocol.
> >> > +
> >> >  config FSL_ESPI
> >> >         bool "Freescale eSPI driver"
> >> >         help
> >> > diff --git a/drivers/spi/cf_spi.c b/drivers/spi/cf_spi.c
> >> > index 522631cbbf..11a11f79c4 100644
> >> > --- a/drivers/spi/cf_spi.c
> >> > +++ b/drivers/spi/cf_spi.c
> >> > @@ -6,16 +6,27 @@
> >> >   *
> >> >   * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
> >> >   * TsiChung Liew (Tsi-Chung.Liew at freescale.com)
> >> > + *
> >> > + * Support for device model:
> >> > + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
> >> > + *
> >> >   */
> >> >
> >> >  #include <common.h>
> >> > +#include <dm.h>
> >> > +#include <dm/platform_data/spi_coldfire.h>
> >> >  #include <spi.h>
> >> >  #include <malloc.h>
> >> >  #include <asm/immap.h>
> >> > +#include <asm/io.h>
> >> >
> >> > -struct cf_spi_slave {
> >> > +struct coldfire_spi_priv {
> >> > +#ifndef CONFIG_DM_SPI
> >> >         struct spi_slave slave;
> >> > +#endif
> >> > +       struct dspi *regs;
> >> >         uint baudrate;
> >> > +       int mode;
> >> >         int charbit;
> >> >  };
> >> >
> >> > @@ -38,14 +49,14 @@ DECLARE_GLOBAL_DATA_PTR;
> >> >  #define SPI_MODE_MOD   0x00200000
> >> >  #define SPI_DBLRATE    0x00100000
> >> >
> >> > -static inline struct cf_spi_slave *to_cf_spi_slave(struct spi_slave *slave)
> >> > -{
> >> > -       return container_of(slave, struct cf_spi_slave, slave);
> >> > -}
> >> > +/* Default values */
> >> > +#define MCF_DSPI_DEFAULT_SCK_FREQ      10000000
> >> > +#define MCF_DSPI_MAX_CHIPSELECTS       4
> >> > +#define MCF_DSPI_MODE                  0
> >> >
> >> > -static void cfspi_init(void)
> >> > +static void __spi_init(struct coldfire_spi_priv *cfspi)
> >> >  {
> >> > -       volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
> >> > +       struct dspi *dspi = cfspi->regs;
> >> >
> >> >         cfspi_port_conf();      /* port configuration */
> >> >
> >> > @@ -56,125 +67,32 @@ static void cfspi_init(void)
> >> >
> >> >         /* Default setting in platform configuration */
> >> >  #ifdef CONFIG_SYS_DSPI_CTAR0
> >> > -       dspi->ctar[0] = CONFIG_SYS_DSPI_CTAR0;
> >> > +       writel(CONFIG_SYS_DSPI_CTAR0, &dspi->ctar[0]);
> >>
> >> What is going on here? I think these CONFIG options are addresses? If
> >> so, they should be read from the DT, not a CONFIG.
> >>
> >
> > These are just default settings for each channel (bus), actually coming
> > from the include/configs/boardxxx.h. Their speed an mode bitfields are
> > rewritten later, with values coming from devicetree.
> > Some driver #define the default value inside the driver itself, in case
> > i may change in this way. No one seems reading them from device tree.
> 
> OK, can we remove these? At least they should not have a CONFIG_
> prefix, so we can remove them from the whitelist.
> 
Ok, i can set a default in the driver itself for now.

> Regards,
> Simon

Regards,
Angelo

[U-Boot] [PATCH 2/7] drivers: spi: cf_spi: migrate to DM and DT

[Angelo Dureghello]

Hi Simon,

On Thu, Sep 27, 2018 at 06:41:37AM -0700, Simon Glass wrote:
> Hi Angelo,
> 
> On 26 September 2018 at 11:53, Angelo Dureghello <angelo@sysam.it> wrote:
> > Hi Simon,
> >
> > thanks for the review.
> >
> > On Tue, Sep 25, 2018 at 10:42:08PM -0700, Simon Glass wrote:
> >> Hi Angelo,
> >>
> >> On 20 September 2018 at 15:07, Angelo Dureghello <angelo@sysam.it> wrote:
> >> > This patch converts cf_spi.c to DM and to read driver
> >> > platform data from flat devicetree.
> >> >
> >> > ---
> >> > Changes from v1:
> >> > - split into 2 patches
> >> >
> >> > Signed-off-by: Angelo Dureghello <angelo@sysam.it>
> >> > ---
> >> >  drivers/spi/Kconfig                     |  18 +-
> >> >  drivers/spi/cf_spi.c                    | 495 ++++++++++++++++--------
> >> >  include/dm/platform_data/spi_coldfire.h |  25 ++
> >> >  3 files changed, 369 insertions(+), 169 deletions(-)
> >> >  create mode 100644 include/dm/platform_data/spi_coldfire.h
> >> >
> >>
> >> Good to see this.
> >>
> >> > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> >> > index dcd719ff0a..974c5bbed8 100644
> >> > --- a/drivers/spi/Kconfig
> >> > +++ b/drivers/spi/Kconfig
> >> > @@ -80,6 +80,12 @@ config CADENCE_QSPI
> >> >           used to access the SPI NOR flash on platforms embedding this
> >> >           Cadence IP core.
> >> >
> >> > +config CF_SPI
> >> > +        bool "ColdFire SPI driver"
> >> > +        help
> >> > +          Enable the ColdFire SPI driver. This driver can be used on
> >> > +          some m68k SoCs.
> >> > +
> >> >  config DESIGNWARE_SPI
> >> >         bool "Designware SPI driver"
> >> >         help
> >> > @@ -244,18 +250,18 @@ config ZYNQMP_GQSPI
> >> >
> >> >  endif # if DM_SPI
> >> >
> >> > -config SOFT_SPI
> >> > -       bool "Soft SPI driver"
> >> > -       help
> >> > -        Enable Soft SPI driver. This driver is to use GPIO simulate
> >> > -        the SPI protocol.
> >>
> >> How come this is changing? That should be a separate patch.
> >>
> > I just respected Kconfig alphabetical order, SOFT_SPI is just moved after.
> 
> OK, well I do think this should be in a separate patch.
> 
this is done, ready into a v2

> >
> >> > -
> >> >  config CF_SPI
> >> >         bool "ColdFire SPI driver"
> >> >         help
> >> >           Enable the ColdFire SPI driver. This driver can be used on
> >> >           some m68k SoCs.
> >> >
> >> > +config SOFT_SPI
> >> > +       bool "Soft SPI driver"
> >> > +       help
> >> > +        Enable Soft SPI driver. This driver is to use GPIO simulate
> >> > +        the SPI protocol.
> >> > +
> >> >  config FSL_ESPI
> >> >         bool "Freescale eSPI driver"
> >> >         help
> >> > diff --git a/drivers/spi/cf_spi.c b/drivers/spi/cf_spi.c
> >> > index 522631cbbf..11a11f79c4 100644
> >> > --- a/drivers/spi/cf_spi.c
> >> > +++ b/drivers/spi/cf_spi.c
> >> > @@ -6,16 +6,27 @@
> >> >   *
> >> >   * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
> >> >   * TsiChung Liew (Tsi-Chung.Liew at freescale.com)
> >> > + *
> >> > + * Support for device model:
> >> > + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
> >> > + *
> >> >   */
> >> >
> >> >  #include <common.h>
> >> > +#include <dm.h>
> >> > +#include <dm/platform_data/spi_coldfire.h>
> >> >  #include <spi.h>
> >> >  #include <malloc.h>
> >> >  #include <asm/immap.h>
> >> > +#include <asm/io.h>
> >> >
> >> > -struct cf_spi_slave {
> >> > +struct coldfire_spi_priv {
> >> > +#ifndef CONFIG_DM_SPI
> >> >         struct spi_slave slave;
> >> > +#endif
> >> > +       struct dspi *regs;
> >> >         uint baudrate;
> >> > +       int mode;
> >> >         int charbit;
> >> >  };
> >> >
> >> > @@ -38,14 +49,14 @@ DECLARE_GLOBAL_DATA_PTR;
> >> >  #define SPI_MODE_MOD   0x00200000
> >> >  #define SPI_DBLRATE    0x00100000
> >> >
> >> > -static inline struct cf_spi_slave *to_cf_spi_slave(struct spi_slave *slave)
> >> > -{
> >> > -       return container_of(slave, struct cf_spi_slave, slave);
> >> > -}
> >> > +/* Default values */
> >> > +#define MCF_DSPI_DEFAULT_SCK_FREQ      10000000
> >> > +#define MCF_DSPI_MAX_CHIPSELECTS       4
> >> > +#define MCF_DSPI_MODE                  0
> >> >
> >> > -static void cfspi_init(void)
> >> > +static void __spi_init(struct coldfire_spi_priv *cfspi)
> >> >  {
> >> > -       volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
> >> > +       struct dspi *dspi = cfspi->regs;
> >> >
> >> >         cfspi_port_conf();      /* port configuration */
> >> >
> >> > @@ -56,125 +67,32 @@ static void cfspi_init(void)
> >> >
> >> >         /* Default setting in platform configuration */
> >> >  #ifdef CONFIG_SYS_DSPI_CTAR0
> >> > -       dspi->ctar[0] = CONFIG_SYS_DSPI_CTAR0;
> >> > +       writel(CONFIG_SYS_DSPI_CTAR0, &dspi->ctar[0]);
> >>
> >> What is going on here? I think these CONFIG options are addresses? If
> >> so, they should be read from the DT, not a CONFIG.
> >>
> >
> > These are just default settings for each channel (bus), actually coming
> > from the include/configs/boardxxx.h. Their speed an mode bitfields are
> > rewritten later, with values coming from devicetree.
> > Some driver #define the default value inside the driver itself, in case
> > i may change in this way. No one seems reading them from device tree.
> 
> OK, can we remove these? At least they should not have a CONFIG_
> prefix, so we can remove them from the whitelist.
>

I verified that in particular 1 m68k board (ls1012aqds.h) wants different
defaults as cs-clock delays. This is something that atually can only be
done by those CONFIG_SYS_DSPI_CTARX.

This settings may be moved into DT but all the related boards should have
been moved to use a dts. Not sure if i can do this now, since i cannot 
test DT migration without owning the related physical board (hw).

How does it work in general ? Should i move al boards to dts, leaving 
tests to board maintaners in the future ? Can we keep those 
CONFIG_SYS_DSPI_CTARX in this way and perform the all-boards conversion
to dts in a later step ?
 
> Regards,
> Simon

Regards,
Angelo

[U-Boot] [PATCH 2/7] drivers: spi: cf_spi: migrate to DM and DT

[Simon Glass]

Hi Angelo,

On 28 September 2018 at 04:22, Angelo Dureghello <angelo@sysam.it> wrote:
> Hi Simon,
>
> On Thu, Sep 27, 2018 at 06:41:37AM -0700, Simon Glass wrote:
>> Hi Angelo,
>>
>> On 26 September 2018 at 11:53, Angelo Dureghello <angelo@sysam.it> wrote:
>> > Hi Simon,
>> >
>> > thanks for the review.
>> >
>> > On Tue, Sep 25, 2018 at 10:42:08PM -0700, Simon Glass wrote:
>> >> Hi Angelo,
>> >>
>> >> On 20 September 2018 at 15:07, Angelo Dureghello <angelo@sysam.it> wrote:
>> >> > This patch converts cf_spi.c to DM and to read driver
>> >> > platform data from flat devicetree.
>> >> >
>> >> > ---
>> >> > Changes from v1:
>> >> > - split into 2 patches
>> >> >
>> >> > Signed-off-by: Angelo Dureghello <angelo@sysam.it>
>> >> > ---
>> >> >  drivers/spi/Kconfig                     |  18 +-
>> >> >  drivers/spi/cf_spi.c                    | 495 ++++++++++++++++--------
>> >> >  include/dm/platform_data/spi_coldfire.h |  25 ++
>> >> >  3 files changed, 369 insertions(+), 169 deletions(-)
>> >> >  create mode 100644 include/dm/platform_data/spi_coldfire.h
>> >> >
>> >>
>> >> Good to see this.
>> >>
>> >> > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
>> >> > index dcd719ff0a..974c5bbed8 100644
>> >> > --- a/drivers/spi/Kconfig
>> >> > +++ b/drivers/spi/Kconfig
>> >> > @@ -80,6 +80,12 @@ config CADENCE_QSPI
>> >> >           used to access the SPI NOR flash on platforms embedding this
>> >> >           Cadence IP core.
>> >> >
>> >> > +config CF_SPI
>> >> > +        bool "ColdFire SPI driver"
>> >> > +        help
>> >> > +          Enable the ColdFire SPI driver. This driver can be used on
>> >> > +          some m68k SoCs.
>> >> > +
>> >> >  config DESIGNWARE_SPI
>> >> >         bool "Designware SPI driver"
>> >> >         help
>> >> > @@ -244,18 +250,18 @@ config ZYNQMP_GQSPI
>> >> >
>> >> >  endif # if DM_SPI
>> >> >
>> >> > -config SOFT_SPI
>> >> > -       bool "Soft SPI driver"
>> >> > -       help
>> >> > -        Enable Soft SPI driver. This driver is to use GPIO simulate
>> >> > -        the SPI protocol.
>> >>
>> >> How come this is changing? That should be a separate patch.
>> >>
>> > I just respected Kconfig alphabetical order, SOFT_SPI is just moved after.
>>
>> OK, well I do think this should be in a separate patch.
>>
> this is done, ready into a v2
>
>> >
>> >> > -
>> >> >  config CF_SPI
>> >> >         bool "ColdFire SPI driver"
>> >> >         help
>> >> >           Enable the ColdFire SPI driver. This driver can be used on
>> >> >           some m68k SoCs.
>> >> >
>> >> > +config SOFT_SPI
>> >> > +       bool "Soft SPI driver"
>> >> > +       help
>> >> > +        Enable Soft SPI driver. This driver is to use GPIO simulate
>> >> > +        the SPI protocol.
>> >> > +
>> >> >  config FSL_ESPI
>> >> >         bool "Freescale eSPI driver"
>> >> >         help
>> >> > diff --git a/drivers/spi/cf_spi.c b/drivers/spi/cf_spi.c
>> >> > index 522631cbbf..11a11f79c4 100644
>> >> > --- a/drivers/spi/cf_spi.c
>> >> > +++ b/drivers/spi/cf_spi.c
>> >> > @@ -6,16 +6,27 @@
>> >> >   *
>> >> >   * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
>> >> >   * TsiChung Liew (Tsi-Chung.Liew at freescale.com)
>> >> > + *
>> >> > + * Support for device model:
>> >> > + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
>> >> > + *
>> >> >   */
>> >> >
>> >> >  #include <common.h>
>> >> > +#include <dm.h>
>> >> > +#include <dm/platform_data/spi_coldfire.h>
>> >> >  #include <spi.h>
>> >> >  #include <malloc.h>
>> >> >  #include <asm/immap.h>
>> >> > +#include <asm/io.h>
>> >> >
>> >> > -struct cf_spi_slave {
>> >> > +struct coldfire_spi_priv {
>> >> > +#ifndef CONFIG_DM_SPI
>> >> >         struct spi_slave slave;
>> >> > +#endif
>> >> > +       struct dspi *regs;
>> >> >         uint baudrate;
>> >> > +       int mode;
>> >> >         int charbit;
>> >> >  };
>> >> >
>> >> > @@ -38,14 +49,14 @@ DECLARE_GLOBAL_DATA_PTR;
>> >> >  #define SPI_MODE_MOD   0x00200000
>> >> >  #define SPI_DBLRATE    0x00100000
>> >> >
>> >> > -static inline struct cf_spi_slave *to_cf_spi_slave(struct spi_slave *slave)
>> >> > -{
>> >> > -       return container_of(slave, struct cf_spi_slave, slave);
>> >> > -}
>> >> > +/* Default values */
>> >> > +#define MCF_DSPI_DEFAULT_SCK_FREQ      10000000
>> >> > +#define MCF_DSPI_MAX_CHIPSELECTS       4
>> >> > +#define MCF_DSPI_MODE                  0
>> >> >
>> >> > -static void cfspi_init(void)
>> >> > +static void __spi_init(struct coldfire_spi_priv *cfspi)
>> >> >  {
>> >> > -       volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
>> >> > +       struct dspi *dspi = cfspi->regs;
>> >> >
>> >> >         cfspi_port_conf();      /* port configuration */
>> >> >
>> >> > @@ -56,125 +67,32 @@ static void cfspi_init(void)
>> >> >
>> >> >         /* Default setting in platform configuration */
>> >> >  #ifdef CONFIG_SYS_DSPI_CTAR0
>> >> > -       dspi->ctar[0] = CONFIG_SYS_DSPI_CTAR0;
>> >> > +       writel(CONFIG_SYS_DSPI_CTAR0, &dspi->ctar[0]);
>> >>
>> >> What is going on here? I think these CONFIG options are addresses? If
>> >> so, they should be read from the DT, not a CONFIG.
>> >>
>> >
>> > These are just default settings for each channel (bus), actually coming
>> > from the include/configs/boardxxx.h. Their speed an mode bitfields are
>> > rewritten later, with values coming from devicetree.
>> > Some driver #define the default value inside the driver itself, in case
>> > i may change in this way. No one seems reading them from device tree.
>>
>> OK, can we remove these? At least they should not have a CONFIG_
>> prefix, so we can remove them from the whitelist.
>>
>
> I verified that in particular 1 m68k board (ls1012aqds.h) wants different
> defaults as cs-clock delays. This is something that atually can only be
> done by those CONFIG_SYS_DSPI_CTARX.
>
> This settings may be moved into DT but all the related boards should have
> been moved to use a dts. Not sure if i can do this now, since i cannot
> test DT migration without owning the related physical board (hw).
>
> How does it work in general ? Should i move al boards to dts, leaving
> tests to board maintaners in the future ? Can we keep those
> CONFIG_SYS_DSPI_CTARX in this way and perform the all-boards conversion
> to dts in a later step ?

Yes you can migrate them forcibly since the alternative is presumably
to delete their support from mainline.

Regards,
Simon