From mboxrd@z Thu Jan 1 00:00:00 1970 From: Gregory CLEMENT Date: Tue, 9 Oct 2018 13:58:33 +0200 Subject: [U-Boot] [PATCH v2 2/7] MIPS: Allow to prefetch and lock instructions into cache In-Reply-To: <20181009115838.21795-1-gregory.clement@bootlin.com> References: <20181009115838.21795-1-gregory.clement@bootlin.com> Message-ID: <20181009115838.21795-3-gregory.clement@bootlin.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de This path add a new helper allowing to prefetch and lock instructions into cache. This is useful very early in the boot when no RAM is available yet. Signed-off-by: Gregory CLEMENT --- arch/mips/include/asm/cacheops.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h index 3161875441..98b67ccc8e 100644 --- a/arch/mips/include/asm/cacheops.h +++ b/arch/mips/include/asm/cacheops.h @@ -19,6 +19,25 @@ static inline void mips_cache(int op, const volatile void *addr) #endif } +#define MIPS32_WHICH_ICACHE 0x0 +#define MIPS32_FETCH_AND_LOCK 0x7 + +#define ICACHE_LOAD_LOCK (MIPS32_WHICH_ICACHE | (MIPS32_FETCH_AND_LOCK << 2)) + +/* Prefetch and lock instructions into cache */ +static inline void icache_lock(void *func, size_t len) +{ + int i, lines = ((len - 1) / ARCH_DMA_MINALIGN) + 1; + + for (i = 0; i < lines; i++) { + asm volatile (" cache %0, %1(%2)" + : /* No Output */ + : "I" ICACHE_LOAD_LOCK, + "n" (i * ARCH_DMA_MINALIGN), + "r" (func) + : /* No Clobbers */); + } +} #endif /* !__ASSEMBLY__ */ /* -- 2.19.1