[U-Boot] [PATCH] sunxi: use 6MHz PLL_VIDEO step for DE2 for higher resolution LCD

[U-Boot] [PATCH] sunxi: use 6MHz PLL_VIDEO step for DE2 for higher resolution LCD

[Vasily Khoruzhick]

From: Icenowy Zheng <icenowy@aosc.io>

DE2 SoCs can support LCDs up to 1080p (e.g. A64), and 3MHz step won't
let PLL_VIDEO be high enough for them.

Use 6MHz step for PLL_VIDEO when using DE2, to satisfy 1080p LCD.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Vasily Khoruzhick <anarsoul@gmail.com>
---
 arch/arm/mach-sunxi/clock_sun6i.c |  4 ++++
 drivers/video/sunxi/lcdc.c        | 22 ++++++++++++++--------
 2 files changed, 18 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c
index 82f6f7f8e3..1628f3a7b6 100644
--- a/arch/arm/mach-sunxi/clock_sun6i.c
+++ b/arch/arm/mach-sunxi/clock_sun6i.c
@@ -149,7 +149,11 @@ void clock_set_pll3(unsigned int clk)
 {
 	struct sunxi_ccm_reg * const ccm =
 		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+#ifdef CONFIG_SUNXI_DE2
+	const int m = 4; /* 6 MHz steps to allow higher frequency for DE2 */
+#else
 	const int m = 8; /* 3 MHz steps just like sun4i, sun5i and sun7i */
+#endif
 
 	if (clk == 0) {
 		clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN);
diff --git a/drivers/video/sunxi/lcdc.c b/drivers/video/sunxi/lcdc.c
index 63c47bf1bc..4cf3a0eb75 100644
--- a/drivers/video/sunxi/lcdc.c
+++ b/drivers/video/sunxi/lcdc.c
@@ -211,11 +211,17 @@ void lcdc_tcon1_mode_set(struct sunxi_lcdc_reg * const lcdc,
 void lcdc_pll_set(struct sunxi_ccm_reg *ccm, int tcon, int dotclock,
 		  int *clk_div, int *clk_double, bool is_composite)
 {
-	int value, n, m, min_m, max_m, diff;
+	int value, n, m, min_m, max_m, diff, step;
 	int best_n = 0, best_m = 0, best_diff = 0x0FFFFFFF;
 	int best_double = 0;
 	bool use_mipi_pll = false;
 
+#ifdef CONFIG_SUNXI_DE2
+	step = 6000;
+#else
+	step = 3000;
+#endif
+
 	if (tcon == 0) {
 #if defined(CONFIG_VIDEO_LCD_IF_PARALLEL) || defined(CONFIG_SUNXI_DE2)
 		min_m = 6;
@@ -237,10 +243,10 @@ void lcdc_pll_set(struct sunxi_ccm_reg *ccm, int tcon, int dotclock,
 	 */
 	for (m = min_m; m <= max_m; m++) {
 #ifndef CONFIG_SUNXI_DE2
-		n = (m * dotclock) / 3000;
+		n = (m * dotclock) / step;
 
 		if ((n >= 9) && (n <= 127)) {
-			value = (3000 * n) / m;
+			value = (step * n) / m;
 			diff = dotclock - value;
 			if (diff < best_diff) {
 				best_diff = diff;
@@ -256,9 +262,9 @@ void lcdc_pll_set(struct sunxi_ccm_reg *ccm, int tcon, int dotclock,
 #endif
 
 		/* No double clock on DE2 */
-		n = (m * dotclock) / 6000;
+		n = (m * dotclock) / (step * 2);
 		if ((n >= 9) && (n <= 127)) {
-			value = (6000 * n) / m;
+			value = (step * 2 * n) / m;
 			diff = dotclock - value;
 			if (diff < best_diff) {
 				best_diff = diff;
@@ -287,11 +293,11 @@ void lcdc_pll_set(struct sunxi_ccm_reg *ccm, int tcon, int dotclock,
 	} else
 #endif
 	{
-		clock_set_pll3(best_n * 3000000);
-		debug("dotclock: %dkHz = %dkHz: (%d * 3MHz * %d) / %d\n",
+		clock_set_pll3(best_n * step * 1000);
+		debug("dotclock: %dkHz = %dkHz: (%d * %dkHz * %d) / %d\n",
 		      dotclock,
 		      (best_double + 1) * clock_get_pll3() / best_m / 1000,
-		      best_double + 1, best_n, best_m);
+		      best_double + 1, step, best_n, best_m);
 	}
 
 	if (tcon == 0) {
-- 
2.19.1

[U-Boot] [PATCH] sunxi: use 6MHz PLL_VIDEO step for DE2 for higher resolution LCD

[Maxime Ripard]

On Sun, Oct 28, 2018 at 02:26:12PM -0700, Vasily Khoruzhick wrote:
> From: Icenowy Zheng <icenowy@aosc.io>
> 
> DE2 SoCs can support LCDs up to 1080p (e.g. A64), and 3MHz step won't
> let PLL_VIDEO be high enough for them.
> 
> Use 6MHz step for PLL_VIDEO when using DE2, to satisfy 1080p LCD.
> 
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
> Tested-by: Vasily Khoruzhick <anarsoul@gmail.com>

I wonder if this will cause any issues with panels and lower
resolutions that will have a smaller tolerancy.

Let's try it,

Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>

Maxime

-- 
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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[U-Boot] [PATCH] sunxi: use 6MHz PLL_VIDEO step for DE2 for higher resolution LCD

[Jagan Teki]

On Mon, Oct 29, 2018 at 2:08 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
>
> On Sun, Oct 28, 2018 at 02:26:12PM -0700, Vasily Khoruzhick wrote:
> > From: Icenowy Zheng <icenowy@aosc.io>
> >
> > DE2 SoCs can support LCDs up to 1080p (e.g. A64), and 3MHz step won't
> > let PLL_VIDEO be high enough for them.
> >
> > Use 6MHz step for PLL_VIDEO when using DE2, to satisfy 1080p LCD.
> >
> > Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> > Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
> > Tested-by: Vasily Khoruzhick <anarsoul@gmail.com>
>
> I wonder if this will cause any issues with panels and lower
> resolutions that will have a smaller tolerancy.

Does it impact lower resolution panels? is it tested?

[U-Boot] [PATCH] sunxi: use 6MHz PLL_VIDEO step for DE2 for higher resolution LCD

[Vasily Khoruzhick]

On Tue, Nov 13, 2018 at 8:32 AM Jagan Teki <jagan@amarulasolutions.com> wrote:
>
> On Mon, Oct 29, 2018 at 2:08 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
> >
> > On Sun, Oct 28, 2018 at 02:26:12PM -0700, Vasily Khoruzhick wrote:
> > > From: Icenowy Zheng <icenowy@aosc.io>
> > >
> > > DE2 SoCs can support LCDs up to 1080p (e.g. A64), and 3MHz step won't
> > > let PLL_VIDEO be high enough for them.
> > >
> > > Use 6MHz step for PLL_VIDEO when using DE2, to satisfy 1080p LCD.
> > >
> > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> > > Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
> > > Tested-by: Vasily Khoruzhick <anarsoul@gmail.com>
> >
> > I wonder if this will cause any issues with panels and lower
> > resolutions that will have a smaller tolerancy.
>
> Does it impact lower resolution panels? is it tested?

It works fine with 1366x768 panel, and I don't have any other panels
that work in u-boot to test. And correct me if I'm wrong but I don't
think that we have any boards with DE2 and low-res panel supported in
u-boot.

[U-Boot] [PATCH] sunxi: use 6MHz PLL_VIDEO step for DE2 for higher resolution LCD

[Jagan Teki]

On Tue, Nov 13, 2018 at 10:11 PM Vasily Khoruzhick <anarsoul@gmail.com> wrote:
>
> On Tue, Nov 13, 2018 at 8:32 AM Jagan Teki <jagan@amarulasolutions.com> wrote:
> >
> > On Mon, Oct 29, 2018 at 2:08 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
> > >
> > > On Sun, Oct 28, 2018 at 02:26:12PM -0700, Vasily Khoruzhick wrote:
> > > > From: Icenowy Zheng <icenowy@aosc.io>
> > > >
> > > > DE2 SoCs can support LCDs up to 1080p (e.g. A64), and 3MHz step won't
> > > > let PLL_VIDEO be high enough for them.
> > > >
> > > > Use 6MHz step for PLL_VIDEO when using DE2, to satisfy 1080p LCD.
> > > >
> > > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> > > > Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
> > > > Tested-by: Vasily Khoruzhick <anarsoul@gmail.com>
> > >
> > > I wonder if this will cause any issues with panels and lower
> > > resolutions that will have a smaller tolerancy.
> >
> > Does it impact lower resolution panels? is it tested?
>
> It works fine with 1366x768 panel, and I don't have any other panels
> that work in u-boot to test. And correct me if I'm wrong but I don't
> think that we have any boards with DE2 and low-res panel supported in
> u-boot.

ie what I wonder too, if we have any thing similar for DE2. anyway

Applied to u-boot-sunxi/master