From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tom Rini Date: Tue, 27 Nov 2018 13:47:42 -0500 Subject: [U-Boot] armv7r: K3: Allow SPL to run only on core 0 In-Reply-To: <20181115053450.17555-1-lokeshvutla@ti.com> References: <20181115053450.17555-1-lokeshvutla@ti.com> Message-ID: <20181127184742.GT11247@bill-the-cat> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Thu, Nov 15, 2018 at 11:04:50AM +0530, Lokesh Vutla wrote: > Based on the MCU R5 efuse settings, R5F cores in MCU domain > either work in split mode or in lock step mode. > > If efuse settings are in lockstep mode: ROM release R5 cores > and SPL continues to run on the R5 core is lockstep mode. > > If efuse settings are in split mode: ROM releases both the R5 > cores simultaneously and allow SPL to run on both the cores. > In this case it is bootloader's responsibility to detect core > 1 and park it. Else both the core will be running bootloader > independently which might result in an unexpected behaviour. > > Signed-off-by: Lokesh Vutla > Reviewed-by: Tom Rini Applied to u-boot/master, thanks! -- Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: not available URL: