[U-Boot] [RFC PATCH v2 08/11] mtd: spi: Add lightweight SPI flash stack for SPL

Vignesh R
2018-12-05T11:09:42Z

On 05/12/18 12:31 PM, Simon Goldschmidt wrote:
> On Tue, Dec 4, 2018 at 1:27 PM Vignesh R <vigneshr@ti.com> wrote:
>>
>> Add a tiny SPI flash stack that just supports reading data/images from
>> SPI flash. This is useful for boards that have SPL size constraints and
>> would need to use SPI flash framework just to read images/data from
>> flash. There is approximately 1.5 to 2KB savings with this.
>
> We could reduce the size further by removing write functionality (and
> everything that's related to write, like write protection, etc.). If
> this was a Kconfig option, write-related code in drivers could be left
> out as well.
>

Yes, for now

> But that's probably work for the future?
>
>> Based on prior work of reducing spi flash id table by
>> Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
>>
>> Signed-off-by: Vignesh R <vigneshr@ti.com>
>> ---
>> common/spl/Kconfig | 9 +
>> drivers/mtd/spi/Makefile | 8 +-
>> drivers/mtd/spi/sf_internal.h | 2 +
>> drivers/mtd/spi/spi-nor-ids.c | 294 ++++++++++++
>> drivers/mtd/spi/spi-nor-tiny.c | 806 +++++++++++++++++++++++++++++++++
>> drivers/mtd/spi/spi-nor.c | 266 +----------
>> 6 files changed, 1122 insertions(+), 263 deletions(-)
>> create mode 100644 drivers/mtd/spi/spi-nor-ids.c
>> create mode 100644 drivers/mtd/spi/spi-nor-tiny.c
>>
>> diff --git a/common/spl/Kconfig b/common/spl/Kconfig
>> index 2b6f315b1cf3..e3597249188c 100644
>> --- a/common/spl/Kconfig
>> +++ b/common/spl/Kconfig
>> @@ -727,6 +727,15 @@ config SPL_SPI_FLASH_SUPPORT
>> lines). This enables the drivers in drivers/mtd/spi as part of an
>> SPL build. This normally requires SPL_SPI_SUPPORT.
>>
>> +config SPL_SPI_FLASH_TINY
>> + bool "Enable low footprint SPL SPI Flash support"
>> + depends on SPL_SPI_FLASH_SUPPORT
>> + help
>> + Enable lightweight SPL SPI Flash support that supports just reading
>> + data/images from flash. No support to write/erase flash. Enable
>> + this if you have SPL size limitations and don't need full
>> + fledged SPI flash support.
>> +
>> config SPL_SPI_FLASH_SFDP_SUPPORT
>
> Am I right that this does not do anything when SPL_SPI_FLASH_TINY is
> enabled? Should it somehow depend on "not tiny"?

Will take care of that.

>
>> bool "SFDP table parsing support for SPI NOR flashes"
>> help
>> diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
>> index 9cd6672e93ce..4d1588ecc169 100644
>> --- a/drivers/mtd/spi/Makefile
>> +++ b/drivers/mtd/spi/Makefile
>> @@ -7,9 +7,15 @@ obj-$(CONFIG_DM_SPI_FLASH) += sf-uclass.o
>>
>> ifdef CONFIG_SPL_BUILD
>> obj-$(CONFIG_SPL_SPI_BOOT) += fsl_espi_spl.o
>> +ifeq ($(CONFIG_SPL_SPI_FLASH_TINY),y)
>> +obj-$(CONFIG_SPL_SPI_FLASH_TINY) += sf_probe.o spi-nor-tiny.o spi-nor-ids.o
>> +else
>> +obj-$(CONFIG_SPI_FLASH) += sf_probe.o spi-nor.o spi-nor-ids.o
>> +endif
>> +else
>> +obj-$(CONFIG_SPI_FLASH) += sf_probe.o spi-nor.o spi-nor-ids.o
>
> Would it make sense to have "sf_probe.o" and "spi-nor-ids.o" the same
> for all 3 configs to reduce duplicate lines?
>
>

Ok, I changed that to:

diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
index 9cd6672e93ce..9f7ab87b4c5f 100644
--- a/drivers/mtd/spi/Makefile
+++ b/drivers/mtd/spi/Makefile
@@ -4,12 +4,20 @@
# Wolfgang Denk, DENX Software Engineering, wd at denx.de.

obj-$(CONFIG_DM_SPI_FLASH) += sf-uclass.o
+spi-flash-y := sf_probe.o spi-nor-ids.o

ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_SPI_BOOT) += fsl_espi_spl.o
+ifeq ($(CONFIG_SPL_SPI_FLASH_TINY),y)
+spi-flash-y += spi-nor-tiny.o
+else
+spi-flash-y += spi-nor.o
+endif
+else
+spi-flash-y += spi-nor.o
endif

-obj-$(CONFIG_SPI_FLASH) += sf_probe.o spi-nor.o
+obj-$(CONFIG_SPI_FLASH) += spi-flash.o

Regards
Vignesh

>> endif
>>
>> -obj-$(CONFIG_SPI_FLASH) += sf_probe.o spi-nor.o
>> obj-$(CONFIG_SPI_FLASH_DATAFLASH) += sf_dataflash.o sf.o
>> obj-$(CONFIG_SPI_FLASH_MTD) += sf_mtd.o
>> obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o
>> diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
>> index 55619f5aea5c..7e7d400cdbdf 100644
>> --- a/drivers/mtd/spi/sf_internal.h
>> +++ b/drivers/mtd/spi/sf_internal.h
>> @@ -16,7 +16,9 @@
>> #define SPI_NOR_MAX_ADDR_WIDTH 4
>>
>> struct flash_info {
>> +#if !CONFIG_IS_ENABLED(SPI_FLASH_TINY)
>> char *name;
>> +#endif
>>
>> /*
>> * This array stores the ID bytes.
>> diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
>> new file mode 100644
>> index 000000000000..fd20c86b3aef
>> --- /dev/null
>> +++ b/drivers/mtd/spi/spi-nor-ids.c
>> @@ -0,0 +1,294 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
>> + */
>> +
>> +#include <common.h>
>> +#include <spi.h>
>> +#include <spi_flash.h>
>> +
>> +#include "sf_internal.h"
>> +
>> +/* Exclude chip names for SPL to save space */
>> +#if !CONFIG_IS_ENABLED(SPI_FLASH_TINY)
>> +#define INFO_NAME(_name) .name = _name,
>> +#else
>> +#define INFO_NAME(_name)
>> +#endif
>> +
>> +/* Used when the "_ext_id" is two bytes at most */
>> +#define INFO(_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
>> + INFO_NAME(_name) \
>> + .id = { \
>> + ((_jedec_id) >> 16) & 0xff, \
>> + ((_jedec_id) >> 8) & 0xff, \
>> + (_jedec_id) & 0xff, \
>> + ((_ext_id) >> 8) & 0xff, \
>> + (_ext_id) & 0xff, \
>> + }, \
>> + .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \
>> + .sector_size = (_sector_size), \
>> + .n_sectors = (_n_sectors), \
>> + .page_size = 256, \
>> + .flags = (_flags),
>> +
>> +#define INFO6(_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
>> + INFO_NAME(_name) \
>> + .id = { \
>> + ((_jedec_id) >> 16) & 0xff, \
>> + ((_jedec_id) >> 8) & 0xff, \
>> + (_jedec_id) & 0xff, \
>> + ((_ext_id) >> 16) & 0xff, \
>> + ((_ext_id) >> 8) & 0xff, \
>> + (_ext_id) & 0xff, \
>> + }, \
>> + .id_len = 6, \
>> + .sector_size = (_sector_size), \
>> + .n_sectors = (_n_sectors), \
>> + .page_size = 256, \
>> + .flags = (_flags),
>> +
>> +/* NOTE: double check command sets and memory organization when you add
>> + * more nor chips. This current list focusses on newer chips, which
>> + * have been converging on command sets which including JEDEC ID.
>> + *
>> + * All newly added entries should describe *hardware* and should use SECT_4K
>> + * (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage
>> + * scenarios excluding small sectors there is config option that can be
>> + * disabled: CONFIG_MTD_SPI_NOR_USE_4K_SECTORS.
>> + * For historical (and compatibility) reasons (before we got above config) some
>> + * old entries may be missing 4K flag.
>> + */
>> +const struct flash_info spi_nor_ids[] = {
>> +#ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */
>> + /* Atmel -- some are (confusingly) marketed as "DataFlash" */
>> + { INFO("at26df321", 0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
>> + { INFO("at25df321a", 0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
>> +
>> + { INFO("at45db011d", 0x1f2200, 0, 64 * 1024, 4, SECT_4K) },
>> + { INFO("at45db021d", 0x1f2300, 0, 64 * 1024, 8, SECT_4K) },
>> + { INFO("at45db041d", 0x1f2400, 0, 64 * 1024, 8, SECT_4K) },
>> + { INFO("at45db081d", 0x1f2500, 0, 64 * 1024, 16, SECT_4K) },
>> + { INFO("at45db161d", 0x1f2600, 0, 64 * 1024, 32, SECT_4K) },
>> + { INFO("at45db321d", 0x1f2700, 0, 64 * 1024, 64, SECT_4K) },
>> + { INFO("at45db641d", 0x1f2800, 0, 64 * 1024, 128, SECT_4K) },
>> + { INFO("at26df081a", 0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
>> +#endif
>> +#ifdef CONFIG_SPI_FLASH_EON /* EON */
>> + /* EON -- en25xxx */
>> + { INFO("en25q32b", 0x1c3016, 0, 64 * 1024, 64, 0) },
>> + { INFO("en25q64", 0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
>> + { INFO("en25qh128", 0x1c7018, 0, 64 * 1024, 256, 0) },
>> + { INFO("en25s64", 0x1c3817, 0, 64 * 1024, 128, SECT_4K) },
>> +#endif
>> +#ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
>> + /* GigaDevice */
>> + {
>> + INFO("gd25q16", 0xc84015, 0, 64 * 1024, 32,
>> + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
>> + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
>> + },
>> + {
>> + INFO("gd25q32", 0xc84016, 0, 64 * 1024, 64,
>> + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
>> + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
>> + },
>> + {
>> + INFO("gd25lq32", 0xc86016, 0, 64 * 1024, 64,
>> + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
>> + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
>> + },
>> + {
>> + INFO("gd25q64", 0xc84017, 0, 64 * 1024, 128,
>> + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
>> + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
>> + },
>> +#endif
>> +#ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */
>> + /* ISSI */
>> + { INFO("is25lq040b", 0x9d4013, 0, 64 * 1024, 8,
>> + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>> + { INFO("is25lp032", 0x9d6016, 0, 64 * 1024, 64, 0) },
>> + { INFO("is25lp064", 0x9d6017, 0, 64 * 1024, 128, 0) },
>> + { INFO("is25lp128", 0x9d6018, 0, 64 * 1024, 256,
>> + SECT_4K | SPI_NOR_DUAL_READ) },
>> + { INFO("is25lp256", 0x9d6019, 0, 64 * 1024, 512,
>> + SECT_4K | SPI_NOR_DUAL_READ) },
>> + { INFO("is25wp032", 0x9d7016, 0, 64 * 1024, 64,
>> + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>> + { INFO("is25wp064", 0x9d7017, 0, 64 * 1024, 128,
>> + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>> + { INFO("is25wp128", 0x9d7018, 0, 64 * 1024, 256,
>> + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>> +#endif
>> +#ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
>> + /* Macronix */
>> + { INFO("mx25l2005a", 0xc22012, 0, 64 * 1024, 4, SECT_4K) },
>> + { INFO("mx25l4005a", 0xc22013, 0, 64 * 1024, 8, SECT_4K) },
>> + { INFO("mx25l8005", 0xc22014, 0, 64 * 1024, 16, 0) },
>> + { INFO("mx25l1606e", 0xc22015, 0, 64 * 1024, 32, SECT_4K) },
>> + { INFO("mx25l3205d", 0xc22016, 0, 64 * 1024, 64, SECT_4K) },
>> + { INFO("mx25l6405d", 0xc22017, 0, 64 * 1024, 128, SECT_4K) },
>> + { INFO("mx25u2033e", 0xc22532, 0, 64 * 1024, 4, SECT_4K) },
>> + { INFO("mx25u1635e", 0xc22535, 0, 64 * 1024, 32, SECT_4K) },
>> + { INFO("mx25u6435f", 0xc22537, 0, 64 * 1024, 128, SECT_4K) },
>> + { INFO("mx25l12805d", 0xc22018, 0, 64 * 1024, 256, 0) },
>> + { INFO("mx25l12855e", 0xc22618, 0, 64 * 1024, 256, 0) },
>> + { INFO("mx25l25635e", 0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>> + { INFO("mx25u25635f", 0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) },
>> + { INFO("mx25l25655e", 0xc22619, 0, 64 * 1024, 512, 0) },
>> + { INFO("mx66l51235l", 0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
>> + { INFO("mx66u51235f", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
>> + { INFO("mx66l1g45g", 0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>> + { INFO("mx25l1633e", 0xc22415, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) },
>> +#endif
>> +
>> +#ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
>> + /* Micron */
>> + { INFO("n25q016a", 0x20bb15, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_QUAD_READ) },
>> + { INFO("n25q032", 0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
>> + { INFO("n25q032a", 0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
>> + { INFO("n25q064", 0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
>> + { INFO("n25q064a", 0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
>> + { INFO("n25q128a11", 0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
>> + { INFO("n25q128a13", 0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
>> + { INFO("n25q256a", 0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>> + { INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
>> + { INFO("n25q512a", 0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
>> + { INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
>> + { INFO("n25q00", 0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
>> + { INFO("n25q00a", 0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
>> + { INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
>> +#endif
>> +#ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */
>> + /* Spansion/Cypress -- single (large) sector size only, at least
>> + * for the chips listed here (without boot sectors).
>> + */
>> + { INFO("s25sl032p", 0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>> + { INFO("s25sl064p", 0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>> + { INFO("s25fl256s0", 0x010219, 0x4d00, 256 * 1024, 128, USE_CLSR) },
>> + { INFO("s25fl256s1", 0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
>> + { INFO6("s25fl512s", 0x010220, 0x4d0081, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
>> + { INFO("s25fl512s_256k", 0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
>> + { INFO("s25fl512s_64k", 0x010220, 0x4d01, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
>> + { INFO("s25fl512s_512k", 0x010220, 0x4f00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
>> + { INFO("s25sl12800", 0x012018, 0x0300, 256 * 1024, 64, 0) },
>> + { INFO("s25sl12801", 0x012018, 0x0301, 64 * 1024, 256, 0) },
>> + { INFO6("s25fl128s", 0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
>> + { INFO("s25fl129p0", 0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
>> + { INFO("s25fl129p1", 0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
>> + { INFO("s25sl008a", 0x010213, 0, 64 * 1024, 16, 0) },
>> + { INFO("s25sl016a", 0x010214, 0, 64 * 1024, 32, 0) },
>> + { INFO("s25sl032a", 0x010215, 0, 64 * 1024, 64, 0) },
>> + { INFO("s25sl064a", 0x010216, 0, 64 * 1024, 128, 0) },
>> + { INFO("s25fl116k", 0x014015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>> + { INFO("s25fl164k", 0x014017, 0, 64 * 1024, 128, SECT_4K) },
>> + { INFO("s25fl208k", 0x014014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ) },
>> + { INFO("s25fl128l", 0x016018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
>> +#endif
>> +#ifdef CONFIG_SPI_FLASH_SST /* SST */
>> + /* SST -- large erase sizes are "overlays", "sectors" are 4K */
>> + { INFO("sst25vf040b", 0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
>> + { INFO("sst25vf080b", 0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
>> + { INFO("sst25vf016b", 0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) },
>> + { INFO("sst25vf032b", 0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) },
>> + { INFO("sst25vf064c", 0xbf254b, 0, 64 * 1024, 128, SECT_4K) },
>> + { INFO("sst25wf512", 0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) },
>> + { INFO("sst25wf010", 0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) },
>> + { INFO("sst25wf020", 0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) },
>> + { INFO("sst25wf020a", 0x621612, 0, 64 * 1024, 4, SECT_4K) },
>> + { INFO("sst25wf040b", 0x621613, 0, 64 * 1024, 8, SECT_4K) },
>> + { INFO("sst25wf040", 0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
>> + { INFO("sst25wf080", 0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
>> + { INFO("sst26vf064b", 0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>> + { INFO("sst26wf016", 0xbf2651, 0, 64 * 1024, 32, SECT_4K) },
>> + { INFO("sst26wf032", 0xbf2622, 0, 64 * 1024, 64, SECT_4K) },
>> + { INFO("sst26wf064", 0xbf2643, 0, 64 * 1024, 128, SECT_4K) },
>> +#endif
>> +#ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
>> + /* ST Microelectronics -- newer production may have feature updates */
>> + { INFO("m25p10", 0x202011, 0, 32 * 1024, 4, 0) },
>> + { INFO("m25p20", 0x202012, 0, 64 * 1024, 4, 0) },
>> + { INFO("m25p40", 0x202013, 0, 64 * 1024, 8, 0) },
>> + { INFO("m25p80", 0x202014, 0, 64 * 1024, 16, 0) },
>> + { INFO("m25p16", 0x202015, 0, 64 * 1024, 32, 0) },
>> + { INFO("m25p32", 0x202016, 0, 64 * 1024, 64, 0) },
>> + { INFO("m25p64", 0x202017, 0, 64 * 1024, 128, 0) },
>> + { INFO("m25p128", 0x202018, 0, 256 * 1024, 64, 0) },
>> + { INFO("m25pe16", 0x208015, 0, 64 * 1024, 32, SECT_4K) },
>> + { INFO("m25px16", 0x207115, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>> + { INFO("m25px64", 0x207117, 0, 64 * 1024, 128, 0) },
>> +#endif
>> +#ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */
>> + /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
>> + { INFO("w25p80", 0xef2014, 0x0, 64 * 1024, 16, 0) },
>> + { INFO("w25p16", 0xef2015, 0x0, 64 * 1024, 32, 0) },
>> + { INFO("w25p32", 0xef2016, 0x0, 64 * 1024, 64, 0) },
>> + { INFO("w25x05", 0xef3010, 0, 64 * 1024, 1, SECT_4K) },
>> + { INFO("w25x40", 0xef3013, 0, 64 * 1024, 8, SECT_4K) },
>> + { INFO("w25x16", 0xef3015, 0, 64 * 1024, 32, SECT_4K) },
>> + {
>> + INFO("w25q16dw", 0xef6015, 0, 64 * 1024, 32,
>> + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
>> + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
>> + },
>> + { INFO("w25x32", 0xef3016, 0, 64 * 1024, 64, SECT_4K) },
>> + { INFO("w25q20cl", 0xef4012, 0, 64 * 1024, 4, SECT_4K) },
>> + { INFO("w25q20bw", 0xef5012, 0, 64 * 1024, 4, SECT_4K) },
>> + { INFO("w25q20ew", 0xef6012, 0, 64 * 1024, 4, SECT_4K) },
>> + { INFO("w25q32", 0xef4016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>> + {
>> + INFO("w25q32dw", 0xef6016, 0, 64 * 1024, 64,
>> + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
>> + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
>> + },
>> + {
>> + INFO("w25q32jv", 0xef7016, 0, 64 * 1024, 64,
>> + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
>> + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
>> + },
>> + { INFO("w25x64", 0xef3017, 0, 64 * 1024, 128, SECT_4K) },
>> + {
>> + INFO("w25q64dw", 0xef6017, 0, 64 * 1024, 128,
>> + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
>> + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
>> + },
>> + {
>> + INFO("w25q64jv", 0xef7017, 0, 64 * 1024, 128,
>> + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
>> + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
>> + },
>> + {
>> + INFO("w25q128fw", 0xef6018, 0, 64 * 1024, 256,
>> + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
>> + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
>> + },
>> + {
>> + INFO("w25q128jv", 0xef7018, 0, 64 * 1024, 256,
>> + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
>> + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
>> + },
>> + {
>> + INFO("w25q256fw", 0xef6019, 0, 64 * 1024, 512,
>> + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
>> + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
>> + },
>> + {
>> + INFO("w25q256jw", 0xef7019, 0, 64 * 1024, 512,
>> + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
>> + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
>> + },
>> + { INFO("w25q80", 0xef5014, 0, 64 * 1024, 16, SECT_4K) },
>> + { INFO("w25q80bl", 0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>> + { INFO("w25q16cl", 0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>> + { INFO("w25q64cv", 0xef4017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>> + { INFO("w25q128", 0xef4018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>> + { INFO("w25q256", 0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>> +#endif
>> +#ifdef CONFIG_SPI_FLASH_XMC
>> + /* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */
>> + { INFO("XM25QH64A", 0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>> + { INFO("XM25QH128A", 0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>> +#endif
>> + { },
>> +};
>> diff --git a/drivers/mtd/spi/spi-nor-tiny.c b/drivers/mtd/spi/spi-nor-tiny.c
>> new file mode 100644
>> index 000000000000..c3075d44bea8
>> --- /dev/null
>> +++ b/drivers/mtd/spi/spi-nor-tiny.c
>> @@ -0,0 +1,806 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Based on m25p80.c, by Mike Lavender (mike at steroidmicros.com), with
>> + * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
>> + *
>> + * Copyright (C) 2005, Intec Automation Inc.
>> + * Copyright (C) 2014, Freescale Semiconductor, Inc.
>> + *
>> + * Synced from Linux v4.19
>> + */
>> +
>> +#include <common.h>
>> +#include <linux/err.h>
>> +#include <linux/errno.h>
>> +#include <linux/log2.h>
>> +#include <linux/math64.h>
>> +#include <linux/sizes.h>
>> +
>> +#include <linux/mtd/mtd.h>
>> +#include <linux/mtd/spi-nor.h>
>> +#include <spi-mem.h>
>> +#include <spi.h>
>> +
>> +#include "sf_internal.h"
>> +
>> +/* Define max times to check status register before we give up. */
>> +
>> +/*
>> + * For everything but full-chip erase; probably could be much smaller, but kept
>> + * around for safety for now
>> + */
>> +
>> +#define HZ CONFIG_SYS_HZ
>> +
>> +#define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
>> +
>> +static int spi_nor_read_write_reg(struct spi_nor *nor, struct spi_mem_op
>> + *op, void *buf)
>> +{
>> + if (op->data.dir == SPI_MEM_DATA_IN)
>> + op->data.buf.in = buf;
>> + else
>> + op->data.buf.out = buf;
>> + return spi_mem_exec_op(nor->spi, op);
>> +}
>> +
>> +static int spi_nor_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len)
>> +{
>> + struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(code, 1),
>> + SPI_MEM_OP_NO_ADDR,
>> + SPI_MEM_OP_NO_DUMMY,
>> + SPI_MEM_OP_DATA_IN(len, NULL, 1));
>> + int ret;
>> +
>> + ret = spi_nor_read_write_reg(nor, &op, val);
>> + if (ret < 0)
>> + dev_dbg(&flash->spimem->spi->dev, "error %d reading %x\n", ret,
>> + code);
>> +
>> + return ret;
>> +}
>> +
>> +static int spi_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
>> +{
>> + struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 1),
>> + SPI_MEM_OP_NO_ADDR,
>> + SPI_MEM_OP_NO_DUMMY,
>> + SPI_MEM_OP_DATA_OUT(len, NULL, 1));
>> +
>> + return spi_nor_read_write_reg(nor, &op, buf);
>> +}
>> +
>> +static ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len,
>> + u_char *buf)
>> +{
>> + struct spi_mem_op op =
>> + SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 1),
>> + SPI_MEM_OP_ADDR(nor->addr_width, from, 1),
>> + SPI_MEM_OP_DUMMY(nor->read_dummy, 1),
>> + SPI_MEM_OP_DATA_IN(len, buf, 1));
>> + size_t remaining = len;
>> + int ret;
>> +
>> + /* get transfer protocols. */
>> + op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->read_proto);
>> + op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->read_proto);
>> + op.dummy.buswidth = op.addr.buswidth;
>> + op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto);
>> +
>> + /* convert the dummy cycles to the number of bytes */
>> + op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8;
>> +
>> + while (remaining) {
>> + op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX;
>> + ret = spi_mem_adjust_op_size(nor->spi, &op);
>> + if (ret)
>> + return ret;
>> +
>> + ret = spi_mem_exec_op(nor->spi, &op);
>> + if (ret)
>> + return ret;
>> +
>> + op.addr.val += op.data.nbytes;
>> + remaining -= op.data.nbytes;
>> + op.data.buf.in += op.data.nbytes;
>> + }
>> +
>> + return len;
>> +}
>> +
>> +#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
>> +/*
>> + * Read configuration register, returning its value in the
>> + * location. Return the configuration register value.
>> + * Returns negative if error occurred.
>> + */
>> +static int read_cr(struct spi_nor *nor)
>> +{
>> + int ret;
>> + u8 val;
>> +
>> + ret = spi_nor_read_reg(nor, SPINOR_OP_RDCR, &val, 1);
>> + if (ret < 0) {
>> + dev_dbg(nor->dev, "error %d reading CR\n", ret);
>> + return ret;
>> + }
>> +
>> + return val;
>> +}
>> +#endif
>> +
>> +/*
>> + * Write status register 1 byte
>> + * Returns negative if error occurred.
>> + */
>> +static inline int write_sr(struct spi_nor *nor, u8 val)
>> +{
>> + nor->cmd_buf[0] = val;
>> + return spi_nor_write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1);
>> +}
>> +
>> +/*
>> + * Set write enable latch with Write Enable command.
>> + * Returns negative if error occurred.
>> + */
>> +static inline int write_enable(struct spi_nor *nor)
>> +{
>> + return spi_nor_write_reg(nor, SPINOR_OP_WREN, NULL, 0);
>> +}
>> +
>> +/*
>> + * Send write disable instruction to the chip.
>> + */
>> +static inline int write_disable(struct spi_nor *nor)
>> +{
>> + return spi_nor_write_reg(nor, SPINOR_OP_WRDI, NULL, 0);
>> +}
>> +
>> +static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
>> +{
>> + return mtd->priv;
>> +}
>> +
>> +static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
>> +{
>> + size_t i;
>> +
>> + for (i = 0; i < size; i++)
>> + if (table[i][0] == opcode)
>> + return table[i][1];
>> +
>> + /* No conversion found, keep input op code. */
>> + return opcode;
>> +}
>> +
>> +static inline u8 spi_nor_convert_3to4_read(u8 opcode)
>> +{
>> + static const u8 spi_nor_3to4_read[][2] = {
>> + { SPINOR_OP_READ, SPINOR_OP_READ_4B },
>> + { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B },
>> + { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B },
>> + { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
>> + { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
>> + { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
>> + };
>> +
>> + return spi_nor_convert_opcode(opcode, spi_nor_3to4_read,
>> + ARRAY_SIZE(spi_nor_3to4_read));
>> +}
>> +
>> +static void spi_nor_set_4byte_opcodes(struct spi_nor *nor,
>> + const struct flash_info *info)
>> +{
>> + nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode);
>> +}
>> +
>> +/* Enable/disable 4-byte addressing mode. */
>> +static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info,
>> + int enable)
>> +{
>> + int status;
>> + bool need_wren = false;
>> + u8 cmd;
>> +
>> + switch (JEDEC_MFR(info)) {
>> + case SNOR_MFR_MICRON:
>> + /* Some Micron need WREN command; all will accept it */
>> + need_wren = true;
>> + case SNOR_MFR_MACRONIX:
>> + case SNOR_MFR_WINBOND:
>> + if (need_wren)
>> + write_enable(nor);
>> +
>> + cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
>> + status = spi_nor_write_reg(nor, cmd, NULL, 0);
>> + if (need_wren)
>> + write_disable(nor);
>> +
>> + if (!status && !enable &&
>> + JEDEC_MFR(info) == SNOR_MFR_WINBOND) {
>> + /*
>> + * On Winbond W25Q256FV, leaving 4byte mode causes
>> + * the Extended Address Register to be set to 1, so all
>> + * 3-byte-address reads come from the second 16M.
>> + * We must clear the register to enable normal behavior.
>> + */
>> + write_enable(nor);
>> + nor->cmd_buf[0] = 0;
>> + spi_nor_write_reg(nor, SPINOR_OP_WREAR,
>> + nor->cmd_buf, 1);
>> + write_disable(nor);
>> + }
>> +
>> + return status;
>> + default:
>> + /* Spansion style */
>> + nor->cmd_buf[0] = enable << 7;
>> + return spi_nor_write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1);
>> + }
>> +}
>> +
>> +#if defined(CONFIG_SPI_FLASH_SPANSION) || \
>> + defined(CONFIG_SPI_FLASH_WINBOND) || \
>> + defined(CONFIG_SPI_FLASH_MACRONIX)
>> +/*
>> + * Read the status register, returning its value in the location
>> + * Return the status register value.
>> + * Returns negative if error occurred.
>> + */
>> +static int read_sr(struct spi_nor *nor)
>> +{
>> + int ret;
>> + u8 val;
>> +
>> + ret = spi_nor_read_reg(nor, SPINOR_OP_RDSR, &val, 1);
>> + if (ret < 0) {
>> + pr_debug("error %d reading SR\n", (int)ret);
>> + return ret;
>> + }
>> +
>> + return val;
>> +}
>> +
>> +/*
>> + * Read the flag status register, returning its value in the location
>> + * Return the status register value.
>> + * Returns negative if error occurred.
>> + */
>> +static int read_fsr(struct spi_nor *nor)
>> +{
>> + int ret;
>> + u8 val;
>> +
>> + ret = spi_nor_read_reg(nor, SPINOR_OP_RDFSR, &val, 1);
>> + if (ret < 0) {
>> + pr_debug("error %d reading FSR\n", ret);
>> + return ret;
>> + }
>> +
>> + return val;
>> +}
>> +
>> +static int spi_nor_sr_ready(struct spi_nor *nor)
>> +{
>> + int sr = read_sr(nor);
>> +
>> + if (sr < 0)
>> + return sr;
>> +
>> + return !(sr & SR_WIP);
>> +}
>> +
>> +static int spi_nor_fsr_ready(struct spi_nor *nor)
>> +{
>> + int fsr = read_fsr(nor);
>> +
>> + if (fsr < 0)
>> + return fsr;
>> + return fsr & FSR_READY;
>> +}
>> +
>> +static int spi_nor_ready(struct spi_nor *nor)
>> +{
>> + int sr, fsr;
>> +
>> + sr = spi_nor_sr_ready(nor);
>> + if (sr < 0)
>> + return sr;
>> + fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
>> + if (fsr < 0)
>> + return fsr;
>> + return sr && fsr;
>> +}
>> +
>> +/*
>> + * Service routine to read status register until ready, or timeout occurs.
>> + * Returns non-zero if error.
>> + */
>> +static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
>> + unsigned long timeout)
>> +{
>> + unsigned long timebase;
>> + int ret;
>> +
>> + timebase = get_timer(0);
>> +
>> + while (get_timer(timebase) < timeout) {
>> + ret = spi_nor_ready(nor);
>> + if (ret < 0)
>> + return ret;
>> + if (ret)
>> + return 0;
>> + }
>> +
>> + dev_err(nor->dev, "flash operation timed out\n");
>> +
>> + return -ETIMEDOUT;
>> +}
>> +
>> +static int spi_nor_wait_till_ready(struct spi_nor *nor)
>> +{
>> + return spi_nor_wait_till_ready_with_timeout(nor,
>> + DEFAULT_READY_WAIT_JIFFIES);
>> +}
>> +#endif /* CONFIG_SPI_FLASH_SPANSION */
>> +
>> +/*
>> + * Erase an address range on the nor chip. The address range may extend
>> + * one or more erase sectors. Return an error is there is a problem erasing.
>> + */
>> +static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
>> +{
>> + return -ENOTSUPP;
>> +}
>> +
>> +static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
>> +{
>> + int tmp;
>> + u8 id[SPI_NOR_MAX_ID_LEN];
>> + const struct flash_info *info;
>> +
>> + tmp = spi_nor_read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
>> + if (tmp < 0) {
>> + dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp);
>> + return ERR_PTR(tmp);
>> + }
>> +
>> + info = spi_nor_ids;
>> + for (; info->sector_size != 0; info++) {
>> + if (info->id_len) {
>> + if (!memcmp(info->id, id, info->id_len))
>> + return info;
>> + }
>> + }
>> + dev_dbg(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
>> + id[0], id[1], id[2]);
>> + return ERR_PTR(-ENODEV);
>> +}
>> +
>> +static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
>> + size_t *retlen, u_char *buf)
>> +{
>> + struct spi_nor *nor = mtd_to_spi_nor(mtd);
>> + int ret;
>> +
>> + dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
>> +
>> + while (len) {
>> + loff_t addr = from;
>> +
>> + ret = spi_nor_read_data(nor, addr, len, buf);
>> + if (ret == 0) {
>> + /* We shouldn't see 0-length reads */
>> + ret = -EIO;
>> + goto read_err;
>> + }
>> + if (ret < 0)
>> + goto read_err;
>> +
>> + *retlen += ret;
>> + buf += ret;
>> + from += ret;
>> + len -= ret;
>> + }
>> + ret = 0;
>> +
>> +read_err:
>> + return ret;
>> +}
>> +
>> +/*
>> + * Write an address range to the nor chip. Data must be written in
>> + * FLASH_PAGESIZE chunks. The address range may be any size provided
>> + * it is within the physical boundaries.
>> + */
>> +static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
>> + size_t *retlen, const u_char *buf)
>> +{
>> + return -ENOTSUPP;
>> +}
>> +
>> +#ifdef CONFIG_SPI_FLASH_MACRONIX
>> +/**
>> + * macronix_quad_enable() - set QE bit in Status Register.
>> + * @nor: pointer to a 'struct spi_nor'
>> + *
>> + * Set the Quad Enable (QE) bit in the Status Register.
>> + *
>> + * bit 6 of the Status Register is the QE bit for Macronix like QSPI memories.
>> + *
>> + * Return: 0 on success, -errno otherwise.
>> + */
>> +static int macronix_quad_enable(struct spi_nor *nor)
>> +{
>> + int ret, val;
>> +
>> + val = read_sr(nor);
>> + if (val < 0)
>> + return val;
>> + if (val & SR_QUAD_EN_MX)
>> + return 0;
>> +
>> + write_enable(nor);
>> +
>> + write_sr(nor, val | SR_QUAD_EN_MX);
>> +
>> + ret = spi_nor_wait_till_ready(nor);
>> + if (ret)
>> + return ret;
>> +
>> + ret = read_sr(nor);
>> + if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
>> + dev_err(nor->dev, "Macronix Quad bit not set\n");
>> + return -EINVAL;
>> + }
>> +
>> + return 0;
>> +}
>> +#endif
>> +
>> +#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
>> +/*
>> + * Write status Register and configuration register with 2 bytes
>> + * The first byte will be written to the status register, while the
>> + * second byte will be written to the configuration register.
>> + * Return negative if error occurred.
>> + */
>> +static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr)
>> +{
>> + int ret;
>> +
>> + write_enable(nor);
>> +
>> + ret = spi_nor_write_reg(nor, SPINOR_OP_WRSR, sr_cr, 2);
>> + if (ret < 0) {
>> + dev_dbg(nor->dev,
>> + "error while writing configuration register\n");
>> + return -EINVAL;
>> + }
>> +
>> + ret = spi_nor_wait_till_ready(nor);
>> + if (ret) {
>> + dev_dbg(nor->dev,
>> + "timeout while writing configuration register\n");
>> + return ret;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +/**
>> + * spansion_read_cr_quad_enable() - set QE bit in Configuration Register.
>> + * @nor: pointer to a 'struct spi_nor'
>> + *
>> + * Set the Quad Enable (QE) bit in the Configuration Register.
>> + * This function should be used with QSPI memories supporting the Read
>> + * Configuration Register (35h) instruction.
>> + *
>> + * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
>> + * memories.
>> + *
>> + * Return: 0 on success, -errno otherwise.
>> + */
>> +static int spansion_read_cr_quad_enable(struct spi_nor *nor)
>> +{
>> + u8 sr_cr[2];
>> + int ret;
>> +
>> + /* Check current Quad Enable bit value. */
>> + ret = read_cr(nor);
>> + if (ret < 0) {
>> + dev_dbg(dev, "error while reading configuration register\n");
>> + return -EINVAL;
>> + }
>> +
>> + if (ret & CR_QUAD_EN_SPAN)
>> + return 0;
>> +
>> + sr_cr[1] = ret | CR_QUAD_EN_SPAN;
>> +
>> + /* Keep the current value of the Status Register. */
>> + ret = read_sr(nor);
>> + if (ret < 0) {
>> + dev_dbg(dev, "error while reading status register\n");
>> + return -EINVAL;
>> + }
>> + sr_cr[0] = ret;
>> +
>> + ret = write_sr_cr(nor, sr_cr);
>> + if (ret)
>> + return ret;
>> +
>> + /* Read back and check it. */
>> + ret = read_cr(nor);
>> + if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
>> + dev_dbg(nor->dev, "Spansion Quad bit not set\n");
>> + return -EINVAL;
>> + }
>> +
>> + return 0;
>> +}
>> +#endif /* CONFIG_SPI_FLASH_SPANSION */
>> +
>> +struct spi_nor_read_command {
>> + u8 num_mode_clocks;
>> + u8 num_wait_states;
>> + u8 opcode;
>> + enum spi_nor_protocol proto;
>> +};
>> +
>> +enum spi_nor_read_command_index {
>> + SNOR_CMD_READ,
>> + SNOR_CMD_READ_FAST,
>> +
>> + /* Quad SPI */
>> + SNOR_CMD_READ_1_1_4,
>> +
>> + SNOR_CMD_READ_MAX
>> +};
>> +
>> +struct spi_nor_flash_parameter {
>> + struct spi_nor_hwcaps hwcaps;
>> + struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
>> +};
>> +
>> +static void
>> +spi_nor_set_read_settings(struct spi_nor_read_command *read,
>> + u8 num_mode_clocks,
>> + u8 num_wait_states,
>> + u8 opcode,
>> + enum spi_nor_protocol proto)
>> +{
>> + read->num_mode_clocks = num_mode_clocks;
>> + read->num_wait_states = num_wait_states;
>> + read->opcode = opcode;
>> + read->proto = proto;
>> +}
>> +
>> +static int spi_nor_init_params(struct spi_nor *nor,
>> + const struct flash_info *info,
>> + struct spi_nor_flash_parameter *params)
>> +{
>> + /* (Fast) Read settings. */
>> + params->hwcaps.mask = SNOR_HWCAPS_READ;
>> + spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ],
>> + 0, 0, SPINOR_OP_READ,
>> + SNOR_PROTO_1_1_1);
>> +
>> + if (!(info->flags & SPI_NOR_NO_FR)) {
>> + params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
>> + spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_FAST],
>> + 0, 8, SPINOR_OP_READ_FAST,
>> + SNOR_PROTO_1_1_1);
>> + }
>> +
>> + if (info->flags & SPI_NOR_QUAD_READ) {
>> + params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
>> + spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_4],
>> + 0, 8, SPINOR_OP_READ_1_1_4,
>> + SNOR_PROTO_1_1_4);
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static int spi_nor_select_read(struct spi_nor *nor,
>> + const struct spi_nor_flash_parameter *params,
>> + u32 shared_hwcaps)
>> +{
>> + int best_match = shared_hwcaps & SNOR_HWCAPS_READ_MASK;
>> + int cmd;
>> + const struct spi_nor_read_command *read;
>> +
>> + if (best_match < 0)
>> + return -EINVAL;
>> +
>> + if (best_match & SNOR_HWCAPS_READ_1_1_4)
>> + cmd = SNOR_CMD_READ_1_1_4;
>> + else
>> + cmd = SNOR_CMD_READ;
>> +
>> + read = &params->reads[cmd];
>> + nor->read_opcode = read->opcode;
>> + nor->read_proto = read->proto;
>> +
>> + /*
>> + * In the spi-nor framework, we don't need to make the difference
>> + * between mode clock cycles and wait state clock cycles.
>> + * Indeed, the value of the mode clock cycles is used by a QSPI
>> + * flash memory to know whether it should enter or leave its 0-4-4
>> + * (Continuous Read / XIP) mode.
>> + * eXecution In Place is out of the scope of the mtd sub-system.
>> + * Hence we choose to merge both mode and wait state clock cycles
>> + * into the so called dummy clock cycles.
>> + */
>> + nor->read_dummy = read->num_mode_clocks + read->num_wait_states;
>> + return 0;
>> +}
>> +
>> +static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info,
>> + const struct spi_nor_flash_parameter *params,
>> + const struct spi_nor_hwcaps *hwcaps)
>> +{
>> + u32 shared_mask;
>> + int err;
>> +
>> + /*
>> + * Keep only the hardware capabilities supported by both the SPI
>> + * controller and the SPI flash memory.
>> + */
>> + shared_mask = hwcaps->mask & params->hwcaps.mask;
>> +
>> + /* Select the (Fast) Read command. */
>> + err = spi_nor_select_read(nor, params, shared_mask);
>> + if (err) {
>> + dev_dbg(nor->dev,
>> + "can't select read settings supported by both the SPI controller and memory.\n");
>> + return err;
>> + }
>> +
>> + /* Enable Quad I/O if needed. */
>> + if (spi_nor_get_protocol_width(nor->read_proto) == 4) {
>> + switch (JEDEC_MFR(info)) {
>> +#ifdef CONFIG_SPI_FLASH_MACRONIX
>> + case SNOR_MFR_MACRONIX:
>> + err = macronix_quad_enable(nor);
>> + break;
>> +#endif
>> + case SNOR_MFR_MICRON:
>> + break;
>> +
>> + default:
>> +#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
>> + /* Kept only for backward compatibility purpose. */
>> + err = spansion_read_cr_quad_enable(nor);
>> +#endif
>> + break;
>> + }
>> + }
>> + if (err) {
>> + dev_dbg(nor->dev, "quad mode not supported\n");
>> + return err;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static int spi_nor_init(struct spi_nor *nor)
>> +{
>> + if (nor->addr_width == 4 &&
>> + (JEDEC_MFR(nor->info) != SNOR_MFR_SPANSION) &&
>> + !(nor->info->flags & SPI_NOR_4B_OPCODES)) {
>> + /*
>> + * If the RESET# pin isn't hooked up properly, or the system
>> + * otherwise doesn't perform a reset command in the boot
>> + * sequence, it's impossible to 100% protect against unexpected
>> + * reboots (e.g., crashes). Warn the user (or hopefully, system
>> + * designer) that this is bad.
>> + */
>> + if (nor->flags & SNOR_F_BROKEN_RESET)
>> + printf("enabling reset hack; may not recover from unexpected reboots\n");
>> + set_4byte(nor, nor->info, 1);
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +int spi_nor_scan(struct spi_nor *nor)
>> +{
>> + struct spi_nor_flash_parameter params;
>> + const struct flash_info *info = NULL;
>> + struct mtd_info *mtd = &nor->mtd;
>> + struct spi_nor_hwcaps hwcaps = {
>> + .mask = SNOR_HWCAPS_READ |
>> + SNOR_HWCAPS_READ_FAST
>> + };
>> + struct spi_slave *spi = nor->spi;
>> + int ret;
>> +
>> + /* Reset SPI protocol for all commands. */
>> + nor->reg_proto = SNOR_PROTO_1_1_1;
>> + nor->read_proto = SNOR_PROTO_1_1_1;
>> + nor->write_proto = SNOR_PROTO_1_1_1;
>> +
>> + if (spi->mode & SPI_RX_QUAD)
>> + hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
>> +
>> + info = spi_nor_read_id(nor);
>> + if (IS_ERR_OR_NULL(info))
>> + return -ENOENT;
>> + /* Parse the Serial Flash Discoverable Parameters table. */
>> + ret = spi_nor_init_params(nor, info, &params);
>> + if (ret)
>> + return ret;
>> +
>> + mtd->name = "spi-flash";
>> + mtd->priv = nor;
>> + mtd->type = MTD_NORFLASH;
>> + mtd->writesize = 1;
>> + mtd->flags = MTD_CAP_NORFLASH;
>> + mtd->size = info->sector_size * info->n_sectors;
>> + mtd->_erase = spi_nor_erase;
>> + mtd->_read = spi_nor_read;
>> + mtd->_write = spi_nor_write;
>> +
>> + nor->size = mtd->size;
>> +
>> + if (info->flags & USE_FSR)
>> + nor->flags |= SNOR_F_USE_FSR;
>> + if (info->flags & USE_CLSR)
>> + nor->flags |= SNOR_F_USE_CLSR;
>> +
>> + if (info->flags & SPI_NOR_NO_FR)
>> + params.hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
>> +
>> + /*
>> + * Configure the SPI memory:
>> + * - select op codes for (Fast) Read, Page Program and Sector Erase.
>> + * - set the number of dummy cycles (mode cycles + wait states).
>> + * - set the SPI protocols for register and memory accesses.
>> + * - set the Quad Enable bit if needed (required by SPI x-y-4 protos).
>> + */
>> + ret = spi_nor_setup(nor, info, &params, &hwcaps);
>> + if (ret)
>> + return ret;
>> +
>> + if (nor->addr_width) {
>> + /* already configured from SFDP */
>> + } else if (info->addr_width) {
>> + nor->addr_width = info->addr_width;
>> + } else if (mtd->size > 0x1000000) {
>> + /* enable 4-byte addressing if the device exceeds 16MiB */
>> + nor->addr_width = 4;
>> + if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
>> + info->flags & SPI_NOR_4B_OPCODES)
>> + spi_nor_set_4byte_opcodes(nor, info);
>> + } else {
>> + nor->addr_width = 3;
>> + }
>> +
>> + if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
>> + dev_dbg(dev, "address width is too large: %u\n",
>> + nor->addr_width);
>> + return -EINVAL;
>> + }
>> +
>> + /* Send all the required SPI flash commands to initialize device */
>> + nor->info = info;
>> + ret = spi_nor_init(nor);
>> + if (ret)
>> + return ret;
>> +
>> + return 0;
>> +}
>> +EXPORT_SYMBOL_GPL(spi_nor_scan);
>> +
>> +/* U-Boot specific functions, need to extend MTD to support these */
>> +int spi_flash_cmd_get_sw_write_prot(struct spi_nor *nor)
>> +{
>> + return -ENOTSUPP;
>> +}
>> +
>> +MODULE_LICENSE("GPL");
>> +MODULE_AUTHOR("Huang Shijie <shijie8@gmail.com>");
>> +MODULE_AUTHOR("Mike Lavender");
>> +MODULE_DESCRIPTION("framework for SPI NOR");
>> diff --git a/drivers/mtd/spi/spi-nor.c b/drivers/mtd/spi/spi-nor.c
>> index a192087882a1..80e6c03bd100 100644
>> --- a/drivers/mtd/spi/spi-nor.c
>> +++ b/drivers/mtd/spi/spi-nor.c
>> @@ -823,284 +823,26 @@ static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
>> return ret;
>> }
>>
>> -/* Used when the "_ext_id" is two bytes at most */
>> -#define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
>> - .id = { \
>> - ((_jedec_id) >> 16) & 0xff, \
>> - ((_jedec_id) >> 8) & 0xff, \
>> - (_jedec_id) & 0xff, \
>> - ((_ext_id) >> 8) & 0xff, \
>> - (_ext_id) & 0xff, \
>> - }, \
>> - .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \
>> - .sector_size = (_sector_size), \
>> - .n_sectors = (_n_sectors), \
>> - .page_size = 256, \
>> - .flags = (_flags),
>> -
>> -#define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
>> - .id = { \
>> - ((_jedec_id) >> 16) & 0xff, \
>> - ((_jedec_id) >> 8) & 0xff, \
>> - (_jedec_id) & 0xff, \
>> - ((_ext_id) >> 16) & 0xff, \
>> - ((_ext_id) >> 8) & 0xff, \
>> - (_ext_id) & 0xff, \
>> - }, \
>> - .id_len = 6, \
>> - .sector_size = (_sector_size), \
>> - .n_sectors = (_n_sectors), \
>> - .page_size = 256, \
>> - .flags = (_flags),
>> -
>> -/* NOTE: double check command sets and memory organization when you add
>> - * more nor chips. This current list focusses on newer chips, which
>> - * have been converging on command sets which including JEDEC ID.
>> - *
>> - * All newly added entries should describe *hardware* and should use SECT_4K
>> - * (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage
>> - * scenarios excluding small sectors there is config option that can be
>> - * disabled: CONFIG_MTD_SPI_NOR_USE_4K_SECTORS.
>> - * For historical (and compatibility) reasons (before we got above config) some
>> - * old entries may be missing 4K flag.
>> - */
>> -const struct flash_info spi_nor_ids[] = {
>> -#ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */
>> - /* Atmel -- some are (confusingly) marketed as "DataFlash" */
>> - { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
>> - { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
>> -
>> - { "at45db011d", INFO(0x1f2200, 0, 64 * 1024, 4, SECT_4K) },
>> - { "at45db021d", INFO(0x1f2300, 0, 64 * 1024, 8, SECT_4K) },
>> - { "at45db041d", INFO(0x1f2400, 0, 64 * 1024, 8, SECT_4K) },
>> - { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) },
>> - { "at45db161d", INFO(0x1f2600, 0, 64 * 1024, 32, SECT_4K) },
>> - { "at45db321d", INFO(0x1f2700, 0, 64 * 1024, 64, SECT_4K) },
>> - { "at45db641d", INFO(0x1f2800, 0, 64 * 1024, 128, SECT_4K) },
>> - { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
>> -#endif
>> -#ifdef CONFIG_SPI_FLASH_EON /* EON */
>> - /* EON -- en25xxx */
>> - { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) },
>> - { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
>> - { "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, 0) },
>> - { "en25s64", INFO(0x1c3817, 0, 64 * 1024, 128, SECT_4K) },
>> -#endif
>> -#ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
>> - /* GigaDevice */
>> - {
>> - "gd25q16", INFO(0xc84015, 0, 64 * 1024, 32,
>> - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
>> - SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
>> - },
>> - {
>> - "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64,
>> - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
>> - SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
>> - },
>> - {
>> - "gd25lq32", INFO(0xc86016, 0, 64 * 1024, 64,
>> - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
>> - SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
>> - },
>> - {
>> - "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128,
>> - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
>> - SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
>> - },
>> -#endif
>> -#ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */
>> - /* ISSI */
>> - { "is25lq040b", INFO(0x9d4013, 0, 64 * 1024, 8,
>> - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>> - { "is25lp032", INFO(0x9d6016, 0, 64 * 1024, 64, 0) },
>> - { "is25lp064", INFO(0x9d6017, 0, 64 * 1024, 128, 0) },
>> - { "is25lp128", INFO(0x9d6018, 0, 64 * 1024, 256,
>> - SECT_4K | SPI_NOR_DUAL_READ) },
>> - { "is25lp256", INFO(0x9d6019, 0, 64 * 1024, 512,
>> - SECT_4K | SPI_NOR_DUAL_READ) },
>> - { "is25wp032", INFO(0x9d7016, 0, 64 * 1024, 64,
>> - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>> - { "is25wp064", INFO(0x9d7017, 0, 64 * 1024, 128,
>> - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>> - { "is25wp128", INFO(0x9d7018, 0, 64 * 1024, 256,
>> - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>> -#endif
>> -#ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
>> - /* Macronix */
>> - { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) },
>> - { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },
>> - { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
>> - { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
>> - { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, SECT_4K) },
>> - { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) },
>> - { "mx25u2033e", INFO(0xc22532, 0, 64 * 1024, 4, SECT_4K) },
>> - { "mx25u1635e", INFO(0xc22535, 0, 64 * 1024, 32, SECT_4K) },
>> - { "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },
>> - { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
>> - { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
>> - { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>> - { "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) },
>> - { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
>> - { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
>> - { "mx66u51235f", INFO(0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
>> - { "mx66l1g45g", INFO(0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>> - { "mx25l1633e", INFO(0xc22415, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) },
>> -#endif
>> -
>> -#ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
>> - /* Micron */
>> - { "n25q016a", INFO(0x20bb15, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_QUAD_READ) },
>> - { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
>> - { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
>> - { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
>> - { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
>> - { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
>> - { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
>> - { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>> - { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
>> - { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
>> - { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
>> - { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
>> - { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
>> - { "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
>> -#endif
>> -#ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */
>> - /* Spansion/Cypress -- single (large) sector size only, at least
>> - * for the chips listed here (without boot sectors).
>> - */
>> - { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>> - { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>> - { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, USE_CLSR) },
>> - { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
>> - { "s25fl512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
>> - { "s25fl512s_256k", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
>> - { "s25fl512s_64k", INFO(0x010220, 0x4d01, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
>> - { "s25fl512s_512k", INFO(0x010220, 0x4f00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
>> - { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
>> - { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
>> - { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
>> - { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
>> - { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
>> - { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
>> - { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
>> - { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
>> - { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
>> - { "s25fl116k", INFO(0x014015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>> - { "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K) },
>> - { "s25fl208k", INFO(0x014014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ) },
>> - { "s25fl128l", INFO(0x016018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
>> -#endif
>> -#ifdef CONFIG_SPI_FLASH_SST /* SST */
>> - /* SST -- large erase sizes are "overlays", "sectors" are 4K */
>> - { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
>> - { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
>> - { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) },
>> - { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) },
>> - { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) },
>> - { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) },
>> - { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) },
>> - { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) },
>> - { "sst25wf020a", INFO(0x621612, 0, 64 * 1024, 4, SECT_4K) },
>> - { "sst25wf040b", INFO(0x621613, 0, 64 * 1024, 8, SECT_4K) },
>> - { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
>> - { "sst25wf080", INFO(0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
>> - { "sst26vf064b", INFO(0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>> - { "sst26wf016", INFO(0xbf2651, 0, 64 * 1024, 32, SECT_4K) },
>> - { "sst26wf032", INFO(0xbf2622, 0, 64 * 1024, 64, SECT_4K) },
>> - { "sst26wf064", INFO(0xbf2643, 0, 64 * 1024, 128, SECT_4K) },
>> -#endif
>> -#ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
>> - /* ST Microelectronics -- newer production may have feature updates */
>> - { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
>> - { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },
>> - { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },
>> - { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },
>> - { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },
>> - { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
>> - { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
>> - { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
>> - { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) },
>> - { "m25px16", INFO(0x207115, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>> - { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) },
>> -#endif
>> -#ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */
>> - /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
>> - { "w25x05", INFO(0xef3010, 0, 64 * 1024, 1, SECT_4K) },
>> - { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
>> - { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },
>> - { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
>> - { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
>> - { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
>> - {
>> - "w25q16dw", INFO(0xef6015, 0, 64 * 1024, 32,
>> - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
>> - SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
>> - },
>> - { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
>> - { "w25q20cl", INFO(0xef4012, 0, 64 * 1024, 4, SECT_4K) },
>> - { "w25q20bw", INFO(0xef5012, 0, 64 * 1024, 4, SECT_4K) },
>> - { "w25q20ew", INFO(0xef6012, 0, 64 * 1024, 4, SECT_4K) },
>> - { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
>> - {
>> - "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64,
>> - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
>> - SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
>> - },
>> - {
>> - "w25q32jv", INFO(0xef7016, 0, 64 * 1024, 64,
>> - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
>> - SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
>> - },
>> - { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
>> - { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
>> - {
>> - "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128,
>> - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
>> - SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
>> - },
>> - {
>> - "w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256,
>> - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
>> - SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
>> - },
>> - { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
>> - { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
>> - { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
>> - { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>> - { "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024,
>> - SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ) },
>> -#endif
>> -#ifdef CONFIG_SPI_FLASH_XMC
>> - /* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */
>> - { "XM25QH64A", INFO(0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>> - { "XM25QH128A", INFO(0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>> -#endif
>> - { },
>> -};
>> -
>> static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
>> {
>> int tmp;
>> u8 id[SPI_NOR_MAX_ID_LEN];
>> const struct flash_info *info;
>>
>> - if (!ARRAY_SIZE(spi_nor_ids))
>> - return ERR_PTR(-ENODEV);
>> -
>> tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
>> if (tmp < 0) {
>> dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp);
>> return ERR_PTR(tmp);
>> }
>>
>> - for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) {
>> - info = &spi_nor_ids[tmp];
>> + info = spi_nor_ids;
>> + for (; info->name; info++) {
>> if (info->id_len) {
>> if (!memcmp(info->id, id, info->id_len))
>> - return &spi_nor_ids[tmp];
>> + return info;
>> }
>> }
>> +
>> dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
>> id[0], id[1], id[2]);
>> return ERR_PTR(-ENODEV);
>> --
>> 2.19.2
>>

--
Regards
Vignesh