From mboxrd@z Thu Jan 1 00:00:00 1970 From: Lukasz Majewski Date: Tue, 15 Jan 2019 09:20:16 +0100 Subject: [U-Boot] [PATCH v1 11/21] ARM: DTS: Update pcm052 based dts files (bk4r1/pcm052.dts) In-Reply-To: <20190114143259.GE5463@bill-the-cat> References: <20190114141740.20429-1-lukma@denx.de> <20190114141740.20429-12-lukma@denx.de> <20190114143259.GE5463@bill-the-cat> Message-ID: <20190115092016.5a5f55bc@jawa> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Tom, > On Mon, Jan 14, 2019 at 03:17:30PM +0100, Lukasz Majewski wrote: > > This commit provides update to the bk4r1.dts file with > > more on SoC HW description. > > Moreover, a new vf610-pcm052.drsi file has been introduced > > to reuse the common code between devices based on Phytec's > > pcm052 modules. > > Ported from Linux kernel - v4.20 (tag) > > > > Signed-off-by: Lukasz Majewski > > --- > > > > arch/arm/dts/bk4r1.dts | 108 ++++++++++++----- > > arch/arm/dts/pcm052.dts | 6 +- > > arch/arm/dts/vf610-pcm052.dtsi | 266 > > +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 346 > > insertions(+), 34 deletions(-) create mode 100644 > > arch/arm/dts/vf610-pcm052.dtsi > > > > diff --git a/arch/arm/dts/bk4r1.dts b/arch/arm/dts/bk4r1.dts > > index 866b80e0b0..55cd53384a 100644 > > --- a/arch/arm/dts/bk4r1.dts > > +++ b/arch/arm/dts/bk4r1.dts > > @@ -1,47 +1,97 @@ > > // SPDX-License-Identifier: GPL-2.0+ OR X11 > > /* > > + * (C) Copyright 2018 > > + * Lukasz Majewski, DENX Software Engineering, lukma at denx.de. > > + * > > * Copyright 2016 Toradex AG > > */ > > > > /dts-v1/; > > -#include "vf.dtsi" > > +#include "vf610-pcm052.dtsi" > > +#include "vf610-pinfunc.h" > > > > / { > > - model = "Phytec phyCORE-Vybrid"; > > - compatible = "phytec,pcm052", "fsl,vf610"; > > + model = "Liebherr (LVF) BK4 Vybrid Board"; > > + compatible = "lvf,bk4", "fsl,vf610"; > > > > - chosen { > > - stdout-path = &uart1; > > - }; > > + leds { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_gpio_leds>; > > > > - aliases { > > - spi0 = &qspi0; > > - }; > > + compatible = "gpio-leds"; > > > > -}; > > + /* PTE15 PORT3[24] H6 green */ > > + led at 0 { > > + label = "0"; > > + gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; > > + default-state = "off"; > > + }; > > + > > + /* PTA12 PORT0[5] H5 green */ > > + led at 1 { > > + label = "1"; > > + gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; > > + default-state = "off"; > > + }; > > + > > + /* PTE20 PORT3[39] H4 green */ > > + led at 2 { > > + label = "2"; > > + gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; > > + default-state = "off"; > > + }; > > > > -&uart1 { > > - status = "okay"; > > + /* PTE12 PORT3[21] H3 green */ > > + led at 3 { > > + label = "3"; > > + gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; > > + default-state = "off"; > > + }; > > + > > + /* LED6 is now PRESET ETH -> PTA16 PORT0[6] H6 > > red */ > > + /* PTE9 PORT3[18] H5 red */ > > + led at 4 { > > + label = "5"; > > + gpios = <&gpio3 18 GPIO_ACTIVE_LOW>; > > + default-state = "off"; > > + }; > > + > > + /* PTE23 PORT4[0] H4 red */ > > + led at 5 { > > + label = "6"; > > + gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; > > + default-state = "off"; > > + }; > > + > > + /* PTE16 PORT3[25] H3 red */ > > + led at 6 { > > + label = "7"; > > + gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; > > + default-state = "off"; > > + }; > > + }; > > }; > > > > -&qspi0 { > > - bus-num = <0>; > > - num-cs = <2>; > > - status = "okay"; > > - > > - qflash0: spi_flash at 0 { > > - #address-cells = <1>; > > - #size-cells = <1>; > > - compatible = "spi-flash"; > > - spi-max-frequency = <108000000>; > > - reg = <0>; > > +&iomuxc { > > + pinctrl-0 = <&pinctrl_ddr &pinctrl_hog>; > > + > > + pinctrl_hog: hoggrp { > > + fsl,pins = < > > + /* ETH control pins */ > > + VF610_PAD_PTE17__GPIO_122 > > 0x1183 > > + VF610_PAD_PTA16__GPIO_6 0x1183 > > + >; > > }; > > > > - qflash1: spi_flash at 1 { > > - #address-cells = <1>; > > - #size-cells = <1>; > > - compatible = "spi-flash"; > > - spi-max-frequency = <66000000>; > > - reg = <1>; > > + pinctrl_gpio_leds: gpioledsgrp { > > + fsl,pins = < > > + /* LEDS */ > > + VF610_PAD_PTE15__GPIO_120 0x1183 > > + VF610_PAD_PTA12__GPIO_5 0x1183 > > + VF610_PAD_PTE9__GPIO_114 0x1183 > > + VF610_PAD_PTE20__GPIO_125 0x1183 > > + VF610_PAD_PTE23__GPIO_128 0x1183 > > + VF610_PAD_PTE16__GPIO_121 0x1183 > > + >; > > }; > > }; > > diff --git a/arch/arm/dts/pcm052.dts b/arch/arm/dts/pcm052.dts > > index 6489fdc6f4..22026024ea 100644 > > --- a/arch/arm/dts/pcm052.dts > > +++ b/arch/arm/dts/pcm052.dts > > @@ -4,7 +4,7 @@ > > */ > > > > /dts-v1/; > > -#include "vf.dtsi" > > +#include "vf610-pcm052.dtsi" > > > > / { > > model = "Phytec phyCORE-Vybrid"; > > @@ -15,7 +15,3 @@ > > }; > > > > }; > > - > > -&uart1 { > > - status = "okay"; > > -}; > > diff --git a/arch/arm/dts/vf610-pcm052.dtsi > > b/arch/arm/dts/vf610-pcm052.dtsi new file mode 100644 > > index 0000000000..034290526d > > --- /dev/null > > +++ b/arch/arm/dts/vf610-pcm052.dtsi > > @@ -0,0 +1,266 @@ > > +// SPDX-License-Identifier: GPL-2.0+ OR X11 > > +/* > > + * (C) Copyright 2018 > > + * Lukasz Majewski, DENX Software Engineering, lukma at denx.de. > > + * > > + */ > > + > > +/dts-v1/; > > +#include "vf.dtsi" > > +#include "vf610-pinfunc.h" > > + > > +/ { > > + chosen { > > + stdout-path = &uart1; > > + }; > > + > > + aliases { > > + spi0 = &qspi0; > > + mmc0 = &esdhc1; > > + }; > > +}; > > + > > +&aips0 { > > + u-boot,dm-pre-reloc; > > +}; > > + > > +&esdhc1 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_esdhc1>; > > + bus-width = <4>; > > + cd-gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; > > + status = "okay"; > > +}; > > + > > +&fec0 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_eth>; > > + > > + phy-mode = "rmii"; > > + status = "okay"; > > +}; > > + > > +&fec1 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_eth1>; > > + > > + phy-mode = "rmii"; > > + status = "okay"; > > +}; > > + > > +&i2c2 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_i2c2>; > > + status = "okay"; > > + > > + eeprom: eeprom at 50 { > > + compatible = "atmel,24c256"; > > + reg = <0x50>; > > + pagesize = <64>; > > + u-boot,i2c-offset-len = <2>; > > + }; > > + > > + m41t62: rtc at 68 { > > + compatible = "st,m41t62"; > > + reg = <0x68>; > > + }; > > +}; > > + > > +&iomuxc { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_ddr>; > > + > > + pinctrl_ddr: ddrgrp { > > + fsl,pins = < > > + VF610_PAD_DDR_A15__DDR_A_15 > > 0x1c0 > > + VF610_PAD_DDR_A14__DDR_A_14 > > 0x1c0 > > + VF610_PAD_DDR_A13__DDR_A_13 > > 0x1c0 > > + VF610_PAD_DDR_A12__DDR_A_12 > > 0x1c0 > > + VF610_PAD_DDR_A11__DDR_A_11 > > 0x1c0 > > + VF610_PAD_DDR_A10__DDR_A_10 > > 0x1c0 > > + VF610_PAD_DDR_A9__DDR_A_9 > > 0x1c0 > > + VF610_PAD_DDR_A8__DDR_A_8 > > 0x1c0 > > + VF610_PAD_DDR_A7__DDR_A_7 > > 0x1c0 > > + VF610_PAD_DDR_A6__DDR_A_6 > > 0x1c0 > > + VF610_PAD_DDR_A5__DDR_A_5 > > 0x1c0 > > + VF610_PAD_DDR_A4__DDR_A_4 > > 0x1c0 > > + VF610_PAD_DDR_A3__DDR_A_3 > > 0x1c0 > > + VF610_PAD_DDR_A2__DDR_A_2 > > 0x1c0 > > + VF610_PAD_DDR_A1__DDR_A_1 > > 0x1c0 > > + VF610_PAD_DDR_A0__DDR_A_0 > > 0x1c0 > > + VF610_PAD_DDR_BA2__DDR_BA_2 > > 0x1c0 > > + VF610_PAD_DDR_BA1__DDR_BA_1 > > 0x1c0 > > + VF610_PAD_DDR_BA0__DDR_BA_0 > > 0x1c0 > > + VF610_PAD_DDR_CAS__DDR_CAS_B > > 0x1c0 > > + VF610_PAD_DDR_CKE__DDR_CKE_0 > > 0x1c0 > > + VF610_PAD_DDR_CLK__DDR_CLK_0 > > 0x101c0 > > + VF610_PAD_DDR_CS__DDR_CS_B_0 > > 0x1c0 > > + VF610_PAD_DDR_D15__DDR_D_15 > > 0x1c0 > > + VF610_PAD_DDR_D14__DDR_D_14 > > 0x1c0 > > + VF610_PAD_DDR_D13__DDR_D_13 > > 0x1c0 > > + VF610_PAD_DDR_D12__DDR_D_12 > > 0x1c0 > > + VF610_PAD_DDR_D11__DDR_D_11 > > 0x1c0 > > + VF610_PAD_DDR_D10__DDR_D_10 > > 0x1c0 > > + VF610_PAD_DDR_D9__DDR_D_9 > > 0x1c0 > > + VF610_PAD_DDR_D8__DDR_D_8 > > 0x1c0 > > + VF610_PAD_DDR_D7__DDR_D_7 > > 0x1c0 > > + VF610_PAD_DDR_D6__DDR_D_6 > > 0x1c0 > > + VF610_PAD_DDR_D5__DDR_D_5 > > 0x1c0 > > + VF610_PAD_DDR_D4__DDR_D_4 > > 0x1c0 > > + VF610_PAD_DDR_D3__DDR_D_3 > > 0x1c0 > > + VF610_PAD_DDR_D2__DDR_D_2 > > 0x1c0 > > + VF610_PAD_DDR_D1__DDR_D_1 > > 0x1c0 > > + VF610_PAD_DDR_D0__DDR_D_0 > > 0x1c0 > > + VF610_PAD_DDR_DQM1__DDR_DQM_1 > > 0x1c0 > > + VF610_PAD_DDR_DQM0__DDR_DQM_0 > > 0x1c0 > > + VF610_PAD_DDR_DQS1__DDR_DQS_1 > > 0x101c0 > > + VF610_PAD_DDR_DQS0__DDR_DQS_0 > > 0x101c0 > > + VF610_PAD_DDR_RAS__DDR_RAS_B > > 0x1c0 > > + VF610_PAD_DDR_WE__DDR_WE_B > > 0x1c0 > > + VF610_PAD_DDR_ODT1__DDR_ODT_0 > > 0x1c0 > > + VF610_PAD_DDR_ODT0__DDR_ODT_1 > > 0x1c0 > > + VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1 > > 0x1c0 > > + VF610_PAD_DDR_DDRBYTE0__DDR_DDRBYTE0 > > 0x1c0 > > + VF610_PAD_DDR_RESETB > > 0x1006c > > + >; > > + u-boot,dm-pre-reloc; > > + }; > > + > > + pinctrl_esdhc1: esdhc1grp { > > + fsl,pins = < > > + VF610_PAD_PTA24__ESDHC1_CLK > > 0x31ef > > + VF610_PAD_PTA25__ESDHC1_CMD > > 0x31ef > > + > > VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef > > + > > VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef > > + > > VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef > > + > > VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef > > + VF610_PAD_PTB28__GPIO_98 > > 0x219d > > + >; > > + }; > > + > > + pinctrl_eth: ethgrp { > > + fsl,pins = < > > + VF610_PAD_PTA6__RMII_CLKIN > > 0x30dd > > + VF610_PAD_PTC0__ENET_RMII0_MDC > > 0x30de > > + VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30df > > + VF610_PAD_PTC2__ENET_RMII0_CRS > > 0x30dd > > + VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30dd > > + VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30dd > > + VF610_PAD_PTC5__ENET_RMII0_RXER 0x30dd > > + VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30de > > + VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30de > > + VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30de > > + >; > > + }; > > + > > + pinctrl_eth1: eth1grp { > > + fsl,pins = < > > + > > VF610_PAD_PTC9__ENET_RMII1_MDC 0x30de > > + VF610_PAD_PTC10__ENET_RMII1_MDIO > > 0x30df > > + VF610_PAD_PTC11__ENET_RMII1_CRS > > 0x30dd > > + VF610_PAD_PTC12__ENET_RMII1_RXD1 > > 0x30dd > > + VF610_PAD_PTC13__ENET_RMII1_RXD0 > > 0x30dd > > + VF610_PAD_PTC14__ENET_RMII1_RXER > > 0x30dd > > + VF610_PAD_PTC15__ENET_RMII1_TXD1 > > 0x30de > > + VF610_PAD_PTC16__ENET_RMII1_TXD0 > > 0x30de > > + VF610_PAD_PTC17__ENET_RMII1_TXEN > > 0x30de > > + >; > > + }; > > + > > + pinctrl_i2c2: i2c2grp { > > + fsl,pins = < > > + VF610_PAD_PTA22__I2C2_SCL > > 0x34df > > + VF610_PAD_PTA23__I2C2_SDA > > 0x34df > > + >; > > + }; > > + > > + pinctrl_nfc: nfcgrp { > > + fsl,pins = < > > + VF610_PAD_PTD31__NF_IO15 > > 0x28df > > + VF610_PAD_PTD30__NF_IO14 > > 0x28df > > + VF610_PAD_PTD29__NF_IO13 > > 0x28df > > + VF610_PAD_PTD28__NF_IO12 > > 0x28df > > + VF610_PAD_PTD27__NF_IO11 > > 0x28df > > + VF610_PAD_PTD26__NF_IO10 > > 0x28df > > + VF610_PAD_PTD25__NF_IO9 > > 0x28df > > + VF610_PAD_PTD24__NF_IO8 > > 0x28df > > + VF610_PAD_PTD23__NF_IO7 > > 0x28df > > + VF610_PAD_PTD22__NF_IO6 > > 0x28df > > + VF610_PAD_PTD21__NF_IO5 > > 0x28df > > + VF610_PAD_PTD20__NF_IO4 > > 0x28df > > + VF610_PAD_PTD19__NF_IO3 > > 0x28df > > + VF610_PAD_PTD18__NF_IO2 > > 0x28df > > + VF610_PAD_PTD17__NF_IO1 > > 0x28df > > + VF610_PAD_PTD16__NF_IO0 > > 0x28df > > + VF610_PAD_PTB24__NF_WE_B > > 0x28c2 > > + VF610_PAD_PTB25__NF_CE0_B > > 0x28c2 > > + VF610_PAD_PTB27__NF_RE_B > > 0x28c2 > > + VF610_PAD_PTC26__NF_RB_B > > 0x283d > > + VF610_PAD_PTC27__NF_ALE > > 0x28c2 > > + VF610_PAD_PTC28__NF_CLE > > 0x28c2 > > + >; > > + }; > > + > > + pinctrl_qspi0: qspi0grp { > > + fsl,pins = < > > + VF610_PAD_PTD0__QSPI0_A_QSCK 0x397f > > + VF610_PAD_PTD1__QSPI0_A_CS0 0x397f > > + VF610_PAD_PTD2__QSPI0_A_DATA3 0x397f > > + VF610_PAD_PTD3__QSPI0_A_DATA2 0x397f > > + VF610_PAD_PTD4__QSPI0_A_DATA1 0x397f > > + VF610_PAD_PTD5__QSPI0_A_DATA0 0x397f > > + VF610_PAD_PTD7__QSPI0_B_QSCK 0x397f > > + VF610_PAD_PTD8__QSPI0_B_CS0 0x397f > > + VF610_PAD_PTD11__QSPI0_B_DATA1 > > 0x397f > > + VF610_PAD_PTD12__QSPI0_B_DATA0 > > 0x397f > > + >; > > + }; > > + > > + pinctrl_uart1: uart1grp { > > + fsl,pins = < > > + VF610_PAD_PTB4__UART1_TX > > 0x21a2 > > + VF610_PAD_PTB5__UART1_RX > > 0x21a1 > > + >; > > + u-boot,dm-pre-reloc; > > + }; > > +}; > > + > > +&nfc { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_nfc>; > > + > > + status = "okay"; > > +}; > > + > > +&uart1 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_uart1>; > > + u-boot,dm-pre-reloc; > > + > > + status = "okay"; > > +}; > > Any/all u-boot,WHATEVER flags go in the $(basename)-u-boot.dtsi file > so that $(basename) can be kept as-is from Linux. Looking things over > briefly I suspect we have a higher level issue in that we shouldn't > have "pcm052.dts" at all and only "vf610-pcm052.dts" or however it > syncs up with what's in Linux. The problem is that pcm052 is not supported / added to Linux (maybe there are some dts files for it out of tree - I don't know. As of v5.0.-rc2 there weren't any). The work done in this patch simply extracts the bk4 and pcm052 common DTS code and creates new vf610-pcm052.dtsi file. Just a side note - the Vybrid structure of DTS/DTSI files in u-boot differs considerably from the one in Linux (v5.0-rc2). For example in u-boot we do not have vf500.dtsi - the structure (of DTS) is trimmed due to constraints of overall u-boot.vyb size (which was apparent when I ported some common code from Linux to vf.dtsi file). > Best regards, Lukasz Majewski -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 488 bytes Desc: OpenPGP digital signature URL: