[U-Boot] [PATCH 1/9] sunxi: clk: add MMC gates/resets

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From: Andre Przywara <andre.przywara@arm.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 1/9] sunxi: clk: add MMC gates/resets
Date: Sat, 19 Jan 2019 01:30:47 +0000	[thread overview]
Message-ID: <20190119013055.28023-2-andre.przywara@arm.com> (raw)
In-Reply-To: <20190119013055.28023-1-andre.przywara@arm.com>

Add the MMC clock gates and reset bits for all the Allwinner SoCs.
This allows them to be used by the MMC driver.

We don't advertise the mod clock yet, as this is still handled by the
MMC driver.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 drivers/clk/sunxi/clk_a10.c  | 4 ++++
 drivers/clk/sunxi/clk_a10s.c | 3 +++
 drivers/clk/sunxi/clk_a23.c  | 6 ++++++
 drivers/clk/sunxi/clk_a31.c  | 8 ++++++++
 drivers/clk/sunxi/clk_a64.c  | 6 ++++++
 drivers/clk/sunxi/clk_a83t.c | 6 ++++++
 drivers/clk/sunxi/clk_h3.c   | 6 ++++++
 drivers/clk/sunxi/clk_h6.c   | 6 ++++++
 drivers/clk/sunxi/clk_r40.c  | 8 ++++++++
 9 files changed, 53 insertions(+)

diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c
index b00f51af8b..2aa41efe17 100644
--- a/drivers/clk/sunxi/clk_a10.c
+++ b/drivers/clk/sunxi/clk_a10.c
@@ -18,6 +18,10 @@ static struct ccu_clk_gate a10_gates[] = {
 	[CLK_AHB_OHCI0]		= GATE(0x060, BIT(2)),
 	[CLK_AHB_EHCI1]		= GATE(0x060, BIT(3)),
 	[CLK_AHB_OHCI1]		= GATE(0x060, BIT(4)),
+	[CLK_AHB_MMC0]		= GATE(0x060, BIT(8)),
+	[CLK_AHB_MMC1]		= GATE(0x060, BIT(9)),
+	[CLK_AHB_MMC2]		= GATE(0x060, BIT(10)),
+	[CLK_AHB_MMC3]		= GATE(0x060, BIT(11)),
 
 	[CLK_APB1_UART0]	= GATE(0x06c, BIT(16)),
 	[CLK_APB1_UART1]	= GATE(0x06c, BIT(17)),
diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c
index aa904ce067..87b74e52dc 100644
--- a/drivers/clk/sunxi/clk_a10s.c
+++ b/drivers/clk/sunxi/clk_a10s.c
@@ -16,6 +16,9 @@ static struct ccu_clk_gate a10s_gates[] = {
 	[CLK_AHB_OTG]		= GATE(0x060, BIT(0)),
 	[CLK_AHB_EHCI]		= GATE(0x060, BIT(1)),
 	[CLK_AHB_OHCI]		= GATE(0x060, BIT(2)),
+	[CLK_AHB_MMC0]		= GATE(0x060, BIT(8)),
+	[CLK_AHB_MMC1]		= GATE(0x060, BIT(9)),
+	[CLK_AHB_MMC2]		= GATE(0x060, BIT(10)),
 
 	[CLK_APB1_UART0]	= GATE(0x06c, BIT(16)),
 	[CLK_APB1_UART1]	= GATE(0x06c, BIT(17)),
diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c
index 854259bf81..1ef2359286 100644
--- a/drivers/clk/sunxi/clk_a23.c
+++ b/drivers/clk/sunxi/clk_a23.c
@@ -13,6 +13,9 @@
 #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
 
 static struct ccu_clk_gate a23_gates[] = {
+	[CLK_BUS_MMC0]		= GATE(0x060, BIT(8)),
+	[CLK_BUS_MMC1]		= GATE(0x060, BIT(9)),
+	[CLK_BUS_MMC2]		= GATE(0x060, BIT(10)),
 	[CLK_BUS_OTG]		= GATE(0x060, BIT(24)),
 	[CLK_BUS_EHCI]		= GATE(0x060, BIT(26)),
 	[CLK_BUS_OHCI]		= GATE(0x060, BIT(29)),
@@ -35,6 +38,9 @@ static struct ccu_reset a23_resets[] = {
 	[RST_USB_PHY1]		= RESET(0x0cc, BIT(1)),
 	[RST_USB_HSIC]		= RESET(0x0cc, BIT(2)),
 
+	[RST_BUS_MMC0]		= RESET(0x2c0, BIT(8)),
+	[RST_BUS_MMC1]		= RESET(0x2c0, BIT(9)),
+	[RST_BUS_MMC2]		= RESET(0x2c0, BIT(10)),
 	[RST_BUS_OTG]		= RESET(0x2c0, BIT(24)),
 	[RST_BUS_EHCI]		= RESET(0x2c0, BIT(26)),
 	[RST_BUS_OHCI]		= RESET(0x2c0, BIT(29)),
diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c
index a38d76cb7c..5bd8b7dccc 100644
--- a/drivers/clk/sunxi/clk_a31.c
+++ b/drivers/clk/sunxi/clk_a31.c
@@ -13,6 +13,10 @@
 #include <dt-bindings/reset/sun6i-a31-ccu.h>
 
 static struct ccu_clk_gate a31_gates[] = {
+	[CLK_AHB1_MMC0]		= GATE(0x060, BIT(8)),
+	[CLK_AHB1_MMC1]		= GATE(0x060, BIT(9)),
+	[CLK_AHB1_MMC2]		= GATE(0x060, BIT(10)),
+	[CLK_AHB1_MMC3]		= GATE(0x060, BIT(11)),
 	[CLK_AHB1_OTG]		= GATE(0x060, BIT(24)),
 	[CLK_AHB1_EHCI0]	= GATE(0x060, BIT(26)),
 	[CLK_AHB1_EHCI1]	= GATE(0x060, BIT(27)),
@@ -40,6 +44,10 @@ static struct ccu_reset a31_resets[] = {
 	[RST_USB_PHY1]		= RESET(0x0cc, BIT(1)),
 	[RST_USB_PHY2]		= RESET(0x0cc, BIT(2)),
 
+	[RST_AHB1_MMC0]		= RESET(0x2c0, BIT(8)),
+	[RST_AHB1_MMC1]		= RESET(0x2c0, BIT(9)),
+	[RST_AHB1_MMC2]		= RESET(0x2c0, BIT(10)),
+	[RST_AHB1_MMC3]		= RESET(0x2c0, BIT(11)),
 	[RST_AHB1_OTG]		= RESET(0x2c0, BIT(24)),
 	[RST_AHB1_EHCI0]	= RESET(0x2c0, BIT(26)),
 	[RST_AHB1_EHCI1]	= RESET(0x2c0, BIT(27)),
diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c
index a2ba6eefc5..910275fbce 100644
--- a/drivers/clk/sunxi/clk_a64.c
+++ b/drivers/clk/sunxi/clk_a64.c
@@ -13,6 +13,9 @@
 #include <dt-bindings/reset/sun50i-a64-ccu.h>
 
 static const struct ccu_clk_gate a64_gates[] = {
+	[CLK_BUS_MMC0]		= GATE(0x060, BIT(8)),
+	[CLK_BUS_MMC1]		= GATE(0x060, BIT(9)),
+	[CLK_BUS_MMC2]		= GATE(0x060, BIT(10)),
 	[CLK_BUS_OTG]		= GATE(0x060, BIT(23)),
 	[CLK_BUS_EHCI0]		= GATE(0x060, BIT(24)),
 	[CLK_BUS_EHCI1]		= GATE(0x060, BIT(25)),
@@ -38,6 +41,9 @@ static const struct ccu_reset a64_resets[] = {
 	[RST_USB_PHY1]          = RESET(0x0cc, BIT(1)),
 	[RST_USB_HSIC]          = RESET(0x0cc, BIT(2)),
 
+	[RST_BUS_MMC0]		= RESET(0x2c0, BIT(8)),
+	[RST_BUS_MMC1]		= RESET(0x2c0, BIT(9)),
+	[RST_BUS_MMC2]		= RESET(0x2c0, BIT(10)),
 	[RST_BUS_OTG]           = RESET(0x2c0, BIT(23)),
 	[RST_BUS_EHCI0]         = RESET(0x2c0, BIT(24)),
 	[RST_BUS_EHCI1]         = RESET(0x2c0, BIT(25)),
diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c
index 1ef6ac5b25..b5a555da36 100644
--- a/drivers/clk/sunxi/clk_a83t.c
+++ b/drivers/clk/sunxi/clk_a83t.c
@@ -13,6 +13,9 @@
 #include <dt-bindings/reset/sun8i-a83t-ccu.h>
 
 static struct ccu_clk_gate a83t_gates[] = {
+	[CLK_BUS_MMC0]		= GATE(0x060, BIT(8)),
+	[CLK_BUS_MMC1]		= GATE(0x060, BIT(9)),
+	[CLK_BUS_MMC2]		= GATE(0x060, BIT(10)),
 	[CLK_BUS_OTG]		= GATE(0x060, BIT(24)),
 	[CLK_BUS_EHCI0]		= GATE(0x060, BIT(26)),
 	[CLK_BUS_EHCI1]		= GATE(0x060, BIT(27)),
@@ -36,6 +39,9 @@ static struct ccu_reset a83t_resets[] = {
 	[RST_USB_PHY1]		= RESET(0x0cc, BIT(1)),
 	[RST_USB_HSIC]		= RESET(0x0cc, BIT(2)),
 
+	[RST_BUS_MMC0]		= RESET(0x2c0, BIT(8)),
+	[RST_BUS_MMC1]		= RESET(0x2c0, BIT(9)),
+	[RST_BUS_MMC2]		= RESET(0x2c0, BIT(10)),
 	[RST_BUS_OTG]		= RESET(0x2c0, BIT(24)),
 	[RST_BUS_EHCI0]		= RESET(0x2c0, BIT(26)),
 	[RST_BUS_EHCI1]		= RESET(0x2c0, BIT(27)),
diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c
index f82949b3b6..98af372ec5 100644
--- a/drivers/clk/sunxi/clk_h3.c
+++ b/drivers/clk/sunxi/clk_h3.c
@@ -13,6 +13,9 @@
 #include <dt-bindings/reset/sun8i-h3-ccu.h>
 
 static struct ccu_clk_gate h3_gates[] = {
+	[CLK_BUS_MMC0]		= GATE(0x060, BIT(8)),
+	[CLK_BUS_MMC1]		= GATE(0x060, BIT(9)),
+	[CLK_BUS_MMC2]		= GATE(0x060, BIT(10)),
 	[CLK_BUS_OTG]		= GATE(0x060, BIT(23)),
 	[CLK_BUS_EHCI0]		= GATE(0x060, BIT(24)),
 	[CLK_BUS_EHCI1]		= GATE(0x060, BIT(25)),
@@ -44,6 +47,9 @@ static struct ccu_reset h3_resets[] = {
 	[RST_USB_PHY2]		= RESET(0x0cc, BIT(2)),
 	[RST_USB_PHY3]		= RESET(0x0cc, BIT(3)),
 
+	[RST_BUS_MMC0]		= RESET(0x2c0, BIT(8)),
+	[RST_BUS_MMC0]		= RESET(0x2c0, BIT(9)),
+	[RST_BUS_MMC0]		= RESET(0x2c0, BIT(10)),
 	[RST_BUS_OTG]		= RESET(0x2c0, BIT(23)),
 	[RST_BUS_EHCI0]		= RESET(0x2c0, BIT(24)),
 	[RST_BUS_EHCI1]		= RESET(0x2c0, BIT(25)),
diff --git a/drivers/clk/sunxi/clk_h6.c b/drivers/clk/sunxi/clk_h6.c
index 0da3a40e3d..902612da91 100644
--- a/drivers/clk/sunxi/clk_h6.c
+++ b/drivers/clk/sunxi/clk_h6.c
@@ -13,6 +13,9 @@
 #include <dt-bindings/reset/sun50i-h6-ccu.h>
 
 static struct ccu_clk_gate h6_gates[] = {
+	[CLK_BUS_MMC0]		= GATE(0x84c, BIT(0)),
+	[CLK_BUS_MMC1]		= GATE(0x84c, BIT(1)),
+	[CLK_BUS_MMC2]		= GATE(0x84c, BIT(2)),
 	[CLK_BUS_UART0]		= GATE(0x90c, BIT(0)),
 	[CLK_BUS_UART1]		= GATE(0x90c, BIT(1)),
 	[CLK_BUS_UART2]		= GATE(0x90c, BIT(2)),
@@ -20,6 +23,9 @@ static struct ccu_clk_gate h6_gates[] = {
 };
 
 static struct ccu_reset h6_resets[] = {
+	[RST_BUS_MMC0]		= RESET(0x84c, BIT(16)),
+	[RST_BUS_MMC1]		= RESET(0x84c, BIT(17)),
+	[RST_BUS_MMC2]		= RESET(0x84c, BIT(18)),
 	[RST_BUS_UART0]		= RESET(0x90c, BIT(16)),
 	[RST_BUS_UART1]		= RESET(0x90c, BIT(17)),
 	[RST_BUS_UART2]		= RESET(0x90c, BIT(18)),
diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c
index fd7aae97ea..b9457e1971 100644
--- a/drivers/clk/sunxi/clk_r40.c
+++ b/drivers/clk/sunxi/clk_r40.c
@@ -13,6 +13,10 @@
 #include <dt-bindings/reset/sun8i-r40-ccu.h>
 
 static struct ccu_clk_gate r40_gates[] = {
+	[CLK_BUS_MMC0]		= GATE(0x060, BIT(8)),
+	[CLK_BUS_MMC1]		= GATE(0x060, BIT(9)),
+	[CLK_BUS_MMC2]		= GATE(0x060, BIT(10)),
+	[CLK_BUS_MMC3]		= GATE(0x060, BIT(11)),
 	[CLK_BUS_OTG]		= GATE(0x060, BIT(25)),
 	[CLK_BUS_EHCI0]		= GATE(0x060, BIT(26)),
 	[CLK_BUS_EHCI1]		= GATE(0x060, BIT(27)),
@@ -43,6 +47,10 @@ static struct ccu_reset r40_resets[] = {
 	[RST_USB_PHY1]		= RESET(0x0cc, BIT(1)),
 	[RST_USB_PHY2]		= RESET(0x0cc, BIT(2)),
 
+	[RST_BUS_MMC0]		= RESET(0x2c0, BIT(8)),
+	[RST_BUS_MMC1]		= RESET(0x2c0, BIT(9)),
+	[RST_BUS_MMC2]		= RESET(0x2c0, BIT(10)),
+	[RST_BUS_MMC3]		= RESET(0x2c0, BIT(11)),
 	[RST_BUS_OTG]		= RESET(0x2c0, BIT(25)),
 	[RST_BUS_EHCI0]		= RESET(0x2c0, BIT(26)),
 	[RST_BUS_EHCI1]		= RESET(0x2c0, BIT(27)),
-- 
2.14.5

next prev parent reply	other threads:[~2019-01-19  1:30 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-19  1:30 [U-Boot] [PATCH 0/9] sunxi: enable DM_MMC Andre Przywara
2019-01-19  1:30 ` Andre Przywara [this message]
2019-01-19  1:30 ` [U-Boot] [PATCH 2/9] sunxi: clk: A80: add MMC clock support Andre Przywara
2019-01-21  9:31   ` [U-Boot] [linux-sunxi] " Jagan Teki
2019-01-21  9:34     ` Chen-Yu Tsai
2019-01-21  9:38       ` Andre Przywara
2019-01-21 10:02         ` Chen-Yu Tsai
2019-01-21 10:12           ` Andre Przywara
2019-01-21 10:29             ` Chen-Yu Tsai
2019-01-19  1:30 ` [U-Boot] [PATCH 3/9] mmc: sunxi: Add DM clk and reset support Andre Przywara
2019-01-19  1:30 ` [U-Boot] [PATCH 4/9] mmc: sunxi: Add H6 support Andre Przywara
2019-01-19  1:30 ` [U-Boot] [PATCH 5/9] mmc: sunxi: Add missing compatible strings Andre Przywara
2019-01-19  1:30 ` [U-Boot] [PATCH 6/9] mmc: sunxi: Add A80 support Andre Przywara
2019-01-19  1:30 ` [U-Boot] [PATCH 7/9] mmc: sunxi: Honour non-removable property in DT Andre Przywara
2019-01-25  7:16   ` [U-Boot] [linux-sunxi] " Jagan Teki
2019-01-25  9:28     ` Andre Przywara
2019-01-29 18:20   ` Jagan Teki
2019-01-19  1:30 ` [U-Boot] [PATCH 8/9] arm: sunxi: Enable DM_MMC Andre Przywara
2019-01-31 10:04   ` Simon Glass
2019-01-19  1:30 ` [U-Boot] [PATCH 9/9] mmc: sunxi: Mark end of DM_MMC #ifdefs Andre Przywara
2019-01-31 10:04   ` Simon Glass
2019-01-31 14:55     ` Andre Przywara
2019-01-19 18:32 ` [U-Boot] [PATCH 0/9] sunxi: enable DM_MMC Vasily Khoruzhick
2019-01-19 20:33   ` André Przywara
2019-01-19 23:42     ` Vasily Khoruzhick
2019-01-20 19:51 ` [U-Boot] [linux-sunxi] " Priit Laes
2019-01-21  0:54   ` André Przywara
2019-01-21  8:22     ` Priit Laes
2019-01-21  8:51       ` Andre Przywara
2019-01-21  9:10         ` Priit Laes
2019-01-22  9:49     ` Lukasz Majewski
2019-01-21  9:22 ` Jagan Teki

find likely ancestor, descendant, or conflicting patches for this message:
( dfblob:b00f51af8 dfblob:2aa41efe1 dfblob:aa904ce06 dfblob:87b74e52d
dfblob:854259bf8 dfblob:1ef235928 dfblob:a38d76cb7 dfblob:5bd8b7dcc
dfblob:a2ba6eefc dfblob:910275fbc dfblob:1ef6ac5b2 dfblob:b5a555da3
dfblob:f82949b3b dfblob:98af372ec dfblob:0da3a40e3 dfblob:902612da9
dfblob:fd7aae97e dfblob:b9457e197 )
 OR (
bs:"[U-Boot] [PATCH 1/9] sunxi: clk: add MMC gates/resets" )
	(help)

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