[U-Boot] [PATCH 1/3] videomodes: Relax EDID validation checks for hsync/vsync pulse width

Priit Laes
2019-01-17T09:29:55Z

From: Priit Laes <priit.laes@paf.com>

Current EDID detailed timing parser errors out when either
horizontal or vertical pulse sync width is 0, thus not
allowing a display with EDID listed below work properly.

Same EDID works ok within Linux although it warns about
these two fields being 0. Therefore relax the checks a bit
so we can actually use this the screen.

Of-course, this is somewhat quirky HDMI display with following
anti-features:
- HPD pin is not usable
- although resolution is 640x480, only top 240 pixels are visible

$ xxd -p display.edid
00ffffffffffff0005a1e00301000000150f0103800f05780a0f6ea05748
9a2610474f200000010101010101010101010101010101012a08804520e0
0b1020004000953600000018000000fd0034441a2403000a202020202020
0000001000310a20202020202020202020200000001000002a4030701300
782d1100001e006b

$ edid-decode display.edid
EDID version: 1.3
Manufacturer: AMA Model 3e0 Serial Number 1
Digital display
Maximum image size: 15 cm x 5 cm
Gamma: 2.20
RGB color display
First detailed timing is preferred timing
Display x,y Chromaticity:
Red: 0.6250, 0.3398
Green: 0.2841, 0.6044
Blue: 0.1494, 0.0644
White: 0.2802, 0.3105
Established timings supported:
640x480 at 60Hz 4:3 HorFreq: 31469 Hz Clock: 25.175 MHz
Standard timings supported:
Detailed mode: Clock 20.900 MHz, 149 mm x 54 mm
640 672 672 709 hborder 0
480 484 484 491 vborder 0
-hsync -vsync
VertFreq: 60 Hz, HorFreq: 29478 Hz
Monitor ranges (GTF): 52-68Hz V, 26-36kHz H, max dotclock 30MHz
Dummy block
Dummy block
Checksum: 0x6b (valid)

Signed-off-by: Priit Laes <priit.laes@paf.com>
---
drivers/video/videomodes.c | 2 --
1 file changed, 2 deletions(-)

diff --git a/drivers/video/videomodes.c b/drivers/video/videomodes.c
index 74bafff011..1cfeaa980f 100644
--- a/drivers/video/videomodes.c
+++ b/drivers/video/videomodes.c
@@ -396,9 +396,7 @@ int video_edid_dtd_to_ctfb_res_modes(struct edid_detailed_timing *t,
EDID_DETAILED_TIMING_VERTICAL_ACTIVE(*t) == 0 ||
EDID_DETAILED_TIMING_VERTICAL_BLANKING(*t) == 0 ||
EDID_DETAILED_TIMING_HSYNC_OFFSET(*t) == 0 ||
- EDID_DETAILED_TIMING_HSYNC_PULSE_WIDTH(*t) == 0 ||
EDID_DETAILED_TIMING_VSYNC_OFFSET(*t) == 0 ||
- EDID_DETAILED_TIMING_VSYNC_PULSE_WIDTH(*t) == 0 ||
/* 3d formats are not supported*/
EDID_DETAILED_TIMING_FLAG_STEREO(*t) != 0)
return -EINVAL;
--
2.11.0