* [U-Boot] [PATCH 01/20] imx: add IMX8MM kconfig entry
2019-01-28 9:39 [U-Boot] [PATCH 00/20] imx: add i.MX8MM support Peng Fan
@ 2019-01-28 9:39 ` Peng Fan
2019-01-28 9:39 ` [U-Boot] [PATCH 02/20] imx8: cpu: restrict checking ROM passover info for revA Peng Fan
` (18 subsequent siblings)
19 siblings, 0 replies; 39+ messages in thread
From: Peng Fan @ 2019-01-28 9:39 UTC (permalink / raw)
To: u-boot
Add IMX8MM kconfig entry
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/mach-imx/imx8m/Kconfig | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 9c487870a6..35c978e863 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -8,6 +8,10 @@ config IMX8MQ
bool
select IMX8M
+config IMX8MM
+ bool
+ select IMX8M
+
config SYS_SOC
default "imx8m"
--
2.14.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* [U-Boot] [PATCH 02/20] imx8: cpu: restrict checking ROM passover info for revA
2019-01-28 9:39 [U-Boot] [PATCH 00/20] imx: add i.MX8MM support Peng Fan
2019-01-28 9:39 ` [U-Boot] [PATCH 01/20] imx: add IMX8MM kconfig entry Peng Fan
@ 2019-01-28 9:39 ` Peng Fan
2019-01-28 9:39 ` [U-Boot] [PATCH 03/20] imx: imx8mm: add clock bindings header Peng Fan
` (17 subsequent siblings)
19 siblings, 0 replies; 39+ messages in thread
From: Peng Fan @ 2019-01-28 9:39 UTC (permalink / raw)
To: u-boot
Passover info only for revA.
move get_cpu_rev out of CONFIG_CPU to avoid build failure when using
get_cpu_rev in SPL.
Add a CONFIG_SPL_BUILD for passover usage, no need to execute it again
in normal U-Boot stage. Also if still checking passover info in normal
U-Boot stage, need to make the passover code executed after
arch_cpu_init_dm.
So to make it easy and clean, only execute the code for SPL stage.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/mach-imx/imx8/cpu.c | 39 ++++++++++++++++++++++-----------------
1 file changed, 22 insertions(+), 17 deletions(-)
diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
index 303cdc3c9a..ac65ae74fd 100644
--- a/arch/arm/mach-imx/imx8/cpu.c
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -35,15 +35,20 @@ struct pass_over_info_t *get_pass_over_info(void)
int arch_cpu_init(void)
{
- struct pass_over_info_t *pass_over = get_pass_over_info();
-
- if (pass_over && pass_over->g_ap_mu == 0) {
- /*
- * When ap_mu is 0, means the U-Boot booted
- * from first container
- */
- sc_misc_boot_status(-1, SC_MISC_BOOT_STATUS_SUCCESS);
+#ifdef CONFIG_SPL_BUILD
+ struct pass_over_info_t *pass_over;
+
+ if (is_soc_rev(CHIP_REV_A)) {
+ pass_over = get_pass_over_info();
+ if (pass_over && pass_over->g_ap_mu == 0) {
+ /*
+ * When ap_mu is 0, means the U-Boot booted
+ * from first container
+ */
+ sc_misc_boot_status(-1, SC_MISC_BOOT_STATUS_SUCCESS);
+ }
}
+#endif
return 0;
}
@@ -507,15 +512,6 @@ err:
printf("%s: fuse %d, err: %d\n", __func__, word[i], ret);
}
-#if CONFIG_IS_ENABLED(CPU)
-struct cpu_imx_platdata {
- const char *name;
- const char *rev;
- const char *type;
- u32 cpurev;
- u32 freq_mhz;
-};
-
u32 get_cpu_rev(void)
{
u32 id = 0, rev = 0;
@@ -531,6 +527,15 @@ u32 get_cpu_rev(void)
return (id << 12) | rev;
}
+#if CONFIG_IS_ENABLED(CPU)
+struct cpu_imx_platdata {
+ const char *name;
+ const char *rev;
+ const char *type;
+ u32 cpurev;
+ u32 freq_mhz;
+};
+
const char *get_imx8_type(u32 imxtype)
{
switch (imxtype) {
--
2.14.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* [U-Boot] [PATCH 03/20] imx: imx8mm: add clock bindings header
2019-01-28 9:39 [U-Boot] [PATCH 00/20] imx: add i.MX8MM support Peng Fan
2019-01-28 9:39 ` [U-Boot] [PATCH 01/20] imx: add IMX8MM kconfig entry Peng Fan
2019-01-28 9:39 ` [U-Boot] [PATCH 02/20] imx8: cpu: restrict checking ROM passover info for revA Peng Fan
@ 2019-01-28 9:39 ` Peng Fan
2019-01-28 9:39 ` [U-Boot] [PATCH 04/20] imx: add pin binding header for i.MX8MM Peng Fan
` (16 subsequent siblings)
19 siblings, 0 replies; 39+ messages in thread
From: Peng Fan @ 2019-01-28 9:39 UTC (permalink / raw)
To: u-boot
Add i.MX8MM clock binding header for i.MX8MM
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
include/dt-bindings/clock/imx8mm-clock.h | 469 +++++++++++++++++++++++++++++++
1 file changed, 469 insertions(+)
create mode 100644 include/dt-bindings/clock/imx8mm-clock.h
diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings/clock/imx8mm-clock.h
new file mode 100644
index 0000000000..d093a87c6f
--- /dev/null
+++ b/include/dt-bindings/clock/imx8mm-clock.h
@@ -0,0 +1,469 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX8MM_H
+#define __DT_BINDINGS_CLOCK_IMX8MM_H
+
+#define IMX8MM_CLK_DUMMY 0
+#define IMX8MM_CLK_32K 1
+#define IMX8MM_CLK_24M 2
+#define IMX8MM_OSC_HDMI_CLK 3
+#define IMX8MM_CLK_EXT1 4
+#define IMX8MM_CLK_EXT2 5
+#define IMX8MM_CLK_EXT3 6
+#define IMX8MM_CLK_EXT4 7
+#define IMX8MM_AUDIO_PLL1_REF_SEL 8
+#define IMX8MM_AUDIO_PLL2_REF_SEL 9
+#define IMX8MM_VIDEO_PLL1_REF_SEL 10
+#define IMX8MM_DRAM_PLL_REF_SEL 11
+#define IMX8MM_GPU_PLL_REF_SEL 12
+#define IMX8MM_VPU_PLL_REF_SEL 13
+#define IMX8MM_ARM_PLL_REF_SEL 14
+#define IMX8MM_SYS_PLL1_REF_SEL 15
+#define IMX8MM_SYS_PLL2_REF_SEL 16
+#define IMX8MM_SYS_PLL3_REF_SEL 17
+#define IMX8MM_AUDIO_PLL1 18
+#define IMX8MM_AUDIO_PLL2 19
+#define IMX8MM_VIDEO_PLL1 20
+#define IMX8MM_DRAM_PLL 21
+#define IMX8MM_GPU_PLL 22
+#define IMX8MM_VPU_PLL 23
+#define IMX8MM_ARM_PLL 24
+#define IMX8MM_SYS_PLL1 25
+#define IMX8MM_SYS_PLL2 26
+#define IMX8MM_SYS_PLL3 27
+#define IMX8MM_AUDIO_PLL1_BYPASS 28
+#define IMX8MM_AUDIO_PLL2_BYPASS 29
+#define IMX8MM_VIDEO_PLL1_BYPASS 30
+#define IMX8MM_DRAM_PLL_BYPASS 31
+#define IMX8MM_GPU_PLL_BYPASS 32
+#define IMX8MM_VPU_PLL_BYPASS 33
+#define IMX8MM_ARM_PLL_BYPASS 34
+#define IMX8MM_SYS_PLL1_BYPASS 35
+#define IMX8MM_SYS_PLL2_BYPASS 36
+#define IMX8MM_SYS_PLL3_BYPASS 37
+#define IMX8MM_AUDIO_PLL1_OUT 38
+#define IMX8MM_AUDIO_PLL2_OUT 39
+#define IMX8MM_VIDEO_PLL1_OUT 40
+#define IMX8MM_DRAM_PLL_OUT 41
+#define IMX8MM_GPU_PLL_OUT 42
+#define IMX8MM_VPU_PLL_OUT 43
+#define IMX8MM_ARM_PLL_OUT 44
+#define IMX8MM_SYS_PLL1_OUT 45
+#define IMX8MM_SYS_PLL2_OUT 46
+#define IMX8MM_SYS_PLL3_OUT 47
+#define IMX8MM_SYS_PLL1_40M 48
+#define IMX8MM_SYS_PLL1_80M 49
+#define IMX8MM_SYS_PLL1_100M 50
+#define IMX8MM_SYS_PLL1_133M 51
+#define IMX8MM_SYS_PLL1_160M 52
+#define IMX8MM_SYS_PLL1_200M 53
+#define IMX8MM_SYS_PLL1_266M 54
+#define IMX8MM_SYS_PLL1_400M 55
+#define IMX8MM_SYS_PLL1_800M 56
+#define IMX8MM_SYS_PLL2_50M 57
+#define IMX8MM_SYS_PLL2_100M 58
+#define IMX8MM_SYS_PLL2_125M 59
+#define IMX8MM_SYS_PLL2_166M 60
+#define IMX8MM_SYS_PLL2_200M 61
+#define IMX8MM_SYS_PLL2_250M 62
+#define IMX8MM_SYS_PLL2_333M 63
+#define IMX8MM_SYS_PLL2_500M 64
+#define IMX8MM_SYS_PLL2_1000M 65
+#define IMX8MM_CLK_A53_SRC 66
+#define IMX8MM_CLK_M4_SRC 67
+#define IMX8MM_CLK_VPU_SRC 68
+#define IMX8MM_CLK_GPU3D_SRC 69
+#define IMX8MM_CLK_GPU2D_SRC 70
+#define IMX8MM_CLK_A53_CG 71
+#define IMX8MM_CLK_M4_CG 72
+#define IMX8MM_CLK_VPU_CG 73
+#define IMX8MM_CLK_GPU3D_CG 74
+#define IMX8MM_CLK_GPU2D_CG 75
+#define IMX8MM_CLK_A53_DIV 76
+#define IMX8MM_CLK_M4_DIV 77
+#define IMX8MM_CLK_VPU_DIV 78
+#define IMX8MM_CLK_GPU3D_DIV 79
+#define IMX8MM_CLK_GPU2D_DIV 80
+#define IMX8MM_CLK_MAIN_AXI_SRC 81
+#define IMX8MM_CLK_ENET_AXI_SRC 82
+#define IMX8MM_CLK_NAND_USDHC_BUS_SRC 83
+#define IMX8MM_CLK_VPU_BUS_SRC 84
+#define IMX8MM_CLK_DISP_AXI_SRC 85
+#define IMX8MM_CLK_DISP_APB_SRC 86
+#define IMX8MM_CLK_DISP_RTRM_SRC 87
+#define IMX8MM_CLK_USB_BUS_SRC 88
+#define IMX8MM_CLK_GPU_AXI_SRC 89
+#define IMX8MM_CLK_GPU_AHB_SRC 90
+#define IMX8MM_CLK_NOC_SRC 91
+#define IMX8MM_CLK_NOC_APB_SRC 92
+#define IMX8MM_CLK_MAIN_AXI_CG 93
+#define IMX8MM_CLK_ENET_AXI_CG 94
+#define IMX8MM_CLK_NAND_USDHC_BUS_CG 95
+#define IMX8MM_CLK_VPU_BUS_CG 96
+#define IMX8MM_CLK_DISP_AXI_CG 97
+#define IMX8MM_CLK_DISP_APB_CG 98
+#define IMX8MM_CLK_DISP_RTRM_CG 99
+#define IMX8MM_CLK_USB_BUS_CG 100
+#define IMX8MM_CLK_GPU_AXI_CG 101
+#define IMX8MM_CLK_GPU_AHB_CG 102
+#define IMX8MM_CLK_NOC_CG 103
+#define IMX8MM_CLK_NOC_APB_CG 104
+#define IMX8MM_CLK_MAIN_AXI_PRE_DIV 105
+#define IMX8MM_CLK_ENET_AXI_PRE_DIV 106
+#define IMX8MM_CLK_NAND_USDHC_BUS_PRE_DIV 107
+#define IMX8MM_CLK_VPU_BUS_PRE_DIV 108
+#define IMX8MM_CLK_DISP_AXI_PRE_DIV 109
+#define IMX8MM_CLK_DISP_APB_PRE_DIV 110
+#define IMX8MM_CLK_DISP_RTRM_PRE_DIV 111
+#define IMX8MM_CLK_USB_BUS_PRE_DIV 112
+#define IMX8MM_CLK_GPU_AXI_PRE_DIV 113
+#define IMX8MM_CLK_GPU_AHB_PRE_DIV 114
+#define IMX8MM_CLK_NOC_PRE_DIV 115
+#define IMX8MM_CLK_NOC_APB_PRE_DIV 116
+#define IMX8MM_CLK_MAIN_AXI_DIV 117
+#define IMX8MM_CLK_ENET_AXI_DIV 118
+#define IMX8MM_CLK_NAND_USDHC_BUS 119
+#define IMX8MM_CLK_VPU_BUS_DIV 120
+#define IMX8MM_CLK_DISP_AXI_DIV 121
+#define IMX8MM_CLK_DISP_APB_DIV 122
+#define IMX8MM_CLK_DISP_RTRM_DIV 123
+#define IMX8MM_CLK_USB_BUS_DIV 124
+#define IMX8MM_CLK_GPU_AXI_DIV 125
+#define IMX8MM_CLK_GPU_AHB_DIV 126
+#define IMX8MM_CLK_NOC_DIV 127
+#define IMX8MM_CLK_NOC_APB_DIV 128
+#define IMX8MM_CLK_AHB_SRC 129
+#define IMX8MM_CLK_AUDIO_AHB_SRC 130
+#define IMX8MM_CLK_DSI_ESC_RX_SRC 131
+#define IMX8MM_CLK_AHB_CG 132
+#define IMX8MM_CLK_AUDIO_AHB_CG 133
+#define IMX8MM_CLK_DSI_ESC_RX_CG 134
+#define IMX8MM_CLK_AHB_PRE_DIV 135
+#define IMX8MM_CLK_AUDIO_AHB_PRE_DIV 136
+#define IMX8MM_CLK_DSI_ESC_RX_PRE_DIV 137
+#define IMX8MM_CLK_AHB_DIV 138
+#define IMX8MM_CLK_AUDIO_AHB_DIV 139
+#define IMX8MM_CLK_DSI_ESC_RX_DIV 140
+#define IMX8MM_CLK_IPG_ROOT 141
+#define IMX8MM_CLK_IPG_AUDIO_ROOT 142
+#define IMX8MM_CLK_IPG_DSI_ESC_RX_ROOT 143
+#define IMX8MM_CLK_DRAM_ALT_SRC 144
+#define IMX8MM_CLK_DRAM_APB_SRC 145
+#define IMX8MM_CLK_VPU_G1_SRC 146
+#define IMX8MM_CLK_VPU_G2_SRC 147
+#define IMX8MM_CLK_DISP_DTRC_SRC 148
+#define IMX8MM_CLK_DISP_DC8000_SRC 149
+#define IMX8MM_CLK_PCIE1_CTRL_SRC 150
+#define IMX8MM_CLK_PCIE1_PHY_SRC 151
+#define IMX8MM_CLK_PCIE1_AUX_SRC 152
+#define IMX8MM_CLK_DC_PIXEL_SRC 153
+#define IMX8MM_CLK_LCDIF_PIXEL_SRC 154
+#define IMX8MM_CLK_SAI1_SRC 155
+#define IMX8MM_CLK_SAI2_SRC 156
+#define IMX8MM_CLK_SAI3_SRC 157
+#define IMX8MM_CLK_SAI4_SRC 158
+#define IMX8MM_CLK_SAI5_SRC 159
+#define IMX8MM_CLK_SAI6_SRC 160
+#define IMX8MM_CLK_SPDIF1_SRC 161
+#define IMX8MM_CLK_SPDIF2_SRC 162
+#define IMX8MM_CLK_ENET_REF_SRC 163
+#define IMX8MM_CLK_ENET_TIMER_SRC 164
+#define IMX8MM_CLK_ENET_PHY_REF_SRC 165
+#define IMX8MM_CLK_NAND_SRC 166
+#define IMX8MM_CLK_QSPI_SRC 167
+#define IMX8MM_CLK_USDHC1_SRC 168
+#define IMX8MM_CLK_USDHC2_SRC 169
+#define IMX8MM_CLK_I2C1_SRC 170
+#define IMX8MM_CLK_I2C2_SRC 171
+#define IMX8MM_CLK_I2C3_SRC 172
+#define IMX8MM_CLK_I2C4_SRC 173
+#define IMX8MM_CLK_UART1_SRC 174
+#define IMX8MM_CLK_UART2_SRC 175
+#define IMX8MM_CLK_UART3_SRC 176
+#define IMX8MM_CLK_UART4_SRC 177
+#define IMX8MM_CLK_USB_CORE_REF_SRC 178
+#define IMX8MM_CLK_USB_PHY_REF_SRC 179
+#define IMX8MM_CLK_ECSPI1_SRC 180
+#define IMX8MM_CLK_ECSPI2_SRC 181
+#define IMX8MM_CLK_PWM1_SRC 182
+#define IMX8MM_CLK_PWM2_SRC 183
+#define IMX8MM_CLK_PWM3_SRC 184
+#define IMX8MM_CLK_PWM4_SRC 185
+#define IMX8MM_CLK_GPT1_SRC 186
+#define IMX8MM_CLK_WDOG_SRC 187
+#define IMX8MM_CLK_WRCLK_SRC 188
+#define IMX8MM_CLK_DSI_CORE_SRC 189
+#define IMX8MM_CLK_DSI_PHY_REF_SRC 190
+#define IMX8MM_CLK_DSI_DBI_SRC 191
+#define IMX8MM_CLK_USDHC3_SRC 192
+#define IMX8MM_CLK_CSI1_CORE_SRC 193
+#define IMX8MM_CLK_CSI1_PHY_REF_SRC 194
+#define IMX8MM_CLK_CSI1_ESC_SRC 195
+#define IMX8MM_CLK_CSI2_CORE_SRC 196
+#define IMX8MM_CLK_CSI2_PHY_REF_SRC 197
+#define IMX8MM_CLK_CSI2_ESC_SRC 198
+#define IMX8MM_CLK_PCIE2_CTRL_SRC 199
+#define IMX8MM_CLK_PCIE2_PHY_SRC 200
+#define IMX8MM_CLK_PCIE2_AUX_SRC 201
+#define IMX8MM_CLK_ECSPI3_SRC 202
+#define IMX8MM_CLK_PDM_SRC 203
+#define IMX8MM_CLK_VPU_H1_SRC 204
+#define IMX8MM_CLK_DRAM_ALT_CG 205
+#define IMX8MM_CLK_DRAM_APB_CG 206
+#define IMX8MM_CLK_VPU_G1_CG 207
+#define IMX8MM_CLK_VPU_G2_CG 208
+#define IMX8MM_CLK_DISP_DTRC_CG 209
+#define IMX8MM_CLK_DISP_DC8000_CG 210
+#define IMX8MM_CLK_PCIE1_CTRL_CG 211
+#define IMX8MM_CLK_PCIE1_PHY_CG 212
+#define IMX8MM_CLK_PCIE1_AUX_CG 213
+#define IMX8MM_CLK_DC_PIXEL_CG 214
+#define IMX8MM_CLK_LCDIF_PIXEL_CG 215
+#define IMX8MM_CLK_SAI1_CG 216
+#define IMX8MM_CLK_SAI2_CG 217
+#define IMX8MM_CLK_SAI3_CG 218
+#define IMX8MM_CLK_SAI4_CG 219
+#define IMX8MM_CLK_SAI5_CG 220
+#define IMX8MM_CLK_SAI6_CG 221
+#define IMX8MM_CLK_SPDIF1_CG 222
+#define IMX8MM_CLK_SPDIF2_CG 223
+#define IMX8MM_CLK_ENET_REF_CG 224
+#define IMX8MM_CLK_ENET_TIMER_CG 225
+#define IMX8MM_CLK_ENET_PHY_REF_CG 226
+#define IMX8MM_CLK_NAND_CG 227
+#define IMX8MM_CLK_QSPI_CG 228
+#define IMX8MM_CLK_USDHC1_CG 229
+#define IMX8MM_CLK_USDHC2_CG 230
+#define IMX8MM_CLK_I2C1_CG 231
+#define IMX8MM_CLK_I2C2_CG 232
+#define IMX8MM_CLK_I2C3_CG 233
+#define IMX8MM_CLK_I2C4_CG 234
+#define IMX8MM_CLK_UART1_CG 235
+#define IMX8MM_CLK_UART2_CG 236
+#define IMX8MM_CLK_UART3_CG 237
+#define IMX8MM_CLK_UART4_CG 238
+#define IMX8MM_CLK_USB_CORE_REF_CG 239
+#define IMX8MM_CLK_USB_PHY_REF_CG 240
+#define IMX8MM_CLK_ECSPI1_CG 241
+#define IMX8MM_CLK_ECSPI2_CG 242
+#define IMX8MM_CLK_PWM1_CG 243
+#define IMX8MM_CLK_PWM2_CG 244
+#define IMX8MM_CLK_PWM3_CG 245
+#define IMX8MM_CLK_PWM4_CG 246
+#define IMX8MM_CLK_GPT1_CG 247
+#define IMX8MM_CLK_WDOG_CG 248
+#define IMX8MM_CLK_WRCLK_CG 249
+#define IMX8MM_CLK_DSI_CORE_CG 250
+#define IMX8MM_CLK_DSI_PHY_REF_CG 251
+#define IMX8MM_CLK_DSI_DBI_CG 252
+#define IMX8MM_CLK_USDHC3_CG 253
+#define IMX8MM_CLK_CSI1_CORE_CG 254
+#define IMX8MM_CLK_CSI1_PHY_REF_CG 255
+#define IMX8MM_CLK_CSI1_ESC_CG 256
+#define IMX8MM_CLK_CSI2_CORE_CG 257
+#define IMX8MM_CLK_CSI2_PHY_REF_CG 258
+#define IMX8MM_CLK_CSI2_ESC_CG 259
+#define IMX8MM_CLK_PCIE2_CTRL_CG 260
+#define IMX8MM_CLK_PCIE2_PHY_CG 261
+#define IMX8MM_CLK_PCIE2_AUX_CG 262
+#define IMX8MM_CLK_ECSPI3_CG 263
+#define IMX8MM_CLK_PDM_CG 264
+#define IMX8MM_CLK_VPU_H1_CG 265
+#define IMX8MM_CLK_DRAM_ALT_PRE_DIV 266
+#define IMX8MM_CLK_DRAM_APB_PRE_DIV 267
+#define IMX8MM_CLK_VPU_G1_PRE_DIV 268
+#define IMX8MM_CLK_VPU_G2_PRE_DIV 269
+#define IMX8MM_CLK_DISP_DTRC_PRE_DIV 270
+#define IMX8MM_CLK_DISP_DC8000_PRE_DIV 271
+#define IMX8MM_CLK_PCIE1_CTRL_PRE_DIV 272
+#define IMX8MM_CLK_PCIE1_PHY_PRE_DIV 273
+#define IMX8MM_CLK_PCIE1_AUX_PRE_DIV 274
+#define IMX8MM_CLK_DC_PIXEL_PRE_DIV 275
+#define IMX8MM_CLK_LCDIF_PIXEL_PRE_DIV 276
+#define IMX8MM_CLK_SAI1_PRE_DIV 277
+#define IMX8MM_CLK_SAI2_PRE_DIV 278
+#define IMX8MM_CLK_SAI3_PRE_DIV 279
+#define IMX8MM_CLK_SAI4_PRE_DIV 280
+#define IMX8MM_CLK_SAI5_PRE_DIV 281
+#define IMX8MM_CLK_SAI6_PRE_DIV 282
+#define IMX8MM_CLK_SPDIF1_PRE_DIV 283
+#define IMX8MM_CLK_SPDIF2_PRE_DIV 284
+#define IMX8MM_CLK_ENET_REF_PRE_DIV 285
+#define IMX8MM_CLK_ENET_TIMER_PRE_DIV 286
+#define IMX8MM_CLK_ENET_PHY_REF_PRE_DIV 287
+#define IMX8MM_CLK_NAND_PRE_DIV 288
+#define IMX8MM_CLK_QSPI_PRE_DIV 289
+#define IMX8MM_CLK_USDHC1_PRE_DIV 290
+#define IMX8MM_CLK_USDHC2_PRE_DIV 291
+#define IMX8MM_CLK_I2C1_PRE_DIV 292
+#define IMX8MM_CLK_I2C2_PRE_DIV 293
+#define IMX8MM_CLK_I2C3_PRE_DIV 294
+#define IMX8MM_CLK_I2C4_PRE_DIV 295
+#define IMX8MM_CLK_UART1_PRE_DIV 296
+#define IMX8MM_CLK_UART2_PRE_DIV 297
+#define IMX8MM_CLK_UART3_PRE_DIV 298
+#define IMX8MM_CLK_UART4_PRE_DIV 299
+#define IMX8MM_CLK_USB_CORE_REF_PRE_DIV 300
+#define IMX8MM_CLK_USB_PHY_REF_PRE_DIV 301
+#define IMX8MM_CLK_ECSPI1_PRE_DIV 302
+#define IMX8MM_CLK_ECSPI2_PRE_DIV 303
+#define IMX8MM_CLK_PWM1_PRE_DIV 304
+#define IMX8MM_CLK_PWM2_PRE_DIV 305
+#define IMX8MM_CLK_PWM3_PRE_DIV 306
+#define IMX8MM_CLK_PWM4_PRE_DIV 307
+#define IMX8MM_CLK_GPT1_PRE_DIV 308
+#define IMX8MM_CLK_WDOG_PRE_DIV 309
+#define IMX8MM_CLK_WRCLK_PRE_DIV 310
+#define IMX8MM_CLK_DSI_CORE_PRE_DIV 311
+#define IMX8MM_CLK_DSI_PHY_REF_PRE_DIV 312
+#define IMX8MM_CLK_DSI_DBI_PRE_DIV 313
+#define IMX8MM_CLK_USDHC3_PRE_DIV 314
+#define IMX8MM_CLK_CSI1_CORE_PRE_DIV 315
+#define IMX8MM_CLK_CSI1_PHY_REF_PRE_DIV 316
+#define IMX8MM_CLK_CSI1_ESC_PRE_DIV 317
+#define IMX8MM_CLK_CSI2_CORE_PRE_DIV 318
+#define IMX8MM_CLK_CSI2_PHY_REF_PRE_DIV 319
+#define IMX8MM_CLK_CSI2_ESC_PRE_DIV 320
+#define IMX8MM_CLK_PCIE2_CTRL_PRE_DIV 321
+#define IMX8MM_CLK_PCIE2_PHY_PRE_DIV 322
+#define IMX8MM_CLK_PCIE2_AUX_PRE_DIV 323
+#define IMX8MM_CLK_ECSPI3_PRE_DIV 324
+#define IMX8MM_CLK_PDM_PRE_DIV 325
+#define IMX8MM_CLK_VPU_H1_PRE_DIV 326
+#define IMX8MM_CLK_DRAM_ALT_DIV 327
+#define IMX8MM_CLK_DRAM_APB_DIV 328
+#define IMX8MM_CLK_VPU_G1_DIV 329
+#define IMX8MM_CLK_VPU_G2_DIV 330
+#define IMX8MM_CLK_DISP_DTRC_DIV 331
+#define IMX8MM_CLK_DISP_DC8000_DIV 332
+#define IMX8MM_CLK_PCIE1_CTRL_DIV 333
+#define IMX8MM_CLK_PCIE1_PHY_DIV 334
+#define IMX8MM_CLK_PCIE1_AUX_DIV 335
+#define IMX8MM_CLK_DC_PIXEL_DIV 336
+#define IMX8MM_CLK_LCDIF_PIXEL_DIV 337
+#define IMX8MM_CLK_SAI1_DIV 338
+#define IMX8MM_CLK_SAI2_DIV 339
+#define IMX8MM_CLK_SAI3_DIV 340
+#define IMX8MM_CLK_SAI4_DIV 341
+#define IMX8MM_CLK_SAI5_DIV 342
+#define IMX8MM_CLK_SAI6_DIV 343
+#define IMX8MM_CLK_SPDIF1_DIV 344
+#define IMX8MM_CLK_SPDIF2_DIV 345
+#define IMX8MM_CLK_ENET_REF_DIV 346
+#define IMX8MM_CLK_ENET_TIMER_DIV 347
+#define IMX8MM_CLK_ENET_PHY_REF_DIV 348
+#define IMX8MM_CLK_NAND_DIV 349
+#define IMX8MM_CLK_QSPI_DIV 350
+#define IMX8MM_CLK_USDHC1 351
+#define IMX8MM_CLK_USDHC2 352
+#define IMX8MM_CLK_I2C1_DIV 353
+#define IMX8MM_CLK_I2C2_DIV 354
+#define IMX8MM_CLK_I2C3_DIV 355
+#define IMX8MM_CLK_I2C4_DIV 356
+#define IMX8MM_CLK_UART1_DIV 357
+#define IMX8MM_CLK_UART2_DIV 358
+#define IMX8MM_CLK_UART3_DIV 359
+#define IMX8MM_CLK_UART4_DIV 360
+#define IMX8MM_CLK_USB_CORE_REF_DIV 361
+#define IMX8MM_CLK_USB_PHY_REF_DIV 362
+#define IMX8MM_CLK_ECSPI1_DIV 363
+#define IMX8MM_CLK_ECSPI2_DIV 364
+#define IMX8MM_CLK_PWM1_DIV 365
+#define IMX8MM_CLK_PWM2_DIV 366
+#define IMX8MM_CLK_PWM3_DIV 367
+#define IMX8MM_CLK_PWM4_DIV 368
+#define IMX8MM_CLK_GPT1_DIV 369
+#define IMX8MM_CLK_WDOG_DIV 370
+#define IMX8MM_CLK_WRCLK_DIV 371
+#define IMX8MM_CLK_DSI_CORE_DIV 372
+#define IMX8MM_CLK_DSI_PHY_REF_DIV 373
+#define IMX8MM_CLK_DSI_DBI_DIV 374
+#define IMX8MM_CLK_USDHC3 375
+#define IMX8MM_CLK_CSI1_CORE_DIV 376
+#define IMX8MM_CLK_CSI1_PHY_REF_DIV 377
+#define IMX8MM_CLK_CSI1_ESC_DIV 378
+#define IMX8MM_CLK_CSI2_CORE_DIV 379
+#define IMX8MM_CLK_CSI2_PHY_REF_DIV 380
+#define IMX8MM_CLK_CSI2_ESC_DIV 381
+#define IMX8MM_CLK_PCIE2_CTRL_DIV 382
+#define IMX8MM_CLK_PCIE2_PHY_DIV 383
+#define IMX8MM_CLK_PCIE2_AUX_DIV 384
+#define IMX8MM_CLK_ECSPI3_DIV 385
+#define IMX8MM_CLK_PDM_DIV 386
+#define IMX8MM_CLK_VPU_H1_DIV 387
+#define IMX8MM_CLK_ECSPI1_ROOT 388
+#define IMX8MM_CLK_ECSPI2_ROOT 389
+#define IMX8MM_CLK_ECSPI3_ROOT 390
+#define IMX8MM_CLK_ENET1_ROOT 391
+#define IMX8MM_CLK_GPT1_ROOT 392
+#define IMX8MM_CLK_I2C1_ROOT 393
+#define IMX8MM_CLK_I2C2_ROOT 394
+#define IMX8MM_CLK_I2C3_ROOT 395
+#define IMX8MM_CLK_I2C4_ROOT 396
+#define IMX8MM_CLK_OCOTP_ROOT 397
+#define IMX8MM_CLK_PCIE1_ROOT 398
+#define IMX8MM_CLK_PWM1_ROOT 399
+#define IMX8MM_CLK_PWM2_ROOT 400
+#define IMX8MM_CLK_PWM3_ROOT 401
+#define IMX8MM_CLK_PWM4_ROOT 402
+#define IMX8MM_CLK_QSPI_ROOT 403
+#define IMX8MM_CLK_NAND_ROOT 404
+#define IMX8MM_CLK_SAI1_ROOT 405
+#define IMX8MM_CLK_SAI1_IPG 406
+#define IMX8MM_CLK_SAI2_ROOT 407
+#define IMX8MM_CLK_SAI2_IPG 408
+#define IMX8MM_CLK_SAI3_ROOT 409
+#define IMX8MM_CLK_SAI3_IPG 410
+#define IMX8MM_CLK_SAI4_ROOT 411
+#define IMX8MM_CLK_SAI4_IPG 412
+#define IMX8MM_CLK_SAI5_ROOT 413
+#define IMX8MM_CLK_SAI5_IPG 414
+#define IMX8MM_CLK_SAI6_ROOT 415
+#define IMX8MM_CLK_SAI6_IPG 416
+#define IMX8MM_CLK_UART1_ROOT 417
+#define IMX8MM_CLK_UART2_ROOT 418
+#define IMX8MM_CLK_UART3_ROOT 419
+#define IMX8MM_CLK_UART4_ROOT 420
+#define IMX8MM_CLK_USB1_CTRL_ROOT 421
+#define IMX8MM_CLK_GPU3D_ROOT 422
+#define IMX8MM_CLK_USDHC1_ROOT 423
+#define IMX8MM_CLK_USDHC2_ROOT 424
+#define IMX8MM_CLK_WDOG1_ROOT 425
+#define IMX8MM_CLK_WDOG2_ROOT 426
+#define IMX8MM_CLK_WDOG3_ROOT 427
+#define IMX8MM_CLK_VPU_G1_ROOT 428
+#define IMX8MM_CLK_GPU_BUS_ROOT 429
+#define IMX8MM_CLK_VPU_H1_ROOT 430
+#define IMX8MM_CLK_VPU_G2_ROOT 431
+#define IMX8MM_CLK_PDM_ROOT 432
+#define IMX8MM_CLK_DISP_ROOT 433
+#define IMX8MM_CLK_DISP_AXI_ROOT 434
+#define IMX8MM_CLK_DISP_APB_ROOT 435
+#define IMX8MM_CLK_DISP_RTRM_ROOT 436
+#define IMX8MM_CLK_USDHC3_ROOT 437
+#define IMX8MM_CLK_TMU_ROOT 438
+#define IMX8MM_CLK_VPU_DEC_ROOT 439
+#define IMX8MM_CLK_SDMA1_ROOT 440
+#define IMX8MM_CLK_SDMA2_ROOT 441
+#define IMX8MM_CLK_SDMA3_ROOT 442
+#define IMX8MM_CLK_GPT_3M 443
+#define IMX8MM_CLK_ARM 444
+#define IMX8MM_CLK_PDM_IPG 445
+#define IMX8MM_CLK_GPU2D_ROOT 446
+#define IMX8MM_CLK_MU_ROOT 447
+#define IMX8MM_CLK_CSI1_ROOT 448
+#define IMX8MM_CLK_CLKO1_SRC 449
+#define IMX8MM_CLK_CLKO1_CG 450
+#define IMX8MM_CLK_CLKO1_PRE_DIV 451
+#define IMX8MM_CLK_CLKO1_DIV 452
+
+#define IMX8MM_CLK_DRAM_CORE 453
+#define IMX8MM_CLK_DRAM_ALT_ROOT 454
+
+#define IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK 455
+
+#define IMX8MM_CLK_END 456
+#endif
--
2.14.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* [U-Boot] [PATCH 04/20] imx: add pin binding header for i.MX8MM
2019-01-28 9:39 [U-Boot] [PATCH 00/20] imx: add i.MX8MM support Peng Fan
` (2 preceding siblings ...)
2019-01-28 9:39 ` [U-Boot] [PATCH 03/20] imx: imx8mm: add clock bindings header Peng Fan
@ 2019-01-28 9:39 ` Peng Fan
2019-01-28 9:39 ` [U-Boot] [PATCH 05/20] imx: add i.MX8MM cpu type Peng Fan
` (15 subsequent siblings)
19 siblings, 0 replies; 39+ messages in thread
From: Peng Fan @ 2019-01-28 9:39 UTC (permalink / raw)
To: u-boot
Add i.MX8MM pin binding header
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
include/dt-bindings/pinctrl/pins-imx8mm.h | 629 ++++++++++++++++++++++++++++++
1 file changed, 629 insertions(+)
create mode 100644 include/dt-bindings/pinctrl/pins-imx8mm.h
diff --git a/include/dt-bindings/pinctrl/pins-imx8mm.h b/include/dt-bindings/pinctrl/pins-imx8mm.h
new file mode 100644
index 0000000000..7147eca59b
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pins-imx8mm.h
@@ -0,0 +1,629 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ */
+
+#ifndef __DTS_IMX8MM_PINFUNC_H
+#define __DTS_IMX8MM_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+
+#define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x030 0x298 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x030 0x298 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x030 0x298 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO02_SJC_DE_B 0x030 0x298 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x034 0x29C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x034 0x29C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x034 0x29C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK 0x034 0x29C 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO03_SJC_DONE 0x034 0x29C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x038 0x2A0 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x038 0x2A0 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x038 0x2A0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV 0x038 0x2A0 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO04_USDHC1_TEST_TRIG 0x038 0x2A0 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x03C 0x2A4 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO05_M4_NMI 0x03C 0x2A4 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY 0x03C 0x2A4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT 0x03C 0x2A4 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO05_USDHC2_TEST_TRIG 0x03C 0x2A4 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x040 0x2A8 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO06_ENET1_MDC 0x040 0x2A8 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x040 0x2A8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3 0x040 0x2A8 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO06_ECSPI1_TEST_TRIG 0x040 0x2A8 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x044 0x2AC 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO07_ENET1_MDIO 0x044 0x2AC 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO07_USDHC1_WP 0x044 0x2AC 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4 0x044 0x2AC 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO07_ECSPI2_TEST_TRIG 0x044 0x2AC 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x048 0x2B0 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x048 0x2B0 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x048 0x2B0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT 0x048 0x2B0 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO08_QSPI_TEST_TRIG 0x048 0x2B0 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x04C 0x2B4 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x04C 0x2B4 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x04C 0x2B4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP 0x04C 0x2B4 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO09_RAWNAND_TEST_TRIG 0x04C 0x2B4 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x050 0x2B8 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x050 0x2B8 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO10_OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x050 0x2B8 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x054 0x2BC 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x054 0x2BC 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY 0x054 0x2BC 0x4BC 0x5 0x1
+#define MX8MM_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0 0x054 0x2BC 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO11_CAAM_WRAPPER_RNG_OSC_OBS 0x054 0x2BC 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x058 0x2C0 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x058 0x2C0 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x058 0x2C0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1 0x058 0x2C0 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO12_CSU_CSU_ALARM_AUT0 0x058 0x2C0 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x05C 0x2C4 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x05C 0x2C4 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO13_PWM2_OUT 0x05C 0x2C4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2 0x05C 0x2C4 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO13_CSU_CSU_ALARM_AUT1 0x05C 0x2C4 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x060 0x2C8 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x060 0x2C8 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO14_PWM3_OUT 0x060 0x2C8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x060 0x2C8 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO14_CSU_CSU_ALARM_AUT2 0x060 0x2C8 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x064 0x2CC 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x064 0x2CC 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO15_PWM4_OUT 0x064 0x2CC 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x064 0x2CC 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO15_CSU_CSU_INT_DEB 0x064 0x2CC 0x000 0x7 0x0
+#define MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x068 0x2D0 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ENET_MDC_GPIO1_IO16 0x068 0x2D0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x06C 0x2D4 0x4C0 0x0 0x1
+#define MX8MM_IOMUXC_ENET_MDIO_GPIO1_IO17 0x06C 0x2D4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x070 0x2D8 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x070 0x2D8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x074 0x2DC 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x074 0x2DC 0x000 0x1 0x0
+#define MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x074 0x2DC 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x078 0x2E0 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x078 0x2E0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x07C 0x2E4 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x07C 0x2E4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x080 0x2E8 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x080 0x2E8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x084 0x2EC 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ENET_TXC_ENET1_TX_ER 0x084 0x2EC 0x000 0x1 0x0
+#define MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x084 0x2EC 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x088 0x2F0 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x088 0x2F0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x08C 0x2F4 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ENET_RXC_ENET1_RX_ER 0x08C 0x2F4 0x000 0x1 0x0
+#define MX8MM_IOMUXC_ENET_RXC_GPIO1_IO25 0x08C 0x2F4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090 0x2F8 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ENET_RD0_GPIO1_IO26 0x090 0x2F8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x094 0x2FC 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ENET_RD1_GPIO1_IO27 0x094 0x2FC 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x098 0x300 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ENET_RD2_GPIO1_IO28 0x098 0x300 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x09C 0x304 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ENET_RD3_GPIO1_IO29 0x09C 0x304 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x0A0 0x308 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x0A0 0x308 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x31 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD1_DATA2_GPIO2_IO4 0x0B0 0x318 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0B4 0x31C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD1_DATA3_GPIO2_IO5 0x0B4 0x31C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0B8 0x320 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0B8 0x320 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0BC 0x324 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x0BC 0x324 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0C0 0x328 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x0C0 0x328 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0C4 0x32C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x0C4 0x32C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x0C8 0x330 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x0C8 0x330 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x0CC 0x334 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x0CC 0x334 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0D0 0x338 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0D0 0x338 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x0D4 0x33C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD2_CLK_GPIO2_IO13 0x0D4 0x33C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0 0x0D4 0x33C 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SD2_CLK_OBSERVE_MUX_OUT0 0x0D4 0x33C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x0D8 0x340 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD2_CMD_GPIO2_IO14 0x0D8 0x340 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1 0x0D8 0x340 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SD2_CMD_OBSERVE_MUX_OUT1 0x0D8 0x340 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0DC 0x344 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD2_DATA0_GPIO2_IO15 0x0DC 0x344 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2 0x0DC 0x344 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SD2_DATA0_OBSERVE_MUX_OUT2 0x0DC 0x344 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0E0 0x348 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD2_DATA1_GPIO2_IO16 0x0E0 0x348 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT 0x0E0 0x348 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SD2_DATA1_OBSERVE_MUX_OUT3 0x0E0 0x348 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0E4 0x34C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD2_DATA2_GPIO2_IO17 0x0E4 0x34C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP 0x0E4 0x34C 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SD2_DATA2_OBSERVE_MUX_OUT4 0x0E4 0x34C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0E8 0x350 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD2_DATA3_GPIO2_IO18 0x0E8 0x350 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET 0x0E8 0x350 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x0EC 0x354 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x0EC 0x354 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET 0x0EC 0x354 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x0F0 0x358 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x0F0 0x358 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD2_WP_SIM_M_HMASTLOCK 0x0F0 0x358 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_ALE_RAWNAND_ALE 0x0F4 0x35C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x0F4 0x35C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x0F4 0x35C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_ALE_SIM_M_HPROT0 0x0F4 0x35C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x0F8 0x360 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x0F8 0x360 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x0F8 0x360 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_CE0_B_SIM_M_HPROT1 0x0F8 0x360 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x0FC 0x364 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x0FC 0x364 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x0FC 0x364 0x000 0x2 0x0
+#define MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x0FC 0x364 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_CE1_B_SIM_M_HPROT2 0x0FC 0x364 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x100 0x368 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x100 0x368 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x100 0x368 0x000 0x2 0x0
+#define MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x100 0x368 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_CE2_B_SIM_M_HPROT3 0x100 0x368 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x104 0x36C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x104 0x36C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x104 0x36C 0x000 0x2 0x0
+#define MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x104 0x36C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_CE3_B_SIM_M_HADDR0 0x104 0x36C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_CLE_RAWNAND_CLE 0x108 0x370 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x108 0x370 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x108 0x370 0x000 0x2 0x0
+#define MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x108 0x370 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_CLE_SIM_M_HADDR1 0x108 0x370 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x10C 0x374 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x10C 0x374 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6 0x10C 0x374 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_DATA00_SIM_M_HADDR2 0x10C 0x374 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x110 0x378 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x110 0x378 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x110 0x378 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_DATA01_SIM_M_HADDR3 0x110 0x378 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x114 0x37C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x114 0x37C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x114 0x37C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_DATA02_SIM_M_HADDR4 0x114 0x37C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x118 0x380 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x118 0x380 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9 0x118 0x380 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_DATA03_SIM_M_HADDR5 0x118 0x380 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x11C 0x384 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x11C 0x384 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x11C 0x384 0x000 0x2 0x0
+#define MX8MM_IOMUXC_NAND_DATA04_GPIO3_IO10 0x11C 0x384 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_DATA04_SIM_M_HADDR6 0x11C 0x384 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x120 0x388 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x120 0x388 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x120 0x388 0x000 0x2 0x0
+#define MX8MM_IOMUXC_NAND_DATA05_GPIO3_IO11 0x120 0x388 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_DATA05_SIM_M_HADDR7 0x120 0x388 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x124 0x38C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x124 0x38C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x124 0x38C 0x000 0x2 0x0
+#define MX8MM_IOMUXC_NAND_DATA06_GPIO3_IO12 0x124 0x38C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_DATA06_SIM_M_HADDR8 0x124 0x38C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x128 0x390 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x128 0x390 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x128 0x390 0x000 0x2 0x0
+#define MX8MM_IOMUXC_NAND_DATA07_GPIO3_IO13 0x128 0x390 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_DATA07_SIM_M_HADDR9 0x128 0x390 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_DQS_RAWNAND_DQS 0x12C 0x394 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x12C 0x394 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_DQS_GPIO3_IO14 0x12C 0x394 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_DQS_SIM_M_HADDR10 0x12C 0x394 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x130 0x398 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_RE_B_QSPI_B_DQS 0x130 0x398 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x130 0x398 0x000 0x2 0x0
+#define MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x130 0x398 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_RE_B_SIM_M_HADDR11 0x130 0x398 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x134 0x39C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x134 0x39C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_READY_B_SIM_M_HADDR12 0x134 0x39C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x138 0x3A0 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x138 0x3A0 0x000 0x12 0x0
+#define MX8MM_IOMUXC_NAND_WE_B_GPIO3_IO17 0x138 0x3A0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_WE_B_SIM_M_HADDR13 0x138 0x3A0 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x13C 0x3A4 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x13C 0x3A4 0x000 0x2 0x0
+#define MX8MM_IOMUXC_NAND_WP_B_GPIO3_IO18 0x13C 0x3A4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_WP_B_SIM_M_HADDR14 0x13C 0x3A4 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x140 0x3A8 0x4E4 0x0 0x0
+#define MX8MM_IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x140 0x3A8 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x140 0x3A8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x144 0x3AC 0x4D0 0x0 0x0
+#define MX8MM_IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x144 0x3AC 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI5_RXC_PDM_CLK 0x144 0x3AC 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x144 0x3AC 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x148 0x3B0 0x4D4 0x0 0x0
+#define MX8MM_IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x148 0x3B0 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0 0x148 0x3B0 0x534 0x4 0x0
+#define MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x148 0x3B0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x14C 0x3B4 0x4D8 0x0 0x0
+#define MX8MM_IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x14C 0x3B4 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x14C 0x3B4 0x4CC 0x2 0x0
+#define MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x14C 0x3B4 0x4EC 0x3 0x0
+#define MX8MM_IOMUXC_SAI5_RXD1_PDM_DATA1 0x14C 0x3B4 0x538 0x4 0x0
+#define MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x14C 0x3B4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x150 0x3B8 0x4DC 0x0 0x0
+#define MX8MM_IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x150 0x3B8 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x150 0x3B8 0x4CC 0x2 0x1
+#define MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x150 0x3B8 0x4E8 0x3 0x0
+#define MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2 0x150 0x3B8 0x53c 0x4 0x0
+#define MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x150 0x3B8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x154 0x3BC 0x4E0 0x0 0x0
+#define MX8MM_IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x154 0x3BC 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x154 0x3BC 0x4CC 0x2 0x2
+#define MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x154 0x3BC 0x000 0x3 0x0
+#define MX8MM_IOMUXC_SAI5_RXD3_PDM_DATA3 0x154 0x3BC 0x540 0x4 0x0
+#define MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x154 0x3BC 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x158 0x3C0 0x52C 0x0 0x0
+#define MX8MM_IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x158 0x3C0 0x4C8 0x1 0x0
+#define MX8MM_IOMUXC_SAI5_MCLK_SAI4_MCLK 0x158 0x3C0 0x000 0x2 0x0
+#define MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x158 0x3C0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI5_MCLK_CCMSRCGPCMIX_TESTER_ACK 0x158 0x3C0 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x15C 0x3C4 0x4C4 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x15C 0x3C4 0x4E4 0x1 0x1
+#define MX8MM_IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x15C 0x3C4 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x15C 0x3C4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_RXFS_SIM_M_HADDR15 0x15C 0x3C4 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x160 0x3C8 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x160 0x3C8 0x4D0 0x1 0x1
+#define MX8MM_IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x160 0x3C8 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x160 0x3C8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_RXC_SIM_M_HADDR16 0x160 0x3C8 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x164 0x3CC 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x164 0x3CC 0x4D4 0x1 0x1
+#define MX8MM_IOMUXC_SAI1_RXD0_PDM_DATA0 0x164 0x3CC 0x534 0x3 0x1
+#define MX8MM_IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x164 0x3CC 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x164 0x3CC 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_RXD0_CCMSRCGPCMIX_BOOT_CFG0 0x164 0x3CC 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_RXD0_SIM_M_HADDR17 0x164 0x3CC 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x168 0x3D0 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x168 0x3D0 0x4D8 0x1 0x1
+#define MX8MM_IOMUXC_SAI1_RXD1_PDM_DATA1 0x168 0x3D0 0x538 0x3 0x1
+#define MX8MM_IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x168 0x3D0 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x168 0x3D0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_RXD1_CCMSRCGPCMIX_BOOT_CFG1 0x168 0x3D0 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_RXD1_SIM_M_HADDR18 0x168 0x3D0 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x16C 0x3D4 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x16C 0x3D4 0x4DC 0x1 0x1
+#define MX8MM_IOMUXC_SAI1_RXD2_PDM_DATA2 0x16C 0x3D4 0x53C 0x3 0x1
+#define MX8MM_IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x16C 0x3D4 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x16C 0x3D4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_RXD2_CCMSRCGPCMIX_BOOT_CFG2 0x16C 0x3D4 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_RXD2_SIM_M_HADDR19 0x16C 0x3D4 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x170 0x3D8 0x4E0 0x0 0x1
+#define MX8MM_IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x170 0x3D8 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI1_RXD3_PDM_DATA3 0x170 0x3D8 0x540 0x3 0x1
+#define MX8MM_IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x170 0x3D8 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x170 0x3D8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_RXD3_CCMSRCGPCMIX_BOOT_CFG3 0x170 0x3D8 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_RXD3_SIM_M_HADDR20 0x170 0x3D8 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x174 0x3DC 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x174 0x3DC 0x51C 0x1 0x0
+#define MX8MM_IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x174 0x3DC 0x510 0x2 0x0
+#define MX8MM_IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x174 0x3DC 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x174 0x3DC 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_RXD4_CCMSRCGPCMIX_BOOT_CFG4 0x174 0x3DC 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_RXD4_SIM_M_HADDR21 0x174 0x3DC 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x178 0x3E0 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x178 0x3E0 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x178 0x3E0 0x514 0x2 0x0
+#define MX8MM_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x178 0x3E0 0x4C4 0x3 0x1
+#define MX8MM_IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x178 0x3E0 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x178 0x3E0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_RXD5_CCMSRCGPCMIX_BOOT_CFG5 0x178 0x3E0 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_RXD5_SIM_M_HADDR22 0x178 0x3E0 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x17C 0x3E4 0x520 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x17C 0x3E4 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x17C 0x3E4 0x518 0x2 0x0
+#define MX8MM_IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x17C 0x3E4 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x17C 0x3E4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_RXD6_CCMSRCGPCMIX_BOOT_CFG6 0x17C 0x3E4 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_RXD6_SIM_M_HADDR23 0x17C 0x3E4 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x180 0x3E8 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_RXD7_SAI6_MCLK 0x180 0x3E8 0x530 0x1 0x0
+#define MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x180 0x3E8 0x4CC 0x2 0x4
+#define MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x180 0x3E8 0x000 0x3 0x0
+#define MX8MM_IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x180 0x3E8 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x180 0x3E8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_RXD7_CCMSRCGPCMIX_BOOT_CFG7 0x180 0x3E8 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_RXD7_SIM_M_HADDR24 0x180 0x3E8 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x184 0x3EC 0x4CC 0x0 0x3
+#define MX8MM_IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x184 0x3EC 0x4EC 0x1 0x1
+#define MX8MM_IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x184 0x3EC 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x184 0x3EC 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_TXFS_SIM_M_HADDR25 0x184 0x3EC 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x188 0x3F0 0x4C8 0x0 0x1
+#define MX8MM_IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x188 0x3F0 0x4E8 0x1 0x1
+#define MX8MM_IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x188 0x3F0 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x188 0x3F0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_TXC_SIM_M_HADDR26 0x188 0x3F0 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x18C 0x3F4 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x18C 0x3F4 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x18C 0x3F4 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x18C 0x3F4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_TXD0_CCMSRCGPCMIX_BOOT_CFG8 0x18C 0x3F4 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_TXD0_SIM_M_HADDR27 0x18C 0x3F4 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x190 0x3F8 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x190 0x3F8 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x190 0x3F8 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x190 0x3F8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_TXD1_CCMSRCGPCMIX_BOOT_CFG9 0x190 0x3F8 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_TXD1_SIM_M_HADDR28 0x190 0x3F8 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x194 0x3FC 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x194 0x3FC 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x194 0x3FC 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x194 0x3FC 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_TXD2_CCMSRCGPCMIX_BOOT_CFG10 0x194 0x3FC 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_TXD2_SIM_M_HADDR29 0x194 0x3FC 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x198 0x400 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x198 0x400 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x198 0x400 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x198 0x400 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_TXD3_CCMSRCGPCMIX_BOOT_CFG11 0x198 0x400 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_TXD3_SIM_M_HADDR30 0x198 0x400 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x19C 0x404 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x19C 0x404 0x510 0x1 0x1
+#define MX8MM_IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x19C 0x404 0x51C 0x2 0x1
+#define MX8MM_IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x19C 0x404 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19C 0x404 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_TXD4_CCMSRCGPCMIX_BOOT_CFG12 0x19C 0x404 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_TXD4_SIM_M_HADDR31 0x19C 0x404 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x1A0 0x408 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x1A0 0x408 0x514 0x1 0x1
+#define MX8MM_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x1A0 0x408 0x000 0x2 0x0
+#define MX8MM_IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x1A0 0x408 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x1A0 0x408 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_TXD5_CCMSRCGPCMIX_BOOT_CFG13 0x1A0 0x408 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_TXD5_SIM_M_HBURST0 0x1A0 0x408 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x1A4 0x40C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x1A4 0x40C 0x518 0x1 0x1
+#define MX8MM_IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x1A4 0x40C 0x520 0x2 0x1
+#define MX8MM_IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x1A4 0x40C 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1A4 0x40C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_TXD6_CCMSRCGPCMIX_BOOT_CFG14 0x1A4 0x40C 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_TXD6_SIM_M_HBURST1 0x1A4 0x40C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x1A8 0x410 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_TXD7_SAI6_MCLK 0x1A8 0x410 0x530 0x1 0x1
+#define MX8MM_IOMUXC_SAI1_TXD7_PDM_CLK 0x1A8 0x410 0x000 0x3 0x0
+#define MX8MM_IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x1A8 0x410 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x1A8 0x410 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_TXD7_CCMSRCGPCMIX_BOOT_CFG15 0x1A8 0x410 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_TXD7_SIM_M_HBURST2 0x1A8 0x410 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0x1AC 0x414 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_MCLK_SAI5_MCLK 0x1AC 0x414 0x52C 0x1 0x1
+#define MX8MM_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x1AC 0x414 0x4C8 0x2 0x2
+#define MX8MM_IOMUXC_SAI1_MCLK_PDM_CLK 0x1AC 0x414 0x000 0x3 0x0
+#define MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1AC 0x414 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_MCLK_SIM_M_HRESP 0x1AC 0x414 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x1B0 0x418 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x1B0 0x418 0x4EC 0x1 0x2
+#define MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x1B0 0x418 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI2_RXFS_SIM_M_HSIZE0 0x1B0 0x418 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x1B4 0x41C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x1B4 0x41C 0x4E8 0x1 0x2
+#define MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1B4 0x41C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI2_RXC_SIM_M_HSIZE1 0x1B4 0x41C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x1B8 0x420 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x1B8 0x420 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x1B8 0x420 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI2_RXD0_SIM_M_HSIZE2 0x1B8 0x420 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x1BC 0x424 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x1BC 0x424 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x1BC 0x424 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI2_TXFS_SIM_M_HWRITE 0x1BC 0x424 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x1C0 0x428 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x1C0 0x428 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x1C0 0x428 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI2_TXC_SIM_M_HREADYOUT 0x1C0 0x428 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x1C4 0x42C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x1C4 0x42C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x1C4 0x42C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI2_TXD0_TPSMP_CLK 0x1C4 0x42C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x1C8 0x430 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI2_MCLK_SAI5_MCLK 0x1C8 0x430 0x52C 0x1 0x2
+#define MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1C8 0x430 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI2_MCLK_TPSMP_HDATA_DIR 0x1C8 0x430 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x1CC 0x434 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x1CC 0x434 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x1CC 0x434 0x4E4 0x2 0x2
+#define MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1CC 0x434 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI3_RXFS_TPSMP_HTRANS0 0x1CC 0x434 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x1D0 0x438 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x1D0 0x438 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x1D0 0x438 0x4D0 0x2 0x2
+#define MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x1D0 0x438 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI3_RXC_TPSMP_HTRANS1 0x1D0 0x438 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x1D4 0x43C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x1D4 0x43C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x1D4 0x43C 0x4D4 0x2 0x2
+#define MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x1D4 0x43C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI3_RXD_TPSMP_HDATA0 0x1D4 0x43C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI3_TXFS_GPT1_CLK 0x1D8 0x440 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x2
+#define MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI3_TXFS_TPSMP_HDATA1 0x1D8 0x440 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x1DC 0x444 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x1DC 0x444 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x1DC 0x444 0x4DC 0x2 0x2
+#define MX8MM_IOMUXC_SAI3_TXC_GPIO5_IO0 0x1DC 0x444 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI3_TXC_TPSMP_HDATA2 0x1DC 0x444 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x1E0 0x448 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x1E0 0x448 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x1E0 0x448 0x4E0 0x2 0x2
+#define MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1E0 0x448 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI3_TXD_TPSMP_HDATA3 0x1E0 0x448 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x1E4 0x44C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI3_MCLK_PWM4_OUT 0x1E4 0x44C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI3_MCLK_SAI5_MCLK 0x1E4 0x44C 0x52C 0x2 0x3
+#define MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1E4 0x44C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI3_MCLK_TPSMP_HDATA4 0x1E4 0x44C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT 0x1E8 0x450 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x1E8 0x450 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1E8 0x450 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SPDIF_TX_TPSMP_HDATA5 0x1E8 0x450 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SPDIF_RX_SPDIF1_IN 0x1EC 0x454 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x1EC 0x454 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x1EC 0x454 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SPDIF_RX_TPSMP_HDATA6 0x1EC 0x454 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x1F0 0x458 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x1F0 0x458 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x1F0 0x458 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SPDIF_EXT_CLK_TPSMP_HDATA7 0x1F0 0x458 0x000 0x7 0x0
+#define MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x1F4 0x45C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1F4 0x45C 0x504 0x1 0x0
+#define MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX 0x1F4 0x45C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x1F4 0x45C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ECSPI1_SCLK_TPSMP_HDATA8 0x1F4 0x45C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x1F8 0x460 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1F8 0x460 0x000 0x1 0x0
+#define MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX 0x1F8 0x460 0x504 0x1 0x1
+#define MX8MM_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x1F8 0x460 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ECSPI1_MOSI_TPSMP_HDATA9 0x1F8 0x460 0x000 0x7 0x0
+#define MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1FC 0x464 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1FC 0x464 0x000 0x1 0x0
+#define MX8MM_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B 0x1FC 0x464 0x500 0x1 0x0
+#define MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x1FC 0x464 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ECSPI1_MISO_TPSMP_HDATA10 0x1FC 0x464 0x000 0x7 0x0
+#define MX8MM_IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x200 0x468 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x200 0x468 0x500 0x1 0x1
+#define MX8MM_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B 0x200 0x468 0x000 0x1 0x0
+#define MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x200 0x468 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ECSPI1_SS0_TPSMP_HDATA11 0x200 0x468 0x000 0x7 0x0
+#define MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x204 0x46C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x204 0x46C 0x50C 0x1 0x0
+#define MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX 0x204 0x46C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x204 0x46C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ECSPI2_SCLK_TPSMP_HDATA12 0x204 0x46C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x208 0x470 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x208 0x470 0x000 0x1 0x0
+#define MX8MM_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX 0x208 0x470 0x50C 0x1 0x1
+#define MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x208 0x470 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ECSPI2_MOSI_TPSMP_HDATA13 0x208 0x470 0x000 0x7 0x0
+#define MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x20C 0x474 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x20C 0x474 0x000 0x1 0x0
+#define MX8MM_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B 0x20C 0x474 0x508 0x1 0x0
+#define MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x20C 0x474 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ECSPI2_MISO_TPSMP_HDATA14 0x20C 0x474 0x000 0x7 0x0
+#define MX8MM_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x210 0x478 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x210 0x478 0x508 0x1 0x1
+#define MX8MM_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B 0x210 0x478 0x000 0x1 0x0
+#define MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x210 0x478 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ECSPI2_SS0_TPSMP_HDATA15 0x210 0x478 0x000 0x7 0x0
+#define MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x214 0x47C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_I2C1_SCL_ENET1_MDC 0x214 0x47C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x214 0x47C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_I2C1_SCL_TPSMP_HDATA16 0x214 0x47C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x218 0x480 0x000 0x0 0x0
+#define MX8MM_IOMUXC_I2C1_SDA_ENET1_MDIO 0x218 0x480 0x4C0 0x1 0x2
+#define MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x218 0x480 0x000 0x5 0x0
+#define MX8MM_IOMUXC_I2C1_SDA_TPSMP_HDATA17 0x218 0x480 0x000 0x7 0x0
+#define MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x21C 0x484 0x000 0x0 0x0
+#define MX8MM_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x21C 0x484 0x000 0x1 0x0
+#define MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x21C 0x484 0x000 0x5 0x0
+#define MX8MM_IOMUXC_I2C2_SCL_TPSMP_HDATA18 0x21C 0x484 0x000 0x7 0x0
+#define MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x220 0x488 0x000 0x0 0x0
+#define MX8MM_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x220 0x488 0x000 0x1 0x0
+#define MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x220 0x488 0x000 0x5 0x0
+#define MX8MM_IOMUXC_I2C2_SDA_TPSMP_HDATA19 0x220 0x488 0x000 0x7 0x0
+#define MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x224 0x48C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_I2C3_SCL_PWM4_OUT 0x224 0x48C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_I2C3_SCL_GPT2_CLK 0x224 0x48C 0x000 0x2 0x0
+#define MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x224 0x48C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_I2C3_SCL_TPSMP_HDATA20 0x224 0x48C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x228 0x490 0x000 0x0 0x0
+#define MX8MM_IOMUXC_I2C3_SDA_PWM3_OUT 0x228 0x490 0x000 0x1 0x0
+#define MX8MM_IOMUXC_I2C3_SDA_GPT3_CLK 0x228 0x490 0x000 0x2 0x0
+#define MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x228 0x490 0x000 0x5 0x0
+#define MX8MM_IOMUXC_I2C3_SDA_TPSMP_HDATA21 0x228 0x490 0x000 0x7 0x0
+#define MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x22C 0x494 0x000 0x0 0x0
+#define MX8MM_IOMUXC_I2C4_SCL_PWM2_OUT 0x22C 0x494 0x000 0x1 0x0
+#define MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x22C 0x494 0x524 0x12 0x0
+#define MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x22C 0x494 0x000 0x5 0x0
+#define MX8MM_IOMUXC_I2C4_SCL_TPSMP_HDATA22 0x22C 0x494 0x000 0x7 0x0
+#define MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x230 0x498 0x000 0x0 0x0
+#define MX8MM_IOMUXC_I2C4_SDA_PWM1_OUT 0x230 0x498 0x000 0x1 0x0
+#define MX8MM_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x230 0x498 0x528 0x2 0x0
+#define MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x230 0x498 0x000 0x5 0x0
+#define MX8MM_IOMUXC_I2C4_SDA_TPSMP_HDATA23 0x230 0x498 0x000 0x7 0x0
+#define MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x234 0x49C 0x4F4 0x0 0x0
+#define MX8MM_IOMUXC_UART1_RXD_UART1_DTE_TX 0x234 0x49C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x234 0x49C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_UART1_RXD_GPIO5_IO22 0x234 0x49C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_UART1_RXD_TPSMP_HDATA24 0x234 0x49C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x238 0x4A0 0x000 0x0 0x0
+#define MX8MM_IOMUXC_UART1_TXD_UART1_DTE_RX 0x238 0x4A0 0x4F4 0x0 0x0
+#define MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x238 0x4A0 0x000 0x1 0x0
+#define MX8MM_IOMUXC_UART1_TXD_GPIO5_IO23 0x238 0x4A0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_UART1_TXD_TPSMP_HDATA25 0x238 0x4A0 0x000 0x7 0x0
+#define MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x23C 0x4A4 0x4FC 0x0 0x0
+#define MX8MM_IOMUXC_UART2_RXD_UART2_DTE_TX 0x23C 0x4A4 0x000 0x0 0x0
+#define MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x23C 0x4A4 0x000 0x1 0x0
+#define MX8MM_IOMUXC_UART2_RXD_GPIO5_IO24 0x23C 0x4A4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_UART2_RXD_TPSMP_HDATA26 0x23C 0x4A4 0x000 0x7 0x0
+#define MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x240 0x4A8 0x000 0x0 0x0
+#define MX8MM_IOMUXC_UART2_TXD_UART2_DTE_RX 0x240 0x4A8 0x4FC 0x0 0x1
+#define MX8MM_IOMUXC_UART2_TXD_ECSPI3_SS0 0x240 0x4A8 0x000 0x1 0x0
+#define MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x240 0x4A8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_UART2_TXD_TPSMP_HDATA27 0x240 0x4A8 0x000 0x7 0x0
+#define MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x244 0x4AC 0x504 0x0 0x2
+#define MX8MM_IOMUXC_UART3_RXD_UART3_DTE_TX 0x244 0x4AC 0x000 0x0 0x0
+#define MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x244 0x4AC 0x000 0x1 0x0
+#define MX8MM_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x244 0x4AC 0x4F0 0x1 0x0
+#define MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x244 0x4AC 0x000 0x5 0x0
+#define MX8MM_IOMUXC_UART3_RXD_TPSMP_HDATA28 0x244 0x4AC 0x000 0x7 0x0
+#define MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x248 0x4B0 0x000 0x0 0x0
+#define MX8MM_IOMUXC_UART3_TXD_UART3_DTE_RX 0x248 0x4B0 0x504 0x0 0x3
+#define MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x248 0x4B0 0x4F0 0x1 0x1
+#define MX8MM_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x248 0x4B0 0x000 0x1 0x0
+#define MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x248 0x4B0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_UART3_TXD_TPSMP_HDATA29 0x248 0x4B0 0x000 0x7 0x0
+#define MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x24C 0x4B4 0x50C 0x0 0x2
+#define MX8MM_IOMUXC_UART4_RXD_UART4_DTE_TX 0x24C 0x4B4 0x000 0x0 0x0
+#define MX8MM_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x24C 0x4B4 0x000 0x1 0x0
+#define MX8MM_IOMUXC_UART4_RXD_UART2_DTE_RTS_B 0x24C 0x4B4 0x4F8 0x1 0x0
+#define MX8MM_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x24C 0x4B4 0x524 0x2 0x1
+#define MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28 0x24C 0x4B4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_UART4_RXD_TPSMP_HDATA30 0x24C 0x4B4 0x000 0x7 0x0
+#define MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x250 0x4B8 0x000 0x0 0x0
+#define MX8MM_IOMUXC_UART4_TXD_UART4_DTE_RX 0x250 0x4B8 0x50C 0x0 0x3
+#define MX8MM_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x250 0x4B8 0x4F8 0x1 0x1
+#define MX8MM_IOMUXC_UART4_TXD_UART2_DTE_CTS_B 0x250 0x4B8 0x000 0x1 0x0
+#define MX8MM_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x250 0x4B8 0x528 0x2 0x1
+#define MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x250 0x4B8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_UART4_TXD_TPSMP_HDATA31 0x250 0x4B8 0x000 0x7 0x0
+
+#endif /* __DTS_IMX8MM_PINFUNC_H */
--
2.14.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* [U-Boot] [PATCH 05/20] imx: add i.MX8MM cpu type
2019-01-28 9:39 [U-Boot] [PATCH 00/20] imx: add i.MX8MM support Peng Fan
` (3 preceding siblings ...)
2019-01-28 9:39 ` [U-Boot] [PATCH 04/20] imx: add pin binding header for i.MX8MM Peng Fan
@ 2019-01-28 9:39 ` Peng Fan
2019-01-28 9:39 ` [U-Boot] [PATCH 06/20] imx8m: update imx-regs for i.MX8MM Peng Fan
` (14 subsequent siblings)
19 siblings, 0 replies; 39+ messages in thread
From: Peng Fan @ 2019-01-28 9:39 UTC (permalink / raw)
To: u-boot
Add i.MX8MM cpu type and related helper functions
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/include/asm/arch-imx/cpu.h | 6 ++++++
arch/arm/include/asm/mach-imx/sys_proto.h | 8 ++++++++
arch/arm/mach-imx/cpu.c | 12 ++++++++++++
3 files changed, 26 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h
index d4a83eef72..4296e47b9e 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -25,6 +25,12 @@
#define MXC_CPU_MX7S 0x71 /* dummy ID */
#define MXC_CPU_MX7D 0x72
#define MXC_CPU_IMX8MQ 0x82
+#define MXC_CPU_IMX8MM 0x85 /* dummy ID */
+#define MXC_CPU_IMX8MML 0x86 /* dummy ID */
+#define MXC_CPU_IMX8MMD 0x87 /* dummy ID */
+#define MXC_CPU_IMX8MMDL 0x88 /* dummy ID */
+#define MXC_CPU_IMX8MMS 0x89 /* dummy ID */
+#define MXC_CPU_IMX8MMSL 0x8a /* dummy ID */
#define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */
#define MXC_CPU_IMX8QM 0x91 /* dummy ID */
#define MXC_CPU_IMX8QXP 0x92 /* dummy ID */
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h
index 8d6832a331..bfe87b577b 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -43,6 +43,14 @@
#define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP))
#define is_imx8mq() (is_cpu_type(MXC_CPU_IMX8MQ))
+#define is_imx8mm() (is_cpu_type(MXC_CPU_IMX8MM) || is_cpu_type(MXC_CPU_IMX8MML) ||\
+ is_cpu_type(MXC_CPU_IMX8MMD) || is_cpu_type(MXC_CPU_IMX8MMDL) || \
+ is_cpu_type(MXC_CPU_IMX8MMS) || is_cpu_type(MXC_CPU_IMX8MMSL))
+#define is_imx8mml() (is_cpu_type(MXC_CPU_IMX8MML))
+#define is_imx8mmd() (is_cpu_type(MXC_CPU_IMX8MMD))
+#define is_imx8mmdl() (is_cpu_type(MXC_CPU_IMX8MMDL))
+#define is_imx8mms() (is_cpu_type(MXC_CPU_IMX8MMS))
+#define is_imx8mmsl() (is_cpu_type(MXC_CPU_IMX8MMSL))
#define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP))
#ifdef CONFIG_MX6
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index 80d9ff48a4..3355b51030 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -142,6 +142,18 @@ unsigned imx_ddr_size(void)
const char *get_imx_type(u32 imxtype)
{
switch (imxtype) {
+ case MXC_CPU_IMX8MM:
+ return "8MMQ"; /* Quad-core version of the imx8mm */
+ case MXC_CPU_IMX8MML:
+ return "8MMQL"; /* Quad-core Lite version of the imx8mm */
+ case MXC_CPU_IMX8MMD:
+ return "8MMD"; /* Dual-core version of the imx8mm */
+ case MXC_CPU_IMX8MMDL:
+ return "8MMDL"; /* Dual-core Lite version of the imx8mm */
+ case MXC_CPU_IMX8MMS:
+ return "8MMS"; /* Single-core version of the imx8mm */
+ case MXC_CPU_IMX8MMSL:
+ return "8MMSL"; /* Single-core Lite version of the imx8mm */
case MXC_CPU_IMX8MQ:
return "8MQ"; /* Quad-core version of the imx8m */
case MXC_CPU_MX7S:
--
2.14.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* [U-Boot] [PATCH 06/20] imx8m: update imx-regs for i.MX8MM
2019-01-28 9:39 [U-Boot] [PATCH 00/20] imx: add i.MX8MM support Peng Fan
` (4 preceding siblings ...)
2019-01-28 9:39 ` [U-Boot] [PATCH 05/20] imx: add i.MX8MM cpu type Peng Fan
@ 2019-01-28 9:39 ` Peng Fan
2019-01-28 9:39 ` [U-Boot] [PATCH 07/20] imx: add get_cpu_rev support " Peng Fan
` (13 subsequent siblings)
19 siblings, 0 replies; 39+ messages in thread
From: Peng Fan @ 2019-01-28 9:39 UTC (permalink / raw)
To: u-boot
i.MX8MM has similar architecture with i.MX8MQ, but it has totally
different PLL design and some register layout change.
Note: Some registers in this file are not updated because not used now.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/include/asm/arch-imx8m/imx-regs.h | 75 ++++++++++++++++++++++++++++--
1 file changed, 71 insertions(+), 4 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index 3facd5450c..44b2f728ee 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -8,8 +8,8 @@
#include <asm/mach-imx/regs-lcdif.h>
-#define ROM_VERSION_A0 0x800
-#define ROM_VERSION_B0 0x83C
+#define ROM_VERSION_A0 IS_ENABLED(CONFIG_IMX8MQ) ? 0x800 : 0x800
+#define ROM_VERSION_B0 IS_ENABLED(CONFIG_IMX8MQ) ? 0x83C : 0x800
#define M4_BOOTROM_BASE_ADDR 0x007E0000
@@ -91,7 +91,11 @@
#define SEMAPHOR_HS_BASE_ADDR 0x30AC0000
#define USDHC1_BASE_ADDR 0x30B40000
#define USDHC2_BASE_ADDR 0x30B50000
+#ifdef CONFIG_IMX8MM
+#define USDHC3_BASE_ADDR 0x30B60000
+#else
#define MIPI_CS2_BASE_ADDR 0x30B60000
+#endif
#define MIPI_CSI_PHY2_BASE_ADDR 0x30B70000
#define CSI2_BASE_ADDR 0x30B80000
#define QSPI0_BASE_ADDR 0x30BB0000
@@ -118,7 +122,8 @@
#define USB1_PHY_BASE_ADDR 0x381F0000
#define USB2_PHY_BASE_ADDR 0x382F0000
-#define MXS_LCDIF_BASE LCDIF_BASE_ADDR
+#define MXS_LCDIF_BASE is_enable(CONFIG_IMX8MQ) ? \
+ 0x30320000 : 0x32e00000
#define SRC_IPS_BASE_ADDR 0x30390000
#define SRC_DDRC_RCR_ADDR 0x30391000
@@ -147,6 +152,9 @@
#define SRC_DDR1_RCR_CORE_RESET_N_MASK BIT(1)
#define SRC_DDR1_RCR_PRESET_N_MASK BIT(0)
+#define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK 0x2000u
+#define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT 13
+
struct iomuxc_gpr_base_regs {
u32 gpr[47];
};
@@ -203,6 +211,7 @@ struct fuse_bank1_regs {
u32 rsvd3[3];
};
+#ifdef CONFIG_IMX8MQ
struct anamix_pll {
u32 audio_pll1_cfg0;
u32 audio_pll1_cfg1;
@@ -237,6 +246,60 @@ struct anamix_pll {
u32 frac_pllout_div_cfg;
u32 sscg_pllout_div_cfg;
};
+#else
+struct anamix_pll {
+ u32 audio_pll1_gnrl_ctl;
+ u32 audio_pll1_fdiv_ctl0;
+ u32 audio_pll1_fdiv_ctl1;
+ u32 audio_pll1_sscg_ctl;
+ u32 audio_pll1_mnit_ctl;
+ u32 audio_pll2_gnrl_ctl;
+ u32 audio_pll2_fdiv_ctl0;
+ u32 audio_pll2_fdiv_ctl1;
+ u32 audio_pll2_sscg_ctl;
+ u32 audio_pll2_mnit_ctl;
+ u32 video_pll1_gnrl_ctl;
+ u32 video_pll1_fdiv_ctl0;
+ u32 video_pll1_fdiv_ctl1;
+ u32 video_pll1_sscg_ctl;
+ u32 video_pll1_mnit_ctl;
+ u32 reserved[5];
+ u32 dram_pll_gnrl_ctl;
+ u32 dram_pll_fdiv_ctl0;
+ u32 dram_pll_fdiv_ctl1;
+ u32 dram_pll_sscg_ctl;
+ u32 dram_pll_mnit_ctl;
+ u32 gpu_pll_gnrl_ctl;
+ u32 gpu_pll_div_ctl;
+ u32 gpu_pll_locked_ctl1;
+ u32 gpu_pll_mnit_ctl;
+ u32 vpu_pll_gnrl_ctl;
+ u32 vpu_pll_div_ctl;
+ u32 vpu_pll_locked_ctl1;
+ u32 vpu_pll_mnit_ctl;
+ u32 arm_pll_gnrl_ctl;
+ u32 arm_pll_div_ctl;
+ u32 arm_pll_locked_ctl1;
+ u32 arm_pll_mnit_ctl;
+ u32 sys_pll1_gnrl_ctl;
+ u32 sys_pll1_div_ctl;
+ u32 sys_pll1_locked_ctl1;
+ u32 reserved2[24];
+ u32 sys_pll1_mnit_ctl;
+ u32 sys_pll2_gnrl_ctl;
+ u32 sys_pll2_div_ctl;
+ u32 sys_pll2_locked_ctl1;
+ u32 sys_pll2_mnit_ctl;
+ u32 sys_pll3_gnrl_ctl;
+ u32 sys_pll3_div_ctl;
+ u32 sys_pll3_locked_ctl1;
+ u32 sys_pll3_mnit_ctl;
+ u32 anamix_misc_ctl;
+ u32 anamix_clk_mnit_ctl;
+ u32 reserved3[437];
+ u32 digprog;
+};
+#endif
struct fuse_bank9_regs {
u32 mac_addr0;
@@ -256,11 +319,13 @@ struct src {
u32 usbophy2_rcr;
u32 mipiphy_rcr;
u32 pciephy_rcr;
+ /* Exits on i.MX8MQ */
u32 hdmi_rcr;
u32 disp_rcr;
u32 reserved2[2];
u32 gpu_rcr;
u32 vpu_rcr;
+ /* The following four exits on i.MX8MQ */
u32 pcie2_rcr;
u32 mipiphy1_rcr;
u32 mipiphy2_rcr;
@@ -283,6 +348,7 @@ struct src {
u32 gpr10;
u32 reserved5[985];
u32 ddr1_rcr;
+ /* Exist on i.MX8MQ */
u32 ddr2_rcr;
};
@@ -457,7 +523,8 @@ struct bootrom_sw_info {
u32 reserved_3[3];
};
-#define ROM_SW_INFO_ADDR_B0 0x00000968
+#define ROM_SW_INFO_ADDR_B0 (IS_ENABLED(CONFIG_IMX8MQ) ? 0x00000968 :\
+ 0x000009e8)
#define ROM_SW_INFO_ADDR_A0 0x000009e8
#define ROM_SW_INFO_ADDR is_soc_rev(CHIP_REV_1_0) ? \
--
2.14.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* [U-Boot] [PATCH 07/20] imx: add get_cpu_rev support for i.MX8MM
2019-01-28 9:39 [U-Boot] [PATCH 00/20] imx: add i.MX8MM support Peng Fan
` (5 preceding siblings ...)
2019-01-28 9:39 ` [U-Boot] [PATCH 06/20] imx8m: update imx-regs for i.MX8MM Peng Fan
@ 2019-01-28 9:39 ` Peng Fan
2019-01-28 9:39 ` [U-Boot] [PATCH 08/20] imx8m: rename clock to clock_imx8mq Peng Fan
` (12 subsequent siblings)
19 siblings, 0 replies; 39+ messages in thread
From: Peng Fan @ 2019-01-28 9:39 UTC (permalink / raw)
To: u-boot
There are several variants based on i.MX8MM, add the support in
get_cpu_rev
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/mach-imx/imx8m/soc.c | 57 +++++++++++++++++++++++++++++++++++--------
1 file changed, 47 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 11251c5f9a..4160a75918 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -130,25 +130,62 @@ static struct mm_region imx8m_mem_map[] = {
struct mm_region *mem_map = imx8m_mem_map;
+static u32 get_cpu_variant_type(u32 type)
+{
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = &ocotp->bank[1];
+ struct fuse_bank1_regs *fuse =
+ (struct fuse_bank1_regs *)bank->fuse_regs;
+
+ u32 value = readl(&fuse->tester4);
+
+ if (type == MXC_CPU_IMX8MM) {
+ switch (value & 0x3) {
+ case 2:
+ if (value & 0x1c0000)
+ return MXC_CPU_IMX8MMDL;
+ else
+ return MXC_CPU_IMX8MMD;
+ case 3:
+ if (value & 0x1c0000)
+ return MXC_CPU_IMX8MMSL;
+ else
+ return MXC_CPU_IMX8MMS;
+ default:
+ if (value & 0x1c0000)
+ return MXC_CPU_IMX8MML;
+ break;
+ }
+ }
+
+ return type;
+}
+
u32 get_cpu_rev(void)
{
struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
u32 reg = readl(&ana_pll->digprog);
u32 type = (reg >> 16) & 0xff;
+ u32 major_low = (reg >> 8) & 0xff;
u32 rom_version;
reg &= 0xff;
- if (reg == CHIP_REV_1_0) {
- /*
- * For B0 chip, the DIGPROG is not updated, still TO1.0.
- * we have to check ROM version further
- */
- rom_version = readl((void __iomem *)ROM_VERSION_A0);
- if (rom_version != CHIP_REV_1_0) {
- rom_version = readl((void __iomem *)ROM_VERSION_B0);
- if (rom_version >= CHIP_REV_2_0)
- reg = CHIP_REV_2_0;
+ /* i.MX8MM */
+ if (major_low == 0x41) {
+ type = get_cpu_variant_type(MXC_CPU_IMX8MM);
+ } else {
+ if (reg == CHIP_REV_1_0) {
+ /*
+ * For B0 chip, the DIGPROG is not updated, still TO1.0.
+ * we have to check ROM version further
+ */
+ rom_version = readl((void __iomem *)ROM_VERSION_A0);
+ if (rom_version != CHIP_REV_1_0) {
+ rom_version = readl((void __iomem *)ROM_VERSION_B0);
+ if (rom_version >= CHIP_REV_2_0)
+ reg = CHIP_REV_2_0;
+ }
}
}
--
2.14.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* [U-Boot] [PATCH 08/20] imx8m: rename clock to clock_imx8mq
2019-01-28 9:39 [U-Boot] [PATCH 00/20] imx: add i.MX8MM support Peng Fan
` (6 preceding siblings ...)
2019-01-28 9:39 ` [U-Boot] [PATCH 07/20] imx: add get_cpu_rev support " Peng Fan
@ 2019-01-28 9:39 ` Peng Fan
2019-01-28 9:39 ` [U-Boot] [PATCH 09/20] imx8m: restructure clock.h Peng Fan
` (11 subsequent siblings)
19 siblings, 0 replies; 39+ messages in thread
From: Peng Fan @ 2019-01-28 9:39 UTC (permalink / raw)
To: u-boot
i.MX8MQ and i.MX8MM has totally different pll design, so
rename clock to clock_imx8mq, then we will add clock_imx8mm.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/mach-imx/imx8m/Makefile | 3 +-
.../arm/mach-imx/imx8m/{clock.c => clock_imx8mq.c} | 0
include/dt-bindings/clock/imx8mm-clock.h | 168 ++++++++++-----------
3 files changed, 86 insertions(+), 85 deletions(-)
rename arch/arm/mach-imx/imx8m/{clock.c => clock_imx8mq.c} (100%)
diff --git a/arch/arm/mach-imx/imx8m/Makefile b/arch/arm/mach-imx/imx8m/Makefile
index feff4941c1..42a1544c6b 100644
--- a/arch/arm/mach-imx/imx8m/Makefile
+++ b/arch/arm/mach-imx/imx8m/Makefile
@@ -3,4 +3,5 @@
# Copyright 2017 NXP
obj-y += lowlevel_init.o
-obj-y += clock.o clock_slice.o soc.o
+obj-y += clock_slice.o soc.o
+obj-$(CONFIG_IMX8MQ) += clock_imx8mq.o
diff --git a/arch/arm/mach-imx/imx8m/clock.c b/arch/arm/mach-imx/imx8m/clock_imx8mq.c
similarity index 100%
rename from arch/arm/mach-imx/imx8m/clock.c
rename to arch/arm/mach-imx/imx8m/clock_imx8mq.c
diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings/clock/imx8mm-clock.h
index d093a87c6f..bb0bf43f71 100644
--- a/include/dt-bindings/clock/imx8mm-clock.h
+++ b/include/dt-bindings/clock/imx8mm-clock.h
@@ -28,44 +28,44 @@
#define IMX8MM_AUDIO_PLL2 19
#define IMX8MM_VIDEO_PLL1 20
#define IMX8MM_DRAM_PLL 21
-#define IMX8MM_GPU_PLL 22
-#define IMX8MM_VPU_PLL 23
-#define IMX8MM_ARM_PLL 24
-#define IMX8MM_SYS_PLL1 25
-#define IMX8MM_SYS_PLL2 26
-#define IMX8MM_SYS_PLL3 27
-#define IMX8MM_AUDIO_PLL1_BYPASS 28
-#define IMX8MM_AUDIO_PLL2_BYPASS 29
+#define IMX8MM_GPU_PLL 22
+#define IMX8MM_VPU_PLL 23
+#define IMX8MM_ARM_PLL 24
+#define IMX8MM_SYS_PLL1 25
+#define IMX8MM_SYS_PLL2 26
+#define IMX8MM_SYS_PLL3 27
+#define IMX8MM_AUDIO_PLL1_BYPASS 28
+#define IMX8MM_AUDIO_PLL2_BYPASS 29
#define IMX8MM_VIDEO_PLL1_BYPASS 30
-#define IMX8MM_DRAM_PLL_BYPASS 31
-#define IMX8MM_GPU_PLL_BYPASS 32
-#define IMX8MM_VPU_PLL_BYPASS 33
-#define IMX8MM_ARM_PLL_BYPASS 34
-#define IMX8MM_SYS_PLL1_BYPASS 35
-#define IMX8MM_SYS_PLL2_BYPASS 36
-#define IMX8MM_SYS_PLL3_BYPASS 37
-#define IMX8MM_AUDIO_PLL1_OUT 38
-#define IMX8MM_AUDIO_PLL2_OUT 39
+#define IMX8MM_DRAM_PLL_BYPASS 31
+#define IMX8MM_GPU_PLL_BYPASS 32
+#define IMX8MM_VPU_PLL_BYPASS 33
+#define IMX8MM_ARM_PLL_BYPASS 34
+#define IMX8MM_SYS_PLL1_BYPASS 35
+#define IMX8MM_SYS_PLL2_BYPASS 36
+#define IMX8MM_SYS_PLL3_BYPASS 37
+#define IMX8MM_AUDIO_PLL1_OUT 38
+#define IMX8MM_AUDIO_PLL2_OUT 39
#define IMX8MM_VIDEO_PLL1_OUT 40
-#define IMX8MM_DRAM_PLL_OUT 41
-#define IMX8MM_GPU_PLL_OUT 42
-#define IMX8MM_VPU_PLL_OUT 43
-#define IMX8MM_ARM_PLL_OUT 44
-#define IMX8MM_SYS_PLL1_OUT 45
-#define IMX8MM_SYS_PLL2_OUT 46
-#define IMX8MM_SYS_PLL3_OUT 47
-#define IMX8MM_SYS_PLL1_40M 48
-#define IMX8MM_SYS_PLL1_80M 49
+#define IMX8MM_DRAM_PLL_OUT 41
+#define IMX8MM_GPU_PLL_OUT 42
+#define IMX8MM_VPU_PLL_OUT 43
+#define IMX8MM_ARM_PLL_OUT 44
+#define IMX8MM_SYS_PLL1_OUT 45
+#define IMX8MM_SYS_PLL2_OUT 46
+#define IMX8MM_SYS_PLL3_OUT 47
+#define IMX8MM_SYS_PLL1_40M 48
+#define IMX8MM_SYS_PLL1_80M 49
#define IMX8MM_SYS_PLL1_100M 50
-#define IMX8MM_SYS_PLL1_133M 51
-#define IMX8MM_SYS_PLL1_160M 52
-#define IMX8MM_SYS_PLL1_200M 53
-#define IMX8MM_SYS_PLL1_266M 54
-#define IMX8MM_SYS_PLL1_400M 55
-#define IMX8MM_SYS_PLL1_800M 56
-#define IMX8MM_SYS_PLL2_50M 57
-#define IMX8MM_SYS_PLL2_100M 58
-#define IMX8MM_SYS_PLL2_125M 59
+#define IMX8MM_SYS_PLL1_133M 51
+#define IMX8MM_SYS_PLL1_160M 52
+#define IMX8MM_SYS_PLL1_200M 53
+#define IMX8MM_SYS_PLL1_266M 54
+#define IMX8MM_SYS_PLL1_400M 55
+#define IMX8MM_SYS_PLL1_800M 56
+#define IMX8MM_SYS_PLL2_50M 57
+#define IMX8MM_SYS_PLL2_100M 58
+#define IMX8MM_SYS_PLL2_125M 59
#define IMX8MM_SYS_PLL2_166M 60
#define IMX8MM_SYS_PLL2_200M 61
#define IMX8MM_SYS_PLL2_250M 62
@@ -77,59 +77,59 @@
#define IMX8MM_CLK_VPU_SRC 68
#define IMX8MM_CLK_GPU3D_SRC 69
#define IMX8MM_CLK_GPU2D_SRC 70
-#define IMX8MM_CLK_A53_CG 71
-#define IMX8MM_CLK_M4_CG 72
-#define IMX8MM_CLK_VPU_CG 73
-#define IMX8MM_CLK_GPU3D_CG 74
-#define IMX8MM_CLK_GPU2D_CG 75
-#define IMX8MM_CLK_A53_DIV 76
-#define IMX8MM_CLK_M4_DIV 77
-#define IMX8MM_CLK_VPU_DIV 78
-#define IMX8MM_CLK_GPU3D_DIV 79
+#define IMX8MM_CLK_A53_CG 71
+#define IMX8MM_CLK_M4_CG 72
+#define IMX8MM_CLK_VPU_CG 73
+#define IMX8MM_CLK_GPU3D_CG 74
+#define IMX8MM_CLK_GPU2D_CG 75
+#define IMX8MM_CLK_A53_DIV 76
+#define IMX8MM_CLK_M4_DIV 77
+#define IMX8MM_CLK_VPU_DIV 78
+#define IMX8MM_CLK_GPU3D_DIV 79
#define IMX8MM_CLK_GPU2D_DIV 80
#define IMX8MM_CLK_MAIN_AXI_SRC 81
-#define IMX8MM_CLK_ENET_AXI_SRC 82
-#define IMX8MM_CLK_NAND_USDHC_BUS_SRC 83
-#define IMX8MM_CLK_VPU_BUS_SRC 84
-#define IMX8MM_CLK_DISP_AXI_SRC 85
-#define IMX8MM_CLK_DISP_APB_SRC 86
-#define IMX8MM_CLK_DISP_RTRM_SRC 87
-#define IMX8MM_CLK_USB_BUS_SRC 88
-#define IMX8MM_CLK_GPU_AXI_SRC 89
+#define IMX8MM_CLK_ENET_AXI_SRC 82
+#define IMX8MM_CLK_NAND_USDHC_BUS_SRC 83
+#define IMX8MM_CLK_VPU_BUS_SRC 84
+#define IMX8MM_CLK_DISP_AXI_SRC 85
+#define IMX8MM_CLK_DISP_APB_SRC 86
+#define IMX8MM_CLK_DISP_RTRM_SRC 87
+#define IMX8MM_CLK_USB_BUS_SRC 88
+#define IMX8MM_CLK_GPU_AXI_SRC 89
#define IMX8MM_CLK_GPU_AHB_SRC 90
-#define IMX8MM_CLK_NOC_SRC 91
-#define IMX8MM_CLK_NOC_APB_SRC 92
-#define IMX8MM_CLK_MAIN_AXI_CG 93
-#define IMX8MM_CLK_ENET_AXI_CG 94
-#define IMX8MM_CLK_NAND_USDHC_BUS_CG 95
-#define IMX8MM_CLK_VPU_BUS_CG 96
-#define IMX8MM_CLK_DISP_AXI_CG 97
-#define IMX8MM_CLK_DISP_APB_CG 98
-#define IMX8MM_CLK_DISP_RTRM_CG 99
+#define IMX8MM_CLK_NOC_SRC 91
+#define IMX8MM_CLK_NOC_APB_SRC 92
+#define IMX8MM_CLK_MAIN_AXI_CG 93
+#define IMX8MM_CLK_ENET_AXI_CG 94
+#define IMX8MM_CLK_NAND_USDHC_BUS_CG 95
+#define IMX8MM_CLK_VPU_BUS_CG 96
+#define IMX8MM_CLK_DISP_AXI_CG 97
+#define IMX8MM_CLK_DISP_APB_CG 98
+#define IMX8MM_CLK_DISP_RTRM_CG 99
#define IMX8MM_CLK_USB_BUS_CG 100
-#define IMX8MM_CLK_GPU_AXI_CG 101
-#define IMX8MM_CLK_GPU_AHB_CG 102
-#define IMX8MM_CLK_NOC_CG 103
-#define IMX8MM_CLK_NOC_APB_CG 104
-#define IMX8MM_CLK_MAIN_AXI_PRE_DIV 105
-#define IMX8MM_CLK_ENET_AXI_PRE_DIV 106
-#define IMX8MM_CLK_NAND_USDHC_BUS_PRE_DIV 107
-#define IMX8MM_CLK_VPU_BUS_PRE_DIV 108
-#define IMX8MM_CLK_DISP_AXI_PRE_DIV 109
-#define IMX8MM_CLK_DISP_APB_PRE_DIV 110
-#define IMX8MM_CLK_DISP_RTRM_PRE_DIV 111
-#define IMX8MM_CLK_USB_BUS_PRE_DIV 112
-#define IMX8MM_CLK_GPU_AXI_PRE_DIV 113
-#define IMX8MM_CLK_GPU_AHB_PRE_DIV 114
-#define IMX8MM_CLK_NOC_PRE_DIV 115
-#define IMX8MM_CLK_NOC_APB_PRE_DIV 116
-#define IMX8MM_CLK_MAIN_AXI_DIV 117
-#define IMX8MM_CLK_ENET_AXI_DIV 118
-#define IMX8MM_CLK_NAND_USDHC_BUS 119
-#define IMX8MM_CLK_VPU_BUS_DIV 120
-#define IMX8MM_CLK_DISP_AXI_DIV 121
-#define IMX8MM_CLK_DISP_APB_DIV 122
-#define IMX8MM_CLK_DISP_RTRM_DIV 123
+#define IMX8MM_CLK_GPU_AXI_CG 101
+#define IMX8MM_CLK_GPU_AHB_CG 102
+#define IMX8MM_CLK_NOC_CG 103
+#define IMX8MM_CLK_NOC_APB_CG 104
+#define IMX8MM_CLK_MAIN_AXI_PRE_DIV 105
+#define IMX8MM_CLK_ENET_AXI_PRE_DIV 106
+#define IMX8MM_CLK_NAND_USDHC_BUS_PRE_DIV 107
+#define IMX8MM_CLK_VPU_BUS_PRE_DIV 108
+#define IMX8MM_CLK_DISP_AXI_PRE_DIV 109
+#define IMX8MM_CLK_DISP_APB_PRE_DIV 110
+#define IMX8MM_CLK_DISP_RTRM_PRE_DIV 111
+#define IMX8MM_CLK_USB_BUS_PRE_DIV 112
+#define IMX8MM_CLK_GPU_AXI_PRE_DIV 113
+#define IMX8MM_CLK_GPU_AHB_PRE_DIV 114
+#define IMX8MM_CLK_NOC_PRE_DIV 115
+#define IMX8MM_CLK_NOC_APB_PRE_DIV 116
+#define IMX8MM_CLK_MAIN_AXI_DIV 117
+#define IMX8MM_CLK_ENET_AXI_DIV 118
+#define IMX8MM_CLK_NAND_USDHC_BUS 119
+#define IMX8MM_CLK_VPU_BUS_DIV 120
+#define IMX8MM_CLK_DISP_AXI_DIV 121
+#define IMX8MM_CLK_DISP_APB_DIV 122
+#define IMX8MM_CLK_DISP_RTRM_DIV 123
#define IMX8MM_CLK_USB_BUS_DIV 124
#define IMX8MM_CLK_GPU_AXI_DIV 125
#define IMX8MM_CLK_GPU_AHB_DIV 126
--
2.14.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* [U-Boot] [PATCH 09/20] imx8m: restructure clock.h
2019-01-28 9:39 [U-Boot] [PATCH 00/20] imx: add i.MX8MM support Peng Fan
` (7 preceding siblings ...)
2019-01-28 9:39 ` [U-Boot] [PATCH 08/20] imx8m: rename clock to clock_imx8mq Peng Fan
@ 2019-01-28 9:39 ` Peng Fan
2019-01-28 9:39 ` [U-Boot] [PATCH 10/20] imx8m: add clk support for i.MX8MM Peng Fan
` (10 subsequent siblings)
19 siblings, 0 replies; 39+ messages in thread
From: Peng Fan @ 2019-01-28 9:39 UTC (permalink / raw)
To: u-boot
i.MX8MQ and i.MX8MM use different analog pll design, but they
share same ccm design.
Add clock_imx8mq.h for i.MX8MQ
keep common part in clock.h
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/include/asm/arch-imx8m/clock.h | 491 +++----------------------
arch/arm/include/asm/arch-imx8m/clock_imx8mq.h | 424 +++++++++++++++++++++
arch/arm/mach-imx/imx8m/clock_imx8mq.c | 5 +-
3 files changed, 467 insertions(+), 453 deletions(-)
create mode 100644 arch/arm/include/asm/arch-imx8m/clock_imx8mq.h
diff --git a/arch/arm/include/asm/arch-imx8m/clock.h b/arch/arm/include/asm/arch-imx8m/clock.h
index e7c1670f6b..7225c760fe 100644
--- a/arch/arm/include/asm/arch-imx8m/clock.h
+++ b/arch/arm/include/asm/arch-imx8m/clock.h
@@ -1,28 +1,29 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2017 NXP
- *
- * Peng Fan <peng.fan@nxp.com>
+ * Copyright 2017-2019 NXP
*/
-#ifndef _ASM_ARCH_IMX8M_CLOCK_H
-#define _ASM_ARCH_IMX8M_CLOCK_H
-
#include <linux/bitops.h>
+#ifdef CONFIG_IMX8MQ
+#include <asm/arch/clock_imx8mq.h>
+#else
+#error "Error no clock.h"
+#endif
+
#define MHZ(X) ((X) * 1000000UL)
-enum pll_clocks {
- ANATOP_ARM_PLL,
- ANATOP_GPU_PLL,
- ANATOP_SYSTEM_PLL1,
- ANATOP_SYSTEM_PLL2,
- ANATOP_SYSTEM_PLL3,
- ANATOP_AUDIO_PLL1,
- ANATOP_AUDIO_PLL2,
- ANATOP_VIDEO_PLL1,
- ANATOP_VIDEO_PLL2,
- ANATOP_DRAM_PLL,
+/* Mainly for compatible to imx common code. */
+enum mxc_clock {
+ MXC_ARM_CLK = 0,
+ MXC_IPG_CLK,
+ MXC_CSPI_CLK,
+ MXC_ESDHC_CLK,
+ MXC_ESDHC2_CLK,
+ MXC_ESDHC3_CLK,
+ MXC_I2C_CLK,
+ MXC_UART_CLK,
+ MXC_QSPI_CLK,
};
enum clk_slice_type {
@@ -35,297 +36,6 @@ enum clk_slice_type {
DRAM_SEL_CLOCK_SLICE,
};
-enum clk_root_index {
- MXC_ARM_CLK = 0,
- ARM_A53_CLK_ROOT = 0,
- ARM_M4_CLK_ROOT = 1,
- VPU_A53_CLK_ROOT = 2,
- GPU_CORE_CLK_ROOT = 3,
- GPU_SHADER_CLK_ROOT = 4,
- MAIN_AXI_CLK_ROOT = 16,
- ENET_AXI_CLK_ROOT = 17,
- NAND_USDHC_BUS_CLK_ROOT = 18,
- VPU_BUS_CLK_ROOT = 19,
- DISPLAY_AXI_CLK_ROOT = 20,
- DISPLAY_APB_CLK_ROOT = 21,
- DISPLAY_RTRM_CLK_ROOT = 22,
- USB_BUS_CLK_ROOT = 23,
- GPU_AXI_CLK_ROOT = 24,
- GPU_AHB_CLK_ROOT = 25,
- NOC_CLK_ROOT = 26,
- NOC_APB_CLK_ROOT = 27,
- AHB_CLK_ROOT = 32,
- IPG_CLK_ROOT = 33,
- MXC_IPG_CLK = 33,
- AUDIO_AHB_CLK_ROOT = 34,
- MIPI_DSI_ESC_RX_CLK_ROOT = 36,
- DRAM_SEL_CFG = 48,
- CORE_SEL_CFG = 49,
- DRAM_ALT_CLK_ROOT = 64,
- DRAM_APB_CLK_ROOT = 65,
- VPU_G1_CLK_ROOT = 66,
- VPU_G2_CLK_ROOT = 67,
- DISPLAY_DTRC_CLK_ROOT = 68,
- DISPLAY_DC8000_CLK_ROOT = 69,
- PCIE1_CTRL_CLK_ROOT = 70,
- PCIE1_PHY_CLK_ROOT = 71,
- PCIE1_AUX_CLK_ROOT = 72,
- DC_PIXEL_CLK_ROOT = 73,
- LCDIF_PIXEL_CLK_ROOT = 74,
- SAI1_CLK_ROOT = 75,
- SAI2_CLK_ROOT = 76,
- SAI3_CLK_ROOT = 77,
- SAI4_CLK_ROOT = 78,
- SAI5_CLK_ROOT = 79,
- SAI6_CLK_ROOT = 80,
- SPDIF1_CLK_ROOT = 81,
- SPDIF2_CLK_ROOT = 82,
- ENET_REF_CLK_ROOT = 83,
- ENET_TIMER_CLK_ROOT = 84,
- ENET_PHY_REF_CLK_ROOT = 85,
- NAND_CLK_ROOT = 86,
- QSPI_CLK_ROOT = 87,
- MXC_ESDHC_CLK = 88,
- USDHC1_CLK_ROOT = 88,
- MXC_ESDHC2_CLK = 89,
- USDHC2_CLK_ROOT = 89,
- I2C1_CLK_ROOT = 90,
- MXC_I2C_CLK = 90,
- I2C2_CLK_ROOT = 91,
- I2C3_CLK_ROOT = 92,
- I2C4_CLK_ROOT = 93,
- UART1_CLK_ROOT = 94,
- UART2_CLK_ROOT = 95,
- UART3_CLK_ROOT = 96,
- UART4_CLK_ROOT = 97,
- USB_CORE_REF_CLK_ROOT = 98,
- USB_PHY_REF_CLK_ROOT = 99,
- GIC_CLK_ROOT = 100,
- ECSPI1_CLK_ROOT = 101,
- ECSPI2_CLK_ROOT = 102,
- PWM1_CLK_ROOT = 103,
- PWM2_CLK_ROOT = 104,
- PWM3_CLK_ROOT = 105,
- PWM4_CLK_ROOT = 106,
- GPT1_CLK_ROOT = 107,
- GPT2_CLK_ROOT = 108,
- GPT3_CLK_ROOT = 109,
- GPT4_CLK_ROOT = 110,
- GPT5_CLK_ROOT = 111,
- GPT6_CLK_ROOT = 112,
- TRACE_CLK_ROOT = 113,
- WDOG_CLK_ROOT = 114,
- WRCLK_CLK_ROOT = 115,
- IPP_DO_CLKO1 = 116,
- IPP_DO_CLKO2 = 117,
- MIPI_DSI_CORE_CLK_ROOT = 118,
- MIPI_DSI_PHY_REF_CLK_ROOT = 119,
- MIPI_DSI_DBI_CLK_ROOT = 120,
- OLD_MIPI_DSI_ESC_CLK_ROOT = 121,
- MIPI_CSI1_CORE_CLK_ROOT = 122,
- MIPI_CSI1_PHY_REF_CLK_ROOT = 123,
- MIPI_CSI1_ESC_CLK_ROOT = 124,
- MIPI_CSI2_CORE_CLK_ROOT = 125,
- MIPI_CSI2_PHY_REF_CLK_ROOT = 126,
- MIPI_CSI2_ESC_CLK_ROOT = 127,
- PCIE2_CTRL_CLK_ROOT = 128,
- PCIE2_PHY_CLK_ROOT = 129,
- PCIE2_AUX_CLK_ROOT = 130,
- ECSPI3_CLK_ROOT = 131,
- OLD_MIPI_DSI_ESC_RX_ROOT = 132,
- DISPLAY_HDMI_CLK_ROOT = 133,
- CLK_ROOT_MAX,
-};
-
-enum clk_root_src {
- OSC_25M_CLK,
- ARM_PLL_CLK,
- DRAM_PLL1_CLK,
- VIDEO_PLL2_CLK,
- VPU_PLL_CLK,
- GPU_PLL_CLK,
- SYSTEM_PLL1_800M_CLK,
- SYSTEM_PLL1_400M_CLK,
- SYSTEM_PLL1_266M_CLK,
- SYSTEM_PLL1_200M_CLK,
- SYSTEM_PLL1_160M_CLK,
- SYSTEM_PLL1_133M_CLK,
- SYSTEM_PLL1_100M_CLK,
- SYSTEM_PLL1_80M_CLK,
- SYSTEM_PLL1_40M_CLK,
- SYSTEM_PLL2_1000M_CLK,
- SYSTEM_PLL2_500M_CLK,
- SYSTEM_PLL2_333M_CLK,
- SYSTEM_PLL2_250M_CLK,
- SYSTEM_PLL2_200M_CLK,
- SYSTEM_PLL2_166M_CLK,
- SYSTEM_PLL2_125M_CLK,
- SYSTEM_PLL2_100M_CLK,
- SYSTEM_PLL2_50M_CLK,
- SYSTEM_PLL3_CLK,
- AUDIO_PLL1_CLK,
- AUDIO_PLL2_CLK,
- VIDEO_PLL_CLK,
- OSC_32K_CLK,
- EXT_CLK_1,
- EXT_CLK_2,
- EXT_CLK_3,
- EXT_CLK_4,
- OSC_27M_CLK,
-};
-
-/* CCGR index */
-enum clk_ccgr_index {
- CCGR_DVFS = 0,
- CCGR_ANAMIX = 1,
- CCGR_CPU = 2,
- CCGR_CSU = 4,
- CCGR_DRAM1 = 5,
- CCGR_DRAM2_OBSOLETE = 6,
- CCGR_ECSPI1 = 7,
- CCGR_ECSPI2 = 8,
- CCGR_ECSPI3 = 9,
- CCGR_ENET1 = 10,
- CCGR_GPIO1 = 11,
- CCGR_GPIO2 = 12,
- CCGR_GPIO3 = 13,
- CCGR_GPIO4 = 14,
- CCGR_GPIO5 = 15,
- CCGR_GPT1 = 16,
- CCGR_GPT2 = 17,
- CCGR_GPT3 = 18,
- CCGR_GPT4 = 19,
- CCGR_GPT5 = 20,
- CCGR_GPT6 = 21,
- CCGR_HS = 22,
- CCGR_I2C1 = 23,
- CCGR_I2C2 = 24,
- CCGR_I2C3 = 25,
- CCGR_I2C4 = 26,
- CCGR_IOMUX = 27,
- CCGR_IOMUX1 = 28,
- CCGR_IOMUX2 = 29,
- CCGR_IOMUX3 = 30,
- CCGR_IOMUX4 = 31,
- CCGR_M4 = 32,
- CCGR_MU = 33,
- CCGR_OCOTP = 34,
- CCGR_OCRAM = 35,
- CCGR_OCRAM_S = 36,
- CCGR_PCIE = 37,
- CCGR_PERFMON1 = 38,
- CCGR_PERFMON2 = 39,
- CCGR_PWM1 = 40,
- CCGR_PWM2 = 41,
- CCGR_PWM3 = 42,
- CCGR_PWM4 = 43,
- CCGR_QOS = 44,
- CCGR_DISMIX = 45,
- CCGR_MEGAMIX = 46,
- CCGR_QSPI = 47,
- CCGR_RAWNAND = 48,
- CCGR_RDC = 49,
- CCGR_ROM = 50,
- CCGR_SAI1 = 51,
- CCGR_SAI2 = 52,
- CCGR_SAI3 = 53,
- CCGR_SAI4 = 54,
- CCGR_SAI5 = 55,
- CCGR_SAI6 = 56,
- CCGR_SCTR = 57,
- CCGR_SDMA1 = 58,
- CCGR_SDMA2 = 59,
- CCGR_SEC_DEBUG = 60,
- CCGR_SEMA1 = 61,
- CCGR_SEMA2 = 62,
- CCGR_SIM_DISPLAY = 63,
- CCGR_SIM_ENET = 64,
- CCGR_SIM_M = 65,
- CCGR_SIM_MAIN = 66,
- CCGR_SIM_S = 67,
- CCGR_SIM_WAKEUP = 68,
- CCGR_SIM_USB = 69,
- CCGR_SIM_VPU = 70,
- CCGR_SNVS = 71,
- CCGR_TRACE = 72,
- CCGR_UART1 = 73,
- CCGR_UART2 = 74,
- CCGR_UART3 = 75,
- CCGR_UART4 = 76,
- CCGR_USB_CTRL1 = 77,
- CCGR_USB_CTRL2 = 78,
- CCGR_USB_PHY1 = 79,
- CCGR_USB_PHY2 = 80,
- CCGR_USDHC1 = 81,
- CCGR_USDHC2 = 82,
- CCGR_WDOG1 = 83,
- CCGR_WDOG2 = 84,
- CCGR_WDOG3 = 85,
- CCGR_VA53 = 86,
- CCGR_GPU = 87,
- CCGR_HEVC = 88,
- CCGR_AVC = 89,
- CCGR_VP9 = 90,
- CCGR_HEVC_INTER = 91,
- CCGR_GIC = 92,
- CCGR_DISPLAY = 93,
- CCGR_HDMI = 94,
- CCGR_HDMI_PHY = 95,
- CCGR_XTAL = 96,
- CCGR_PLL = 97,
- CCGR_TSENSOR = 98,
- CCGR_VPU_DEC = 99,
- CCGR_PCIE2 = 100,
- CCGR_MIPI_CSI1 = 101,
- CCGR_MIPI_CSI2 = 102,
- CCGR_MAX,
-};
-
-/* src index */
-enum clk_src_index {
- CLK_SRC_CKIL_SYNC_REQ = 0,
- CLK_SRC_ARM_PLL_EN = 1,
- CLK_SRC_GPU_PLL_EN = 2,
- CLK_SRC_VPU_PLL_EN = 3,
- CLK_SRC_DRAM_PLL_EN = 4,
- CLK_SRC_SYSTEM_PLL1_EN = 5,
- CLK_SRC_SYSTEM_PLL2_EN = 6,
- CLK_SRC_SYSTEM_PLL3_EN = 7,
- CLK_SRC_AUDIO_PLL1_EN = 8,
- CLK_SRC_AUDIO_PLL2_EN = 9,
- CLK_SRC_VIDEO_PLL1_EN = 10,
- CLK_SRC_VIDEO_PLL2_EN = 11,
- CLK_SRC_ARM_PLL = 12,
- CLK_SRC_GPU_PLL = 13,
- CLK_SRC_VPU_PLL = 14,
- CLK_SRC_DRAM_PLL = 15,
- CLK_SRC_SYSTEM_PLL1_800M = 16,
- CLK_SRC_SYSTEM_PLL1_400M = 17,
- CLK_SRC_SYSTEM_PLL1_266M = 18,
- CLK_SRC_SYSTEM_PLL1_200M = 19,
- CLK_SRC_SYSTEM_PLL1_160M = 20,
- CLK_SRC_SYSTEM_PLL1_133M = 21,
- CLK_SRC_SYSTEM_PLL1_100M = 22,
- CLK_SRC_SYSTEM_PLL1_80M = 23,
- CLK_SRC_SYSTEM_PLL1_40M = 24,
- CLK_SRC_SYSTEM_PLL2_1000M = 25,
- CLK_SRC_SYSTEM_PLL2_500M = 26,
- CLK_SRC_SYSTEM_PLL2_333M = 27,
- CLK_SRC_SYSTEM_PLL2_250M = 28,
- CLK_SRC_SYSTEM_PLL2_200M = 29,
- CLK_SRC_SYSTEM_PLL2_166M = 30,
- CLK_SRC_SYSTEM_PLL2_125M = 31,
- CLK_SRC_SYSTEM_PLL2_100M = 32,
- CLK_SRC_SYSTEM_PLL2_50M = 33,
- CLK_SRC_SYSTEM_PLL3 = 34,
- CLK_SRC_AUDIO_PLL1 = 35,
- CLK_SRC_AUDIO_PLL2 = 36,
- CLK_SRC_VIDEO_PLL1 = 37,
- CLK_SRC_VIDEO_PLL2 = 38,
- CLK_SRC_OSC_25M = 39,
- CLK_SRC_OSC_27M = 40,
-};
-
enum root_pre_div {
CLK_ROOT_PRE_DIV1 = 0,
CLK_ROOT_PRE_DIV2,
@@ -466,6 +176,29 @@ struct ccm_reg {
struct ccm_root ip_root[78];
};
+enum enet_freq {
+ ENET_25MHZ = 0,
+ ENET_50MHZ,
+ ENET_125MHZ,
+};
+
+#define DRAM_BYPASS_ROOT_CONFIG(_rate, _m, _p, _s, _k) \
+ { \
+ .clk = (_rate), \
+ .alt_root_sel = (_m), \
+ .alt_pre_div = (_p), \
+ .apb_root_sel = (_s), \
+ .apb_pre_div = (_k), \
+ }
+
+struct dram_bypass_clk_setting {
+ ulong clk;
+ int alt_root_sel;
+ enum root_pre_div alt_pre_div;
+ int apb_root_sel;
+ enum root_pre_div apb_pre_div;
+};
+
#define CCGR_CLK_ON_MASK 0x03
#define CLK_SRC_ON_MASK 0x03
@@ -503,117 +236,6 @@ struct ccm_reg {
#define CLK_ROOT_IPG_POST_DIV_MASK 0x3
#define CLK_ROOT_POST_DIV_SHIFT 0
#define CLK_ROOT_POST_DIV(n) ((n) & 0x3f)
-
-/* AUDIO PLL1/2 VIDEO PLL1 GPU PLL VPU PLL ARM PLL*/
-#define FRAC_PLL_LOCK_MASK BIT(31)
-#define FRAC_PLL_CLKE_MASK BIT(21)
-#define FRAC_PLL_PD_MASK BIT(19)
-#define FRAC_PLL_REFCLK_SEL_MASK BIT(16)
-#define FRAC_PLL_LOCK_SEL_MASK BIT(15)
-#define FRAC_PLL_BYPASS_MASK BIT(14)
-#define FRAC_PLL_COUNTCLK_SEL_MASK BIT(13)
-#define FRAC_PLL_NEWDIV_VAL_MASK BIT(12)
-#define FRAC_PLL_NEWDIV_ACK_MASK BIT(11)
-#define FRAC_PLL_REFCLK_DIV_VAL(n) (((n) << 5) & (0x3f << 5))
-#define FRAC_PLL_REFCLK_DIV_VAL_MASK (0x3f << 5)
-#define FRAC_PLL_REFCLK_DIV_VAL_SHIFT 5
-#define FRAC_PLL_OUTPUT_DIV_VAL_MASK 0x1f
-#define FRAC_PLL_OUTPUT_DIV_VAL(n) ((n) & 0x1f)
-
-#define FRAC_PLL_REFCLK_SEL_OSC_25M (0 << 16)
-#define FRAC_PLL_REFCLK_SEL_OSC_27M BIT(16)
-#define FRAC_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16)
-#define FRAC_PLL_REFCLK_SEL_CLK_PN (3 << 16)
-
-#define FRAC_PLL_FRAC_DIV_CTL_MASK (0x1ffffff << 7)
-#define FRAC_PLL_FRAC_DIV_CTL_SHIFT 7
-#define FRAC_PLL_INT_DIV_CTL_MASK 0x7f
-#define FRAC_PLL_INT_DIV_CTL_VAL(n) ((n) & 0x7f)
-
-/* SYS PLL1/2/3 VIDEO PLL2 DRAM PLL */
-#define SSCG_PLL_LOCK_MASK BIT(31)
-#define SSCG_PLL_CLKE_MASK BIT(25)
-#define SSCG_PLL_DIV2_CLKE_MASK BIT(23)
-#define SSCG_PLL_DIV3_CLKE_MASK BIT(21)
-#define SSCG_PLL_DIV4_CLKE_MASK BIT(19)
-#define SSCG_PLL_DIV5_CLKE_MASK BIT(17)
-#define SSCG_PLL_DIV6_CLKE_MASK BIT(15)
-#define SSCG_PLL_DIV8_CLKE_MASK BIT(13)
-#define SSCG_PLL_DIV10_CLKE_MASK BIT(11)
-#define SSCG_PLL_DIV20_CLKE_MASK BIT(9)
-#define SSCG_PLL_VIDEO_PLL2_CLKE_MASK BIT(9)
-#define SSCG_PLL_DRAM_PLL_CLKE_MASK BIT(9)
-#define SSCG_PLL_PLL3_CLKE_MASK BIT(9)
-#define SSCG_PLL_PD_MASK BIT(7)
-#define SSCG_PLL_BYPASS1_MASK BIT(5)
-#define SSCG_PLL_BYPASS2_MASK BIT(4)
-#define SSCG_PLL_LOCK_SEL_MASK BIT(3)
-#define SSCG_PLL_COUNTCLK_SEL_MASK BIT(2)
-#define SSCG_PLL_REFCLK_SEL_MASK 0x3
-#define SSCG_PLL_REFCLK_SEL_OSC_25M (0 << 16)
-#define SSCG_PLL_REFCLK_SEL_OSC_27M BIT(16)
-#define SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16)
-#define SSCG_PLL_REFCLK_SEL_CLK_PN (3 << 16)
-
-#define SSCG_PLL_SSDS_MASK BIT(8)
-#define SSCG_PLL_SSMD_MASK (0x7 << 5)
-#define SSCG_PLL_SSMF_MASK (0xf << 1)
-#define SSCG_PLL_SSE_MASK 0x1
-
-#define SSCG_PLL_REF_DIVR1_MASK (0x7 << 25)
-#define SSCG_PLL_REF_DIVR1_SHIFT 25
-#define SSCG_PLL_REF_DIVR1_VAL(n) (((n) << 25) & SSCG_PLL_REF_DIVR1_MASK)
-#define SSCG_PLL_REF_DIVR2_MASK (0x3f << 19)
-#define SSCG_PLL_REF_DIVR2_SHIFT 19
-#define SSCG_PLL_REF_DIVR2_VAL(n) (((n) << 19) & SSCG_PLL_REF_DIVR2_MASK)
-#define SSCG_PLL_FEEDBACK_DIV_F1_MASK (0x3f << 13)
-#define SSCG_PLL_FEEDBACK_DIV_F1_SHIFT 13
-#define SSCG_PLL_FEEDBACK_DIV_F1_VAL(n) (((n) << 13) & \
- SSCG_PLL_FEEDBACK_DIV_F1_MASK)
-#define SSCG_PLL_FEEDBACK_DIV_F2_MASK (0x3f << 7)
-#define SSCG_PLL_FEEDBACK_DIV_F2_SHIFT 7
-#define SSCG_PLL_FEEDBACK_DIV_F2_VAL(n) (((n) << 7) & \
- SSCG_PLL_FEEDBACK_DIV_F2_MASK)
-#define SSCG_PLL_OUTPUT_DIV_VAL_MASK (0x3f << 1)
-#define SSCG_PLL_OUTPUT_DIV_VAL_SHIFT 1
-#define SSCG_PLL_OUTPUT_DIV_VAL(n) (((n) << 1) & \
- SSCG_PLL_OUTPUT_DIV_VAL_MASK)
-#define SSCG_PLL_FILTER_RANGE_MASK 0x1
-
-#define HW_DIGPROG_MAJOR_UPPER_MASK (0xff << 16)
-#define HW_DIGPROG_MAJOR_LOWER_MASK (0xff << 8)
-#define HW_DIGPROG_MINOR_MASK 0xff
-
-#define HW_OSC_27M_CLKE_MASK BIT(4)
-#define HW_OSC_25M_CLKE_MASK BIT(2)
-#define HW_OSC_32K_SEL_MASK 0x1
-#define HW_OSC_32K_SEL_RTC 0x1
-#define HW_OSC_32K_SEL_25M_DIV800 0x0
-
-#define HW_FRAC_ARM_PLL_DIV_MASK (0x7 << 20)
-#define HW_FRAC_ARM_PLL_DIV_SHIFT 20
-#define HW_FRAC_VPU_PLL_DIV_MASK (0x7 << 16)
-#define HW_FRAC_VPU_PLL_DIV_SHIFT 16
-#define HW_FRAC_GPU_PLL_DIV_MASK (0x7 << 12)
-#define HW_FRAC_GPU_PLL_DIV_SHIFT 12
-#define HW_FRAC_VIDEO_PLL1_DIV_MASK (0x7 << 10)
-#define HW_FRAC_VIDEO_PLL1_DIV_SHIFT 10
-#define HW_FRAC_AUDIO_PLL2_DIV_MASK (0x7 << 4)
-#define HW_FRAC_AUDIO_PLL2_DIV_SHIFT 4
-#define HW_FRAC_AUDIO_PLL1_DIV_MASK 0x7
-#define HW_FRAC_AUDIO_PLL1_DIV_SHIFT 0
-
-#define HW_SSCG_VIDEO_PLL2_DIV_MASK (0x7 << 16)
-#define HW_SSCG_VIDEO_PLL2_DIV_SHIFT 16
-#define HW_SSCG_DRAM_PLL_DIV_MASK (0x7 << 14)
-#define HW_SSCG_DRAM_PLL_DIV_SHIFT 14
-#define HW_SSCG_SYSTEM_PLL3_DIV_MASK (0x7 << 8)
-#define HW_SSCG_SYSTEM_PLL3_DIV_SHIFT 8
-#define HW_SSCG_SYSTEM_PLL2_DIV_MASK (0x7 << 4)
-#define HW_SSCG_SYSTEM_PLL2_DIV_SHIFT 4
-#define HW_SSCG_SYSTEM_PLL1_DIV_MASK 0x7
-#define HW_SSCG_SYSTEM_PLL1_DIV_SHIFT 0
-
#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x01000000
#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000
#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x03000000
@@ -622,34 +244,6 @@ struct ccm_reg {
#define ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x01000000
-enum enet_freq {
- ENET_25MHZ = 0,
- ENET_50MHZ,
- ENET_125MHZ,
-};
-
-enum frac_pll_out_val {
- FRAC_PLL_OUT_1000M,
- FRAC_PLL_OUT_1600M,
-};
-
-#define DRAM_BYPASS_ROOT_CONFIG(_rate, _m, _p, _s, _k) \
- { \
- .clk = (_rate), \
- .alt_root_sel = (_m), \
- .alt_pre_div = (_p), \
- .apb_root_sel = (_s), \
- .apb_pre_div = (_k), \
- }
-
-struct dram_bypass_clk_setting {
- ulong clk;
- int alt_root_sel;
- enum root_pre_div alt_pre_div;
- int apb_root_sel;
- enum root_pre_div apb_pre_div;
-};
-
void dram_pll_init(ulong pll_val);
void dram_enable_bypass(ulong clk_val);
void dram_disable_bypass(void);
@@ -659,7 +253,7 @@ int clock_init(void);
void init_clk_usdhc(u32 index);
void init_uart_clk(u32 index);
void init_wdog_clk(void);
-unsigned int mxc_get_clock(enum clk_root_index clk);
+unsigned int mxc_get_clock(enum mxc_clock clk);
int clock_enable(enum clk_ccgr_index index, bool enable);
int clock_root_enabled(enum clk_root_index clock_id);
int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div,
@@ -675,4 +269,3 @@ int set_clk_qspi(void);
void enable_ocotp_clk(unsigned char enable);
int enable_i2c_clk(unsigned char enable, unsigned int i2c_num);
int set_clk_enet(enum enet_freq type);
-#endif
diff --git a/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h b/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h
new file mode 100644
index 0000000000..9fa9eb2687
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h
@@ -0,0 +1,424 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2017 NXP
+ *
+ * Peng Fan <peng.fan@nxp.com>
+ */
+
+#ifndef _ASM_ARCH_IMX8M_CLOCK_H
+#define _ASM_ARCH_IMX8M_CLOCK_H
+
+enum pll_clocks {
+ ANATOP_ARM_PLL,
+ ANATOP_GPU_PLL,
+ ANATOP_SYSTEM_PLL1,
+ ANATOP_SYSTEM_PLL2,
+ ANATOP_SYSTEM_PLL3,
+ ANATOP_AUDIO_PLL1,
+ ANATOP_AUDIO_PLL2,
+ ANATOP_VIDEO_PLL1,
+ ANATOP_VIDEO_PLL2,
+ ANATOP_DRAM_PLL,
+};
+
+enum clk_root_index {
+ ARM_A53_CLK_ROOT = 0,
+ ARM_M4_CLK_ROOT = 1,
+ VPU_A53_CLK_ROOT = 2,
+ GPU_CORE_CLK_ROOT = 3,
+ GPU_SHADER_CLK_ROOT = 4,
+ MAIN_AXI_CLK_ROOT = 16,
+ ENET_AXI_CLK_ROOT = 17,
+ NAND_USDHC_BUS_CLK_ROOT = 18,
+ VPU_BUS_CLK_ROOT = 19,
+ DISPLAY_AXI_CLK_ROOT = 20,
+ DISPLAY_APB_CLK_ROOT = 21,
+ DISPLAY_RTRM_CLK_ROOT = 22,
+ USB_BUS_CLK_ROOT = 23,
+ GPU_AXI_CLK_ROOT = 24,
+ GPU_AHB_CLK_ROOT = 25,
+ NOC_CLK_ROOT = 26,
+ NOC_APB_CLK_ROOT = 27,
+ AHB_CLK_ROOT = 32,
+ IPG_CLK_ROOT = 33,
+ AUDIO_AHB_CLK_ROOT = 34,
+ MIPI_DSI_ESC_RX_CLK_ROOT = 36,
+ DRAM_SEL_CFG = 48,
+ CORE_SEL_CFG = 49,
+ DRAM_ALT_CLK_ROOT = 64,
+ DRAM_APB_CLK_ROOT = 65,
+ VPU_G1_CLK_ROOT = 66,
+ VPU_G2_CLK_ROOT = 67,
+ DISPLAY_DTRC_CLK_ROOT = 68,
+ DISPLAY_DC8000_CLK_ROOT = 69,
+ PCIE1_CTRL_CLK_ROOT = 70,
+ PCIE1_PHY_CLK_ROOT = 71,
+ PCIE1_AUX_CLK_ROOT = 72,
+ DC_PIXEL_CLK_ROOT = 73,
+ LCDIF_PIXEL_CLK_ROOT = 74,
+ SAI1_CLK_ROOT = 75,
+ SAI2_CLK_ROOT = 76,
+ SAI3_CLK_ROOT = 77,
+ SAI4_CLK_ROOT = 78,
+ SAI5_CLK_ROOT = 79,
+ SAI6_CLK_ROOT = 80,
+ SPDIF1_CLK_ROOT = 81,
+ SPDIF2_CLK_ROOT = 82,
+ ENET_REF_CLK_ROOT = 83,
+ ENET_TIMER_CLK_ROOT = 84,
+ ENET_PHY_REF_CLK_ROOT = 85,
+ NAND_CLK_ROOT = 86,
+ QSPI_CLK_ROOT = 87,
+ USDHC1_CLK_ROOT = 88,
+ USDHC2_CLK_ROOT = 89,
+ I2C1_CLK_ROOT = 90,
+ I2C2_CLK_ROOT = 91,
+ I2C3_CLK_ROOT = 92,
+ I2C4_CLK_ROOT = 93,
+ UART1_CLK_ROOT = 94,
+ UART2_CLK_ROOT = 95,
+ UART3_CLK_ROOT = 96,
+ UART4_CLK_ROOT = 97,
+ USB_CORE_REF_CLK_ROOT = 98,
+ USB_PHY_REF_CLK_ROOT = 99,
+ GIC_CLK_ROOT = 100,
+ ECSPI1_CLK_ROOT = 101,
+ ECSPI2_CLK_ROOT = 102,
+ PWM1_CLK_ROOT = 103,
+ PWM2_CLK_ROOT = 104,
+ PWM3_CLK_ROOT = 105,
+ PWM4_CLK_ROOT = 106,
+ GPT1_CLK_ROOT = 107,
+ GPT2_CLK_ROOT = 108,
+ GPT3_CLK_ROOT = 109,
+ GPT4_CLK_ROOT = 110,
+ GPT5_CLK_ROOT = 111,
+ GPT6_CLK_ROOT = 112,
+ TRACE_CLK_ROOT = 113,
+ WDOG_CLK_ROOT = 114,
+ WRCLK_CLK_ROOT = 115,
+ IPP_DO_CLKO1 = 116,
+ IPP_DO_CLKO2 = 117,
+ MIPI_DSI_CORE_CLK_ROOT = 118,
+ MIPI_DSI_PHY_REF_CLK_ROOT = 119,
+ MIPI_DSI_DBI_CLK_ROOT = 120,
+ OLD_MIPI_DSI_ESC_CLK_ROOT = 121,
+ MIPI_CSI1_CORE_CLK_ROOT = 122,
+ MIPI_CSI1_PHY_REF_CLK_ROOT = 123,
+ MIPI_CSI1_ESC_CLK_ROOT = 124,
+ MIPI_CSI2_CORE_CLK_ROOT = 125,
+ MIPI_CSI2_PHY_REF_CLK_ROOT = 126,
+ MIPI_CSI2_ESC_CLK_ROOT = 127,
+ PCIE2_CTRL_CLK_ROOT = 128,
+ PCIE2_PHY_CLK_ROOT = 129,
+ PCIE2_AUX_CLK_ROOT = 130,
+ ECSPI3_CLK_ROOT = 131,
+ OLD_MIPI_DSI_ESC_RX_ROOT = 132,
+ DISPLAY_HDMI_CLK_ROOT = 133,
+ CLK_ROOT_MAX,
+};
+
+enum clk_root_src {
+ OSC_25M_CLK,
+ ARM_PLL_CLK,
+ DRAM_PLL1_CLK,
+ VIDEO_PLL2_CLK,
+ VPU_PLL_CLK,
+ GPU_PLL_CLK,
+ SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL1_400M_CLK,
+ SYSTEM_PLL1_266M_CLK,
+ SYSTEM_PLL1_200M_CLK,
+ SYSTEM_PLL1_160M_CLK,
+ SYSTEM_PLL1_133M_CLK,
+ SYSTEM_PLL1_100M_CLK,
+ SYSTEM_PLL1_80M_CLK,
+ SYSTEM_PLL1_40M_CLK,
+ SYSTEM_PLL2_1000M_CLK,
+ SYSTEM_PLL2_500M_CLK,
+ SYSTEM_PLL2_333M_CLK,
+ SYSTEM_PLL2_250M_CLK,
+ SYSTEM_PLL2_200M_CLK,
+ SYSTEM_PLL2_166M_CLK,
+ SYSTEM_PLL2_125M_CLK,
+ SYSTEM_PLL2_100M_CLK,
+ SYSTEM_PLL2_50M_CLK,
+ SYSTEM_PLL3_CLK,
+ AUDIO_PLL1_CLK,
+ AUDIO_PLL2_CLK,
+ VIDEO_PLL_CLK,
+ OSC_32K_CLK,
+ EXT_CLK_1,
+ EXT_CLK_2,
+ EXT_CLK_3,
+ EXT_CLK_4,
+ OSC_27M_CLK,
+};
+
+/* CCGR index */
+enum clk_ccgr_index {
+ CCGR_DVFS = 0,
+ CCGR_ANAMIX = 1,
+ CCGR_CPU = 2,
+ CCGR_CSU = 4,
+ CCGR_DRAM1 = 5,
+ CCGR_DRAM2_OBSOLETE = 6,
+ CCGR_ECSPI1 = 7,
+ CCGR_ECSPI2 = 8,
+ CCGR_ECSPI3 = 9,
+ CCGR_ENET1 = 10,
+ CCGR_GPIO1 = 11,
+ CCGR_GPIO2 = 12,
+ CCGR_GPIO3 = 13,
+ CCGR_GPIO4 = 14,
+ CCGR_GPIO5 = 15,
+ CCGR_GPT1 = 16,
+ CCGR_GPT2 = 17,
+ CCGR_GPT3 = 18,
+ CCGR_GPT4 = 19,
+ CCGR_GPT5 = 20,
+ CCGR_GPT6 = 21,
+ CCGR_HS = 22,
+ CCGR_I2C1 = 23,
+ CCGR_I2C2 = 24,
+ CCGR_I2C3 = 25,
+ CCGR_I2C4 = 26,
+ CCGR_IOMUX = 27,
+ CCGR_IOMUX1 = 28,
+ CCGR_IOMUX2 = 29,
+ CCGR_IOMUX3 = 30,
+ CCGR_IOMUX4 = 31,
+ CCGR_M4 = 32,
+ CCGR_MU = 33,
+ CCGR_OCOTP = 34,
+ CCGR_OCRAM = 35,
+ CCGR_OCRAM_S = 36,
+ CCGR_PCIE = 37,
+ CCGR_PERFMON1 = 38,
+ CCGR_PERFMON2 = 39,
+ CCGR_PWM1 = 40,
+ CCGR_PWM2 = 41,
+ CCGR_PWM3 = 42,
+ CCGR_PWM4 = 43,
+ CCGR_QOS = 44,
+ CCGR_DISMIX = 45,
+ CCGR_MEGAMIX = 46,
+ CCGR_QSPI = 47,
+ CCGR_RAWNAND = 48,
+ CCGR_RDC = 49,
+ CCGR_ROM = 50,
+ CCGR_SAI1 = 51,
+ CCGR_SAI2 = 52,
+ CCGR_SAI3 = 53,
+ CCGR_SAI4 = 54,
+ CCGR_SAI5 = 55,
+ CCGR_SAI6 = 56,
+ CCGR_SCTR = 57,
+ CCGR_SDMA1 = 58,
+ CCGR_SDMA2 = 59,
+ CCGR_SEC_DEBUG = 60,
+ CCGR_SEMA1 = 61,
+ CCGR_SEMA2 = 62,
+ CCGR_SIM_DISPLAY = 63,
+ CCGR_SIM_ENET = 64,
+ CCGR_SIM_M = 65,
+ CCGR_SIM_MAIN = 66,
+ CCGR_SIM_S = 67,
+ CCGR_SIM_WAKEUP = 68,
+ CCGR_SIM_USB = 69,
+ CCGR_SIM_VPU = 70,
+ CCGR_SNVS = 71,
+ CCGR_TRACE = 72,
+ CCGR_UART1 = 73,
+ CCGR_UART2 = 74,
+ CCGR_UART3 = 75,
+ CCGR_UART4 = 76,
+ CCGR_USB_CTRL1 = 77,
+ CCGR_USB_CTRL2 = 78,
+ CCGR_USB_PHY1 = 79,
+ CCGR_USB_PHY2 = 80,
+ CCGR_USDHC1 = 81,
+ CCGR_USDHC2 = 82,
+ CCGR_WDOG1 = 83,
+ CCGR_WDOG2 = 84,
+ CCGR_WDOG3 = 85,
+ CCGR_VA53 = 86,
+ CCGR_GPU = 87,
+ CCGR_HEVC = 88,
+ CCGR_AVC = 89,
+ CCGR_VP9 = 90,
+ CCGR_HEVC_INTER = 91,
+ CCGR_GIC = 92,
+ CCGR_DISPLAY = 93,
+ CCGR_HDMI = 94,
+ CCGR_HDMI_PHY = 95,
+ CCGR_XTAL = 96,
+ CCGR_PLL = 97,
+ CCGR_TSENSOR = 98,
+ CCGR_VPU_DEC = 99,
+ CCGR_PCIE2 = 100,
+ CCGR_MIPI_CSI1 = 101,
+ CCGR_MIPI_CSI2 = 102,
+ CCGR_MAX,
+};
+
+/* src index */
+enum clk_src_index {
+ CLK_SRC_CKIL_SYNC_REQ = 0,
+ CLK_SRC_ARM_PLL_EN = 1,
+ CLK_SRC_GPU_PLL_EN = 2,
+ CLK_SRC_VPU_PLL_EN = 3,
+ CLK_SRC_DRAM_PLL_EN = 4,
+ CLK_SRC_SYSTEM_PLL1_EN = 5,
+ CLK_SRC_SYSTEM_PLL2_EN = 6,
+ CLK_SRC_SYSTEM_PLL3_EN = 7,
+ CLK_SRC_AUDIO_PLL1_EN = 8,
+ CLK_SRC_AUDIO_PLL2_EN = 9,
+ CLK_SRC_VIDEO_PLL1_EN = 10,
+ CLK_SRC_VIDEO_PLL2_EN = 11,
+ CLK_SRC_ARM_PLL = 12,
+ CLK_SRC_GPU_PLL = 13,
+ CLK_SRC_VPU_PLL = 14,
+ CLK_SRC_DRAM_PLL = 15,
+ CLK_SRC_SYSTEM_PLL1_800M = 16,
+ CLK_SRC_SYSTEM_PLL1_400M = 17,
+ CLK_SRC_SYSTEM_PLL1_266M = 18,
+ CLK_SRC_SYSTEM_PLL1_200M = 19,
+ CLK_SRC_SYSTEM_PLL1_160M = 20,
+ CLK_SRC_SYSTEM_PLL1_133M = 21,
+ CLK_SRC_SYSTEM_PLL1_100M = 22,
+ CLK_SRC_SYSTEM_PLL1_80M = 23,
+ CLK_SRC_SYSTEM_PLL1_40M = 24,
+ CLK_SRC_SYSTEM_PLL2_1000M = 25,
+ CLK_SRC_SYSTEM_PLL2_500M = 26,
+ CLK_SRC_SYSTEM_PLL2_333M = 27,
+ CLK_SRC_SYSTEM_PLL2_250M = 28,
+ CLK_SRC_SYSTEM_PLL2_200M = 29,
+ CLK_SRC_SYSTEM_PLL2_166M = 30,
+ CLK_SRC_SYSTEM_PLL2_125M = 31,
+ CLK_SRC_SYSTEM_PLL2_100M = 32,
+ CLK_SRC_SYSTEM_PLL2_50M = 33,
+ CLK_SRC_SYSTEM_PLL3 = 34,
+ CLK_SRC_AUDIO_PLL1 = 35,
+ CLK_SRC_AUDIO_PLL2 = 36,
+ CLK_SRC_VIDEO_PLL1 = 37,
+ CLK_SRC_VIDEO_PLL2 = 38,
+ CLK_SRC_OSC_25M = 39,
+ CLK_SRC_OSC_27M = 40,
+};
+
+/* AUDIO PLL1/2 VIDEO PLL1 GPU PLL VPU PLL ARM PLL*/
+#define FRAC_PLL_LOCK_MASK BIT(31)
+#define FRAC_PLL_CLKE_MASK BIT(21)
+#define FRAC_PLL_PD_MASK BIT(19)
+#define FRAC_PLL_REFCLK_SEL_MASK BIT(16)
+#define FRAC_PLL_LOCK_SEL_MASK BIT(15)
+#define FRAC_PLL_BYPASS_MASK BIT(14)
+#define FRAC_PLL_COUNTCLK_SEL_MASK BIT(13)
+#define FRAC_PLL_NEWDIV_VAL_MASK BIT(12)
+#define FRAC_PLL_NEWDIV_ACK_MASK BIT(11)
+#define FRAC_PLL_REFCLK_DIV_VAL(n) (((n) << 5) & (0x3f << 5))
+#define FRAC_PLL_REFCLK_DIV_VAL_MASK (0x3f << 5)
+#define FRAC_PLL_REFCLK_DIV_VAL_SHIFT 5
+#define FRAC_PLL_OUTPUT_DIV_VAL_MASK 0x1f
+#define FRAC_PLL_OUTPUT_DIV_VAL(n) ((n) & 0x1f)
+
+#define FRAC_PLL_REFCLK_SEL_OSC_25M (0 << 16)
+#define FRAC_PLL_REFCLK_SEL_OSC_27M BIT(16)
+#define FRAC_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16)
+#define FRAC_PLL_REFCLK_SEL_CLK_PN (3 << 16)
+
+#define FRAC_PLL_FRAC_DIV_CTL_MASK (0x1ffffff << 7)
+#define FRAC_PLL_FRAC_DIV_CTL_SHIFT 7
+#define FRAC_PLL_INT_DIV_CTL_MASK 0x7f
+#define FRAC_PLL_INT_DIV_CTL_VAL(n) ((n) & 0x7f)
+
+/* SYS PLL1/2/3 VIDEO PLL2 DRAM PLL */
+#define SSCG_PLL_LOCK_MASK BIT(31)
+#define SSCG_PLL_CLKE_MASK BIT(25)
+#define SSCG_PLL_DIV2_CLKE_MASK BIT(23)
+#define SSCG_PLL_DIV3_CLKE_MASK BIT(21)
+#define SSCG_PLL_DIV4_CLKE_MASK BIT(19)
+#define SSCG_PLL_DIV5_CLKE_MASK BIT(17)
+#define SSCG_PLL_DIV6_CLKE_MASK BIT(15)
+#define SSCG_PLL_DIV8_CLKE_MASK BIT(13)
+#define SSCG_PLL_DIV10_CLKE_MASK BIT(11)
+#define SSCG_PLL_DIV20_CLKE_MASK BIT(9)
+#define SSCG_PLL_VIDEO_PLL2_CLKE_MASK BIT(9)
+#define SSCG_PLL_DRAM_PLL_CLKE_MASK BIT(9)
+#define SSCG_PLL_PLL3_CLKE_MASK BIT(9)
+#define SSCG_PLL_PD_MASK BIT(7)
+#define SSCG_PLL_BYPASS1_MASK BIT(5)
+#define SSCG_PLL_BYPASS2_MASK BIT(4)
+#define SSCG_PLL_LOCK_SEL_MASK BIT(3)
+#define SSCG_PLL_COUNTCLK_SEL_MASK BIT(2)
+#define SSCG_PLL_REFCLK_SEL_MASK 0x3
+#define SSCG_PLL_REFCLK_SEL_OSC_25M (0 << 16)
+#define SSCG_PLL_REFCLK_SEL_OSC_27M BIT(16)
+#define SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16)
+#define SSCG_PLL_REFCLK_SEL_CLK_PN (3 << 16)
+
+#define SSCG_PLL_SSDS_MASK BIT(8)
+#define SSCG_PLL_SSMD_MASK (0x7 << 5)
+#define SSCG_PLL_SSMF_MASK (0xf << 1)
+#define SSCG_PLL_SSE_MASK 0x1
+
+#define SSCG_PLL_REF_DIVR1_MASK (0x7 << 25)
+#define SSCG_PLL_REF_DIVR1_SHIFT 25
+#define SSCG_PLL_REF_DIVR1_VAL(n) (((n) << 25) & SSCG_PLL_REF_DIVR1_MASK)
+#define SSCG_PLL_REF_DIVR2_MASK (0x3f << 19)
+#define SSCG_PLL_REF_DIVR2_SHIFT 19
+#define SSCG_PLL_REF_DIVR2_VAL(n) (((n) << 19) & SSCG_PLL_REF_DIVR2_MASK)
+#define SSCG_PLL_FEEDBACK_DIV_F1_MASK (0x3f << 13)
+#define SSCG_PLL_FEEDBACK_DIV_F1_SHIFT 13
+#define SSCG_PLL_FEEDBACK_DIV_F1_VAL(n) (((n) << 13) & \
+ SSCG_PLL_FEEDBACK_DIV_F1_MASK)
+#define SSCG_PLL_FEEDBACK_DIV_F2_MASK (0x3f << 7)
+#define SSCG_PLL_FEEDBACK_DIV_F2_SHIFT 7
+#define SSCG_PLL_FEEDBACK_DIV_F2_VAL(n) (((n) << 7) & \
+ SSCG_PLL_FEEDBACK_DIV_F2_MASK)
+#define SSCG_PLL_OUTPUT_DIV_VAL_MASK (0x3f << 1)
+#define SSCG_PLL_OUTPUT_DIV_VAL_SHIFT 1
+#define SSCG_PLL_OUTPUT_DIV_VAL(n) (((n) << 1) & \
+ SSCG_PLL_OUTPUT_DIV_VAL_MASK)
+#define SSCG_PLL_FILTER_RANGE_MASK 0x1
+
+#define HW_DIGPROG_MAJOR_UPPER_MASK (0xff << 16)
+#define HW_DIGPROG_MAJOR_LOWER_MASK (0xff << 8)
+#define HW_DIGPROG_MINOR_MASK 0xff
+
+#define HW_OSC_27M_CLKE_MASK BIT(4)
+#define HW_OSC_25M_CLKE_MASK BIT(2)
+#define HW_OSC_32K_SEL_MASK 0x1
+#define HW_OSC_32K_SEL_RTC 0x1
+#define HW_OSC_32K_SEL_25M_DIV800 0x0
+
+#define HW_FRAC_ARM_PLL_DIV_MASK (0x7 << 20)
+#define HW_FRAC_ARM_PLL_DIV_SHIFT 20
+#define HW_FRAC_VPU_PLL_DIV_MASK (0x7 << 16)
+#define HW_FRAC_VPU_PLL_DIV_SHIFT 16
+#define HW_FRAC_GPU_PLL_DIV_MASK (0x7 << 12)
+#define HW_FRAC_GPU_PLL_DIV_SHIFT 12
+#define HW_FRAC_VIDEO_PLL1_DIV_MASK (0x7 << 10)
+#define HW_FRAC_VIDEO_PLL1_DIV_SHIFT 10
+#define HW_FRAC_AUDIO_PLL2_DIV_MASK (0x7 << 4)
+#define HW_FRAC_AUDIO_PLL2_DIV_SHIFT 4
+#define HW_FRAC_AUDIO_PLL1_DIV_MASK 0x7
+#define HW_FRAC_AUDIO_PLL1_DIV_SHIFT 0
+
+#define HW_SSCG_VIDEO_PLL2_DIV_MASK (0x7 << 16)
+#define HW_SSCG_VIDEO_PLL2_DIV_SHIFT 16
+#define HW_SSCG_DRAM_PLL_DIV_MASK (0x7 << 14)
+#define HW_SSCG_DRAM_PLL_DIV_SHIFT 14
+#define HW_SSCG_SYSTEM_PLL3_DIV_MASK (0x7 << 8)
+#define HW_SSCG_SYSTEM_PLL3_DIV_SHIFT 8
+#define HW_SSCG_SYSTEM_PLL2_DIV_MASK (0x7 << 4)
+#define HW_SSCG_SYSTEM_PLL2_DIV_SHIFT 4
+#define HW_SSCG_SYSTEM_PLL1_DIV_MASK 0x7
+#define HW_SSCG_SYSTEM_PLL1_DIV_SHIFT 0
+
+enum frac_pll_out_val {
+ FRAC_PLL_OUT_1000M,
+ FRAC_PLL_OUT_1600M,
+};
+#endif
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mq.c b/arch/arm/mach-imx/imx8m/clock_imx8mq.c
index 289b9417aa..feecdb50f6 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mq.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mq.c
@@ -322,13 +322,10 @@ int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
return 0;
}
-unsigned int mxc_get_clock(enum clk_root_index clk)
+unsigned int mxc_get_clock(enum mxc_clock clk)
{
u32 val;
- if (clk >= CLK_ROOT_MAX)
- return 0;
-
if (clk == MXC_ARM_CLK)
return get_root_clk(ARM_A53_CLK_ROOT);
--
2.14.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* [U-Boot] [PATCH 10/20] imx8m: add clk support for i.MX8MM
2019-01-28 9:39 [U-Boot] [PATCH 00/20] imx: add i.MX8MM support Peng Fan
` (8 preceding siblings ...)
2019-01-28 9:39 ` [U-Boot] [PATCH 09/20] imx8m: restructure clock.h Peng Fan
@ 2019-01-28 9:39 ` Peng Fan
2019-01-29 22:54 ` Lukasz Majewski
2019-01-28 9:39 ` [U-Boot] [PATCH 11/20] imx8m: add pin header " Peng Fan
` (9 subsequent siblings)
19 siblings, 1 reply; 39+ messages in thread
From: Peng Fan @ 2019-01-28 9:39 UTC (permalink / raw)
To: u-boot
Introduce clk implementation for i.MX8MM, including pll configuration,
pll decoding, ccm configuration.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/include/asm/arch-imx8m/clock.h | 2 +
arch/arm/include/asm/arch-imx8m/clock_imx8mm.h | 387 +++++++++++
arch/arm/mach-imx/imx8m/Makefile | 1 +
arch/arm/mach-imx/imx8m/clock_imx8mm.c | 866 +++++++++++++++++++++++++
arch/arm/mach-imx/imx8m/clock_slice.c | 461 +++++++++++++
5 files changed, 1717 insertions(+)
create mode 100644 arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
create mode 100644 arch/arm/mach-imx/imx8m/clock_imx8mm.c
diff --git a/arch/arm/include/asm/arch-imx8m/clock.h b/arch/arm/include/asm/arch-imx8m/clock.h
index 7225c760fe..ead4b8d3dc 100644
--- a/arch/arm/include/asm/arch-imx8m/clock.h
+++ b/arch/arm/include/asm/arch-imx8m/clock.h
@@ -7,6 +7,8 @@
#ifdef CONFIG_IMX8MQ
#include <asm/arch/clock_imx8mq.h>
+#elif defined(CONFIG_IMX8MM)
+#include <asm/arch/clock_imx8mm.h>
#else
#error "Error no clock.h"
#endif
diff --git a/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h b/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
new file mode 100644
index 0000000000..305514a4ec
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
@@ -0,0 +1,387 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018-2019 NXP
+ *
+ * Peng Fan <peng.fan@nxp.com>
+ */
+
+#ifndef _ASM_ARCH_IMX8MM_CLOCK_H
+#define _ASM_ARCH_IMX8MM_CLOCK_H
+
+#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
+ { \
+ .rate = (_rate), \
+ .mdiv = (_m), \
+ .pdiv = (_p), \
+ .sdiv = (_s), \
+ .kdiv = (_k), \
+ }
+
+#define LOCK_STATUS BIT(31)
+#define LOCK_SEL_MASK BIT(29)
+#define CLKE_MASK BIT(11)
+#define RST_MASK BIT(9)
+#define BYPASS_MASK BIT(4)
+#define MDIV_SHIFT 12
+#define MDIV_MASK GENMASK(21, 12)
+#define PDIV_SHIFT 4
+#define PDIV_MASK GENMASK(9, 4)
+#define SDIV_SHIFT 0
+#define SDIV_MASK GENMASK(2, 0)
+#define KDIV_SHIFT 0
+#define KDIV_MASK GENMASK(15, 0)
+
+struct imx_int_pll_rate_table {
+ u32 rate;
+ int mdiv;
+ int pdiv;
+ int sdiv;
+ int kdiv;
+};
+
+enum pll_clocks {
+ ANATOP_ARM_PLL,
+ ANATOP_VPU_PLL,
+ ANATOP_GPU_PLL,
+ ANATOP_SYSTEM_PLL1,
+ ANATOP_SYSTEM_PLL2,
+ ANATOP_SYSTEM_PLL3,
+ ANATOP_AUDIO_PLL1,
+ ANATOP_AUDIO_PLL2,
+ ANATOP_VIDEO_PLL,
+ ANATOP_DRAM_PLL,
+};
+
+enum clk_root_index {
+ ARM_A53_CLK_ROOT = 0,
+ ARM_M4_CLK_ROOT = 1,
+ VPU_A53_CLK_ROOT = 2,
+ GPU3D_CLK_ROOT = 3,
+ GPU2D_CLK_ROOT = 4,
+ MAIN_AXI_CLK_ROOT = 16,
+ ENET_AXI_CLK_ROOT = 17,
+ NAND_USDHC_BUS_CLK_ROOT = 18,
+ VPU_BUS_CLK_ROOT = 19,
+ DISPLAY_AXI_CLK_ROOT = 20,
+ DISPLAY_APB_CLK_ROOT = 21,
+ DISPLAY_RTRM_CLK_ROOT = 22,
+ USB_BUS_CLK_ROOT = 23,
+ GPU_AXI_CLK_ROOT = 24,
+ GPU_AHB_CLK_ROOT = 25,
+ NOC_CLK_ROOT = 26,
+ NOC_APB_CLK_ROOT = 27,
+ AHB_CLK_ROOT = 32,
+ IPG_CLK_ROOT = 33,
+ AUDIO_AHB_CLK_ROOT = 34,
+ MIPI_DSI_ESC_RX_CLK_ROOT = 36,
+ DRAM_SEL_CFG = 48,
+ CORE_SEL_CFG = 49,
+ DRAM_ALT_CLK_ROOT = 64,
+ DRAM_APB_CLK_ROOT = 65,
+ VPU_G1_CLK_ROOT = 66,
+ VPU_G2_CLK_ROOT = 67,
+ DISPLAY_DTRC_CLK_ROOT = 68,
+ DISPLAY_DC8000_CLK_ROOT = 69,
+ PCIE_CTRL_CLK_ROOT = 70,
+ PCIE_PHY_CLK_ROOT = 71,
+ PCIE_AUX_CLK_ROOT = 72,
+ DC_PIXEL_CLK_ROOT = 73,
+ LCDIF_PIXEL_CLK_ROOT = 74,
+ SAI1_CLK_ROOT = 75,
+ SAI2_CLK_ROOT = 76,
+ SAI3_CLK_ROOT = 77,
+ SAI4_CLK_ROOT = 78,
+ SAI5_CLK_ROOT = 79,
+ SAI6_CLK_ROOT = 80,
+ SPDIF1_CLK_ROOT = 81,
+ SPDIF2_CLK_ROOT = 82,
+ ENET_REF_CLK_ROOT = 83,
+ ENET_TIMER_CLK_ROOT = 84,
+ ENET_PHY_REF_CLK_ROOT = 85,
+ NAND_CLK_ROOT = 86,
+ QSPI_CLK_ROOT = 87,
+ USDHC1_CLK_ROOT = 88,
+ USDHC2_CLK_ROOT = 89,
+ I2C1_CLK_ROOT = 90,
+ I2C2_CLK_ROOT = 91,
+ I2C3_CLK_ROOT = 92,
+ I2C4_CLK_ROOT = 93,
+ UART1_CLK_ROOT = 94,
+ UART2_CLK_ROOT = 95,
+ UART3_CLK_ROOT = 96,
+ UART4_CLK_ROOT = 97,
+ USB_CORE_REF_CLK_ROOT = 98,
+ USB_PHY_REF_CLK_ROOT = 99,
+ GIC_CLK_ROOT = 100,
+ ECSPI1_CLK_ROOT = 101,
+ ECSPI2_CLK_ROOT = 102,
+ PWM1_CLK_ROOT = 103,
+ PWM2_CLK_ROOT = 104,
+ PWM3_CLK_ROOT = 105,
+ PWM4_CLK_ROOT = 106,
+ GPT1_CLK_ROOT = 107,
+ GPT2_CLK_ROOT = 108,
+ GPT3_CLK_ROOT = 109,
+ GPT4_CLK_ROOT = 110,
+ GPT5_CLK_ROOT = 111,
+ GPT6_CLK_ROOT = 112,
+ TRACE_CLK_ROOT = 113,
+ WDOG_CLK_ROOT = 114,
+ WRCLK_CLK_ROOT = 115,
+ IPP_DO_CLKO1 = 116,
+ IPP_DO_CLKO2 = 117,
+ MIPI_DSI_CORE_CLK_ROOT = 118,
+ MIPI_DSI_PHY_REF_CLK_ROOT = 119,
+ MIPI_DSI_DBI_CLK_ROOT = 120,
+ USDHC3_CLK_ROOT = 121,
+ MIPI_CSI1_CORE_CLK_ROOT = 122,
+ MIPI_CSI1_PHY_REF_CLK_ROOT = 123,
+ MIPI_CSI1_ESC_CLK_ROOT = 124,
+ MIPI_CSI2_CORE_CLK_ROOT = 125,
+ MIPI_CSI2_PHY_REF_CLK_ROOT = 126,
+ MIPI_CSI2_ESC_CLK_ROOT = 127,
+ PCIE2_CTRL_CLK_ROOT = 128,
+ PCIE2_PHY_CLK_ROOT = 129,
+ PCIE2_AUX_CLK_ROOT = 130,
+ ECSPI3_CLK_ROOT = 131,
+ PDM_CLK_ROOT = 132,
+ VPU_H1_CLK_ROOT = 133,
+ CLK_ROOT_MAX,
+};
+
+enum clk_root_src {
+ OSC_24M_CLK,
+ ARM_PLL_CLK,
+ DRAM_PLL1_CLK,
+ VIDEO_PLL2_CLK,
+ VPU_PLL_CLK,
+ GPU_PLL_CLK,
+ SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL1_400M_CLK,
+ SYSTEM_PLL1_266M_CLK,
+ SYSTEM_PLL1_200M_CLK,
+ SYSTEM_PLL1_160M_CLK,
+ SYSTEM_PLL1_133M_CLK,
+ SYSTEM_PLL1_100M_CLK,
+ SYSTEM_PLL1_80M_CLK,
+ SYSTEM_PLL1_40M_CLK,
+ SYSTEM_PLL2_1000M_CLK,
+ SYSTEM_PLL2_500M_CLK,
+ SYSTEM_PLL2_333M_CLK,
+ SYSTEM_PLL2_250M_CLK,
+ SYSTEM_PLL2_200M_CLK,
+ SYSTEM_PLL2_166M_CLK,
+ SYSTEM_PLL2_125M_CLK,
+ SYSTEM_PLL2_100M_CLK,
+ SYSTEM_PLL2_50M_CLK,
+ SYSTEM_PLL3_CLK,
+ AUDIO_PLL1_CLK,
+ AUDIO_PLL2_CLK,
+ VIDEO_PLL_CLK,
+ OSC_32K_CLK,
+ EXT_CLK_1,
+ EXT_CLK_2,
+ EXT_CLK_3,
+ EXT_CLK_4,
+ OSC_HDMI_CLK
+};
+
+enum clk_ccgr_index {
+ CCGR_DVFS = 0,
+ CCGR_ANAMIX = 1,
+ CCGR_CPU = 2,
+ CCGR_CSU = 3,
+ CCGR_DEBUG = 4,
+ CCGR_DDR1 = 5,
+ CCGR_ECSPI1 = 7,
+ CCGR_ECSPI2 = 8,
+ CCGR_ECSPI3 = 9,
+ CCGR_ENET1 = 10,
+ CCGR_GPIO1 = 11,
+ CCGR_GPIO2 = 12,
+ CCGR_GPIO3 = 13,
+ CCGR_GPIO4 = 14,
+ CCGR_GPIO5 = 15,
+ CCGR_GPT1 = 16,
+ CCGR_GPT2 = 17,
+ CCGR_GPT3 = 18,
+ CCGR_GPT4 = 19,
+ CCGR_GPT5 = 20,
+ CCGR_GPT6 = 21,
+ CCGR_HS = 22,
+ CCGR_I2C1 = 23,
+ CCGR_I2C2 = 24,
+ CCGR_I2C3 = 25,
+ CCGR_I2C4 = 26,
+ CCGR_IOMUX = 27,
+ CCGR_IOMUX1 = 28,
+ CCGR_IOMUX2 = 29,
+ CCGR_IOMUX3 = 30,
+ CCGR_IOMUX4 = 31,
+ CCGR_SNVSMIX_IPG_CLK = 32,
+ CCGR_MU = 33,
+ CCGR_OCOTP = 34,
+ CCGR_OCRAM = 35,
+ CCGR_OCRAM_S = 36,
+ CCGR_PCIE = 37,
+ CCGR_PERFMON1 = 38,
+ CCGR_PERFMON2 = 39,
+ CCGR_PWM1 = 40,
+ CCGR_PWM2 = 41,
+ CCGR_PWM3 = 42,
+ CCGR_PWM4 = 43,
+ CCGR_QOS = 44,
+ CCGR_QOS_DISPMIX = 45,
+ CCGR_QOS_ETHENET = 46,
+ CCGR_QSPI = 47,
+ CCGR_RAWNAND = 48,
+ CCGR_RDC = 49,
+ CCGR_ROM = 50,
+ CCGR_SAI1 = 51,
+ CCGR_SAI2 = 52,
+ CCGR_SAI3 = 53,
+ CCGR_SAI4 = 54,
+ CCGR_SAI5 = 55,
+ CCGR_SAI6 = 56,
+ CCGR_SCTR = 57,
+ CCGR_SDMA1 = 58,
+ CCGR_SDMA2 = 59,
+ CCGR_SEC_DEBUG = 60,
+ CCGR_SEMA1 = 61,
+ CCGR_SEMA2 = 62,
+ CCGR_SIM_DISPLAY = 63,
+ CCGR_SIM_ENET = 64,
+ CCGR_SIM_M = 65,
+ CCGR_SIM_MAIN = 66,
+ CCGR_SIM_S = 67,
+ CCGR_SIM_WAKEUP = 68,
+ CCGR_SIM_HSIO = 69,
+ CCGR_SIM_VPU = 70,
+ CCGR_SNVS = 71,
+ CCGR_TRACE = 72,
+ CCGR_UART1 = 73,
+ CCGR_UART2 = 74,
+ CCGR_UART3 = 75,
+ CCGR_UART4 = 76,
+ CCGR_USB_MSCALE_PL301 = 77,
+ CCGR_GPU3D = 79,
+ CCGR_USDHC1 = 81,
+ CCGR_USDHC2 = 82,
+ CCGR_WDOG1 = 83,
+ CCGR_WDOG2 = 84,
+ CCGR_WDOG3 = 85,
+ CCGR_VPUG1 = 86,
+ CCGR_GPU_BUS = 87,
+ CCGR_VPUH1 = 89,
+ CCGR_VPUG2 = 90,
+ CCGR_PDM = 91,
+ CCGR_GIC = 92,
+ CCGR_DISPMIX = 93,
+ CCGR_USDHC3 = 94,
+ CCGR_SDMA3 = 95,
+ CCGR_XTAL = 96,
+ CCGR_PLL = 97,
+ CCGR_TEMP_SENSOR = 98,
+ CCGR_VPUMIX_BUS = 99,
+ CCGR_GPU2D = 102,
+ CCGR_MAX
+};
+
+enum clk_src_index {
+ CLK_SRC_CKIL_SYNC_REQ = 0,
+ CLK_SRC_ARM_PLL_EN = 1,
+ CLK_SRC_GPU_PLL_EN = 2,
+ CLK_SRC_VPU_PLL_EN = 3,
+ CLK_SRC_DRAM_PLL_EN = 4,
+ CLK_SRC_SYSTEM_PLL1_EN = 5,
+ CLK_SRC_SYSTEM_PLL2_EN = 6,
+ CLK_SRC_SYSTEM_PLL3_EN = 7,
+ CLK_SRC_AUDIO_PLL1_EN = 8,
+ CLK_SRC_AUDIO_PLL2_EN = 9,
+ CLK_SRC_VIDEO_PLL1_EN = 10,
+ CLK_SRC_RESERVED = 11,
+ CLK_SRC_ARM_PLL = 12,
+ CLK_SRC_GPU_PLL = 13,
+ CLK_SRC_VPU_PLL = 14,
+ CLK_SRC_DRAM_PLL = 15,
+ CLK_SRC_SYSTEM_PLL1_800M = 16,
+ CLK_SRC_SYSTEM_PLL1_400M = 17,
+ CLK_SRC_SYSTEM_PLL1_266M = 18,
+ CLK_SRC_SYSTEM_PLL1_200M = 19,
+ CLK_SRC_SYSTEM_PLL1_160M = 20,
+ CLK_SRC_SYSTEM_PLL1_133M = 21,
+ CLK_SRC_SYSTEM_PLL1_100M = 22,
+ CLK_SRC_SYSTEM_PLL1_80M = 23,
+ CLK_SRC_SYSTEM_PLL1_40M = 24,
+ CLK_SRC_SYSTEM_PLL2_1000M = 25,
+ CLK_SRC_SYSTEM_PLL2_500M = 26,
+ CLK_SRC_SYSTEM_PLL2_333M = 27,
+ CLK_SRC_SYSTEM_PLL2_250M = 28,
+ CLK_SRC_SYSTEM_PLL2_200M = 29,
+ CLK_SRC_SYSTEM_PLL2_166M = 30,
+ CLK_SRC_SYSTEM_PLL2_125M = 31,
+ CLK_SRC_SYSTEM_PLL2_100M = 32,
+ CLK_SRC_SYSTEM_PLL2_50M = 33,
+ CLK_SRC_SYSTEM_PLL3 = 34,
+ CLK_SRC_AUDIO_PLL1 = 35,
+ CLK_SRC_AUDIO_PLL2 = 36,
+ CLK_SRC_VIDEO_PLL1 = 37,
+};
+
+#define INTPLL_LOCK_MASK BIT(31)
+#define INTPLL_LOCK_SEL_MASK BIT(29)
+#define INTPLL_EXT_BYPASS_MASK BIT(28)
+#define INTPLL_DIV20_CLKE_MASK BIT(27)
+#define INTPLL_DIV20_CLKE_OVERRIDE_MASK BIT(26)
+#define INTPLL_DIV10_CLKE_MASK BIT(25)
+#define INTPLL_DIV10_CLKE_OVERRIDE_MASK BIT(24)
+#define INTPLL_DIV8_CLKE_MASK BIT(23)
+#define INTPLL_DIV8_CLKE_OVERRIDE_MASK BIT(22)
+#define INTPLL_DIV6_CLKE_MASK BIT(21)
+#define INTPLL_DIV6_CLKE_OVERRIDE_MASK BIT(20)
+#define INTPLL_DIV5_CLKE_MASK BIT(19)
+#define INTPLL_DIV5_CLKE_OVERRIDE_MASK BIT(18)
+#define INTPLL_DIV4_CLKE_MASK BIT(17)
+#define INTPLL_DIV4_CLKE_OVERRIDE_MASK BIT(16)
+#define INTPLL_DIV3_CLKE_MASK BIT(15)
+#define INTPLL_DIV3_CLKE_OVERRIDE_MASK BIT(14)
+#define INTPLL_DIV2_CLKE_MASK BIT(13)
+#define INTPLL_DIV2_CLKE_OVERRIDE_MASK BIT(12)
+#define INTPLL_CLKE_MASK BIT(11)
+#define INTPLL_CLKE_OVERRIDE_MASK BIT(10)
+#define INTPLL_RST_MASK BIT(9)
+#define INTPLL_RST_OVERRIDE_MASK BIT(8)
+#define INTPLL_BYPASS_MASK BIT(4)
+#define INTPLL_PAD_CLK_SEL_MASK GENMASK(3, 2)
+#define INTPLL_REF_CLK_SEL_MASK GENMASK(1, 0)
+
+#define INTPLL_MAIN_DIV_MASK GENMASK(21, 12)
+#define INTPLL_MAIN_DIV_VAL(n) ((n << 12) & GENMASK(21, 12))
+#define INTPLL_MAIN_DIV_SHIFT 12
+#define INTPLL_PRE_DIV_MASK GENMASK(9, 4)
+#define INTPLL_PRE_DIV_VAL(n) ((n << 4) & GENMASK(9, 4))
+#define INTPLL_PRE_DIV_SHIFT 4
+#define INTPLL_POST_DIV_MASK GENMASK(2, 0)
+#define INTPLL_POST_DIV_VAL(n) ((n << 0) & GENMASK(2, 0))
+#define INTPLL_POST_DIV_SHIFT 0
+
+#define INTPLL_LOCK_CON_DLY_MASK GENMASK(5, 4)
+#define INTPLL_LOCK_CON_DLY_SHIFT 4
+#define INTPLL_LOCK_CON_OUT_MASK GENMASK(3, 2)
+#define INTPLL_LOCK_CON_OUT_SHIFT 2
+#define INTPLL_LOCK_CON_IN_MASK GENMASK(1, 0)
+#define INTPLL_LOCK_CON_IN_SHIFT 0
+
+#define INTPLL_LRD_EN_MASK BIT(21)
+#define INTPLL_FOUT_MASK BIT(20)
+#define INTPLL_AFC_SEL_MASK BIT(19)
+#define INTPLL_PBIAS_CTRL_MASK BIT(18)
+#define INTPLL_PBIAS_CTRL_EN_MASK BIT(17)
+#define INTPLL_AFCINIT_SEL_MASK BIT(16)
+#define INTPLL_FSEL_MASK BIT(14)
+#define INTPLL_FEED_EN_MASK BIT(13)
+#define INTPLL_EXTAFC_MASK GENMASK(7, 3)
+#define INTPLL_AFC_EN_MASK BIT(2)
+#define INTPLL_ICP_MASK GENMASK(1, 0)
+
+#endif
diff --git a/arch/arm/mach-imx/imx8m/Makefile b/arch/arm/mach-imx/imx8m/Makefile
index 42a1544c6b..92184f3135 100644
--- a/arch/arm/mach-imx/imx8m/Makefile
+++ b/arch/arm/mach-imx/imx8m/Makefile
@@ -5,3 +5,4 @@
obj-y += lowlevel_init.o
obj-y += clock_slice.o soc.o
obj-$(CONFIG_IMX8MQ) += clock_imx8mq.o
+obj-$(CONFIG_IMX8MM) += clock_imx8mm.o
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
new file mode 100644
index 0000000000..beddd2d68b
--- /dev/null
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@ -0,0 +1,866 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018-2019 NXP
+ *
+ * Peng Fan <peng.fan@nxp.com>
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <div64.h>
+#include <errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
+
+void enable_ocotp_clk(unsigned char enable)
+{
+ clock_enable(CCGR_OCOTP, !!enable);
+}
+
+int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
+{
+ /* 0 - 3 is valid i2c num */
+ if (i2c_num > 3)
+ return -EINVAL;
+
+ clock_enable(CCGR_I2C1 + i2c_num, !!enable);
+
+ return 0;
+}
+
+u32 decode_intpll(enum clk_root_src intpll)
+{
+ u32 pll_gnrl_ctl, pll_div_ctl, pll_clke_mask;
+ u32 main_div, pre_div, post_div, div;
+ u64 freq;
+
+ switch (intpll) {
+ case ARM_PLL_CLK:
+ pll_gnrl_ctl = readl(&ana_pll->arm_pll_gnrl_ctl);
+ pll_div_ctl = readl(&ana_pll->arm_pll_div_ctl);
+ break;
+ case GPU_PLL_CLK:
+ pll_gnrl_ctl = readl(&ana_pll->gpu_pll_gnrl_ctl);
+ pll_div_ctl = readl(&ana_pll->gpu_pll_div_ctl);
+ break;
+ case VPU_PLL_CLK:
+ pll_gnrl_ctl = readl(&ana_pll->vpu_pll_gnrl_ctl);
+ pll_div_ctl = readl(&ana_pll->vpu_pll_div_ctl);
+ break;
+ case SYSTEM_PLL1_800M_CLK:
+ case SYSTEM_PLL1_400M_CLK:
+ case SYSTEM_PLL1_266M_CLK:
+ case SYSTEM_PLL1_200M_CLK:
+ case SYSTEM_PLL1_160M_CLK:
+ case SYSTEM_PLL1_133M_CLK:
+ case SYSTEM_PLL1_100M_CLK:
+ case SYSTEM_PLL1_80M_CLK:
+ case SYSTEM_PLL1_40M_CLK:
+ pll_gnrl_ctl = readl(&ana_pll->sys_pll1_gnrl_ctl);
+ pll_div_ctl = readl(&ana_pll->sys_pll1_div_ctl);
+ break;
+ case SYSTEM_PLL2_1000M_CLK:
+ case SYSTEM_PLL2_500M_CLK:
+ case SYSTEM_PLL2_333M_CLK:
+ case SYSTEM_PLL2_250M_CLK:
+ case SYSTEM_PLL2_200M_CLK:
+ case SYSTEM_PLL2_166M_CLK:
+ case SYSTEM_PLL2_125M_CLK:
+ case SYSTEM_PLL2_100M_CLK:
+ case SYSTEM_PLL2_50M_CLK:
+ pll_gnrl_ctl = readl(&ana_pll->sys_pll2_gnrl_ctl);
+ pll_div_ctl = readl(&ana_pll->sys_pll2_div_ctl);
+ break;
+ case SYSTEM_PLL3_CLK:
+ pll_gnrl_ctl = readl(&ana_pll->sys_pll3_gnrl_ctl);
+ pll_div_ctl = readl(&ana_pll->sys_pll3_div_ctl);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ /* Only support SYS_XTAL 24M, PAD_CLK not take into consideration */
+ if ((pll_gnrl_ctl & INTPLL_REF_CLK_SEL_MASK) != 0)
+ return 0;
+
+ if ((pll_gnrl_ctl & INTPLL_RST_MASK) == 0)
+ return 0;
+
+ /*
+ * When BYPASS is equal to 1, PLL enters the bypass mode
+ * regardless of the values of RESETB
+ */
+ if (pll_gnrl_ctl & INTPLL_BYPASS_MASK)
+ return 24000000u;
+
+ if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) {
+ puts("pll not locked\n");
+ return 0;
+ }
+
+ switch (intpll) {
+ case ARM_PLL_CLK:
+ case GPU_PLL_CLK:
+ case VPU_PLL_CLK:
+ case SYSTEM_PLL3_CLK:
+ case SYSTEM_PLL1_800M_CLK:
+ case SYSTEM_PLL2_1000M_CLK:
+ pll_clke_mask = INTPLL_CLKE_MASK;
+ div = 1;
+ break;
+
+ case SYSTEM_PLL1_400M_CLK:
+ case SYSTEM_PLL2_500M_CLK:
+ pll_clke_mask = INTPLL_DIV2_CLKE_MASK;
+ div = 2;
+ break;
+
+ case SYSTEM_PLL1_266M_CLK:
+ case SYSTEM_PLL2_333M_CLK:
+ pll_clke_mask = INTPLL_DIV3_CLKE_MASK;
+ div = 3;
+ break;
+
+ case SYSTEM_PLL1_200M_CLK:
+ case SYSTEM_PLL2_250M_CLK:
+ pll_clke_mask = INTPLL_DIV4_CLKE_MASK;
+ div = 4;
+ break;
+
+ case SYSTEM_PLL1_160M_CLK:
+ case SYSTEM_PLL2_200M_CLK:
+ pll_clke_mask = INTPLL_DIV5_CLKE_MASK;
+ div = 5;
+ break;
+
+ case SYSTEM_PLL1_133M_CLK:
+ case SYSTEM_PLL2_166M_CLK:
+ pll_clke_mask = INTPLL_DIV6_CLKE_MASK;
+ div = 6;
+ break;
+
+ case SYSTEM_PLL1_100M_CLK:
+ case SYSTEM_PLL2_125M_CLK:
+ pll_clke_mask = INTPLL_DIV8_CLKE_MASK;
+ div = 8;
+ break;
+
+ case SYSTEM_PLL1_80M_CLK:
+ case SYSTEM_PLL2_100M_CLK:
+ pll_clke_mask = INTPLL_DIV10_CLKE_MASK;
+ div = 10;
+ break;
+
+ case SYSTEM_PLL1_40M_CLK:
+ case SYSTEM_PLL2_50M_CLK:
+ pll_clke_mask = INTPLL_DIV20_CLKE_MASK;
+ div = 20;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if ((pll_gnrl_ctl & pll_clke_mask) == 0)
+ return 0;
+
+ main_div = (pll_div_ctl & INTPLL_MAIN_DIV_MASK) >>
+ INTPLL_MAIN_DIV_SHIFT;
+ pre_div = (pll_div_ctl & INTPLL_PRE_DIV_MASK) >>
+ INTPLL_PRE_DIV_SHIFT;
+ post_div = (pll_div_ctl & INTPLL_POST_DIV_MASK) >>
+ INTPLL_POST_DIV_SHIFT;
+
+ /* FFVCO = (m * FFIN) / p, FFOUT = (m * FFIN) / (p * 2^s) */
+ freq = 24000000ULL * main_div;
+ return lldiv(freq, pre_div * (1 << post_div) * div);
+}
+
+u32 decode_fracpll(enum clk_root_src frac_pll)
+{
+ u32 pll_gnrl_ctl, pll_fdiv_ctl0, pll_fdiv_ctl1;
+ u32 main_div, pre_div, post_div, k;
+
+ switch (frac_pll) {
+ case DRAM_PLL1_CLK:
+ pll_gnrl_ctl = readl(&ana_pll->dram_pll_gnrl_ctl);
+ pll_fdiv_ctl0 = readl(&ana_pll->dram_pll_fdiv_ctl0);
+ pll_fdiv_ctl1 = readl(&ana_pll->dram_pll_fdiv_ctl1);
+ break;
+ case AUDIO_PLL1_CLK:
+ pll_gnrl_ctl = readl(&ana_pll->audio_pll1_gnrl_ctl);
+ pll_fdiv_ctl0 = readl(&ana_pll->audio_pll1_fdiv_ctl0);
+ pll_fdiv_ctl1 = readl(&ana_pll->audio_pll1_fdiv_ctl1);
+ break;
+ case AUDIO_PLL2_CLK:
+ pll_gnrl_ctl = readl(&ana_pll->audio_pll2_gnrl_ctl);
+ pll_fdiv_ctl0 = readl(&ana_pll->audio_pll2_fdiv_ctl0);
+ pll_fdiv_ctl1 = readl(&ana_pll->audio_pll2_fdiv_ctl1);
+ break;
+ case VIDEO_PLL_CLK:
+ pll_gnrl_ctl = readl(&ana_pll->video_pll1_gnrl_ctl);
+ pll_fdiv_ctl0 = readl(&ana_pll->video_pll1_fdiv_ctl0);
+ pll_fdiv_ctl1 = readl(&ana_pll->video_pll1_fdiv_ctl1);
+ break;
+ default:
+ printf("Not supported\n");
+ return 0;
+ }
+
+ /* Only support SYS_XTAL 24M, PAD_CLK not take into consideration */
+ if ((pll_gnrl_ctl & INTPLL_REF_CLK_SEL_MASK) != 0)
+ return 0;
+
+ if ((pll_gnrl_ctl & INTPLL_RST_MASK) == 0)
+ return 0;
+ /*
+ * When BYPASS is equal to 1, PLL enters the bypass mode
+ * regardless of the values of RESETB
+ */
+ if (pll_gnrl_ctl & INTPLL_BYPASS_MASK)
+ return 24000000u;
+
+ if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) {
+ puts("pll not locked\n");
+ return 0;
+ }
+
+ if (!(pll_gnrl_ctl & INTPLL_CLKE_MASK))
+ return 0;
+
+ main_div = (pll_fdiv_ctl0 & INTPLL_MAIN_DIV_MASK) >>
+ INTPLL_MAIN_DIV_SHIFT;
+ pre_div = (pll_fdiv_ctl0 & INTPLL_PRE_DIV_MASK) >>
+ INTPLL_PRE_DIV_SHIFT;
+ post_div = (pll_fdiv_ctl0 & INTPLL_POST_DIV_MASK) >>
+ INTPLL_POST_DIV_SHIFT;
+
+ k = pll_fdiv_ctl1 & GENMASK(15, 0);
+
+ /*
+ * FFOUT = ((m + k / 65536) * FFIN) / (p * 2^s),
+ * 1 ≤ p ≤ 63, 64 ≤ m ≤ 1023, 0 ≤ s ≤ 6
+ */
+ return lldiv((main_div * 65536 + k) * 24000000ULL,
+ 65536 * pre_div * (1 << post_div));
+}
+
+static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = {
+ PLL_1443X_RATE(800000000U, 300, 9, 0, 0),
+ PLL_1443X_RATE(750000000U, 250, 8, 0, 0),
+ PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
+ PLL_1443X_RATE(600000000U, 300, 3, 2, 0),
+ PLL_1443X_RATE(594000000U, 99, 1, 2, 0),
+ PLL_1443X_RATE(400000000U, 300, 9, 1, 0),
+ PLL_1443X_RATE(266666667U, 400, 9, 2, 0),
+ PLL_1443X_RATE(167000000U, 334, 3, 4, 0),
+ PLL_1443X_RATE(100000000U, 300, 9, 3, 0),
+};
+
+int fracpll_configure(enum pll_clocks pll, u32 freq)
+{
+ int i;
+ u32 tmp, div_val;
+ void *pll_base;
+ struct imx_int_pll_rate_table *rate;
+
+ for (i = 0; i < ARRAY_SIZE(imx8mm_fracpll_tbl); i++) {
+ if (freq == imx8mm_fracpll_tbl[i].rate)
+ break;
+ }
+
+ if (i == ARRAY_SIZE(imx8mm_fracpll_tbl)) {
+ printf("No matched freq table %u\n", freq);
+ return -EINVAL;
+ }
+
+ rate = &imx8mm_fracpll_tbl[i];
+
+ switch (pll) {
+ case ANATOP_DRAM_PLL:
+ setbits_le32(GPC_BASE_ADDR + 0xEC, 1 << 7);
+ setbits_le32(GPC_BASE_ADDR + 0xF8, 1 << 5);
+ writel(SRC_DDR1_ENABLE_MASK, SRC_BASE_ADDR + 0x1004);
+
+ pll_base = &ana_pll->dram_pll_gnrl_ctl;
+ break;
+ case ANATOP_VIDEO_PLL:
+ pll_base = &ana_pll->video_pll1_gnrl_ctl;
+ break;
+ default:
+ return 0;
+ }
+ /* Bypass clock and set lock to pll output lock */
+ tmp = readl(pll_base);
+ tmp |= BYPASS_MASK;
+ writel(tmp, pll_base);
+
+ /* Enable RST */
+ tmp &= ~RST_MASK;
+ writel(tmp, pll_base);
+
+ div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
+ (rate->sdiv << SDIV_SHIFT);
+ writel(div_val, pll_base + 4);
+ writel(rate->kdiv << KDIV_SHIFT, pll_base + 8);
+
+ __udelay(100);
+
+ /* Disable RST */
+ tmp |= RST_MASK;
+ writel(tmp, pll_base);
+
+ /* Wait Lock*/
+ while (!(readl(pll_base) & LOCK_STATUS))
+ ;
+
+ /* Bypass */
+ tmp &= ~BYPASS_MASK;
+ writel(tmp, pll_base);
+
+ return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+void dram_pll_init(ulong pll_val)
+{
+ fracpll_configure(ANATOP_DRAM_PLL, pll_val);
+}
+
+static struct dram_bypass_clk_setting imx8mm_dram_bypass_tbl[] = {
+ DRAM_BYPASS_ROOT_CONFIG(MHZ(100), 2, CLK_ROOT_PRE_DIV1, 2,
+ CLK_ROOT_PRE_DIV2),
+ DRAM_BYPASS_ROOT_CONFIG(MHZ(250), 3, CLK_ROOT_PRE_DIV2, 2,
+ CLK_ROOT_PRE_DIV2),
+ DRAM_BYPASS_ROOT_CONFIG(MHZ(400), 1, CLK_ROOT_PRE_DIV2, 3,
+ CLK_ROOT_PRE_DIV2),
+};
+
+void dram_enable_bypass(ulong clk_val)
+{
+ int i;
+ struct dram_bypass_clk_setting *config;
+
+ for (i = 0; i < ARRAY_SIZE(imx8mm_dram_bypass_tbl); i++) {
+ if (clk_val == imx8mm_dram_bypass_tbl[i].clk)
+ break;
+ }
+
+ if (i == ARRAY_SIZE(imx8mm_dram_bypass_tbl)) {
+ printf("No matched freq table %lu\n", clk_val);
+ return;
+ }
+
+ config = &imx8mm_dram_bypass_tbl[i];
+
+ clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(config->alt_root_sel) |
+ CLK_ROOT_PRE_DIV(config->alt_pre_div));
+ clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(config->apb_root_sel) |
+ CLK_ROOT_PRE_DIV(config->apb_pre_div));
+ clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(1));
+}
+
+void dram_disable_bypass(void)
+{
+ clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(0));
+ clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(4) |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV5));
+}
+#endif
+
+int intpll_configure(enum pll_clocks pll, ulong freq)
+{
+ void __iomem *pll_gnrl_ctl, __iomem *pll_div_ctl;
+ u32 pll_div_ctl_val, pll_clke_masks;
+
+ switch (pll) {
+ case ANATOP_SYSTEM_PLL1:
+ pll_gnrl_ctl = &ana_pll->sys_pll1_gnrl_ctl;
+ pll_div_ctl = &ana_pll->sys_pll1_div_ctl;
+ pll_clke_masks = INTPLL_DIV20_CLKE_MASK |
+ INTPLL_DIV10_CLKE_MASK | INTPLL_DIV8_CLKE_MASK |
+ INTPLL_DIV6_CLKE_MASK | INTPLL_DIV5_CLKE_MASK |
+ INTPLL_DIV4_CLKE_MASK | INTPLL_DIV3_CLKE_MASK |
+ INTPLL_DIV2_CLKE_MASK | INTPLL_CLKE_MASK;
+ break;
+ case ANATOP_SYSTEM_PLL2:
+ pll_gnrl_ctl = &ana_pll->sys_pll2_gnrl_ctl;
+ pll_div_ctl = &ana_pll->sys_pll2_div_ctl;
+ pll_clke_masks = INTPLL_DIV20_CLKE_MASK |
+ INTPLL_DIV10_CLKE_MASK | INTPLL_DIV8_CLKE_MASK |
+ INTPLL_DIV6_CLKE_MASK | INTPLL_DIV5_CLKE_MASK |
+ INTPLL_DIV4_CLKE_MASK | INTPLL_DIV3_CLKE_MASK |
+ INTPLL_DIV2_CLKE_MASK | INTPLL_CLKE_MASK;
+ break;
+ case ANATOP_SYSTEM_PLL3:
+ pll_gnrl_ctl = &ana_pll->sys_pll3_gnrl_ctl;
+ pll_div_ctl = &ana_pll->sys_pll3_div_ctl;
+ pll_clke_masks = INTPLL_CLKE_MASK;
+ break;
+ case ANATOP_ARM_PLL:
+ pll_gnrl_ctl = &ana_pll->arm_pll_gnrl_ctl;
+ pll_div_ctl = &ana_pll->arm_pll_div_ctl;
+ pll_clke_masks = INTPLL_CLKE_MASK;
+ break;
+ case ANATOP_GPU_PLL:
+ pll_gnrl_ctl = &ana_pll->gpu_pll_gnrl_ctl;
+ pll_div_ctl = &ana_pll->gpu_pll_div_ctl;
+ pll_clke_masks = INTPLL_CLKE_MASK;
+ break;
+ case ANATOP_VPU_PLL:
+ pll_gnrl_ctl = &ana_pll->vpu_pll_gnrl_ctl;
+ pll_div_ctl = &ana_pll->vpu_pll_div_ctl;
+ pll_clke_masks = INTPLL_CLKE_MASK;
+ break;
+ default:
+ return -EINVAL;
+ };
+
+ switch (freq) {
+ case MHZ(750):
+ /* 24 * 0xfa / 2 / 2 ^ 2 */
+ pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xfa) |
+ INTPLL_PRE_DIV_VAL(2) | INTPLL_POST_DIV_VAL(2);
+ break;
+ case MHZ(800):
+ /* 24 * 0x190 / 3 / 2 ^ 2 */
+ pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0x190) |
+ INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(2);
+ break;
+ case MHZ(1000):
+ /* 24 * 0xfa / 3 / 2 ^ 1 */
+ pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xfa) |
+ INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(1);
+ break;
+ case MHZ(1200):
+ /* 24 * 0xc8 / 2 / 2 ^ 1 */
+ pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xc8) |
+ INTPLL_PRE_DIV_VAL(2) | INTPLL_POST_DIV_VAL(1);
+ break;
+ case MHZ(2000):
+ /* 24 * 0xfa / 3 / 2 ^ 0 */
+ pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xfa) |
+ INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(0);
+ break;
+ default:
+ return -EINVAL;
+ };
+ /* Bypass clock and set lock to pll output lock */
+ setbits_le32(pll_gnrl_ctl, INTPLL_BYPASS_MASK | INTPLL_LOCK_SEL_MASK);
+ /* Enable reset */
+ clrbits_le32(pll_gnrl_ctl, INTPLL_RST_MASK);
+ /* Configure */
+ writel(pll_div_ctl_val, pll_div_ctl);
+
+ __udelay(100);
+
+ /* Disable reset */
+ setbits_le32(pll_gnrl_ctl, INTPLL_RST_MASK);
+ /* Wait Lock */
+ while (!(readl(pll_gnrl_ctl) & INTPLL_LOCK_MASK))
+ ;
+ /* Clear bypass */
+ clrbits_le32(pll_gnrl_ctl, INTPLL_BYPASS_MASK);
+ setbits_le32(pll_gnrl_ctl, pll_clke_masks);
+
+ return 0;
+}
+
+void init_uart_clk(u32 index)
+{
+ /*
+ * set uart clock root
+ * 24M OSC
+ */
+ switch (index) {
+ case 0:
+ clock_enable(CCGR_UART1, 0);
+ clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(0));
+ clock_enable(CCGR_UART1, 1);
+ return;
+ case 1:
+ clock_enable(CCGR_UART2, 0);
+ clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(0));
+ clock_enable(CCGR_UART2, 1);
+ return;
+ case 2:
+ clock_enable(CCGR_UART3, 0);
+ clock_set_target_val(UART3_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(0));
+ clock_enable(CCGR_UART3, 1);
+ return;
+ case 3:
+ clock_enable(CCGR_UART4, 0);
+ clock_set_target_val(UART4_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(0));
+ clock_enable(CCGR_UART4, 1);
+ return;
+ default:
+ printf("Invalid uart index\n");
+ return;
+ }
+}
+
+void init_wdog_clk(void)
+{
+ clock_enable(CCGR_WDOG1, 0);
+ clock_enable(CCGR_WDOG2, 0);
+ clock_enable(CCGR_WDOG3, 0);
+ clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(0));
+ clock_enable(CCGR_WDOG1, 1);
+ clock_enable(CCGR_WDOG2, 1);
+ clock_enable(CCGR_WDOG3, 1);
+}
+
+void init_clk_usdhc(u32 index)
+{
+ /*
+ * set usdhc clock root
+ * sys pll1 400M
+ */
+ switch (index) {
+ case 0:
+ clock_enable(CCGR_USDHC1, 0);
+ clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
+ clock_enable(CCGR_USDHC1, 1);
+ return;
+ case 1:
+ clock_enable(CCGR_USDHC2, 0);
+ clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
+ clock_enable(CCGR_USDHC2, 1);
+ return;
+ case 2:
+ clock_enable(CCGR_USDHC3, 0);
+ clock_set_target_val(USDHC3_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
+ clock_enable(CCGR_USDHC3, 1);
+ return;
+ default:
+ printf("Invalid usdhc index\n");
+ return;
+ }
+}
+
+int clock_init(void)
+{
+ u32 val_cfg0;
+
+ /* Configure ARM at 1GHz */
+ clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(0));
+
+ intpll_configure(ANATOP_ARM_PLL, MHZ(1200));
+
+ clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1));
+
+ /*
+ * According to ANAMIX SPEC
+ * sys pll1 fixed at 800MHz
+ * sys pll2 fixed at 1GHz
+ * Here we only enable the outputs.
+ */
+ val_cfg0 = readl(&ana_pll->sys_pll1_gnrl_ctl);
+ val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK |
+ INTPLL_DIV3_CLKE_MASK | INTPLL_DIV4_CLKE_MASK |
+ INTPLL_DIV5_CLKE_MASK | INTPLL_DIV6_CLKE_MASK |
+ INTPLL_DIV8_CLKE_MASK | INTPLL_DIV10_CLKE_MASK |
+ INTPLL_DIV20_CLKE_MASK;
+ writel(val_cfg0, &ana_pll->sys_pll1_gnrl_ctl);
+
+ val_cfg0 = readl(&ana_pll->sys_pll2_gnrl_ctl);
+ val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK |
+ INTPLL_DIV3_CLKE_MASK | INTPLL_DIV4_CLKE_MASK |
+ INTPLL_DIV5_CLKE_MASK | INTPLL_DIV6_CLKE_MASK |
+ INTPLL_DIV8_CLKE_MASK | INTPLL_DIV10_CLKE_MASK |
+ INTPLL_DIV20_CLKE_MASK;
+ writel(val_cfg0, &ana_pll->sys_pll2_gnrl_ctl);
+
+ intpll_configure(ANATOP_SYSTEM_PLL3, MHZ(750));
+ clock_set_target_val(NOC_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(2));
+
+ /* config GIC to sys_pll2_100m */
+ clock_enable(CCGR_GIC, 0);
+ clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(3));
+ clock_enable(CCGR_GIC, 1);
+
+ clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(1));
+
+ clock_enable(CCGR_DDR1, 0);
+ clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(1));
+ clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(1));
+ clock_enable(CCGR_DDR1, 1);
+
+ init_wdog_clk();
+
+ clock_enable(CCGR_TEMP_SENSOR, 1);
+
+ clock_enable(CCGR_SEC_DEBUG, 1);
+
+ return 0;
+};
+
+int set_clk_qspi(void)
+{
+ /*
+ * set qspi root
+ * sys pll1 100M
+ */
+ clock_enable(CCGR_QSPI, 0);
+ clock_set_target_val(QSPI_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(7));
+ clock_enable(CCGR_QSPI, 1);
+
+ return 0;
+}
+
+#ifdef CONFIG_FEC_MXC
+int set_clk_enet(enum enet_freq type)
+{
+ u32 target;
+ u32 enet1_ref;
+
+ /* disable the clock first */
+ clock_enable(CCGR_ENET1, 0);
+ clock_enable(CCGR_SIM_ENET, 0);
+
+ switch (type) {
+ case ENET_125MHZ:
+ enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
+ break;
+ case ENET_50MHZ:
+ enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
+ break;
+ case ENET_25MHZ:
+ enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ /* set enet axi clock 266Mhz */
+ target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(ENET_AXI_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | enet1_ref |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(ENET_REF_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
+ clock_set_target_val(ENET_TIMER_CLK_ROOT, target);
+
+#ifdef CONFIG_FEC_MXC_25M_REF_CLK
+ target = CLK_ROOT_ON |
+ ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(ENET_PHY_REF_CLK_ROOT, target);
+#endif
+ /* enable clock */
+ clock_enable(CCGR_SIM_ENET, 1);
+ clock_enable(CCGR_ENET1, 1);
+
+ return 0;
+}
+#endif
+
+u32 get_root_src_clk(enum clk_root_src root_src)
+{
+ switch (root_src) {
+ case OSC_24M_CLK:
+ return 24000000u;
+ case OSC_HDMI_CLK:
+ return 26000000u;
+ case OSC_32K_CLK:
+ return 32000u;
+ case ARM_PLL_CLK:
+ case GPU_PLL_CLK:
+ case VPU_PLL_CLK:
+ case SYSTEM_PLL1_800M_CLK:
+ case SYSTEM_PLL1_400M_CLK:
+ case SYSTEM_PLL1_266M_CLK:
+ case SYSTEM_PLL1_200M_CLK:
+ case SYSTEM_PLL1_160M_CLK:
+ case SYSTEM_PLL1_133M_CLK:
+ case SYSTEM_PLL1_100M_CLK:
+ case SYSTEM_PLL1_80M_CLK:
+ case SYSTEM_PLL1_40M_CLK:
+ case SYSTEM_PLL2_1000M_CLK:
+ case SYSTEM_PLL2_500M_CLK:
+ case SYSTEM_PLL2_333M_CLK:
+ case SYSTEM_PLL2_250M_CLK:
+ case SYSTEM_PLL2_200M_CLK:
+ case SYSTEM_PLL2_166M_CLK:
+ case SYSTEM_PLL2_125M_CLK:
+ case SYSTEM_PLL2_100M_CLK:
+ case SYSTEM_PLL2_50M_CLK:
+ case SYSTEM_PLL3_CLK:
+ return decode_intpll(root_src);
+ case DRAM_PLL1_CLK:
+ case AUDIO_PLL1_CLK:
+ case AUDIO_PLL2_CLK:
+ case VIDEO_PLL_CLK:
+ return decode_fracpll(root_src);
+ default:
+ return 0;
+ }
+
+ return 0;
+}
+
+u32 get_root_clk(enum clk_root_index clock_id)
+{
+ enum clk_root_src root_src;
+ u32 post_podf, pre_podf, root_src_clk;
+
+ if (clock_root_enabled(clock_id) <= 0)
+ return 0;
+
+ if (clock_get_prediv(clock_id, &pre_podf) < 0)
+ return 0;
+
+ if (clock_get_postdiv(clock_id, &post_podf) < 0)
+ return 0;
+
+ if (clock_get_src(clock_id, &root_src) < 0)
+ return 0;
+
+ root_src_clk = get_root_src_clk(root_src);
+
+ return root_src_clk / (post_podf + 1) / (pre_podf + 1);
+}
+
+u32 mxc_get_clock(enum mxc_clock clk)
+{
+ u32 val;
+
+ switch (clk) {
+ case MXC_ARM_CLK:
+ return get_root_clk(ARM_A53_CLK_ROOT);
+ case MXC_IPG_CLK:
+ clock_get_target_val(IPG_CLK_ROOT, &val);
+ val = val & 0x3;
+ return get_root_clk(AHB_CLK_ROOT) / 2 / (val + 1);
+ case MXC_CSPI_CLK:
+ return get_root_clk(ECSPI1_CLK_ROOT);
+ case MXC_ESDHC_CLK:
+ return get_root_clk(USDHC1_CLK_ROOT);
+ case MXC_ESDHC2_CLK:
+ return get_root_clk(USDHC2_CLK_ROOT);
+ case MXC_ESDHC3_CLK:
+ return get_root_clk(USDHC3_CLK_ROOT);
+ case MXC_I2C_CLK:
+ return get_root_clk(I2C1_CLK_ROOT);
+ case MXC_UART_CLK:
+ return get_root_clk(UART1_CLK_ROOT);
+ case MXC_QSPI_CLK:
+ return get_root_clk(QSPI_CLK_ROOT);
+ default:
+ printf("Unsupported mxc_clock %d\n", clk);
+ break;
+ }
+
+ return 0;
+}
+
+u32 imx_get_uartclk(void)
+{
+ return mxc_get_clock(MXC_UART_CLK);
+}
+
+u32 imx_get_fecclk(void)
+{
+ return get_root_clk(ENET_AXI_CLK_ROOT);
+}
+
+/*
+ * Dump some clockes.
+ */
+#ifndef CONFIG_SPL_BUILD
+int do_mscale_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ u32 freq;
+
+ freq = decode_intpll(ARM_PLL_CLK);
+ printf("ARM_PLL %8d MHz\n", freq / 1000000);
+ freq = decode_intpll(SYSTEM_PLL1_800M_CLK);
+ printf("SYS_PLL1_800 %8d MHz\n", freq / 1000000);
+ freq = decode_intpll(SYSTEM_PLL1_400M_CLK);
+ printf("SYS_PLL1_400 %8d MHz\n", freq / 1000000);
+ freq = decode_intpll(SYSTEM_PLL1_266M_CLK);
+ printf("SYS_PLL1_266 %8d MHz\n", freq / 1000000);
+ freq = decode_intpll(SYSTEM_PLL1_160M_CLK);
+ printf("SYS_PLL1_160 %8d MHz\n", freq / 1000000);
+ freq = decode_intpll(SYSTEM_PLL1_133M_CLK);
+ printf("SYS_PLL1_133 %8d MHz\n", freq / 1000000);
+ freq = decode_intpll(SYSTEM_PLL1_100M_CLK);
+ printf("SYS_PLL1_100 %8d MHz\n", freq / 1000000);
+ freq = decode_intpll(SYSTEM_PLL1_80M_CLK);
+ printf("SYS_PLL1_80 %8d MHz\n", freq / 1000000);
+ freq = decode_intpll(SYSTEM_PLL1_40M_CLK);
+ printf("SYS_PLL1_40 %8d MHz\n", freq / 1000000);
+ freq = decode_intpll(SYSTEM_PLL2_1000M_CLK);
+ printf("SYS_PLL2_1000 %8d MHz\n", freq / 1000000);
+ freq = decode_intpll(SYSTEM_PLL2_500M_CLK);
+ printf("SYS_PLL2_500 %8d MHz\n", freq / 1000000);
+ freq = decode_intpll(SYSTEM_PLL2_333M_CLK);
+ printf("SYS_PLL2_333 %8d MHz\n", freq / 1000000);
+ freq = decode_intpll(SYSTEM_PLL2_250M_CLK);
+ printf("SYS_PLL2_250 %8d MHz\n", freq / 1000000);
+ freq = decode_intpll(SYSTEM_PLL2_200M_CLK);
+ printf("SYS_PLL2_200 %8d MHz\n", freq / 1000000);
+ freq = decode_intpll(SYSTEM_PLL2_166M_CLK);
+ printf("SYS_PLL2_166 %8d MHz\n", freq / 1000000);
+ freq = decode_intpll(SYSTEM_PLL2_125M_CLK);
+ printf("SYS_PLL2_125 %8d MHz\n", freq / 1000000);
+ freq = decode_intpll(SYSTEM_PLL2_100M_CLK);
+ printf("SYS_PLL2_100 %8d MHz\n", freq / 1000000);
+ freq = decode_intpll(SYSTEM_PLL2_50M_CLK);
+ printf("SYS_PLL2_50 %8d MHz\n", freq / 1000000);
+ freq = decode_intpll(SYSTEM_PLL3_CLK);
+ printf("SYS_PLL3 %8d MHz\n", freq / 1000000);
+ freq = mxc_get_clock(MXC_UART_CLK);
+ printf("UART1 %8d MHz\n", freq / 1000000);
+ freq = mxc_get_clock(MXC_ESDHC_CLK);
+ printf("USDHC1 %8d MHz\n", freq / 1000000);
+ freq = mxc_get_clock(MXC_QSPI_CLK);
+ printf("QSPI %8d MHz\n", freq / 1000000);
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ clocks, CONFIG_SYS_MAXARGS, 1, do_mscale_showclocks,
+ "display clocks",
+ ""
+);
+#endif
diff --git a/arch/arm/mach-imx/imx8m/clock_slice.c b/arch/arm/mach-imx/imx8m/clock_slice.c
index 1a67c626f1..dc2a018e00 100644
--- a/arch/arm/mach-imx/imx8m/clock_slice.c
+++ b/arch/arm/mach-imx/imx8m/clock_slice.c
@@ -13,6 +13,7 @@
static struct ccm_reg *ccm_reg = (struct ccm_reg *)CCM_BASE_ADDR;
+#ifdef CONFIG_IMX8MQ
static struct clk_root_map root_array[] = {
{ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0,
{OSC_25M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
@@ -474,6 +475,466 @@ static struct clk_root_map root_array[] = {
{DRAM_PLL1_CLK}
},
};
+#elif defined(CONFIG_IMX8MM)
+static struct clk_root_map root_array[] = {
+ {ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0,
+ {OSC_24M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
+ SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL3_CLK}
+ },
+ {ARM_M4_CLK_ROOT, CORE_CLOCK_SLICE, 1,
+ {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_250M_CLK,
+ SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
+ AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
+ },
+ {VPU_A53_CLK_ROOT, CORE_CLOCK_SLICE, 2,
+ {OSC_24M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
+ SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, VPU_PLL_CLK}
+ },
+ {GPU3D_CLK_ROOT, CORE_CLOCK_SLICE, 3,
+ {OSC_24M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
+ AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+ },
+ {GPU2D_CLK_ROOT, CORE_CLOCK_SLICE, 4,
+ {OSC_24M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
+ AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+ },
+ {MAIN_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 0,
+ {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_1000M_CLK,
+ AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL1_100M_CLK}
+ },
+ {ENET_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 1,
+ {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
+ AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
+ },
+ {NAND_USDHC_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 2,
+ {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL1_CLK}
+ },
+ {VPU_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 3,
+ {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, VPU_PLL_CLK,
+ AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
+ SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_100M_CLK}
+ },
+ {DISPLAY_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 4,
+ {OSC_24M_CLK, SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK, AUDIO_PLL2_CLK,
+ EXT_CLK_1, EXT_CLK_4}
+ },
+ {DISPLAY_APB_CLK_ROOT, BUS_CLOCK_SLICE, 5,
+ {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK, AUDIO_PLL2_CLK,
+ EXT_CLK_1, EXT_CLK_3}
+ },
+ {DISPLAY_RTRM_CLK_ROOT, BUS_CLOCK_SLICE, 6,
+ {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_200M_CLK,
+ SYSTEM_PLL2_1000M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
+ EXT_CLK_2, EXT_CLK_3}
+ },
+ {USB_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 7,
+ {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
+ EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
+ },
+ {GPU_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 8,
+ {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
+ AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+ },
+ {GPU_AHB_CLK_ROOT, BUS_CLOCK_SLICE, 9,
+ {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
+ AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+ },
+ {NOC_CLK_ROOT, BUS_CLOCK_SLICE, 10,
+ {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK,
+ SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK,
+ AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+ },
+ {NOC_APB_CLK_ROOT, BUS_CLOCK_SLICE, 11,
+ {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL3_CLK,
+ SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_200M_CLK,
+ SYSTEM_PLL1_800M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
+ },
+ {AHB_CLK_ROOT, AHB_CLOCK_SLICE, 0,
+ {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_125M_CLK,
+ SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
+ },
+ {AUDIO_AHB_CLK_ROOT, AHB_CLOCK_SLICE, 1,
+ {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_166M_CLK,
+ SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
+ },
+ {MIPI_DSI_ESC_RX_CLK_ROOT, AHB_CLOCK_SLICE, 2,
+ {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
+ SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+ SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
+ },
+ {DRAM_ALT_CLK_ROOT, IP_CLOCK_SLICE, 0,
+ {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL1_100M_CLK,
+ SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_1000M_CLK,
+ SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL1_266M_CLK}
+ },
+ {DRAM_APB_CLK_ROOT, IP_CLOCK_SLICE, 1,
+ {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
+ SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
+ },
+ {VPU_G1_CLK_ROOT, IP_CLOCK_SLICE, 2,
+ {OSC_24M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_100M_CLK,
+ SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
+ },
+ {VPU_G2_CLK_ROOT, IP_CLOCK_SLICE, 3,
+ {OSC_24M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_100M_CLK,
+ SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
+ },
+ {DISPLAY_DTRC_CLK_ROOT, IP_CLOCK_SLICE, 4,
+ {OSC_24M_CLK, VIDEO_PLL2_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_160M_CLK,
+ VIDEO_PLL_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK}
+ },
+ {DISPLAY_DC8000_CLK_ROOT, IP_CLOCK_SLICE, 5,
+ {OSC_24M_CLK, VIDEO_PLL2_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_160M_CLK,
+ VIDEO_PLL_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK}
+ },
+ {PCIE_CTRL_CLK_ROOT, IP_CLOCK_SLICE, 6,
+ {OSC_24M_CLK, SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
+ SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL3_CLK}
+ },
+ {PCIE_PHY_CLK_ROOT, IP_CLOCK_SLICE, 7,
+ {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_500M_CLK,
+ EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
+ SYSTEM_PLL1_400M_CLK}
+ },
+ {PCIE_AUX_CLK_ROOT, IP_CLOCK_SLICE, 8,
+ {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_50M_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
+ SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_200M_CLK}
+ },
+ {DC_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 9,
+ {OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
+ AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
+ },
+ {LCDIF_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 10,
+ {OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
+ AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
+ },
+ {SAI1_CLK_ROOT, IP_CLOCK_SLICE, 11,
+ {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+ VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+ OSC_HDMI_CLK, EXT_CLK_1, EXT_CLK_2}
+ },
+ {SAI2_CLK_ROOT, IP_CLOCK_SLICE, 12,
+ {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+ VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+ OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
+ },
+ {SAI3_CLK_ROOT, IP_CLOCK_SLICE, 13,
+ {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+ VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+ OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
+ },
+ {SAI4_CLK_ROOT, IP_CLOCK_SLICE, 14,
+ {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+ VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+ OSC_HDMI_CLK, EXT_CLK_1, EXT_CLK_2}
+ },
+ {SAI5_CLK_ROOT, IP_CLOCK_SLICE, 15,
+ {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+ VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+ OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
+ },
+ {SAI6_CLK_ROOT, IP_CLOCK_SLICE, 16,
+ {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+ VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+ OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
+ },
+ {SPDIF1_CLK_ROOT, IP_CLOCK_SLICE, 17,
+ {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+ VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+ OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
+ },
+ {SPDIF2_CLK_ROOT, IP_CLOCK_SLICE, 18,
+ {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+ VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+ OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
+ },
+ {ENET_REF_CLK_ROOT, IP_CLOCK_SLICE, 19,
+ {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_50M_CLK,
+ SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
+ AUDIO_PLL1_CLK, VIDEO_PLL_CLK, EXT_CLK_4}
+ },
+ {ENET_TIMER_CLK_ROOT, IP_CLOCK_SLICE, 20,
+ {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK,
+ EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
+ VIDEO_PLL_CLK}
+ },
+ {ENET_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 21,
+ {OSC_24M_CLK, SYSTEM_PLL2_50M_CLK, SYSTEM_PLL2_125M_CLK,
+ SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_500M_CLK,
+ AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+ },
+ {NAND_CLK_ROOT, IP_CLOCK_SLICE, 22,
+ {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, AUDIO_PLL1_CLK,
+ SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK,
+ SYSTEM_PLL2_250M_CLK, VIDEO_PLL_CLK}
+ },
+ {QSPI_CLK_ROOT, IP_CLOCK_SLICE, 23,
+ {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_333M_CLK,
+ SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK,
+ SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK}
+ },
+ {USDHC1_CLK_ROOT, IP_CLOCK_SLICE, 24,
+ {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
+ SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
+ },
+ {USDHC2_CLK_ROOT, IP_CLOCK_SLICE, 25,
+ {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
+ SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
+ },
+ {I2C1_CLK_ROOT, IP_CLOCK_SLICE, 26,
+ {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
+ SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
+ AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
+ },
+ {I2C2_CLK_ROOT, IP_CLOCK_SLICE, 27,
+ {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
+ SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
+ AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
+ },
+ {I2C3_CLK_ROOT, IP_CLOCK_SLICE, 28,
+ {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
+ SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
+ AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
+ },
+ {I2C4_CLK_ROOT, IP_CLOCK_SLICE, 29,
+ {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
+ SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
+ AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
+ },
+ {UART1_CLK_ROOT, IP_CLOCK_SLICE, 30,
+ {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
+ SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
+ EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
+ },
+ {UART2_CLK_ROOT, IP_CLOCK_SLICE, 31,
+ {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
+ SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
+ EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
+ },
+ {UART3_CLK_ROOT, IP_CLOCK_SLICE, 32,
+ {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
+ SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
+ EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
+ },
+ {UART4_CLK_ROOT, IP_CLOCK_SLICE, 33,
+ {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
+ SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
+ EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
+ },
+ {USB_CORE_REF_CLK_ROOT, IP_CLOCK_SLICE, 34,
+ {OSC_24M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
+ SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
+ EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
+ },
+ {USB_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 35,
+ {OSC_24M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
+ SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
+ EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
+ },
+ {GIC_CLK_ROOT, IP_CLOCK_SLICE, 36,
+ {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
+ SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_800M_CLK,
+ EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
+ },
+ {ECSPI1_CLK_ROOT, IP_CLOCK_SLICE, 37,
+ {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
+ SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
+ },
+ {ECSPI2_CLK_ROOT, IP_CLOCK_SLICE, 38,
+ {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
+ SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
+ },
+ {PWM1_CLK_ROOT, IP_CLOCK_SLICE, 39,
+ {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
+ SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
+ SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
+ },
+ {PWM2_CLK_ROOT, IP_CLOCK_SLICE, 40,
+ {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
+ SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
+ SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
+ },
+ {PWM3_CLK_ROOT, IP_CLOCK_SLICE, 41,
+ {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
+ SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2,
+ SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
+ },
+ {PWM4_CLK_ROOT, IP_CLOCK_SLICE, 42,
+ {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
+ SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2,
+ SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
+ },
+ {GPT1_CLK_ROOT, IP_CLOCK_SLICE, 43,
+ {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+ SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+ SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
+ },
+ {GPT2_CLK_ROOT, IP_CLOCK_SLICE, 44,
+ {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+ SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+ SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
+ },
+ {GPT3_CLK_ROOT, IP_CLOCK_SLICE, 45,
+ {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+ SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+ SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
+ },
+ {GPT4_CLK_ROOT, IP_CLOCK_SLICE, 46,
+ {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+ SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+ SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
+ },
+ {GPT5_CLK_ROOT, IP_CLOCK_SLICE, 47,
+ {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+ SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+ SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
+ },
+ {GPT6_CLK_ROOT, IP_CLOCK_SLICE, 48,
+ {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+ SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+ SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
+ },
+ {TRACE_CLK_ROOT, IP_CLOCK_SLICE, 49,
+ {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
+ VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
+ SYSTEM_PLL3_CLK, EXT_CLK_1, EXT_CLK_3}
+ },
+ {WDOG_CLK_ROOT, IP_CLOCK_SLICE, 50,
+ {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
+ VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_166M_CLK}
+ },
+ {WRCLK_CLK_ROOT, IP_CLOCK_SLICE, 51,
+ {OSC_24M_CLK, SYSTEM_PLL1_40M_CLK, VPU_PLL_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL2_200M_CLK,
+ SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_100M_CLK}
+ },
+ {IPP_DO_CLKO1, IP_CLOCK_SLICE, 52,
+ {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, OSC_HDMI_CLK,
+ SYSTEM_PLL1_200M_CLK, AUDIO_PLL2_CLK,
+ SYSTEM_PLL2_500M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_80M_CLK}
+ },
+ {IPP_DO_CLKO2, IP_CLOCK_SLICE, 53,
+ {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_400M_CLK,
+ SYSTEM_PLL2_166M_CLK, SYSTEM_PLL3_CLK,
+ AUDIO_PLL1_CLK, VIDEO_PLL_CLK, OSC_32K_CLK}
+ },
+ {MIPI_DSI_CORE_CLK_ROOT, IP_CLOCK_SLICE, 54,
+ {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
+ SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+ SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+ },
+ {MIPI_DSI_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 55,
+ {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_100M_CLK,
+ SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+ EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+ },
+ {MIPI_DSI_DBI_CLK_ROOT, IP_CLOCK_SLICE, 56,
+ {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_100M_CLK,
+ SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+ SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+ },
+ {USDHC3_CLK_ROOT, IP_CLOCK_SLICE, 57,
+ {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
+ SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
+ },
+ {MIPI_CSI1_CORE_CLK_ROOT, IP_CLOCK_SLICE, 58,
+ {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
+ SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+ SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+ },
+ {MIPI_CSI1_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 59,
+ {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK,
+ SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+ EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+ },
+ {MIPI_CSI1_ESC_CLK_ROOT, IP_CLOCK_SLICE, 60,
+ {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
+ SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+ SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
+ },
+ {MIPI_CSI2_CORE_CLK_ROOT, IP_CLOCK_SLICE, 61,
+ {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
+ SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+ SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+ },
+ {MIPI_CSI2_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 62,
+ {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK,
+ SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+ EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+ },
+ {MIPI_CSI2_ESC_CLK_ROOT, IP_CLOCK_SLICE, 63,
+ {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
+ SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+ SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
+ },
+ {PCIE2_CTRL_CLK_ROOT, IP_CLOCK_SLICE, 64,
+ {OSC_24M_CLK, SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
+ SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL3_CLK}
+ },
+ {PCIE2_PHY_CLK_ROOT, IP_CLOCK_SLICE, 65,
+ {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_500M_CLK,
+ EXT_CLK_1, EXT_CLK_2, EXT_CLK_3,
+ EXT_CLK_4, SYSTEM_PLL1_400M_CLK}
+ },
+ {PCIE2_AUX_CLK_ROOT, IP_CLOCK_SLICE, 66,
+ {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_50M_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL2_100M_CLK,
+ SYSTEM_PLL1_80M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_200M_CLK}
+ },
+ {ECSPI3_CLK_ROOT, IP_CLOCK_SLICE, 67,
+ {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
+ SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
+ },
+ {PDM_CLK_ROOT, IP_CLOCK_SLICE, 68,
+ {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK,
+ SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+ SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK},
+ },
+ {VPU_H1_CLK_ROOT, IP_CLOCK_SLICE, 69,
+ {OSC_24M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_1000M_CLK, AUDIO_PLL2_CLK,
+ SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
+ },
+ {DRAM_SEL_CFG, DRAM_SEL_CLOCK_SLICE, 0,
+ {DRAM_PLL1_CLK}
+ },
+ {CORE_SEL_CFG, CORE_SEL_CLOCK_SLICE, 0,
+ {DRAM_PLL1_CLK}
+ },
+};
+#endif
static int select(enum clk_root_index clock_id)
{
--
2.14.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* [U-Boot] [PATCH 10/20] imx8m: add clk support for i.MX8MM
2019-01-28 9:39 ` [U-Boot] [PATCH 10/20] imx8m: add clk support for i.MX8MM Peng Fan
@ 2019-01-29 22:54 ` Lukasz Majewski
2019-01-30 5:46 ` Peng Fan
0 siblings, 1 reply; 39+ messages in thread
From: Lukasz Majewski @ 2019-01-29 22:54 UTC (permalink / raw)
To: u-boot
Hi Peng,
> Introduce clk implementation for i.MX8MM, including pll configuration,
> pll decoding, ccm configuration.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> arch/arm/include/asm/arch-imx8m/clock.h | 2 +
> arch/arm/include/asm/arch-imx8m/clock_imx8mm.h | 387 +++++++++++
> arch/arm/mach-imx/imx8m/Makefile | 1 +
> arch/arm/mach-imx/imx8m/clock_imx8mm.c | 866
> +++++++++++++++++++++++++
> arch/arm/mach-imx/imx8m/clock_slice.c | 461 +++++++++++++ 5
> files changed, 1717 insertions(+) create mode 100644
> arch/arm/include/asm/arch-imx8m/clock_imx8mm.h create mode 100644
> arch/arm/mach-imx/imx8m/clock_imx8mm.c
As fair as I see this approach is not similar to the one from Linux
kernel:
https://elixir.bootlin.com/linux/v5.0-rc3/source/drivers/clk/imx/clk-imx8mq.c
or simpler:
https://git.pengutronix.de/cgit/barebox/tree/drivers/clk/imx/clk-imx8mq.c
Also Fabio pointed out in the other mail that we shall stick to Linux
kernel Common Clock Framework.
IMHO we shall add the simple CCF look alike code (I'm going to post
imx6q port in a few days).
>
> diff --git a/arch/arm/include/asm/arch-imx8m/clock.h
> b/arch/arm/include/asm/arch-imx8m/clock.h index
> 7225c760fe..ead4b8d3dc 100644 ---
> a/arch/arm/include/asm/arch-imx8m/clock.h +++
> b/arch/arm/include/asm/arch-imx8m/clock.h @@ -7,6 +7,8 @@
>
> #ifdef CONFIG_IMX8MQ
> #include <asm/arch/clock_imx8mq.h>
> +#elif defined(CONFIG_IMX8MM)
> +#include <asm/arch/clock_imx8mm.h>
> #else
> #error "Error no clock.h"
> #endif
> diff --git a/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
> b/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h new file mode 100644
> index 0000000000..305514a4ec
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
> @@ -0,0 +1,387 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2018-2019 NXP
> + *
> + * Peng Fan <peng.fan@nxp.com>
> + */
> +
> +#ifndef _ASM_ARCH_IMX8MM_CLOCK_H
> +#define _ASM_ARCH_IMX8MM_CLOCK_H
> +
> +#define PLL_1443X_RATE(_rate, _m, _p, _s, _k)
> \
> + { \
> + .rate =
> (_rate), \
> + .mdiv =
> (_m), \
> + .pdiv =
> (_p), \
> + .sdiv =
> (_s), \
> + .kdiv =
> (_k), \
> + }
> +
> +#define LOCK_STATUS BIT(31)
> +#define LOCK_SEL_MASK BIT(29)
> +#define CLKE_MASK BIT(11)
> +#define RST_MASK BIT(9)
> +#define BYPASS_MASK BIT(4)
> +#define MDIV_SHIFT 12
> +#define MDIV_MASK GENMASK(21, 12)
> +#define PDIV_SHIFT 4
> +#define PDIV_MASK GENMASK(9, 4)
> +#define SDIV_SHIFT 0
> +#define SDIV_MASK GENMASK(2, 0)
> +#define KDIV_SHIFT 0
> +#define KDIV_MASK GENMASK(15, 0)
> +
> +struct imx_int_pll_rate_table {
> + u32 rate;
> + int mdiv;
> + int pdiv;
> + int sdiv;
> + int kdiv;
> +};
> +
> +enum pll_clocks {
> + ANATOP_ARM_PLL,
> + ANATOP_VPU_PLL,
> + ANATOP_GPU_PLL,
> + ANATOP_SYSTEM_PLL1,
> + ANATOP_SYSTEM_PLL2,
> + ANATOP_SYSTEM_PLL3,
> + ANATOP_AUDIO_PLL1,
> + ANATOP_AUDIO_PLL2,
> + ANATOP_VIDEO_PLL,
> + ANATOP_DRAM_PLL,
> +};
> +
> +enum clk_root_index {
> + ARM_A53_CLK_ROOT = 0,
> + ARM_M4_CLK_ROOT = 1,
> + VPU_A53_CLK_ROOT = 2,
> + GPU3D_CLK_ROOT = 3,
> + GPU2D_CLK_ROOT = 4,
> + MAIN_AXI_CLK_ROOT = 16,
> + ENET_AXI_CLK_ROOT = 17,
> + NAND_USDHC_BUS_CLK_ROOT = 18,
> + VPU_BUS_CLK_ROOT = 19,
> + DISPLAY_AXI_CLK_ROOT = 20,
> + DISPLAY_APB_CLK_ROOT = 21,
> + DISPLAY_RTRM_CLK_ROOT = 22,
> + USB_BUS_CLK_ROOT = 23,
> + GPU_AXI_CLK_ROOT = 24,
> + GPU_AHB_CLK_ROOT = 25,
> + NOC_CLK_ROOT = 26,
> + NOC_APB_CLK_ROOT = 27,
> + AHB_CLK_ROOT = 32,
> + IPG_CLK_ROOT = 33,
> + AUDIO_AHB_CLK_ROOT = 34,
> + MIPI_DSI_ESC_RX_CLK_ROOT = 36,
> + DRAM_SEL_CFG = 48,
> + CORE_SEL_CFG = 49,
> + DRAM_ALT_CLK_ROOT = 64,
> + DRAM_APB_CLK_ROOT = 65,
> + VPU_G1_CLK_ROOT = 66,
> + VPU_G2_CLK_ROOT = 67,
> + DISPLAY_DTRC_CLK_ROOT = 68,
> + DISPLAY_DC8000_CLK_ROOT = 69,
> + PCIE_CTRL_CLK_ROOT = 70,
> + PCIE_PHY_CLK_ROOT = 71,
> + PCIE_AUX_CLK_ROOT = 72,
> + DC_PIXEL_CLK_ROOT = 73,
> + LCDIF_PIXEL_CLK_ROOT = 74,
> + SAI1_CLK_ROOT = 75,
> + SAI2_CLK_ROOT = 76,
> + SAI3_CLK_ROOT = 77,
> + SAI4_CLK_ROOT = 78,
> + SAI5_CLK_ROOT = 79,
> + SAI6_CLK_ROOT = 80,
> + SPDIF1_CLK_ROOT = 81,
> + SPDIF2_CLK_ROOT = 82,
> + ENET_REF_CLK_ROOT = 83,
> + ENET_TIMER_CLK_ROOT = 84,
> + ENET_PHY_REF_CLK_ROOT = 85,
> + NAND_CLK_ROOT = 86,
> + QSPI_CLK_ROOT = 87,
> + USDHC1_CLK_ROOT = 88,
> + USDHC2_CLK_ROOT = 89,
> + I2C1_CLK_ROOT = 90,
> + I2C2_CLK_ROOT = 91,
> + I2C3_CLK_ROOT = 92,
> + I2C4_CLK_ROOT = 93,
> + UART1_CLK_ROOT = 94,
> + UART2_CLK_ROOT = 95,
> + UART3_CLK_ROOT = 96,
> + UART4_CLK_ROOT = 97,
> + USB_CORE_REF_CLK_ROOT = 98,
> + USB_PHY_REF_CLK_ROOT = 99,
> + GIC_CLK_ROOT = 100,
> + ECSPI1_CLK_ROOT = 101,
> + ECSPI2_CLK_ROOT = 102,
> + PWM1_CLK_ROOT = 103,
> + PWM2_CLK_ROOT = 104,
> + PWM3_CLK_ROOT = 105,
> + PWM4_CLK_ROOT = 106,
> + GPT1_CLK_ROOT = 107,
> + GPT2_CLK_ROOT = 108,
> + GPT3_CLK_ROOT = 109,
> + GPT4_CLK_ROOT = 110,
> + GPT5_CLK_ROOT = 111,
> + GPT6_CLK_ROOT = 112,
> + TRACE_CLK_ROOT = 113,
> + WDOG_CLK_ROOT = 114,
> + WRCLK_CLK_ROOT = 115,
> + IPP_DO_CLKO1 = 116,
> + IPP_DO_CLKO2 = 117,
> + MIPI_DSI_CORE_CLK_ROOT = 118,
> + MIPI_DSI_PHY_REF_CLK_ROOT = 119,
> + MIPI_DSI_DBI_CLK_ROOT = 120,
> + USDHC3_CLK_ROOT = 121,
> + MIPI_CSI1_CORE_CLK_ROOT = 122,
> + MIPI_CSI1_PHY_REF_CLK_ROOT = 123,
> + MIPI_CSI1_ESC_CLK_ROOT = 124,
> + MIPI_CSI2_CORE_CLK_ROOT = 125,
> + MIPI_CSI2_PHY_REF_CLK_ROOT = 126,
> + MIPI_CSI2_ESC_CLK_ROOT = 127,
> + PCIE2_CTRL_CLK_ROOT = 128,
> + PCIE2_PHY_CLK_ROOT = 129,
> + PCIE2_AUX_CLK_ROOT = 130,
> + ECSPI3_CLK_ROOT = 131,
> + PDM_CLK_ROOT = 132,
> + VPU_H1_CLK_ROOT = 133,
> + CLK_ROOT_MAX,
> +};
> +
> +enum clk_root_src {
> + OSC_24M_CLK,
> + ARM_PLL_CLK,
> + DRAM_PLL1_CLK,
> + VIDEO_PLL2_CLK,
> + VPU_PLL_CLK,
> + GPU_PLL_CLK,
> + SYSTEM_PLL1_800M_CLK,
> + SYSTEM_PLL1_400M_CLK,
> + SYSTEM_PLL1_266M_CLK,
> + SYSTEM_PLL1_200M_CLK,
> + SYSTEM_PLL1_160M_CLK,
> + SYSTEM_PLL1_133M_CLK,
> + SYSTEM_PLL1_100M_CLK,
> + SYSTEM_PLL1_80M_CLK,
> + SYSTEM_PLL1_40M_CLK,
> + SYSTEM_PLL2_1000M_CLK,
> + SYSTEM_PLL2_500M_CLK,
> + SYSTEM_PLL2_333M_CLK,
> + SYSTEM_PLL2_250M_CLK,
> + SYSTEM_PLL2_200M_CLK,
> + SYSTEM_PLL2_166M_CLK,
> + SYSTEM_PLL2_125M_CLK,
> + SYSTEM_PLL2_100M_CLK,
> + SYSTEM_PLL2_50M_CLK,
> + SYSTEM_PLL3_CLK,
> + AUDIO_PLL1_CLK,
> + AUDIO_PLL2_CLK,
> + VIDEO_PLL_CLK,
> + OSC_32K_CLK,
> + EXT_CLK_1,
> + EXT_CLK_2,
> + EXT_CLK_3,
> + EXT_CLK_4,
> + OSC_HDMI_CLK
> +};
> +
> +enum clk_ccgr_index {
> + CCGR_DVFS = 0,
> + CCGR_ANAMIX = 1,
> + CCGR_CPU = 2,
> + CCGR_CSU = 3,
> + CCGR_DEBUG = 4,
> + CCGR_DDR1 = 5,
> + CCGR_ECSPI1 = 7,
> + CCGR_ECSPI2 = 8,
> + CCGR_ECSPI3 = 9,
> + CCGR_ENET1 = 10,
> + CCGR_GPIO1 = 11,
> + CCGR_GPIO2 = 12,
> + CCGR_GPIO3 = 13,
> + CCGR_GPIO4 = 14,
> + CCGR_GPIO5 = 15,
> + CCGR_GPT1 = 16,
> + CCGR_GPT2 = 17,
> + CCGR_GPT3 = 18,
> + CCGR_GPT4 = 19,
> + CCGR_GPT5 = 20,
> + CCGR_GPT6 = 21,
> + CCGR_HS = 22,
> + CCGR_I2C1 = 23,
> + CCGR_I2C2 = 24,
> + CCGR_I2C3 = 25,
> + CCGR_I2C4 = 26,
> + CCGR_IOMUX = 27,
> + CCGR_IOMUX1 = 28,
> + CCGR_IOMUX2 = 29,
> + CCGR_IOMUX3 = 30,
> + CCGR_IOMUX4 = 31,
> + CCGR_SNVSMIX_IPG_CLK = 32,
> + CCGR_MU = 33,
> + CCGR_OCOTP = 34,
> + CCGR_OCRAM = 35,
> + CCGR_OCRAM_S = 36,
> + CCGR_PCIE = 37,
> + CCGR_PERFMON1 = 38,
> + CCGR_PERFMON2 = 39,
> + CCGR_PWM1 = 40,
> + CCGR_PWM2 = 41,
> + CCGR_PWM3 = 42,
> + CCGR_PWM4 = 43,
> + CCGR_QOS = 44,
> + CCGR_QOS_DISPMIX = 45,
> + CCGR_QOS_ETHENET = 46,
> + CCGR_QSPI = 47,
> + CCGR_RAWNAND = 48,
> + CCGR_RDC = 49,
> + CCGR_ROM = 50,
> + CCGR_SAI1 = 51,
> + CCGR_SAI2 = 52,
> + CCGR_SAI3 = 53,
> + CCGR_SAI4 = 54,
> + CCGR_SAI5 = 55,
> + CCGR_SAI6 = 56,
> + CCGR_SCTR = 57,
> + CCGR_SDMA1 = 58,
> + CCGR_SDMA2 = 59,
> + CCGR_SEC_DEBUG = 60,
> + CCGR_SEMA1 = 61,
> + CCGR_SEMA2 = 62,
> + CCGR_SIM_DISPLAY = 63,
> + CCGR_SIM_ENET = 64,
> + CCGR_SIM_M = 65,
> + CCGR_SIM_MAIN = 66,
> + CCGR_SIM_S = 67,
> + CCGR_SIM_WAKEUP = 68,
> + CCGR_SIM_HSIO = 69,
> + CCGR_SIM_VPU = 70,
> + CCGR_SNVS = 71,
> + CCGR_TRACE = 72,
> + CCGR_UART1 = 73,
> + CCGR_UART2 = 74,
> + CCGR_UART3 = 75,
> + CCGR_UART4 = 76,
> + CCGR_USB_MSCALE_PL301 = 77,
> + CCGR_GPU3D = 79,
> + CCGR_USDHC1 = 81,
> + CCGR_USDHC2 = 82,
> + CCGR_WDOG1 = 83,
> + CCGR_WDOG2 = 84,
> + CCGR_WDOG3 = 85,
> + CCGR_VPUG1 = 86,
> + CCGR_GPU_BUS = 87,
> + CCGR_VPUH1 = 89,
> + CCGR_VPUG2 = 90,
> + CCGR_PDM = 91,
> + CCGR_GIC = 92,
> + CCGR_DISPMIX = 93,
> + CCGR_USDHC3 = 94,
> + CCGR_SDMA3 = 95,
> + CCGR_XTAL = 96,
> + CCGR_PLL = 97,
> + CCGR_TEMP_SENSOR = 98,
> + CCGR_VPUMIX_BUS = 99,
> + CCGR_GPU2D = 102,
> + CCGR_MAX
> +};
> +
> +enum clk_src_index {
> + CLK_SRC_CKIL_SYNC_REQ = 0,
> + CLK_SRC_ARM_PLL_EN = 1,
> + CLK_SRC_GPU_PLL_EN = 2,
> + CLK_SRC_VPU_PLL_EN = 3,
> + CLK_SRC_DRAM_PLL_EN = 4,
> + CLK_SRC_SYSTEM_PLL1_EN = 5,
> + CLK_SRC_SYSTEM_PLL2_EN = 6,
> + CLK_SRC_SYSTEM_PLL3_EN = 7,
> + CLK_SRC_AUDIO_PLL1_EN = 8,
> + CLK_SRC_AUDIO_PLL2_EN = 9,
> + CLK_SRC_VIDEO_PLL1_EN = 10,
> + CLK_SRC_RESERVED = 11,
> + CLK_SRC_ARM_PLL = 12,
> + CLK_SRC_GPU_PLL = 13,
> + CLK_SRC_VPU_PLL = 14,
> + CLK_SRC_DRAM_PLL = 15,
> + CLK_SRC_SYSTEM_PLL1_800M = 16,
> + CLK_SRC_SYSTEM_PLL1_400M = 17,
> + CLK_SRC_SYSTEM_PLL1_266M = 18,
> + CLK_SRC_SYSTEM_PLL1_200M = 19,
> + CLK_SRC_SYSTEM_PLL1_160M = 20,
> + CLK_SRC_SYSTEM_PLL1_133M = 21,
> + CLK_SRC_SYSTEM_PLL1_100M = 22,
> + CLK_SRC_SYSTEM_PLL1_80M = 23,
> + CLK_SRC_SYSTEM_PLL1_40M = 24,
> + CLK_SRC_SYSTEM_PLL2_1000M = 25,
> + CLK_SRC_SYSTEM_PLL2_500M = 26,
> + CLK_SRC_SYSTEM_PLL2_333M = 27,
> + CLK_SRC_SYSTEM_PLL2_250M = 28,
> + CLK_SRC_SYSTEM_PLL2_200M = 29,
> + CLK_SRC_SYSTEM_PLL2_166M = 30,
> + CLK_SRC_SYSTEM_PLL2_125M = 31,
> + CLK_SRC_SYSTEM_PLL2_100M = 32,
> + CLK_SRC_SYSTEM_PLL2_50M = 33,
> + CLK_SRC_SYSTEM_PLL3 = 34,
> + CLK_SRC_AUDIO_PLL1 = 35,
> + CLK_SRC_AUDIO_PLL2 = 36,
> + CLK_SRC_VIDEO_PLL1 = 37,
> +};
> +
> +#define INTPLL_LOCK_MASK BIT(31)
> +#define INTPLL_LOCK_SEL_MASK BIT(29)
> +#define INTPLL_EXT_BYPASS_MASK BIT(28)
> +#define INTPLL_DIV20_CLKE_MASK BIT(27)
> +#define INTPLL_DIV20_CLKE_OVERRIDE_MASK BIT(26)
> +#define INTPLL_DIV10_CLKE_MASK BIT(25)
> +#define INTPLL_DIV10_CLKE_OVERRIDE_MASK BIT(24)
> +#define INTPLL_DIV8_CLKE_MASK BIT(23)
> +#define INTPLL_DIV8_CLKE_OVERRIDE_MASK BIT(22)
> +#define INTPLL_DIV6_CLKE_MASK BIT(21)
> +#define INTPLL_DIV6_CLKE_OVERRIDE_MASK BIT(20)
> +#define INTPLL_DIV5_CLKE_MASK BIT(19)
> +#define INTPLL_DIV5_CLKE_OVERRIDE_MASK BIT(18)
> +#define INTPLL_DIV4_CLKE_MASK BIT(17)
> +#define INTPLL_DIV4_CLKE_OVERRIDE_MASK BIT(16)
> +#define INTPLL_DIV3_CLKE_MASK BIT(15)
> +#define INTPLL_DIV3_CLKE_OVERRIDE_MASK BIT(14)
> +#define INTPLL_DIV2_CLKE_MASK BIT(13)
> +#define INTPLL_DIV2_CLKE_OVERRIDE_MASK BIT(12)
> +#define INTPLL_CLKE_MASK BIT(11)
> +#define INTPLL_CLKE_OVERRIDE_MASK BIT(10)
> +#define INTPLL_RST_MASK BIT(9)
> +#define INTPLL_RST_OVERRIDE_MASK BIT(8)
> +#define INTPLL_BYPASS_MASK BIT(4)
> +#define INTPLL_PAD_CLK_SEL_MASK GENMASK(3, 2)
> +#define INTPLL_REF_CLK_SEL_MASK GENMASK(1, 0)
> +
> +#define INTPLL_MAIN_DIV_MASK GENMASK(21, 12)
> +#define INTPLL_MAIN_DIV_VAL(n) ((n << 12) &
> GENMASK(21, 12)) +#define INTPLL_MAIN_DIV_SHIFT 12
> +#define INTPLL_PRE_DIV_MASK GENMASK(9, 4)
> +#define INTPLL_PRE_DIV_VAL(n) ((n << 4) & GENMASK(9,
> 4)) +#define INTPLL_PRE_DIV_SHIFT 4
> +#define INTPLL_POST_DIV_MASK GENMASK(2, 0)
> +#define INTPLL_POST_DIV_VAL(n) ((n << 0) & GENMASK(2,
> 0)) +#define INTPLL_POST_DIV_SHIFT 0
> +
> +#define INTPLL_LOCK_CON_DLY_MASK GENMASK(5, 4)
> +#define INTPLL_LOCK_CON_DLY_SHIFT 4
> +#define INTPLL_LOCK_CON_OUT_MASK GENMASK(3, 2)
> +#define INTPLL_LOCK_CON_OUT_SHIFT 2
> +#define INTPLL_LOCK_CON_IN_MASK GENMASK(1, 0)
> +#define INTPLL_LOCK_CON_IN_SHIFT 0
> +
> +#define INTPLL_LRD_EN_MASK BIT(21)
> +#define INTPLL_FOUT_MASK BIT(20)
> +#define INTPLL_AFC_SEL_MASK BIT(19)
> +#define INTPLL_PBIAS_CTRL_MASK BIT(18)
> +#define INTPLL_PBIAS_CTRL_EN_MASK BIT(17)
> +#define INTPLL_AFCINIT_SEL_MASK BIT(16)
> +#define INTPLL_FSEL_MASK BIT(14)
> +#define INTPLL_FEED_EN_MASK BIT(13)
> +#define INTPLL_EXTAFC_MASK GENMASK(7, 3)
> +#define INTPLL_AFC_EN_MASK BIT(2)
> +#define INTPLL_ICP_MASK GENMASK(1, 0)
> +
> +#endif
> diff --git a/arch/arm/mach-imx/imx8m/Makefile
> b/arch/arm/mach-imx/imx8m/Makefile index 42a1544c6b..92184f3135 100644
> --- a/arch/arm/mach-imx/imx8m/Makefile
> +++ b/arch/arm/mach-imx/imx8m/Makefile
> @@ -5,3 +5,4 @@
> obj-y += lowlevel_init.o
> obj-y += clock_slice.o soc.o
> obj-$(CONFIG_IMX8MQ) += clock_imx8mq.o
> +obj-$(CONFIG_IMX8MM) += clock_imx8mm.o
> diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> b/arch/arm/mach-imx/imx8m/clock_imx8mm.c new file mode 100644
> index 0000000000..beddd2d68b
> --- /dev/null
> +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> @@ -0,0 +1,866 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2018-2019 NXP
> + *
> + * Peng Fan <peng.fan@nxp.com>
> + */
> +
> +#include <common.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/imx-regs.h>
> +#include <asm/arch/sys_proto.h>
> +#include <asm/io.h>
> +#include <div64.h>
> +#include <errno.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static struct anamix_pll *ana_pll = (struct anamix_pll
> *)ANATOP_BASE_ADDR; +
> +void enable_ocotp_clk(unsigned char enable)
> +{
> + clock_enable(CCGR_OCOTP, !!enable);
> +}
> +
> +int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
> +{
> + /* 0 - 3 is valid i2c num */
> + if (i2c_num > 3)
> + return -EINVAL;
> +
> + clock_enable(CCGR_I2C1 + i2c_num, !!enable);
> +
> + return 0;
> +}
> +
> +u32 decode_intpll(enum clk_root_src intpll)
> +{
> + u32 pll_gnrl_ctl, pll_div_ctl, pll_clke_mask;
> + u32 main_div, pre_div, post_div, div;
> + u64 freq;
> +
> + switch (intpll) {
> + case ARM_PLL_CLK:
> + pll_gnrl_ctl = readl(&ana_pll->arm_pll_gnrl_ctl);
> + pll_div_ctl = readl(&ana_pll->arm_pll_div_ctl);
> + break;
> + case GPU_PLL_CLK:
> + pll_gnrl_ctl = readl(&ana_pll->gpu_pll_gnrl_ctl);
> + pll_div_ctl = readl(&ana_pll->gpu_pll_div_ctl);
> + break;
> + case VPU_PLL_CLK:
> + pll_gnrl_ctl = readl(&ana_pll->vpu_pll_gnrl_ctl);
> + pll_div_ctl = readl(&ana_pll->vpu_pll_div_ctl);
> + break;
> + case SYSTEM_PLL1_800M_CLK:
> + case SYSTEM_PLL1_400M_CLK:
> + case SYSTEM_PLL1_266M_CLK:
> + case SYSTEM_PLL1_200M_CLK:
> + case SYSTEM_PLL1_160M_CLK:
> + case SYSTEM_PLL1_133M_CLK:
> + case SYSTEM_PLL1_100M_CLK:
> + case SYSTEM_PLL1_80M_CLK:
> + case SYSTEM_PLL1_40M_CLK:
> + pll_gnrl_ctl = readl(&ana_pll->sys_pll1_gnrl_ctl);
> + pll_div_ctl = readl(&ana_pll->sys_pll1_div_ctl);
> + break;
> + case SYSTEM_PLL2_1000M_CLK:
> + case SYSTEM_PLL2_500M_CLK:
> + case SYSTEM_PLL2_333M_CLK:
> + case SYSTEM_PLL2_250M_CLK:
> + case SYSTEM_PLL2_200M_CLK:
> + case SYSTEM_PLL2_166M_CLK:
> + case SYSTEM_PLL2_125M_CLK:
> + case SYSTEM_PLL2_100M_CLK:
> + case SYSTEM_PLL2_50M_CLK:
> + pll_gnrl_ctl = readl(&ana_pll->sys_pll2_gnrl_ctl);
> + pll_div_ctl = readl(&ana_pll->sys_pll2_div_ctl);
> + break;
> + case SYSTEM_PLL3_CLK:
> + pll_gnrl_ctl = readl(&ana_pll->sys_pll3_gnrl_ctl);
> + pll_div_ctl = readl(&ana_pll->sys_pll3_div_ctl);
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + /* Only support SYS_XTAL 24M, PAD_CLK not take into
> consideration */
> + if ((pll_gnrl_ctl & INTPLL_REF_CLK_SEL_MASK) != 0)
> + return 0;
> +
> + if ((pll_gnrl_ctl & INTPLL_RST_MASK) == 0)
> + return 0;
> +
> + /*
> + * When BYPASS is equal to 1, PLL enters the bypass mode
> + * regardless of the values of RESETB
> + */
> + if (pll_gnrl_ctl & INTPLL_BYPASS_MASK)
> + return 24000000u;
> +
> + if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) {
> + puts("pll not locked\n");
> + return 0;
> + }
> +
> + switch (intpll) {
> + case ARM_PLL_CLK:
> + case GPU_PLL_CLK:
> + case VPU_PLL_CLK:
> + case SYSTEM_PLL3_CLK:
> + case SYSTEM_PLL1_800M_CLK:
> + case SYSTEM_PLL2_1000M_CLK:
> + pll_clke_mask = INTPLL_CLKE_MASK;
> + div = 1;
> + break;
> +
> + case SYSTEM_PLL1_400M_CLK:
> + case SYSTEM_PLL2_500M_CLK:
> + pll_clke_mask = INTPLL_DIV2_CLKE_MASK;
> + div = 2;
> + break;
> +
> + case SYSTEM_PLL1_266M_CLK:
> + case SYSTEM_PLL2_333M_CLK:
> + pll_clke_mask = INTPLL_DIV3_CLKE_MASK;
> + div = 3;
> + break;
> +
> + case SYSTEM_PLL1_200M_CLK:
> + case SYSTEM_PLL2_250M_CLK:
> + pll_clke_mask = INTPLL_DIV4_CLKE_MASK;
> + div = 4;
> + break;
> +
> + case SYSTEM_PLL1_160M_CLK:
> + case SYSTEM_PLL2_200M_CLK:
> + pll_clke_mask = INTPLL_DIV5_CLKE_MASK;
> + div = 5;
> + break;
> +
> + case SYSTEM_PLL1_133M_CLK:
> + case SYSTEM_PLL2_166M_CLK:
> + pll_clke_mask = INTPLL_DIV6_CLKE_MASK;
> + div = 6;
> + break;
> +
> + case SYSTEM_PLL1_100M_CLK:
> + case SYSTEM_PLL2_125M_CLK:
> + pll_clke_mask = INTPLL_DIV8_CLKE_MASK;
> + div = 8;
> + break;
> +
> + case SYSTEM_PLL1_80M_CLK:
> + case SYSTEM_PLL2_100M_CLK:
> + pll_clke_mask = INTPLL_DIV10_CLKE_MASK;
> + div = 10;
> + break;
> +
> + case SYSTEM_PLL1_40M_CLK:
> + case SYSTEM_PLL2_50M_CLK:
> + pll_clke_mask = INTPLL_DIV20_CLKE_MASK;
> + div = 20;
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + if ((pll_gnrl_ctl & pll_clke_mask) == 0)
> + return 0;
> +
> + main_div = (pll_div_ctl & INTPLL_MAIN_DIV_MASK) >>
> + INTPLL_MAIN_DIV_SHIFT;
> + pre_div = (pll_div_ctl & INTPLL_PRE_DIV_MASK) >>
> + INTPLL_PRE_DIV_SHIFT;
> + post_div = (pll_div_ctl & INTPLL_POST_DIV_MASK) >>
> + INTPLL_POST_DIV_SHIFT;
> +
> + /* FFVCO = (m * FFIN) / p, FFOUT = (m * FFIN) / (p * 2^s) */
> + freq = 24000000ULL * main_div;
> + return lldiv(freq, pre_div * (1 << post_div) * div);
> +}
> +
> +u32 decode_fracpll(enum clk_root_src frac_pll)
> +{
> + u32 pll_gnrl_ctl, pll_fdiv_ctl0, pll_fdiv_ctl1;
> + u32 main_div, pre_div, post_div, k;
> +
> + switch (frac_pll) {
> + case DRAM_PLL1_CLK:
> + pll_gnrl_ctl = readl(&ana_pll->dram_pll_gnrl_ctl);
> + pll_fdiv_ctl0 = readl(&ana_pll->dram_pll_fdiv_ctl0);
> + pll_fdiv_ctl1 = readl(&ana_pll->dram_pll_fdiv_ctl1);
> + break;
> + case AUDIO_PLL1_CLK:
> + pll_gnrl_ctl = readl(&ana_pll->audio_pll1_gnrl_ctl);
> + pll_fdiv_ctl0 =
> readl(&ana_pll->audio_pll1_fdiv_ctl0);
> + pll_fdiv_ctl1 =
> readl(&ana_pll->audio_pll1_fdiv_ctl1);
> + break;
> + case AUDIO_PLL2_CLK:
> + pll_gnrl_ctl = readl(&ana_pll->audio_pll2_gnrl_ctl);
> + pll_fdiv_ctl0 =
> readl(&ana_pll->audio_pll2_fdiv_ctl0);
> + pll_fdiv_ctl1 =
> readl(&ana_pll->audio_pll2_fdiv_ctl1);
> + break;
> + case VIDEO_PLL_CLK:
> + pll_gnrl_ctl = readl(&ana_pll->video_pll1_gnrl_ctl);
> + pll_fdiv_ctl0 =
> readl(&ana_pll->video_pll1_fdiv_ctl0);
> + pll_fdiv_ctl1 =
> readl(&ana_pll->video_pll1_fdiv_ctl1);
> + break;
> + default:
> + printf("Not supported\n");
> + return 0;
> + }
> +
> + /* Only support SYS_XTAL 24M, PAD_CLK not take into
> consideration */
> + if ((pll_gnrl_ctl & INTPLL_REF_CLK_SEL_MASK) != 0)
> + return 0;
> +
> + if ((pll_gnrl_ctl & INTPLL_RST_MASK) == 0)
> + return 0;
> + /*
> + * When BYPASS is equal to 1, PLL enters the bypass mode
> + * regardless of the values of RESETB
> + */
> + if (pll_gnrl_ctl & INTPLL_BYPASS_MASK)
> + return 24000000u;
> +
> + if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) {
> + puts("pll not locked\n");
> + return 0;
> + }
> +
> + if (!(pll_gnrl_ctl & INTPLL_CLKE_MASK))
> + return 0;
> +
> + main_div = (pll_fdiv_ctl0 & INTPLL_MAIN_DIV_MASK) >>
> + INTPLL_MAIN_DIV_SHIFT;
> + pre_div = (pll_fdiv_ctl0 & INTPLL_PRE_DIV_MASK) >>
> + INTPLL_PRE_DIV_SHIFT;
> + post_div = (pll_fdiv_ctl0 & INTPLL_POST_DIV_MASK) >>
> + INTPLL_POST_DIV_SHIFT;
> +
> + k = pll_fdiv_ctl1 & GENMASK(15, 0);
> +
> + /*
> + * FFOUT = ((m + k / 65536) * FFIN) / (p * 2^s),
> + * 1 ≤ p ≤ 63, 64 ≤ m ≤ 1023, 0 ≤ s ≤ 6
> + */
> + return lldiv((main_div * 65536 + k) * 24000000ULL,
> + 65536 * pre_div * (1 << post_div));
> +}
> +
> +static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = {
> + PLL_1443X_RATE(800000000U, 300, 9, 0, 0),
> + PLL_1443X_RATE(750000000U, 250, 8, 0, 0),
> + PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
> + PLL_1443X_RATE(600000000U, 300, 3, 2, 0),
> + PLL_1443X_RATE(594000000U, 99, 1, 2, 0),
> + PLL_1443X_RATE(400000000U, 300, 9, 1, 0),
> + PLL_1443X_RATE(266666667U, 400, 9, 2, 0),
> + PLL_1443X_RATE(167000000U, 334, 3, 4, 0),
> + PLL_1443X_RATE(100000000U, 300, 9, 3, 0),
> +};
> +
> +int fracpll_configure(enum pll_clocks pll, u32 freq)
> +{
> + int i;
> + u32 tmp, div_val;
> + void *pll_base;
> + struct imx_int_pll_rate_table *rate;
> +
> + for (i = 0; i < ARRAY_SIZE(imx8mm_fracpll_tbl); i++) {
> + if (freq == imx8mm_fracpll_tbl[i].rate)
> + break;
> + }
> +
> + if (i == ARRAY_SIZE(imx8mm_fracpll_tbl)) {
> + printf("No matched freq table %u\n", freq);
> + return -EINVAL;
> + }
> +
> + rate = &imx8mm_fracpll_tbl[i];
> +
> + switch (pll) {
> + case ANATOP_DRAM_PLL:
> + setbits_le32(GPC_BASE_ADDR + 0xEC, 1 << 7);
> + setbits_le32(GPC_BASE_ADDR + 0xF8, 1 << 5);
> + writel(SRC_DDR1_ENABLE_MASK, SRC_BASE_ADDR + 0x1004);
> +
> + pll_base = &ana_pll->dram_pll_gnrl_ctl;
> + break;
> + case ANATOP_VIDEO_PLL:
> + pll_base = &ana_pll->video_pll1_gnrl_ctl;
> + break;
> + default:
> + return 0;
> + }
> + /* Bypass clock and set lock to pll output lock */
> + tmp = readl(pll_base);
> + tmp |= BYPASS_MASK;
> + writel(tmp, pll_base);
> +
> + /* Enable RST */
> + tmp &= ~RST_MASK;
> + writel(tmp, pll_base);
> +
> + div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv <<
> PDIV_SHIFT) |
> + (rate->sdiv << SDIV_SHIFT);
> + writel(div_val, pll_base + 4);
> + writel(rate->kdiv << KDIV_SHIFT, pll_base + 8);
> +
> + __udelay(100);
> +
> + /* Disable RST */
> + tmp |= RST_MASK;
> + writel(tmp, pll_base);
> +
> + /* Wait Lock*/
> + while (!(readl(pll_base) & LOCK_STATUS))
> + ;
> +
> + /* Bypass */
> + tmp &= ~BYPASS_MASK;
> + writel(tmp, pll_base);
> +
> + return 0;
> +}
> +
> +#ifdef CONFIG_SPL_BUILD
> +void dram_pll_init(ulong pll_val)
> +{
> + fracpll_configure(ANATOP_DRAM_PLL, pll_val);
> +}
> +
> +static struct dram_bypass_clk_setting imx8mm_dram_bypass_tbl[] = {
> + DRAM_BYPASS_ROOT_CONFIG(MHZ(100), 2, CLK_ROOT_PRE_DIV1, 2,
> + CLK_ROOT_PRE_DIV2),
> + DRAM_BYPASS_ROOT_CONFIG(MHZ(250), 3, CLK_ROOT_PRE_DIV2, 2,
> + CLK_ROOT_PRE_DIV2),
> + DRAM_BYPASS_ROOT_CONFIG(MHZ(400), 1, CLK_ROOT_PRE_DIV2, 3,
> + CLK_ROOT_PRE_DIV2),
> +};
> +
> +void dram_enable_bypass(ulong clk_val)
> +{
> + int i;
> + struct dram_bypass_clk_setting *config;
> +
> + for (i = 0; i < ARRAY_SIZE(imx8mm_dram_bypass_tbl); i++) {
> + if (clk_val == imx8mm_dram_bypass_tbl[i].clk)
> + break;
> + }
> +
> + if (i == ARRAY_SIZE(imx8mm_dram_bypass_tbl)) {
> + printf("No matched freq table %lu\n", clk_val);
> + return;
> + }
> +
> + config = &imx8mm_dram_bypass_tbl[i];
> +
> + clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
> +
> CLK_ROOT_SOURCE_SEL(config->alt_root_sel) |
> + CLK_ROOT_PRE_DIV(config->alt_pre_div));
> + clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
> +
> CLK_ROOT_SOURCE_SEL(config->apb_root_sel) |
> + CLK_ROOT_PRE_DIV(config->apb_pre_div));
> + clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
> + CLK_ROOT_SOURCE_SEL(1));
> +}
> +
> +void dram_disable_bypass(void)
> +{
> + clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
> + CLK_ROOT_SOURCE_SEL(0));
> + clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
> + CLK_ROOT_SOURCE_SEL(4) |
> + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV5));
> +}
> +#endif
> +
> +int intpll_configure(enum pll_clocks pll, ulong freq)
> +{
> + void __iomem *pll_gnrl_ctl, __iomem *pll_div_ctl;
> + u32 pll_div_ctl_val, pll_clke_masks;
> +
> + switch (pll) {
> + case ANATOP_SYSTEM_PLL1:
> + pll_gnrl_ctl = &ana_pll->sys_pll1_gnrl_ctl;
> + pll_div_ctl = &ana_pll->sys_pll1_div_ctl;
> + pll_clke_masks = INTPLL_DIV20_CLKE_MASK |
> + INTPLL_DIV10_CLKE_MASK |
> INTPLL_DIV8_CLKE_MASK |
> + INTPLL_DIV6_CLKE_MASK |
> INTPLL_DIV5_CLKE_MASK |
> + INTPLL_DIV4_CLKE_MASK |
> INTPLL_DIV3_CLKE_MASK |
> + INTPLL_DIV2_CLKE_MASK | INTPLL_CLKE_MASK;
> + break;
> + case ANATOP_SYSTEM_PLL2:
> + pll_gnrl_ctl = &ana_pll->sys_pll2_gnrl_ctl;
> + pll_div_ctl = &ana_pll->sys_pll2_div_ctl;
> + pll_clke_masks = INTPLL_DIV20_CLKE_MASK |
> + INTPLL_DIV10_CLKE_MASK |
> INTPLL_DIV8_CLKE_MASK |
> + INTPLL_DIV6_CLKE_MASK |
> INTPLL_DIV5_CLKE_MASK |
> + INTPLL_DIV4_CLKE_MASK |
> INTPLL_DIV3_CLKE_MASK |
> + INTPLL_DIV2_CLKE_MASK | INTPLL_CLKE_MASK;
> + break;
> + case ANATOP_SYSTEM_PLL3:
> + pll_gnrl_ctl = &ana_pll->sys_pll3_gnrl_ctl;
> + pll_div_ctl = &ana_pll->sys_pll3_div_ctl;
> + pll_clke_masks = INTPLL_CLKE_MASK;
> + break;
> + case ANATOP_ARM_PLL:
> + pll_gnrl_ctl = &ana_pll->arm_pll_gnrl_ctl;
> + pll_div_ctl = &ana_pll->arm_pll_div_ctl;
> + pll_clke_masks = INTPLL_CLKE_MASK;
> + break;
> + case ANATOP_GPU_PLL:
> + pll_gnrl_ctl = &ana_pll->gpu_pll_gnrl_ctl;
> + pll_div_ctl = &ana_pll->gpu_pll_div_ctl;
> + pll_clke_masks = INTPLL_CLKE_MASK;
> + break;
> + case ANATOP_VPU_PLL:
> + pll_gnrl_ctl = &ana_pll->vpu_pll_gnrl_ctl;
> + pll_div_ctl = &ana_pll->vpu_pll_div_ctl;
> + pll_clke_masks = INTPLL_CLKE_MASK;
> + break;
> + default:
> + return -EINVAL;
> + };
> +
> + switch (freq) {
> + case MHZ(750):
> + /* 24 * 0xfa / 2 / 2 ^ 2 */
> + pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xfa) |
> + INTPLL_PRE_DIV_VAL(2) |
> INTPLL_POST_DIV_VAL(2);
> + break;
> + case MHZ(800):
> + /* 24 * 0x190 / 3 / 2 ^ 2 */
> + pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0x190) |
> + INTPLL_PRE_DIV_VAL(3) |
> INTPLL_POST_DIV_VAL(2);
> + break;
> + case MHZ(1000):
> + /* 24 * 0xfa / 3 / 2 ^ 1 */
> + pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xfa) |
> + INTPLL_PRE_DIV_VAL(3) |
> INTPLL_POST_DIV_VAL(1);
> + break;
> + case MHZ(1200):
> + /* 24 * 0xc8 / 2 / 2 ^ 1 */
> + pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xc8) |
> + INTPLL_PRE_DIV_VAL(2) |
> INTPLL_POST_DIV_VAL(1);
> + break;
> + case MHZ(2000):
> + /* 24 * 0xfa / 3 / 2 ^ 0 */
> + pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xfa) |
> + INTPLL_PRE_DIV_VAL(3) |
> INTPLL_POST_DIV_VAL(0);
> + break;
> + default:
> + return -EINVAL;
> + };
> + /* Bypass clock and set lock to pll output lock */
> + setbits_le32(pll_gnrl_ctl, INTPLL_BYPASS_MASK |
> INTPLL_LOCK_SEL_MASK);
> + /* Enable reset */
> + clrbits_le32(pll_gnrl_ctl, INTPLL_RST_MASK);
> + /* Configure */
> + writel(pll_div_ctl_val, pll_div_ctl);
> +
> + __udelay(100);
> +
> + /* Disable reset */
> + setbits_le32(pll_gnrl_ctl, INTPLL_RST_MASK);
> + /* Wait Lock */
> + while (!(readl(pll_gnrl_ctl) & INTPLL_LOCK_MASK))
> + ;
> + /* Clear bypass */
> + clrbits_le32(pll_gnrl_ctl, INTPLL_BYPASS_MASK);
> + setbits_le32(pll_gnrl_ctl, pll_clke_masks);
> +
> + return 0;
> +}
> +
> +void init_uart_clk(u32 index)
> +{
> + /*
> + * set uart clock root
> + * 24M OSC
> + */
> + switch (index) {
> + case 0:
> + clock_enable(CCGR_UART1, 0);
> + clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON |
> + CLK_ROOT_SOURCE_SEL(0));
> + clock_enable(CCGR_UART1, 1);
> + return;
> + case 1:
> + clock_enable(CCGR_UART2, 0);
> + clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON |
> + CLK_ROOT_SOURCE_SEL(0));
> + clock_enable(CCGR_UART2, 1);
> + return;
> + case 2:
> + clock_enable(CCGR_UART3, 0);
> + clock_set_target_val(UART3_CLK_ROOT, CLK_ROOT_ON |
> + CLK_ROOT_SOURCE_SEL(0));
> + clock_enable(CCGR_UART3, 1);
> + return;
> + case 3:
> + clock_enable(CCGR_UART4, 0);
> + clock_set_target_val(UART4_CLK_ROOT, CLK_ROOT_ON |
> + CLK_ROOT_SOURCE_SEL(0));
> + clock_enable(CCGR_UART4, 1);
> + return;
> + default:
> + printf("Invalid uart index\n");
> + return;
> + }
> +}
> +
> +void init_wdog_clk(void)
> +{
> + clock_enable(CCGR_WDOG1, 0);
> + clock_enable(CCGR_WDOG2, 0);
> + clock_enable(CCGR_WDOG3, 0);
> + clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
> + CLK_ROOT_SOURCE_SEL(0));
> + clock_enable(CCGR_WDOG1, 1);
> + clock_enable(CCGR_WDOG2, 1);
> + clock_enable(CCGR_WDOG3, 1);
> +}
> +
> +void init_clk_usdhc(u32 index)
> +{
> + /*
> + * set usdhc clock root
> + * sys pll1 400M
> + */
> + switch (index) {
> + case 0:
> + clock_enable(CCGR_USDHC1, 0);
> + clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON |
> + CLK_ROOT_SOURCE_SEL(1) |
> +
> CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
> + clock_enable(CCGR_USDHC1, 1);
> + return;
> + case 1:
> + clock_enable(CCGR_USDHC2, 0);
> + clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON |
> + CLK_ROOT_SOURCE_SEL(1) |
> +
> CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
> + clock_enable(CCGR_USDHC2, 1);
> + return;
> + case 2:
> + clock_enable(CCGR_USDHC3, 0);
> + clock_set_target_val(USDHC3_CLK_ROOT, CLK_ROOT_ON |
> + CLK_ROOT_SOURCE_SEL(1) |
> +
> CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
> + clock_enable(CCGR_USDHC3, 1);
> + return;
> + default:
> + printf("Invalid usdhc index\n");
> + return;
> + }
> +}
> +
> +int clock_init(void)
> +{
> + u32 val_cfg0;
> +
> + /* Configure ARM at 1GHz */
> + clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
> + CLK_ROOT_SOURCE_SEL(0));
> +
> + intpll_configure(ANATOP_ARM_PLL, MHZ(1200));
> +
> + clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
> + CLK_ROOT_SOURCE_SEL(1) |
> + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1));
> +
> + /*
> + * According to ANAMIX SPEC
> + * sys pll1 fixed at 800MHz
> + * sys pll2 fixed at 1GHz
> + * Here we only enable the outputs.
> + */
> + val_cfg0 = readl(&ana_pll->sys_pll1_gnrl_ctl);
> + val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK |
> + INTPLL_DIV3_CLKE_MASK | INTPLL_DIV4_CLKE_MASK |
> + INTPLL_DIV5_CLKE_MASK | INTPLL_DIV6_CLKE_MASK |
> + INTPLL_DIV8_CLKE_MASK | INTPLL_DIV10_CLKE_MASK |
> + INTPLL_DIV20_CLKE_MASK;
> + writel(val_cfg0, &ana_pll->sys_pll1_gnrl_ctl);
> +
> + val_cfg0 = readl(&ana_pll->sys_pll2_gnrl_ctl);
> + val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK |
> + INTPLL_DIV3_CLKE_MASK | INTPLL_DIV4_CLKE_MASK |
> + INTPLL_DIV5_CLKE_MASK | INTPLL_DIV6_CLKE_MASK |
> + INTPLL_DIV8_CLKE_MASK | INTPLL_DIV10_CLKE_MASK |
> + INTPLL_DIV20_CLKE_MASK;
> + writel(val_cfg0, &ana_pll->sys_pll2_gnrl_ctl);
> +
> + intpll_configure(ANATOP_SYSTEM_PLL3, MHZ(750));
> + clock_set_target_val(NOC_CLK_ROOT, CLK_ROOT_ON |
> + CLK_ROOT_SOURCE_SEL(2));
> +
> + /* config GIC to sys_pll2_100m */
> + clock_enable(CCGR_GIC, 0);
> + clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON |
> + CLK_ROOT_SOURCE_SEL(3));
> + clock_enable(CCGR_GIC, 1);
> +
> + clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON |
> + CLK_ROOT_SOURCE_SEL(1));
> +
> + clock_enable(CCGR_DDR1, 0);
> + clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
> + CLK_ROOT_SOURCE_SEL(1));
> + clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
> + CLK_ROOT_SOURCE_SEL(1));
> + clock_enable(CCGR_DDR1, 1);
> +
> + init_wdog_clk();
> +
> + clock_enable(CCGR_TEMP_SENSOR, 1);
> +
> + clock_enable(CCGR_SEC_DEBUG, 1);
> +
> + return 0;
> +};
> +
> +int set_clk_qspi(void)
> +{
> + /*
> + * set qspi root
> + * sys pll1 100M
> + */
> + clock_enable(CCGR_QSPI, 0);
> + clock_set_target_val(QSPI_CLK_ROOT, CLK_ROOT_ON |
> + CLK_ROOT_SOURCE_SEL(7));
> + clock_enable(CCGR_QSPI, 1);
> +
> + return 0;
> +}
> +
> +#ifdef CONFIG_FEC_MXC
> +int set_clk_enet(enum enet_freq type)
> +{
> + u32 target;
> + u32 enet1_ref;
> +
> + /* disable the clock first */
> + clock_enable(CCGR_ENET1, 0);
> + clock_enable(CCGR_SIM_ENET, 0);
> +
> + switch (type) {
> + case ENET_125MHZ:
> + enet1_ref =
> ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
> + break;
> + case ENET_50MHZ:
> + enet1_ref =
> ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
> + break;
> + case ENET_25MHZ:
> + enet1_ref =
> ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + /* set enet axi clock 266Mhz */
> + target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
> + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
> + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
> + clock_set_target_val(ENET_AXI_CLK_ROOT, target);
> +
> + target = CLK_ROOT_ON | enet1_ref |
> + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
> + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
> + clock_set_target_val(ENET_REF_CLK_ROOT, target);
> +
> + target = CLK_ROOT_ON |
> ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
> + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
> + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
> + clock_set_target_val(ENET_TIMER_CLK_ROOT, target);
> +
> +#ifdef CONFIG_FEC_MXC_25M_REF_CLK
> + target = CLK_ROOT_ON |
> + ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK |
> + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
> + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
> + clock_set_target_val(ENET_PHY_REF_CLK_ROOT, target);
> +#endif
> + /* enable clock */
> + clock_enable(CCGR_SIM_ENET, 1);
> + clock_enable(CCGR_ENET1, 1);
> +
> + return 0;
> +}
> +#endif
> +
> +u32 get_root_src_clk(enum clk_root_src root_src)
> +{
> + switch (root_src) {
> + case OSC_24M_CLK:
> + return 24000000u;
> + case OSC_HDMI_CLK:
> + return 26000000u;
> + case OSC_32K_CLK:
> + return 32000u;
> + case ARM_PLL_CLK:
> + case GPU_PLL_CLK:
> + case VPU_PLL_CLK:
> + case SYSTEM_PLL1_800M_CLK:
> + case SYSTEM_PLL1_400M_CLK:
> + case SYSTEM_PLL1_266M_CLK:
> + case SYSTEM_PLL1_200M_CLK:
> + case SYSTEM_PLL1_160M_CLK:
> + case SYSTEM_PLL1_133M_CLK:
> + case SYSTEM_PLL1_100M_CLK:
> + case SYSTEM_PLL1_80M_CLK:
> + case SYSTEM_PLL1_40M_CLK:
> + case SYSTEM_PLL2_1000M_CLK:
> + case SYSTEM_PLL2_500M_CLK:
> + case SYSTEM_PLL2_333M_CLK:
> + case SYSTEM_PLL2_250M_CLK:
> + case SYSTEM_PLL2_200M_CLK:
> + case SYSTEM_PLL2_166M_CLK:
> + case SYSTEM_PLL2_125M_CLK:
> + case SYSTEM_PLL2_100M_CLK:
> + case SYSTEM_PLL2_50M_CLK:
> + case SYSTEM_PLL3_CLK:
> + return decode_intpll(root_src);
> + case DRAM_PLL1_CLK:
> + case AUDIO_PLL1_CLK:
> + case AUDIO_PLL2_CLK:
> + case VIDEO_PLL_CLK:
> + return decode_fracpll(root_src);
> + default:
> + return 0;
> + }
> +
> + return 0;
> +}
> +
> +u32 get_root_clk(enum clk_root_index clock_id)
> +{
> + enum clk_root_src root_src;
> + u32 post_podf, pre_podf, root_src_clk;
> +
> + if (clock_root_enabled(clock_id) <= 0)
> + return 0;
> +
> + if (clock_get_prediv(clock_id, &pre_podf) < 0)
> + return 0;
> +
> + if (clock_get_postdiv(clock_id, &post_podf) < 0)
> + return 0;
> +
> + if (clock_get_src(clock_id, &root_src) < 0)
> + return 0;
> +
> + root_src_clk = get_root_src_clk(root_src);
> +
> + return root_src_clk / (post_podf + 1) / (pre_podf + 1);
> +}
> +
> +u32 mxc_get_clock(enum mxc_clock clk)
> +{
> + u32 val;
> +
> + switch (clk) {
> + case MXC_ARM_CLK:
> + return get_root_clk(ARM_A53_CLK_ROOT);
> + case MXC_IPG_CLK:
> + clock_get_target_val(IPG_CLK_ROOT, &val);
> + val = val & 0x3;
> + return get_root_clk(AHB_CLK_ROOT) / 2 / (val + 1);
> + case MXC_CSPI_CLK:
> + return get_root_clk(ECSPI1_CLK_ROOT);
> + case MXC_ESDHC_CLK:
> + return get_root_clk(USDHC1_CLK_ROOT);
> + case MXC_ESDHC2_CLK:
> + return get_root_clk(USDHC2_CLK_ROOT);
> + case MXC_ESDHC3_CLK:
> + return get_root_clk(USDHC3_CLK_ROOT);
> + case MXC_I2C_CLK:
> + return get_root_clk(I2C1_CLK_ROOT);
> + case MXC_UART_CLK:
> + return get_root_clk(UART1_CLK_ROOT);
> + case MXC_QSPI_CLK:
> + return get_root_clk(QSPI_CLK_ROOT);
> + default:
> + printf("Unsupported mxc_clock %d\n", clk);
> + break;
> + }
> +
> + return 0;
> +}
> +
> +u32 imx_get_uartclk(void)
> +{
> + return mxc_get_clock(MXC_UART_CLK);
> +}
> +
> +u32 imx_get_fecclk(void)
> +{
> + return get_root_clk(ENET_AXI_CLK_ROOT);
> +}
> +
> +/*
> + * Dump some clockes.
> + */
> +#ifndef CONFIG_SPL_BUILD
> +int do_mscale_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
> + char * const argv[])
> +{
> + u32 freq;
> +
> + freq = decode_intpll(ARM_PLL_CLK);
> + printf("ARM_PLL %8d MHz\n", freq / 1000000);
> + freq = decode_intpll(SYSTEM_PLL1_800M_CLK);
> + printf("SYS_PLL1_800 %8d MHz\n", freq / 1000000);
> + freq = decode_intpll(SYSTEM_PLL1_400M_CLK);
> + printf("SYS_PLL1_400 %8d MHz\n", freq / 1000000);
> + freq = decode_intpll(SYSTEM_PLL1_266M_CLK);
> + printf("SYS_PLL1_266 %8d MHz\n", freq / 1000000);
> + freq = decode_intpll(SYSTEM_PLL1_160M_CLK);
> + printf("SYS_PLL1_160 %8d MHz\n", freq / 1000000);
> + freq = decode_intpll(SYSTEM_PLL1_133M_CLK);
> + printf("SYS_PLL1_133 %8d MHz\n", freq / 1000000);
> + freq = decode_intpll(SYSTEM_PLL1_100M_CLK);
> + printf("SYS_PLL1_100 %8d MHz\n", freq / 1000000);
> + freq = decode_intpll(SYSTEM_PLL1_80M_CLK);
> + printf("SYS_PLL1_80 %8d MHz\n", freq / 1000000);
> + freq = decode_intpll(SYSTEM_PLL1_40M_CLK);
> + printf("SYS_PLL1_40 %8d MHz\n", freq / 1000000);
> + freq = decode_intpll(SYSTEM_PLL2_1000M_CLK);
> + printf("SYS_PLL2_1000 %8d MHz\n", freq / 1000000);
> + freq = decode_intpll(SYSTEM_PLL2_500M_CLK);
> + printf("SYS_PLL2_500 %8d MHz\n", freq / 1000000);
> + freq = decode_intpll(SYSTEM_PLL2_333M_CLK);
> + printf("SYS_PLL2_333 %8d MHz\n", freq / 1000000);
> + freq = decode_intpll(SYSTEM_PLL2_250M_CLK);
> + printf("SYS_PLL2_250 %8d MHz\n", freq / 1000000);
> + freq = decode_intpll(SYSTEM_PLL2_200M_CLK);
> + printf("SYS_PLL2_200 %8d MHz\n", freq / 1000000);
> + freq = decode_intpll(SYSTEM_PLL2_166M_CLK);
> + printf("SYS_PLL2_166 %8d MHz\n", freq / 1000000);
> + freq = decode_intpll(SYSTEM_PLL2_125M_CLK);
> + printf("SYS_PLL2_125 %8d MHz\n", freq / 1000000);
> + freq = decode_intpll(SYSTEM_PLL2_100M_CLK);
> + printf("SYS_PLL2_100 %8d MHz\n", freq / 1000000);
> + freq = decode_intpll(SYSTEM_PLL2_50M_CLK);
> + printf("SYS_PLL2_50 %8d MHz\n", freq / 1000000);
> + freq = decode_intpll(SYSTEM_PLL3_CLK);
> + printf("SYS_PLL3 %8d MHz\n", freq / 1000000);
> + freq = mxc_get_clock(MXC_UART_CLK);
> + printf("UART1 %8d MHz\n", freq / 1000000);
> + freq = mxc_get_clock(MXC_ESDHC_CLK);
> + printf("USDHC1 %8d MHz\n", freq / 1000000);
> + freq = mxc_get_clock(MXC_QSPI_CLK);
> + printf("QSPI %8d MHz\n", freq / 1000000);
> +
> + return 0;
> +}
> +
> +U_BOOT_CMD(
> + clocks, CONFIG_SYS_MAXARGS, 1, do_mscale_showclocks,
> + "display clocks",
> + ""
> +);
> +#endif
> diff --git a/arch/arm/mach-imx/imx8m/clock_slice.c
> b/arch/arm/mach-imx/imx8m/clock_slice.c index 1a67c626f1..dc2a018e00
> 100644 --- a/arch/arm/mach-imx/imx8m/clock_slice.c
> +++ b/arch/arm/mach-imx/imx8m/clock_slice.c
> @@ -13,6 +13,7 @@
>
> static struct ccm_reg *ccm_reg = (struct ccm_reg *)CCM_BASE_ADDR;
>
> +#ifdef CONFIG_IMX8MQ
> static struct clk_root_map root_array[] = {
> {ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0,
> {OSC_25M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
> @@ -474,6 +475,466 @@ static struct clk_root_map root_array[] = {
> {DRAM_PLL1_CLK}
> },
> };
> +#elif defined(CONFIG_IMX8MM)
> +static struct clk_root_map root_array[] = {
> + {ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0,
> + {OSC_24M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
> + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
> + SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL3_CLK}
> + },
> + {ARM_M4_CLK_ROOT, CORE_CLOCK_SLICE, 1,
> + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_250M_CLK,
> + SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
> + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
> + },
> + {VPU_A53_CLK_ROOT, CORE_CLOCK_SLICE, 2,
> + {OSC_24M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
> + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
> + SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, VPU_PLL_CLK}
> + },
> + {GPU3D_CLK_ROOT, CORE_CLOCK_SLICE, 3,
> + {OSC_24M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
> + SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
> + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
> + },
> + {GPU2D_CLK_ROOT, CORE_CLOCK_SLICE, 4,
> + {OSC_24M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
> + SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
> + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
> + },
> + {MAIN_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 0,
> + {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL1_800M_CLK,
> + SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_1000M_CLK,
> + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL1_100M_CLK}
> + },
> + {ENET_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 1,
> + {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
> + SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
> + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
> + },
> + {NAND_USDHC_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 2,
> + {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
> + SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK,
> + SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL1_CLK}
> + },
> + {VPU_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 3,
> + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, VPU_PLL_CLK,
> + AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
> + SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_100M_CLK}
> + },
> + {DISPLAY_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 4,
> + {OSC_24M_CLK, SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
> + SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK, AUDIO_PLL2_CLK,
> + EXT_CLK_1, EXT_CLK_4}
> + },
> + {DISPLAY_APB_CLK_ROOT, BUS_CLOCK_SLICE, 5,
> + {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK,
> + SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK, AUDIO_PLL2_CLK,
> + EXT_CLK_1, EXT_CLK_3}
> + },
> + {DISPLAY_RTRM_CLK_ROOT, BUS_CLOCK_SLICE, 6,
> + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_200M_CLK,
> + SYSTEM_PLL2_1000M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
> + EXT_CLK_2, EXT_CLK_3}
> + },
> + {USB_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 7,
> + {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
> + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
> + EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
> + },
> + {GPU_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 8,
> + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
> + SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
> + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
> + },
> + {GPU_AHB_CLK_ROOT, BUS_CLOCK_SLICE, 9,
> + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
> + SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
> + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
> + },
> + {NOC_CLK_ROOT, BUS_CLOCK_SLICE, 10,
> + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK,
> + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK,
> + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
> + },
> + {NOC_APB_CLK_ROOT, BUS_CLOCK_SLICE, 11,
> + {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL3_CLK,
> + SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_200M_CLK,
> + SYSTEM_PLL1_800M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
> + },
> + {AHB_CLK_ROOT, AHB_CLOCK_SLICE, 0,
> + {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_800M_CLK,
> + SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_125M_CLK,
> + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
> + },
> + {AUDIO_AHB_CLK_ROOT, AHB_CLOCK_SLICE, 1,
> + {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
> + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_166M_CLK,
> + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
> + },
> + {MIPI_DSI_ESC_RX_CLK_ROOT, AHB_CLOCK_SLICE, 2,
> + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
> + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> + SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
> + },
> + {DRAM_ALT_CLK_ROOT, IP_CLOCK_SLICE, 0,
> + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL1_100M_CLK,
> + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_1000M_CLK,
> + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL1_266M_CLK}
> + },
> + {DRAM_APB_CLK_ROOT, IP_CLOCK_SLICE, 1,
> + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
> + SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
> + SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
> + },
> + {VPU_G1_CLK_ROOT, IP_CLOCK_SLICE, 2,
> + {OSC_24M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
> + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_100M_CLK,
> + SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
> + },
> + {VPU_G2_CLK_ROOT, IP_CLOCK_SLICE, 3,
> + {OSC_24M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
> + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_100M_CLK,
> + SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
> + },
> + {DISPLAY_DTRC_CLK_ROOT, IP_CLOCK_SLICE, 4,
> + {OSC_24M_CLK, VIDEO_PLL2_CLK, SYSTEM_PLL1_800M_CLK,
> + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_160M_CLK,
> + VIDEO_PLL_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK}
> + },
> + {DISPLAY_DC8000_CLK_ROOT, IP_CLOCK_SLICE, 5,
> + {OSC_24M_CLK, VIDEO_PLL2_CLK, SYSTEM_PLL1_800M_CLK,
> + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_160M_CLK,
> + VIDEO_PLL_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK}
> + },
> + {PCIE_CTRL_CLK_ROOT, IP_CLOCK_SLICE, 6,
> + {OSC_24M_CLK, SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
> + SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
> + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_333M_CLK,
> SYSTEM_PLL3_CLK}
> + },
> + {PCIE_PHY_CLK_ROOT, IP_CLOCK_SLICE, 7,
> + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_500M_CLK,
> + EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
> + SYSTEM_PLL1_400M_CLK}
> + },
> + {PCIE_AUX_CLK_ROOT, IP_CLOCK_SLICE, 8,
> + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_50M_CLK,
> + SYSTEM_PLL3_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
> + SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_200M_CLK}
> + },
> + {DC_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 9,
> + {OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
> + AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
> + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
> + },
> + {LCDIF_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 10,
> + {OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
> + AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
> + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
> + },
> + {SAI1_CLK_ROOT, IP_CLOCK_SLICE, 11,
> + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
> + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
> + OSC_HDMI_CLK, EXT_CLK_1, EXT_CLK_2}
> + },
> + {SAI2_CLK_ROOT, IP_CLOCK_SLICE, 12,
> + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
> + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
> + OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
> + },
> + {SAI3_CLK_ROOT, IP_CLOCK_SLICE, 13,
> + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
> + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
> + OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
> + },
> + {SAI4_CLK_ROOT, IP_CLOCK_SLICE, 14,
> + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
> + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
> + OSC_HDMI_CLK, EXT_CLK_1, EXT_CLK_2}
> + },
> + {SAI5_CLK_ROOT, IP_CLOCK_SLICE, 15,
> + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
> + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
> + OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
> + },
> + {SAI6_CLK_ROOT, IP_CLOCK_SLICE, 16,
> + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
> + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
> + OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
> + },
> + {SPDIF1_CLK_ROOT, IP_CLOCK_SLICE, 17,
> + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
> + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
> + OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
> + },
> + {SPDIF2_CLK_ROOT, IP_CLOCK_SLICE, 18,
> + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
> + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
> + OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
> + },
> + {ENET_REF_CLK_ROOT, IP_CLOCK_SLICE, 19,
> + {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_50M_CLK,
> + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
> + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, EXT_CLK_4}
> + },
> + {ENET_TIMER_CLK_ROOT, IP_CLOCK_SLICE, 20,
> + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK,
> + EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
> + VIDEO_PLL_CLK}
> + },
> + {ENET_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 21,
> + {OSC_24M_CLK, SYSTEM_PLL2_50M_CLK, SYSTEM_PLL2_125M_CLK,
> + SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_500M_CLK,
> + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
> + },
> + {NAND_CLK_ROOT, IP_CLOCK_SLICE, 22,
> + {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, AUDIO_PLL1_CLK,
> + SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK,
> + SYSTEM_PLL2_250M_CLK, VIDEO_PLL_CLK}
> + },
> + {QSPI_CLK_ROOT, IP_CLOCK_SLICE, 23,
> + {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_333M_CLK,
> + SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK,
> + SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK,
> SYSTEM_PLL1_100M_CLK}
> + },
> + {USDHC1_CLK_ROOT, IP_CLOCK_SLICE, 24,
> + {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
> + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
> + SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
> + },
> + {USDHC2_CLK_ROOT, IP_CLOCK_SLICE, 25,
> + {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
> + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
> + SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
> + },
> + {I2C1_CLK_ROOT, IP_CLOCK_SLICE, 26,
> + {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
> + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
> + AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
> + },
> + {I2C2_CLK_ROOT, IP_CLOCK_SLICE, 27,
> + {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
> + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
> + AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
> + },
> + {I2C3_CLK_ROOT, IP_CLOCK_SLICE, 28,
> + {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
> + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
> + AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
> + },
> + {I2C4_CLK_ROOT, IP_CLOCK_SLICE, 29,
> + {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
> + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
> + AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
> + },
> + {UART1_CLK_ROOT, IP_CLOCK_SLICE, 30,
> + {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
> + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
> + EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
> + },
> + {UART2_CLK_ROOT, IP_CLOCK_SLICE, 31,
> + {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
> + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
> + EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
> + },
> + {UART3_CLK_ROOT, IP_CLOCK_SLICE, 32,
> + {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
> + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
> + EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
> + },
> + {UART4_CLK_ROOT, IP_CLOCK_SLICE, 33,
> + {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
> + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
> + EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
> + },
> + {USB_CORE_REF_CLK_ROOT, IP_CLOCK_SLICE, 34,
> + {OSC_24M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
> + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
> + EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
> + },
> + {USB_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 35,
> + {OSC_24M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
> + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
> + EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
> + },
> + {GIC_CLK_ROOT, IP_CLOCK_SLICE, 36,
> + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
> + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_800M_CLK,
> + EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
> + },
> + {ECSPI1_CLK_ROOT, IP_CLOCK_SLICE, 37,
> + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
> + SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
> + SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
> + },
> + {ECSPI2_CLK_ROOT, IP_CLOCK_SLICE, 38,
> + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
> + SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
> + SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
> + },
> + {PWM1_CLK_ROOT, IP_CLOCK_SLICE, 39,
> + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
> + SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
> + SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
> + },
> + {PWM2_CLK_ROOT, IP_CLOCK_SLICE, 40,
> + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
> + SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
> + SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
> + },
> + {PWM3_CLK_ROOT, IP_CLOCK_SLICE, 41,
> + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
> + SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2,
> + SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
> + },
> + {PWM4_CLK_ROOT, IP_CLOCK_SLICE, 42,
> + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
> + SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2,
> + SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
> + },
> + {GPT1_CLK_ROOT, IP_CLOCK_SLICE, 43,
> + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
> + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
> + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
> + },
> + {GPT2_CLK_ROOT, IP_CLOCK_SLICE, 44,
> + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
> + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
> + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
> + },
> + {GPT3_CLK_ROOT, IP_CLOCK_SLICE, 45,
> + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
> + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
> + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
> + },
> + {GPT4_CLK_ROOT, IP_CLOCK_SLICE, 46,
> + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
> + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
> + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
> + },
> + {GPT5_CLK_ROOT, IP_CLOCK_SLICE, 47,
> + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
> + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
> + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
> + },
> + {GPT6_CLK_ROOT, IP_CLOCK_SLICE, 48,
> + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
> + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
> + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
> + },
> + {TRACE_CLK_ROOT, IP_CLOCK_SLICE, 49,
> + {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
> + VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
> + SYSTEM_PLL3_CLK, EXT_CLK_1, EXT_CLK_3}
> + },
> + {WDOG_CLK_ROOT, IP_CLOCK_SLICE, 50,
> + {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
> + VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
> + SYSTEM_PLL3_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_166M_CLK}
> + },
> + {WRCLK_CLK_ROOT, IP_CLOCK_SLICE, 51,
> + {OSC_24M_CLK, SYSTEM_PLL1_40M_CLK, VPU_PLL_CLK,
> + SYSTEM_PLL3_CLK, SYSTEM_PLL2_200M_CLK,
> + SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_500M_CLK,
> SYSTEM_PLL1_100M_CLK}
> + },
> + {IPP_DO_CLKO1, IP_CLOCK_SLICE, 52,
> + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, OSC_HDMI_CLK,
> + SYSTEM_PLL1_200M_CLK, AUDIO_PLL2_CLK,
> + SYSTEM_PLL2_500M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_80M_CLK}
> + },
> + {IPP_DO_CLKO2, IP_CLOCK_SLICE, 53,
> + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_400M_CLK,
> + SYSTEM_PLL2_166M_CLK, SYSTEM_PLL3_CLK,
> + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, OSC_32K_CLK}
> + },
> + {MIPI_DSI_CORE_CLK_ROOT, IP_CLOCK_SLICE, 54,
> + {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
> + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> + SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
> + },
> + {MIPI_DSI_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 55,
> + {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_100M_CLK,
> + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> + EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
> + },
> + {MIPI_DSI_DBI_CLK_ROOT, IP_CLOCK_SLICE, 56,
> + {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_100M_CLK,
> + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> + SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
> + },
> + {USDHC3_CLK_ROOT, IP_CLOCK_SLICE, 57,
> + {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
> + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
> + SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
> + },
> + {MIPI_CSI1_CORE_CLK_ROOT, IP_CLOCK_SLICE, 58,
> + {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
> + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> + SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
> + },
> + {MIPI_CSI1_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 59,
> + {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK,
> + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> + EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
> + },
> + {MIPI_CSI1_ESC_CLK_ROOT, IP_CLOCK_SLICE, 60,
> + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
> + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> + SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
> + },
> + {MIPI_CSI2_CORE_CLK_ROOT, IP_CLOCK_SLICE, 61,
> + {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
> + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> + SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
> + },
> + {MIPI_CSI2_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 62,
> + {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK,
> + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> + EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
> + },
> + {MIPI_CSI2_ESC_CLK_ROOT, IP_CLOCK_SLICE, 63,
> + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
> + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> + SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
> + },
> + {PCIE2_CTRL_CLK_ROOT, IP_CLOCK_SLICE, 64,
> + {OSC_24M_CLK, SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
> + SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
> + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_333M_CLK,
> SYSTEM_PLL3_CLK}
> + },
> + {PCIE2_PHY_CLK_ROOT, IP_CLOCK_SLICE, 65,
> + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_500M_CLK,
> + EXT_CLK_1, EXT_CLK_2, EXT_CLK_3,
> + EXT_CLK_4, SYSTEM_PLL1_400M_CLK}
> + },
> + {PCIE2_AUX_CLK_ROOT, IP_CLOCK_SLICE, 66,
> + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_50M_CLK,
> + SYSTEM_PLL3_CLK, SYSTEM_PLL2_100M_CLK,
> + SYSTEM_PLL1_80M_CLK, SYSTEM_PLL1_160M_CLK,
> SYSTEM_PLL1_200M_CLK}
> + },
> + {ECSPI3_CLK_ROOT, IP_CLOCK_SLICE, 67,
> + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
> + SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
> + SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
> + },
> + {PDM_CLK_ROOT, IP_CLOCK_SLICE, 68,
> + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK,
> + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> + SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK},
> + },
> + {VPU_H1_CLK_ROOT, IP_CLOCK_SLICE, 69,
> + {OSC_24M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
> + SYSTEM_PLL2_1000M_CLK, AUDIO_PLL2_CLK,
> + SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
> + },
> + {DRAM_SEL_CFG, DRAM_SEL_CLOCK_SLICE, 0,
> + {DRAM_PLL1_CLK}
> + },
> + {CORE_SEL_CFG, CORE_SEL_CLOCK_SLICE, 0,
> + {DRAM_PLL1_CLK}
> + },
> +};
> +#endif
>
> static int select(enum clk_root_index clock_id)
> {
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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^ permalink raw reply [flat|nested] 39+ messages in thread* [U-Boot] [PATCH 10/20] imx8m: add clk support for i.MX8MM
2019-01-29 22:54 ` Lukasz Majewski
@ 2019-01-30 5:46 ` Peng Fan
2019-01-30 6:46 ` Lukasz Majewski
0 siblings, 1 reply; 39+ messages in thread
From: Peng Fan @ 2019-01-30 5:46 UTC (permalink / raw)
To: u-boot
Hi Lukasz,
> -----Original Message-----
> From: Lukasz Majewski [mailto:lukma at denx.de]
> Sent: 2019年1月30日 6:55
> To: Peng Fan <peng.fan@nxp.com>
> Cc: sbabic at denx.de; Fabio Estevam <fabio.estevam@nxp.com>;
> dl-uboot-imx <uboot-imx@nxp.com>; u-boot at lists.denx.de
> Subject: Re: [U-Boot] [PATCH 10/20] imx8m: add clk support for i.MX8MM
>
> Hi Peng,
>
> > Introduce clk implementation for i.MX8MM, including pll configuration,
> > pll decoding, ccm configuration.
> >
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > ---
> > arch/arm/include/asm/arch-imx8m/clock.h | 2 +
> > arch/arm/include/asm/arch-imx8m/clock_imx8mm.h | 387 +++++++++++
> > arch/arm/mach-imx/imx8m/Makefile | 1 +
> > arch/arm/mach-imx/imx8m/clock_imx8mm.c | 866
> > +++++++++++++++++++++++++
> > arch/arm/mach-imx/imx8m/clock_slice.c | 461
> +++++++++++++ 5
> > files changed, 1717 insertions(+) create mode 100644
> > arch/arm/include/asm/arch-imx8m/clock_imx8mm.h create mode 100644
> > arch/arm/mach-imx/imx8m/clock_imx8mm.c
>
> As fair as I see this approach is not similar to the one from Linux
> kernel:
>
> https://elixir.bootlin.com/linux/v5.0-rc3/source/drivers/clk/imx/clk-imx8mq.
> c
> or simpler:
> https://git.pengutronix.de/cgit/barebox/tree/drivers/clk/imx/clk-imx8mq.c
>
> Also Fabio pointed out in the other mail that we shall stick to Linux
> kernel Common Clock Framework.
>
> IMHO we shall add the simple CCF look alike code (I'm going to post
> imx6q port in a few days).
That will be too complicated for SPL and it will bring more efforts when
we do pre/post silicon bringup.
Regards,
Peng.
>
> >
> > diff --git a/arch/arm/include/asm/arch-imx8m/clock.h
> > b/arch/arm/include/asm/arch-imx8m/clock.h index
> > 7225c760fe..ead4b8d3dc 100644 ---
> > a/arch/arm/include/asm/arch-imx8m/clock.h +++
> > b/arch/arm/include/asm/arch-imx8m/clock.h @@ -7,6 +7,8 @@
> >
> > #ifdef CONFIG_IMX8MQ
> > #include <asm/arch/clock_imx8mq.h>
> > +#elif defined(CONFIG_IMX8MM)
> > +#include <asm/arch/clock_imx8mm.h>
> > #else
> > #error "Error no clock.h"
> > #endif
> > diff --git a/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
> > b/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h new file mode
> 100644
> > index 0000000000..305514a4ec
> > --- /dev/null
> > +++ b/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
> > @@ -0,0 +1,387 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * Copyright 2018-2019 NXP
> > + *
> > + * Peng Fan <peng.fan@nxp.com>
> > + */
> > +
> > +#ifndef _ASM_ARCH_IMX8MM_CLOCK_H
> > +#define _ASM_ARCH_IMX8MM_CLOCK_H
> > +
> > +#define PLL_1443X_RATE(_rate, _m, _p, _s, _k)
> > \
> > + { \
> > + .rate =
> > (_rate), \
> > + .mdiv =
> > (_m), \
> > + .pdiv =
> > (_p), \
> > + .sdiv =
> > (_s), \
> > + .kdiv =
> > (_k), \
> > + }
> > +
> > +#define LOCK_STATUS BIT(31)
> > +#define LOCK_SEL_MASK BIT(29)
> > +#define CLKE_MASK BIT(11)
> > +#define RST_MASK BIT(9)
> > +#define BYPASS_MASK BIT(4)
> > +#define MDIV_SHIFT 12
> > +#define MDIV_MASK GENMASK(21, 12)
> > +#define PDIV_SHIFT 4
> > +#define PDIV_MASK GENMASK(9, 4)
> > +#define SDIV_SHIFT 0
> > +#define SDIV_MASK GENMASK(2, 0)
> > +#define KDIV_SHIFT 0
> > +#define KDIV_MASK GENMASK(15, 0)
> > +
> > +struct imx_int_pll_rate_table {
> > + u32 rate;
> > + int mdiv;
> > + int pdiv;
> > + int sdiv;
> > + int kdiv;
> > +};
> > +
> > +enum pll_clocks {
> > + ANATOP_ARM_PLL,
> > + ANATOP_VPU_PLL,
> > + ANATOP_GPU_PLL,
> > + ANATOP_SYSTEM_PLL1,
> > + ANATOP_SYSTEM_PLL2,
> > + ANATOP_SYSTEM_PLL3,
> > + ANATOP_AUDIO_PLL1,
> > + ANATOP_AUDIO_PLL2,
> > + ANATOP_VIDEO_PLL,
> > + ANATOP_DRAM_PLL,
> > +};
> > +
> > +enum clk_root_index {
> > + ARM_A53_CLK_ROOT = 0,
> > + ARM_M4_CLK_ROOT = 1,
> > + VPU_A53_CLK_ROOT = 2,
> > + GPU3D_CLK_ROOT = 3,
> > + GPU2D_CLK_ROOT = 4,
> > + MAIN_AXI_CLK_ROOT = 16,
> > + ENET_AXI_CLK_ROOT = 17,
> > + NAND_USDHC_BUS_CLK_ROOT = 18,
> > + VPU_BUS_CLK_ROOT = 19,
> > + DISPLAY_AXI_CLK_ROOT = 20,
> > + DISPLAY_APB_CLK_ROOT = 21,
> > + DISPLAY_RTRM_CLK_ROOT = 22,
> > + USB_BUS_CLK_ROOT = 23,
> > + GPU_AXI_CLK_ROOT = 24,
> > + GPU_AHB_CLK_ROOT = 25,
> > + NOC_CLK_ROOT = 26,
> > + NOC_APB_CLK_ROOT = 27,
> > + AHB_CLK_ROOT = 32,
> > + IPG_CLK_ROOT = 33,
> > + AUDIO_AHB_CLK_ROOT = 34,
> > + MIPI_DSI_ESC_RX_CLK_ROOT = 36,
> > + DRAM_SEL_CFG = 48,
> > + CORE_SEL_CFG = 49,
> > + DRAM_ALT_CLK_ROOT = 64,
> > + DRAM_APB_CLK_ROOT = 65,
> > + VPU_G1_CLK_ROOT = 66,
> > + VPU_G2_CLK_ROOT = 67,
> > + DISPLAY_DTRC_CLK_ROOT = 68,
> > + DISPLAY_DC8000_CLK_ROOT = 69,
> > + PCIE_CTRL_CLK_ROOT = 70,
> > + PCIE_PHY_CLK_ROOT = 71,
> > + PCIE_AUX_CLK_ROOT = 72,
> > + DC_PIXEL_CLK_ROOT = 73,
> > + LCDIF_PIXEL_CLK_ROOT = 74,
> > + SAI1_CLK_ROOT = 75,
> > + SAI2_CLK_ROOT = 76,
> > + SAI3_CLK_ROOT = 77,
> > + SAI4_CLK_ROOT = 78,
> > + SAI5_CLK_ROOT = 79,
> > + SAI6_CLK_ROOT = 80,
> > + SPDIF1_CLK_ROOT = 81,
> > + SPDIF2_CLK_ROOT = 82,
> > + ENET_REF_CLK_ROOT = 83,
> > + ENET_TIMER_CLK_ROOT = 84,
> > + ENET_PHY_REF_CLK_ROOT = 85,
> > + NAND_CLK_ROOT = 86,
> > + QSPI_CLK_ROOT = 87,
> > + USDHC1_CLK_ROOT = 88,
> > + USDHC2_CLK_ROOT = 89,
> > + I2C1_CLK_ROOT = 90,
> > + I2C2_CLK_ROOT = 91,
> > + I2C3_CLK_ROOT = 92,
> > + I2C4_CLK_ROOT = 93,
> > + UART1_CLK_ROOT = 94,
> > + UART2_CLK_ROOT = 95,
> > + UART3_CLK_ROOT = 96,
> > + UART4_CLK_ROOT = 97,
> > + USB_CORE_REF_CLK_ROOT = 98,
> > + USB_PHY_REF_CLK_ROOT = 99,
> > + GIC_CLK_ROOT = 100,
> > + ECSPI1_CLK_ROOT = 101,
> > + ECSPI2_CLK_ROOT = 102,
> > + PWM1_CLK_ROOT = 103,
> > + PWM2_CLK_ROOT = 104,
> > + PWM3_CLK_ROOT = 105,
> > + PWM4_CLK_ROOT = 106,
> > + GPT1_CLK_ROOT = 107,
> > + GPT2_CLK_ROOT = 108,
> > + GPT3_CLK_ROOT = 109,
> > + GPT4_CLK_ROOT = 110,
> > + GPT5_CLK_ROOT = 111,
> > + GPT6_CLK_ROOT = 112,
> > + TRACE_CLK_ROOT = 113,
> > + WDOG_CLK_ROOT = 114,
> > + WRCLK_CLK_ROOT = 115,
> > + IPP_DO_CLKO1 = 116,
> > + IPP_DO_CLKO2 = 117,
> > + MIPI_DSI_CORE_CLK_ROOT = 118,
> > + MIPI_DSI_PHY_REF_CLK_ROOT = 119,
> > + MIPI_DSI_DBI_CLK_ROOT = 120,
> > + USDHC3_CLK_ROOT = 121,
> > + MIPI_CSI1_CORE_CLK_ROOT = 122,
> > + MIPI_CSI1_PHY_REF_CLK_ROOT = 123,
> > + MIPI_CSI1_ESC_CLK_ROOT = 124,
> > + MIPI_CSI2_CORE_CLK_ROOT = 125,
> > + MIPI_CSI2_PHY_REF_CLK_ROOT = 126,
> > + MIPI_CSI2_ESC_CLK_ROOT = 127,
> > + PCIE2_CTRL_CLK_ROOT = 128,
> > + PCIE2_PHY_CLK_ROOT = 129,
> > + PCIE2_AUX_CLK_ROOT = 130,
> > + ECSPI3_CLK_ROOT = 131,
> > + PDM_CLK_ROOT = 132,
> > + VPU_H1_CLK_ROOT = 133,
> > + CLK_ROOT_MAX,
> > +};
> > +
> > +enum clk_root_src {
> > + OSC_24M_CLK,
> > + ARM_PLL_CLK,
> > + DRAM_PLL1_CLK,
> > + VIDEO_PLL2_CLK,
> > + VPU_PLL_CLK,
> > + GPU_PLL_CLK,
> > + SYSTEM_PLL1_800M_CLK,
> > + SYSTEM_PLL1_400M_CLK,
> > + SYSTEM_PLL1_266M_CLK,
> > + SYSTEM_PLL1_200M_CLK,
> > + SYSTEM_PLL1_160M_CLK,
> > + SYSTEM_PLL1_133M_CLK,
> > + SYSTEM_PLL1_100M_CLK,
> > + SYSTEM_PLL1_80M_CLK,
> > + SYSTEM_PLL1_40M_CLK,
> > + SYSTEM_PLL2_1000M_CLK,
> > + SYSTEM_PLL2_500M_CLK,
> > + SYSTEM_PLL2_333M_CLK,
> > + SYSTEM_PLL2_250M_CLK,
> > + SYSTEM_PLL2_200M_CLK,
> > + SYSTEM_PLL2_166M_CLK,
> > + SYSTEM_PLL2_125M_CLK,
> > + SYSTEM_PLL2_100M_CLK,
> > + SYSTEM_PLL2_50M_CLK,
> > + SYSTEM_PLL3_CLK,
> > + AUDIO_PLL1_CLK,
> > + AUDIO_PLL2_CLK,
> > + VIDEO_PLL_CLK,
> > + OSC_32K_CLK,
> > + EXT_CLK_1,
> > + EXT_CLK_2,
> > + EXT_CLK_3,
> > + EXT_CLK_4,
> > + OSC_HDMI_CLK
> > +};
> > +
> > +enum clk_ccgr_index {
> > + CCGR_DVFS = 0,
> > + CCGR_ANAMIX = 1,
> > + CCGR_CPU = 2,
> > + CCGR_CSU = 3,
> > + CCGR_DEBUG = 4,
> > + CCGR_DDR1 = 5,
> > + CCGR_ECSPI1 = 7,
> > + CCGR_ECSPI2 = 8,
> > + CCGR_ECSPI3 = 9,
> > + CCGR_ENET1 = 10,
> > + CCGR_GPIO1 = 11,
> > + CCGR_GPIO2 = 12,
> > + CCGR_GPIO3 = 13,
> > + CCGR_GPIO4 = 14,
> > + CCGR_GPIO5 = 15,
> > + CCGR_GPT1 = 16,
> > + CCGR_GPT2 = 17,
> > + CCGR_GPT3 = 18,
> > + CCGR_GPT4 = 19,
> > + CCGR_GPT5 = 20,
> > + CCGR_GPT6 = 21,
> > + CCGR_HS = 22,
> > + CCGR_I2C1 = 23,
> > + CCGR_I2C2 = 24,
> > + CCGR_I2C3 = 25,
> > + CCGR_I2C4 = 26,
> > + CCGR_IOMUX = 27,
> > + CCGR_IOMUX1 = 28,
> > + CCGR_IOMUX2 = 29,
> > + CCGR_IOMUX3 = 30,
> > + CCGR_IOMUX4 = 31,
> > + CCGR_SNVSMIX_IPG_CLK = 32,
> > + CCGR_MU = 33,
> > + CCGR_OCOTP = 34,
> > + CCGR_OCRAM = 35,
> > + CCGR_OCRAM_S = 36,
> > + CCGR_PCIE = 37,
> > + CCGR_PERFMON1 = 38,
> > + CCGR_PERFMON2 = 39,
> > + CCGR_PWM1 = 40,
> > + CCGR_PWM2 = 41,
> > + CCGR_PWM3 = 42,
> > + CCGR_PWM4 = 43,
> > + CCGR_QOS = 44,
> > + CCGR_QOS_DISPMIX = 45,
> > + CCGR_QOS_ETHENET = 46,
> > + CCGR_QSPI = 47,
> > + CCGR_RAWNAND = 48,
> > + CCGR_RDC = 49,
> > + CCGR_ROM = 50,
> > + CCGR_SAI1 = 51,
> > + CCGR_SAI2 = 52,
> > + CCGR_SAI3 = 53,
> > + CCGR_SAI4 = 54,
> > + CCGR_SAI5 = 55,
> > + CCGR_SAI6 = 56,
> > + CCGR_SCTR = 57,
> > + CCGR_SDMA1 = 58,
> > + CCGR_SDMA2 = 59,
> > + CCGR_SEC_DEBUG = 60,
> > + CCGR_SEMA1 = 61,
> > + CCGR_SEMA2 = 62,
> > + CCGR_SIM_DISPLAY = 63,
> > + CCGR_SIM_ENET = 64,
> > + CCGR_SIM_M = 65,
> > + CCGR_SIM_MAIN = 66,
> > + CCGR_SIM_S = 67,
> > + CCGR_SIM_WAKEUP = 68,
> > + CCGR_SIM_HSIO = 69,
> > + CCGR_SIM_VPU = 70,
> > + CCGR_SNVS = 71,
> > + CCGR_TRACE = 72,
> > + CCGR_UART1 = 73,
> > + CCGR_UART2 = 74,
> > + CCGR_UART3 = 75,
> > + CCGR_UART4 = 76,
> > + CCGR_USB_MSCALE_PL301 = 77,
> > + CCGR_GPU3D = 79,
> > + CCGR_USDHC1 = 81,
> > + CCGR_USDHC2 = 82,
> > + CCGR_WDOG1 = 83,
> > + CCGR_WDOG2 = 84,
> > + CCGR_WDOG3 = 85,
> > + CCGR_VPUG1 = 86,
> > + CCGR_GPU_BUS = 87,
> > + CCGR_VPUH1 = 89,
> > + CCGR_VPUG2 = 90,
> > + CCGR_PDM = 91,
> > + CCGR_GIC = 92,
> > + CCGR_DISPMIX = 93,
> > + CCGR_USDHC3 = 94,
> > + CCGR_SDMA3 = 95,
> > + CCGR_XTAL = 96,
> > + CCGR_PLL = 97,
> > + CCGR_TEMP_SENSOR = 98,
> > + CCGR_VPUMIX_BUS = 99,
> > + CCGR_GPU2D = 102,
> > + CCGR_MAX
> > +};
> > +
> > +enum clk_src_index {
> > + CLK_SRC_CKIL_SYNC_REQ = 0,
> > + CLK_SRC_ARM_PLL_EN = 1,
> > + CLK_SRC_GPU_PLL_EN = 2,
> > + CLK_SRC_VPU_PLL_EN = 3,
> > + CLK_SRC_DRAM_PLL_EN = 4,
> > + CLK_SRC_SYSTEM_PLL1_EN = 5,
> > + CLK_SRC_SYSTEM_PLL2_EN = 6,
> > + CLK_SRC_SYSTEM_PLL3_EN = 7,
> > + CLK_SRC_AUDIO_PLL1_EN = 8,
> > + CLK_SRC_AUDIO_PLL2_EN = 9,
> > + CLK_SRC_VIDEO_PLL1_EN = 10,
> > + CLK_SRC_RESERVED = 11,
> > + CLK_SRC_ARM_PLL = 12,
> > + CLK_SRC_GPU_PLL = 13,
> > + CLK_SRC_VPU_PLL = 14,
> > + CLK_SRC_DRAM_PLL = 15,
> > + CLK_SRC_SYSTEM_PLL1_800M = 16,
> > + CLK_SRC_SYSTEM_PLL1_400M = 17,
> > + CLK_SRC_SYSTEM_PLL1_266M = 18,
> > + CLK_SRC_SYSTEM_PLL1_200M = 19,
> > + CLK_SRC_SYSTEM_PLL1_160M = 20,
> > + CLK_SRC_SYSTEM_PLL1_133M = 21,
> > + CLK_SRC_SYSTEM_PLL1_100M = 22,
> > + CLK_SRC_SYSTEM_PLL1_80M = 23,
> > + CLK_SRC_SYSTEM_PLL1_40M = 24,
> > + CLK_SRC_SYSTEM_PLL2_1000M = 25,
> > + CLK_SRC_SYSTEM_PLL2_500M = 26,
> > + CLK_SRC_SYSTEM_PLL2_333M = 27,
> > + CLK_SRC_SYSTEM_PLL2_250M = 28,
> > + CLK_SRC_SYSTEM_PLL2_200M = 29,
> > + CLK_SRC_SYSTEM_PLL2_166M = 30,
> > + CLK_SRC_SYSTEM_PLL2_125M = 31,
> > + CLK_SRC_SYSTEM_PLL2_100M = 32,
> > + CLK_SRC_SYSTEM_PLL2_50M = 33,
> > + CLK_SRC_SYSTEM_PLL3 = 34,
> > + CLK_SRC_AUDIO_PLL1 = 35,
> > + CLK_SRC_AUDIO_PLL2 = 36,
> > + CLK_SRC_VIDEO_PLL1 = 37,
> > +};
> > +
> > +#define INTPLL_LOCK_MASK BIT(31)
> > +#define INTPLL_LOCK_SEL_MASK BIT(29)
> > +#define INTPLL_EXT_BYPASS_MASK BIT(28)
> > +#define INTPLL_DIV20_CLKE_MASK BIT(27)
> > +#define INTPLL_DIV20_CLKE_OVERRIDE_MASK BIT(26)
> > +#define INTPLL_DIV10_CLKE_MASK BIT(25)
> > +#define INTPLL_DIV10_CLKE_OVERRIDE_MASK BIT(24)
> > +#define INTPLL_DIV8_CLKE_MASK BIT(23)
> > +#define INTPLL_DIV8_CLKE_OVERRIDE_MASK BIT(22)
> > +#define INTPLL_DIV6_CLKE_MASK BIT(21)
> > +#define INTPLL_DIV6_CLKE_OVERRIDE_MASK BIT(20)
> > +#define INTPLL_DIV5_CLKE_MASK BIT(19)
> > +#define INTPLL_DIV5_CLKE_OVERRIDE_MASK BIT(18)
> > +#define INTPLL_DIV4_CLKE_MASK BIT(17)
> > +#define INTPLL_DIV4_CLKE_OVERRIDE_MASK BIT(16)
> > +#define INTPLL_DIV3_CLKE_MASK BIT(15)
> > +#define INTPLL_DIV3_CLKE_OVERRIDE_MASK BIT(14)
> > +#define INTPLL_DIV2_CLKE_MASK BIT(13)
> > +#define INTPLL_DIV2_CLKE_OVERRIDE_MASK BIT(12)
> > +#define INTPLL_CLKE_MASK BIT(11)
> > +#define INTPLL_CLKE_OVERRIDE_MASK BIT(10)
> > +#define INTPLL_RST_MASK BIT(9)
> > +#define INTPLL_RST_OVERRIDE_MASK BIT(8)
> > +#define INTPLL_BYPASS_MASK BIT(4)
> > +#define INTPLL_PAD_CLK_SEL_MASK GENMASK(3, 2)
> > +#define INTPLL_REF_CLK_SEL_MASK GENMASK(1, 0)
> > +
> > +#define INTPLL_MAIN_DIV_MASK GENMASK(21, 12)
> > +#define INTPLL_MAIN_DIV_VAL(n) ((n << 12) &
> > GENMASK(21, 12)) +#define INTPLL_MAIN_DIV_SHIFT 12
> > +#define INTPLL_PRE_DIV_MASK GENMASK(9, 4)
> > +#define INTPLL_PRE_DIV_VAL(n) ((n << 4) & GENMASK(9,
> > 4)) +#define INTPLL_PRE_DIV_SHIFT 4
> > +#define INTPLL_POST_DIV_MASK GENMASK(2, 0)
> > +#define INTPLL_POST_DIV_VAL(n) ((n << 0) & GENMASK(2,
> > 0)) +#define INTPLL_POST_DIV_SHIFT 0
> > +
> > +#define INTPLL_LOCK_CON_DLY_MASK GENMASK(5, 4)
> > +#define INTPLL_LOCK_CON_DLY_SHIFT 4
> > +#define INTPLL_LOCK_CON_OUT_MASK GENMASK(3, 2)
> > +#define INTPLL_LOCK_CON_OUT_SHIFT 2
> > +#define INTPLL_LOCK_CON_IN_MASK GENMASK(1, 0)
> > +#define INTPLL_LOCK_CON_IN_SHIFT 0
> > +
> > +#define INTPLL_LRD_EN_MASK BIT(21)
> > +#define INTPLL_FOUT_MASK BIT(20)
> > +#define INTPLL_AFC_SEL_MASK BIT(19)
> > +#define INTPLL_PBIAS_CTRL_MASK BIT(18)
> > +#define INTPLL_PBIAS_CTRL_EN_MASK BIT(17)
> > +#define INTPLL_AFCINIT_SEL_MASK BIT(16)
> > +#define INTPLL_FSEL_MASK BIT(14)
> > +#define INTPLL_FEED_EN_MASK BIT(13)
> > +#define INTPLL_EXTAFC_MASK GENMASK(7, 3)
> > +#define INTPLL_AFC_EN_MASK BIT(2)
> > +#define INTPLL_ICP_MASK GENMASK(1, 0)
> > +
> > +#endif
> > diff --git a/arch/arm/mach-imx/imx8m/Makefile
> > b/arch/arm/mach-imx/imx8m/Makefile index 42a1544c6b..92184f3135
> 100644
> > --- a/arch/arm/mach-imx/imx8m/Makefile
> > +++ b/arch/arm/mach-imx/imx8m/Makefile
> > @@ -5,3 +5,4 @@
> > obj-y += lowlevel_init.o
> > obj-y += clock_slice.o soc.o
> > obj-$(CONFIG_IMX8MQ) += clock_imx8mq.o
> > +obj-$(CONFIG_IMX8MM) += clock_imx8mm.o
> > diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> > b/arch/arm/mach-imx/imx8m/clock_imx8mm.c new file mode 100644
> > index 0000000000..beddd2d68b
> > --- /dev/null
> > +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> > @@ -0,0 +1,866 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright 2018-2019 NXP
> > + *
> > + * Peng Fan <peng.fan@nxp.com>
> > + */
> > +
> > +#include <common.h>
> > +#include <asm/arch/clock.h>
> > +#include <asm/arch/imx-regs.h>
> > +#include <asm/arch/sys_proto.h>
> > +#include <asm/io.h>
> > +#include <div64.h>
> > +#include <errno.h>
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +static struct anamix_pll *ana_pll = (struct anamix_pll
> > *)ANATOP_BASE_ADDR; +
> > +void enable_ocotp_clk(unsigned char enable)
> > +{
> > + clock_enable(CCGR_OCOTP, !!enable);
> > +}
> > +
> > +int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
> > +{
> > + /* 0 - 3 is valid i2c num */
> > + if (i2c_num > 3)
> > + return -EINVAL;
> > +
> > + clock_enable(CCGR_I2C1 + i2c_num, !!enable);
> > +
> > + return 0;
> > +}
> > +
> > +u32 decode_intpll(enum clk_root_src intpll)
> > +{
> > + u32 pll_gnrl_ctl, pll_div_ctl, pll_clke_mask;
> > + u32 main_div, pre_div, post_div, div;
> > + u64 freq;
> > +
> > + switch (intpll) {
> > + case ARM_PLL_CLK:
> > + pll_gnrl_ctl = readl(&ana_pll->arm_pll_gnrl_ctl);
> > + pll_div_ctl = readl(&ana_pll->arm_pll_div_ctl);
> > + break;
> > + case GPU_PLL_CLK:
> > + pll_gnrl_ctl = readl(&ana_pll->gpu_pll_gnrl_ctl);
> > + pll_div_ctl = readl(&ana_pll->gpu_pll_div_ctl);
> > + break;
> > + case VPU_PLL_CLK:
> > + pll_gnrl_ctl = readl(&ana_pll->vpu_pll_gnrl_ctl);
> > + pll_div_ctl = readl(&ana_pll->vpu_pll_div_ctl);
> > + break;
> > + case SYSTEM_PLL1_800M_CLK:
> > + case SYSTEM_PLL1_400M_CLK:
> > + case SYSTEM_PLL1_266M_CLK:
> > + case SYSTEM_PLL1_200M_CLK:
> > + case SYSTEM_PLL1_160M_CLK:
> > + case SYSTEM_PLL1_133M_CLK:
> > + case SYSTEM_PLL1_100M_CLK:
> > + case SYSTEM_PLL1_80M_CLK:
> > + case SYSTEM_PLL1_40M_CLK:
> > + pll_gnrl_ctl = readl(&ana_pll->sys_pll1_gnrl_ctl);
> > + pll_div_ctl = readl(&ana_pll->sys_pll1_div_ctl);
> > + break;
> > + case SYSTEM_PLL2_1000M_CLK:
> > + case SYSTEM_PLL2_500M_CLK:
> > + case SYSTEM_PLL2_333M_CLK:
> > + case SYSTEM_PLL2_250M_CLK:
> > + case SYSTEM_PLL2_200M_CLK:
> > + case SYSTEM_PLL2_166M_CLK:
> > + case SYSTEM_PLL2_125M_CLK:
> > + case SYSTEM_PLL2_100M_CLK:
> > + case SYSTEM_PLL2_50M_CLK:
> > + pll_gnrl_ctl = readl(&ana_pll->sys_pll2_gnrl_ctl);
> > + pll_div_ctl = readl(&ana_pll->sys_pll2_div_ctl);
> > + break;
> > + case SYSTEM_PLL3_CLK:
> > + pll_gnrl_ctl = readl(&ana_pll->sys_pll3_gnrl_ctl);
> > + pll_div_ctl = readl(&ana_pll->sys_pll3_div_ctl);
> > + break;
> > + default:
> > + return -EINVAL;
> > + }
> > +
> > + /* Only support SYS_XTAL 24M, PAD_CLK not take into
> > consideration */
> > + if ((pll_gnrl_ctl & INTPLL_REF_CLK_SEL_MASK) != 0)
> > + return 0;
> > +
> > + if ((pll_gnrl_ctl & INTPLL_RST_MASK) == 0)
> > + return 0;
> > +
> > + /*
> > + * When BYPASS is equal to 1, PLL enters the bypass mode
> > + * regardless of the values of RESETB
> > + */
> > + if (pll_gnrl_ctl & INTPLL_BYPASS_MASK)
> > + return 24000000u;
> > +
> > + if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) {
> > + puts("pll not locked\n");
> > + return 0;
> > + }
> > +
> > + switch (intpll) {
> > + case ARM_PLL_CLK:
> > + case GPU_PLL_CLK:
> > + case VPU_PLL_CLK:
> > + case SYSTEM_PLL3_CLK:
> > + case SYSTEM_PLL1_800M_CLK:
> > + case SYSTEM_PLL2_1000M_CLK:
> > + pll_clke_mask = INTPLL_CLKE_MASK;
> > + div = 1;
> > + break;
> > +
> > + case SYSTEM_PLL1_400M_CLK:
> > + case SYSTEM_PLL2_500M_CLK:
> > + pll_clke_mask = INTPLL_DIV2_CLKE_MASK;
> > + div = 2;
> > + break;
> > +
> > + case SYSTEM_PLL1_266M_CLK:
> > + case SYSTEM_PLL2_333M_CLK:
> > + pll_clke_mask = INTPLL_DIV3_CLKE_MASK;
> > + div = 3;
> > + break;
> > +
> > + case SYSTEM_PLL1_200M_CLK:
> > + case SYSTEM_PLL2_250M_CLK:
> > + pll_clke_mask = INTPLL_DIV4_CLKE_MASK;
> > + div = 4;
> > + break;
> > +
> > + case SYSTEM_PLL1_160M_CLK:
> > + case SYSTEM_PLL2_200M_CLK:
> > + pll_clke_mask = INTPLL_DIV5_CLKE_MASK;
> > + div = 5;
> > + break;
> > +
> > + case SYSTEM_PLL1_133M_CLK:
> > + case SYSTEM_PLL2_166M_CLK:
> > + pll_clke_mask = INTPLL_DIV6_CLKE_MASK;
> > + div = 6;
> > + break;
> > +
> > + case SYSTEM_PLL1_100M_CLK:
> > + case SYSTEM_PLL2_125M_CLK:
> > + pll_clke_mask = INTPLL_DIV8_CLKE_MASK;
> > + div = 8;
> > + break;
> > +
> > + case SYSTEM_PLL1_80M_CLK:
> > + case SYSTEM_PLL2_100M_CLK:
> > + pll_clke_mask = INTPLL_DIV10_CLKE_MASK;
> > + div = 10;
> > + break;
> > +
> > + case SYSTEM_PLL1_40M_CLK:
> > + case SYSTEM_PLL2_50M_CLK:
> > + pll_clke_mask = INTPLL_DIV20_CLKE_MASK;
> > + div = 20;
> > + break;
> > + default:
> > + return -EINVAL;
> > + }
> > +
> > + if ((pll_gnrl_ctl & pll_clke_mask) == 0)
> > + return 0;
> > +
> > + main_div = (pll_div_ctl & INTPLL_MAIN_DIV_MASK) >>
> > + INTPLL_MAIN_DIV_SHIFT;
> > + pre_div = (pll_div_ctl & INTPLL_PRE_DIV_MASK) >>
> > + INTPLL_PRE_DIV_SHIFT;
> > + post_div = (pll_div_ctl & INTPLL_POST_DIV_MASK) >>
> > + INTPLL_POST_DIV_SHIFT;
> > +
> > + /* FFVCO = (m * FFIN) / p, FFOUT = (m * FFIN) / (p * 2^s) */
> > + freq = 24000000ULL * main_div;
> > + return lldiv(freq, pre_div * (1 << post_div) * div);
> > +}
> > +
> > +u32 decode_fracpll(enum clk_root_src frac_pll)
> > +{
> > + u32 pll_gnrl_ctl, pll_fdiv_ctl0, pll_fdiv_ctl1;
> > + u32 main_div, pre_div, post_div, k;
> > +
> > + switch (frac_pll) {
> > + case DRAM_PLL1_CLK:
> > + pll_gnrl_ctl = readl(&ana_pll->dram_pll_gnrl_ctl);
> > + pll_fdiv_ctl0 = readl(&ana_pll->dram_pll_fdiv_ctl0);
> > + pll_fdiv_ctl1 = readl(&ana_pll->dram_pll_fdiv_ctl1);
> > + break;
> > + case AUDIO_PLL1_CLK:
> > + pll_gnrl_ctl = readl(&ana_pll->audio_pll1_gnrl_ctl);
> > + pll_fdiv_ctl0 =
> > readl(&ana_pll->audio_pll1_fdiv_ctl0);
> > + pll_fdiv_ctl1 =
> > readl(&ana_pll->audio_pll1_fdiv_ctl1);
> > + break;
> > + case AUDIO_PLL2_CLK:
> > + pll_gnrl_ctl = readl(&ana_pll->audio_pll2_gnrl_ctl);
> > + pll_fdiv_ctl0 =
> > readl(&ana_pll->audio_pll2_fdiv_ctl0);
> > + pll_fdiv_ctl1 =
> > readl(&ana_pll->audio_pll2_fdiv_ctl1);
> > + break;
> > + case VIDEO_PLL_CLK:
> > + pll_gnrl_ctl = readl(&ana_pll->video_pll1_gnrl_ctl);
> > + pll_fdiv_ctl0 =
> > readl(&ana_pll->video_pll1_fdiv_ctl0);
> > + pll_fdiv_ctl1 =
> > readl(&ana_pll->video_pll1_fdiv_ctl1);
> > + break;
> > + default:
> > + printf("Not supported\n");
> > + return 0;
> > + }
> > +
> > + /* Only support SYS_XTAL 24M, PAD_CLK not take into
> > consideration */
> > + if ((pll_gnrl_ctl & INTPLL_REF_CLK_SEL_MASK) != 0)
> > + return 0;
> > +
> > + if ((pll_gnrl_ctl & INTPLL_RST_MASK) == 0)
> > + return 0;
> > + /*
> > + * When BYPASS is equal to 1, PLL enters the bypass mode
> > + * regardless of the values of RESETB
> > + */
> > + if (pll_gnrl_ctl & INTPLL_BYPASS_MASK)
> > + return 24000000u;
> > +
> > + if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) {
> > + puts("pll not locked\n");
> > + return 0;
> > + }
> > +
> > + if (!(pll_gnrl_ctl & INTPLL_CLKE_MASK))
> > + return 0;
> > +
> > + main_div = (pll_fdiv_ctl0 & INTPLL_MAIN_DIV_MASK) >>
> > + INTPLL_MAIN_DIV_SHIFT;
> > + pre_div = (pll_fdiv_ctl0 & INTPLL_PRE_DIV_MASK) >>
> > + INTPLL_PRE_DIV_SHIFT;
> > + post_div = (pll_fdiv_ctl0 & INTPLL_POST_DIV_MASK) >>
> > + INTPLL_POST_DIV_SHIFT;
> > +
> > + k = pll_fdiv_ctl1 & GENMASK(15, 0);
> > +
> > + /*
> > + * FFOUT = ((m + k / 65536) * FFIN) / (p * 2^s),
> > + * 1 ≤ p ≤ 63, 64 ≤ m ≤ 1023, 0 ≤ s ≤ 6
> > + */
> > + return lldiv((main_div * 65536 + k) * 24000000ULL,
> > + 65536 * pre_div * (1 << post_div));
> > +}
> > +
> > +static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = {
> > + PLL_1443X_RATE(800000000U, 300, 9, 0, 0),
> > + PLL_1443X_RATE(750000000U, 250, 8, 0, 0),
> > + PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
> > + PLL_1443X_RATE(600000000U, 300, 3, 2, 0),
> > + PLL_1443X_RATE(594000000U, 99, 1, 2, 0),
> > + PLL_1443X_RATE(400000000U, 300, 9, 1, 0),
> > + PLL_1443X_RATE(266666667U, 400, 9, 2, 0),
> > + PLL_1443X_RATE(167000000U, 334, 3, 4, 0),
> > + PLL_1443X_RATE(100000000U, 300, 9, 3, 0),
> > +};
> > +
> > +int fracpll_configure(enum pll_clocks pll, u32 freq)
> > +{
> > + int i;
> > + u32 tmp, div_val;
> > + void *pll_base;
> > + struct imx_int_pll_rate_table *rate;
> > +
> > + for (i = 0; i < ARRAY_SIZE(imx8mm_fracpll_tbl); i++) {
> > + if (freq == imx8mm_fracpll_tbl[i].rate)
> > + break;
> > + }
> > +
> > + if (i == ARRAY_SIZE(imx8mm_fracpll_tbl)) {
> > + printf("No matched freq table %u\n", freq);
> > + return -EINVAL;
> > + }
> > +
> > + rate = &imx8mm_fracpll_tbl[i];
> > +
> > + switch (pll) {
> > + case ANATOP_DRAM_PLL:
> > + setbits_le32(GPC_BASE_ADDR + 0xEC, 1 << 7);
> > + setbits_le32(GPC_BASE_ADDR + 0xF8, 1 << 5);
> > + writel(SRC_DDR1_ENABLE_MASK, SRC_BASE_ADDR + 0x1004);
> > +
> > + pll_base = &ana_pll->dram_pll_gnrl_ctl;
> > + break;
> > + case ANATOP_VIDEO_PLL:
> > + pll_base = &ana_pll->video_pll1_gnrl_ctl;
> > + break;
> > + default:
> > + return 0;
> > + }
> > + /* Bypass clock and set lock to pll output lock */
> > + tmp = readl(pll_base);
> > + tmp |= BYPASS_MASK;
> > + writel(tmp, pll_base);
> > +
> > + /* Enable RST */
> > + tmp &= ~RST_MASK;
> > + writel(tmp, pll_base);
> > +
> > + div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv <<
> > PDIV_SHIFT) |
> > + (rate->sdiv << SDIV_SHIFT);
> > + writel(div_val, pll_base + 4);
> > + writel(rate->kdiv << KDIV_SHIFT, pll_base + 8);
> > +
> > + __udelay(100);
> > +
> > + /* Disable RST */
> > + tmp |= RST_MASK;
> > + writel(tmp, pll_base);
> > +
> > + /* Wait Lock*/
> > + while (!(readl(pll_base) & LOCK_STATUS))
> > + ;
> > +
> > + /* Bypass */
> > + tmp &= ~BYPASS_MASK;
> > + writel(tmp, pll_base);
> > +
> > + return 0;
> > +}
> > +
> > +#ifdef CONFIG_SPL_BUILD
> > +void dram_pll_init(ulong pll_val)
> > +{
> > + fracpll_configure(ANATOP_DRAM_PLL, pll_val);
> > +}
> > +
> > +static struct dram_bypass_clk_setting imx8mm_dram_bypass_tbl[] = {
> > + DRAM_BYPASS_ROOT_CONFIG(MHZ(100), 2, CLK_ROOT_PRE_DIV1, 2,
> > + CLK_ROOT_PRE_DIV2),
> > + DRAM_BYPASS_ROOT_CONFIG(MHZ(250), 3, CLK_ROOT_PRE_DIV2, 2,
> > + CLK_ROOT_PRE_DIV2),
> > + DRAM_BYPASS_ROOT_CONFIG(MHZ(400), 1, CLK_ROOT_PRE_DIV2, 3,
> > + CLK_ROOT_PRE_DIV2),
> > +};
> > +
> > +void dram_enable_bypass(ulong clk_val)
> > +{
> > + int i;
> > + struct dram_bypass_clk_setting *config;
> > +
> > + for (i = 0; i < ARRAY_SIZE(imx8mm_dram_bypass_tbl); i++) {
> > + if (clk_val == imx8mm_dram_bypass_tbl[i].clk)
> > + break;
> > + }
> > +
> > + if (i == ARRAY_SIZE(imx8mm_dram_bypass_tbl)) {
> > + printf("No matched freq table %lu\n", clk_val);
> > + return;
> > + }
> > +
> > + config = &imx8mm_dram_bypass_tbl[i];
> > +
> > + clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
> > +
> > CLK_ROOT_SOURCE_SEL(config->alt_root_sel) |
> > + CLK_ROOT_PRE_DIV(config->alt_pre_div));
> > + clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
> > +
> > CLK_ROOT_SOURCE_SEL(config->apb_root_sel) |
> > + CLK_ROOT_PRE_DIV(config->apb_pre_div));
> > + clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
> > + CLK_ROOT_SOURCE_SEL(1));
> > +}
> > +
> > +void dram_disable_bypass(void)
> > +{
> > + clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
> > + CLK_ROOT_SOURCE_SEL(0));
> > + clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
> > + CLK_ROOT_SOURCE_SEL(4) |
> > + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV5));
> > +}
> > +#endif
> > +
> > +int intpll_configure(enum pll_clocks pll, ulong freq)
> > +{
> > + void __iomem *pll_gnrl_ctl, __iomem *pll_div_ctl;
> > + u32 pll_div_ctl_val, pll_clke_masks;
> > +
> > + switch (pll) {
> > + case ANATOP_SYSTEM_PLL1:
> > + pll_gnrl_ctl = &ana_pll->sys_pll1_gnrl_ctl;
> > + pll_div_ctl = &ana_pll->sys_pll1_div_ctl;
> > + pll_clke_masks = INTPLL_DIV20_CLKE_MASK |
> > + INTPLL_DIV10_CLKE_MASK |
> > INTPLL_DIV8_CLKE_MASK |
> > + INTPLL_DIV6_CLKE_MASK |
> > INTPLL_DIV5_CLKE_MASK |
> > + INTPLL_DIV4_CLKE_MASK |
> > INTPLL_DIV3_CLKE_MASK |
> > + INTPLL_DIV2_CLKE_MASK | INTPLL_CLKE_MASK;
> > + break;
> > + case ANATOP_SYSTEM_PLL2:
> > + pll_gnrl_ctl = &ana_pll->sys_pll2_gnrl_ctl;
> > + pll_div_ctl = &ana_pll->sys_pll2_div_ctl;
> > + pll_clke_masks = INTPLL_DIV20_CLKE_MASK |
> > + INTPLL_DIV10_CLKE_MASK |
> > INTPLL_DIV8_CLKE_MASK |
> > + INTPLL_DIV6_CLKE_MASK |
> > INTPLL_DIV5_CLKE_MASK |
> > + INTPLL_DIV4_CLKE_MASK |
> > INTPLL_DIV3_CLKE_MASK |
> > + INTPLL_DIV2_CLKE_MASK | INTPLL_CLKE_MASK;
> > + break;
> > + case ANATOP_SYSTEM_PLL3:
> > + pll_gnrl_ctl = &ana_pll->sys_pll3_gnrl_ctl;
> > + pll_div_ctl = &ana_pll->sys_pll3_div_ctl;
> > + pll_clke_masks = INTPLL_CLKE_MASK;
> > + break;
> > + case ANATOP_ARM_PLL:
> > + pll_gnrl_ctl = &ana_pll->arm_pll_gnrl_ctl;
> > + pll_div_ctl = &ana_pll->arm_pll_div_ctl;
> > + pll_clke_masks = INTPLL_CLKE_MASK;
> > + break;
> > + case ANATOP_GPU_PLL:
> > + pll_gnrl_ctl = &ana_pll->gpu_pll_gnrl_ctl;
> > + pll_div_ctl = &ana_pll->gpu_pll_div_ctl;
> > + pll_clke_masks = INTPLL_CLKE_MASK;
> > + break;
> > + case ANATOP_VPU_PLL:
> > + pll_gnrl_ctl = &ana_pll->vpu_pll_gnrl_ctl;
> > + pll_div_ctl = &ana_pll->vpu_pll_div_ctl;
> > + pll_clke_masks = INTPLL_CLKE_MASK;
> > + break;
> > + default:
> > + return -EINVAL;
> > + };
> > +
> > + switch (freq) {
> > + case MHZ(750):
> > + /* 24 * 0xfa / 2 / 2 ^ 2 */
> > + pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xfa) |
> > + INTPLL_PRE_DIV_VAL(2) |
> > INTPLL_POST_DIV_VAL(2);
> > + break;
> > + case MHZ(800):
> > + /* 24 * 0x190 / 3 / 2 ^ 2 */
> > + pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0x190) |
> > + INTPLL_PRE_DIV_VAL(3) |
> > INTPLL_POST_DIV_VAL(2);
> > + break;
> > + case MHZ(1000):
> > + /* 24 * 0xfa / 3 / 2 ^ 1 */
> > + pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xfa) |
> > + INTPLL_PRE_DIV_VAL(3) |
> > INTPLL_POST_DIV_VAL(1);
> > + break;
> > + case MHZ(1200):
> > + /* 24 * 0xc8 / 2 / 2 ^ 1 */
> > + pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xc8) |
> > + INTPLL_PRE_DIV_VAL(2) |
> > INTPLL_POST_DIV_VAL(1);
> > + break;
> > + case MHZ(2000):
> > + /* 24 * 0xfa / 3 / 2 ^ 0 */
> > + pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xfa) |
> > + INTPLL_PRE_DIV_VAL(3) |
> > INTPLL_POST_DIV_VAL(0);
> > + break;
> > + default:
> > + return -EINVAL;
> > + };
> > + /* Bypass clock and set lock to pll output lock */
> > + setbits_le32(pll_gnrl_ctl, INTPLL_BYPASS_MASK |
> > INTPLL_LOCK_SEL_MASK);
> > + /* Enable reset */
> > + clrbits_le32(pll_gnrl_ctl, INTPLL_RST_MASK);
> > + /* Configure */
> > + writel(pll_div_ctl_val, pll_div_ctl);
> > +
> > + __udelay(100);
> > +
> > + /* Disable reset */
> > + setbits_le32(pll_gnrl_ctl, INTPLL_RST_MASK);
> > + /* Wait Lock */
> > + while (!(readl(pll_gnrl_ctl) & INTPLL_LOCK_MASK))
> > + ;
> > + /* Clear bypass */
> > + clrbits_le32(pll_gnrl_ctl, INTPLL_BYPASS_MASK);
> > + setbits_le32(pll_gnrl_ctl, pll_clke_masks);
> > +
> > + return 0;
> > +}
> > +
> > +void init_uart_clk(u32 index)
> > +{
> > + /*
> > + * set uart clock root
> > + * 24M OSC
> > + */
> > + switch (index) {
> > + case 0:
> > + clock_enable(CCGR_UART1, 0);
> > + clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON |
> > + CLK_ROOT_SOURCE_SEL(0));
> > + clock_enable(CCGR_UART1, 1);
> > + return;
> > + case 1:
> > + clock_enable(CCGR_UART2, 0);
> > + clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON |
> > + CLK_ROOT_SOURCE_SEL(0));
> > + clock_enable(CCGR_UART2, 1);
> > + return;
> > + case 2:
> > + clock_enable(CCGR_UART3, 0);
> > + clock_set_target_val(UART3_CLK_ROOT, CLK_ROOT_ON |
> > + CLK_ROOT_SOURCE_SEL(0));
> > + clock_enable(CCGR_UART3, 1);
> > + return;
> > + case 3:
> > + clock_enable(CCGR_UART4, 0);
> > + clock_set_target_val(UART4_CLK_ROOT, CLK_ROOT_ON |
> > + CLK_ROOT_SOURCE_SEL(0));
> > + clock_enable(CCGR_UART4, 1);
> > + return;
> > + default:
> > + printf("Invalid uart index\n");
> > + return;
> > + }
> > +}
> > +
> > +void init_wdog_clk(void)
> > +{
> > + clock_enable(CCGR_WDOG1, 0);
> > + clock_enable(CCGR_WDOG2, 0);
> > + clock_enable(CCGR_WDOG3, 0);
> > + clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
> > + CLK_ROOT_SOURCE_SEL(0));
> > + clock_enable(CCGR_WDOG1, 1);
> > + clock_enable(CCGR_WDOG2, 1);
> > + clock_enable(CCGR_WDOG3, 1);
> > +}
> > +
> > +void init_clk_usdhc(u32 index)
> > +{
> > + /*
> > + * set usdhc clock root
> > + * sys pll1 400M
> > + */
> > + switch (index) {
> > + case 0:
> > + clock_enable(CCGR_USDHC1, 0);
> > + clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON |
> > + CLK_ROOT_SOURCE_SEL(1) |
> > +
> > CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
> > + clock_enable(CCGR_USDHC1, 1);
> > + return;
> > + case 1:
> > + clock_enable(CCGR_USDHC2, 0);
> > + clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON |
> > + CLK_ROOT_SOURCE_SEL(1) |
> > +
> > CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
> > + clock_enable(CCGR_USDHC2, 1);
> > + return;
> > + case 2:
> > + clock_enable(CCGR_USDHC3, 0);
> > + clock_set_target_val(USDHC3_CLK_ROOT, CLK_ROOT_ON |
> > + CLK_ROOT_SOURCE_SEL(1) |
> > +
> > CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
> > + clock_enable(CCGR_USDHC3, 1);
> > + return;
> > + default:
> > + printf("Invalid usdhc index\n");
> > + return;
> > + }
> > +}
> > +
> > +int clock_init(void)
> > +{
> > + u32 val_cfg0;
> > +
> > + /* Configure ARM at 1GHz */
> > + clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
> > + CLK_ROOT_SOURCE_SEL(0));
> > +
> > + intpll_configure(ANATOP_ARM_PLL, MHZ(1200));
> > +
> > + clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
> > + CLK_ROOT_SOURCE_SEL(1) |
> > + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1));
> > +
> > + /*
> > + * According to ANAMIX SPEC
> > + * sys pll1 fixed at 800MHz
> > + * sys pll2 fixed at 1GHz
> > + * Here we only enable the outputs.
> > + */
> > + val_cfg0 = readl(&ana_pll->sys_pll1_gnrl_ctl);
> > + val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK |
> > + INTPLL_DIV3_CLKE_MASK | INTPLL_DIV4_CLKE_MASK |
> > + INTPLL_DIV5_CLKE_MASK | INTPLL_DIV6_CLKE_MASK |
> > + INTPLL_DIV8_CLKE_MASK | INTPLL_DIV10_CLKE_MASK |
> > + INTPLL_DIV20_CLKE_MASK;
> > + writel(val_cfg0, &ana_pll->sys_pll1_gnrl_ctl);
> > +
> > + val_cfg0 = readl(&ana_pll->sys_pll2_gnrl_ctl);
> > + val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK |
> > + INTPLL_DIV3_CLKE_MASK | INTPLL_DIV4_CLKE_MASK |
> > + INTPLL_DIV5_CLKE_MASK | INTPLL_DIV6_CLKE_MASK |
> > + INTPLL_DIV8_CLKE_MASK | INTPLL_DIV10_CLKE_MASK |
> > + INTPLL_DIV20_CLKE_MASK;
> > + writel(val_cfg0, &ana_pll->sys_pll2_gnrl_ctl);
> > +
> > + intpll_configure(ANATOP_SYSTEM_PLL3, MHZ(750));
> > + clock_set_target_val(NOC_CLK_ROOT, CLK_ROOT_ON |
> > + CLK_ROOT_SOURCE_SEL(2));
> > +
> > + /* config GIC to sys_pll2_100m */
> > + clock_enable(CCGR_GIC, 0);
> > + clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON |
> > + CLK_ROOT_SOURCE_SEL(3));
> > + clock_enable(CCGR_GIC, 1);
> > +
> > + clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON |
> > + CLK_ROOT_SOURCE_SEL(1));
> > +
> > + clock_enable(CCGR_DDR1, 0);
> > + clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
> > + CLK_ROOT_SOURCE_SEL(1));
> > + clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
> > + CLK_ROOT_SOURCE_SEL(1));
> > + clock_enable(CCGR_DDR1, 1);
> > +
> > + init_wdog_clk();
> > +
> > + clock_enable(CCGR_TEMP_SENSOR, 1);
> > +
> > + clock_enable(CCGR_SEC_DEBUG, 1);
> > +
> > + return 0;
> > +};
> > +
> > +int set_clk_qspi(void)
> > +{
> > + /*
> > + * set qspi root
> > + * sys pll1 100M
> > + */
> > + clock_enable(CCGR_QSPI, 0);
> > + clock_set_target_val(QSPI_CLK_ROOT, CLK_ROOT_ON |
> > + CLK_ROOT_SOURCE_SEL(7));
> > + clock_enable(CCGR_QSPI, 1);
> > +
> > + return 0;
> > +}
> > +
> > +#ifdef CONFIG_FEC_MXC
> > +int set_clk_enet(enum enet_freq type)
> > +{
> > + u32 target;
> > + u32 enet1_ref;
> > +
> > + /* disable the clock first */
> > + clock_enable(CCGR_ENET1, 0);
> > + clock_enable(CCGR_SIM_ENET, 0);
> > +
> > + switch (type) {
> > + case ENET_125MHZ:
> > + enet1_ref =
> > ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
> > + break;
> > + case ENET_50MHZ:
> > + enet1_ref =
> > ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
> > + break;
> > + case ENET_25MHZ:
> > + enet1_ref =
> > ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
> > + break;
> > + default:
> > + return -EINVAL;
> > + }
> > +
> > + /* set enet axi clock 266Mhz */
> > + target = CLK_ROOT_ON |
> ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
> > + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
> > + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
> > + clock_set_target_val(ENET_AXI_CLK_ROOT, target);
> > +
> > + target = CLK_ROOT_ON | enet1_ref |
> > + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
> > + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
> > + clock_set_target_val(ENET_REF_CLK_ROOT, target);
> > +
> > + target = CLK_ROOT_ON |
> > ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
> > + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
> > + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
> > + clock_set_target_val(ENET_TIMER_CLK_ROOT, target);
> > +
> > +#ifdef CONFIG_FEC_MXC_25M_REF_CLK
> > + target = CLK_ROOT_ON |
> > + ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK |
> > + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
> > + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
> > + clock_set_target_val(ENET_PHY_REF_CLK_ROOT, target);
> > +#endif
> > + /* enable clock */
> > + clock_enable(CCGR_SIM_ENET, 1);
> > + clock_enable(CCGR_ENET1, 1);
> > +
> > + return 0;
> > +}
> > +#endif
> > +
> > +u32 get_root_src_clk(enum clk_root_src root_src)
> > +{
> > + switch (root_src) {
> > + case OSC_24M_CLK:
> > + return 24000000u;
> > + case OSC_HDMI_CLK:
> > + return 26000000u;
> > + case OSC_32K_CLK:
> > + return 32000u;
> > + case ARM_PLL_CLK:
> > + case GPU_PLL_CLK:
> > + case VPU_PLL_CLK:
> > + case SYSTEM_PLL1_800M_CLK:
> > + case SYSTEM_PLL1_400M_CLK:
> > + case SYSTEM_PLL1_266M_CLK:
> > + case SYSTEM_PLL1_200M_CLK:
> > + case SYSTEM_PLL1_160M_CLK:
> > + case SYSTEM_PLL1_133M_CLK:
> > + case SYSTEM_PLL1_100M_CLK:
> > + case SYSTEM_PLL1_80M_CLK:
> > + case SYSTEM_PLL1_40M_CLK:
> > + case SYSTEM_PLL2_1000M_CLK:
> > + case SYSTEM_PLL2_500M_CLK:
> > + case SYSTEM_PLL2_333M_CLK:
> > + case SYSTEM_PLL2_250M_CLK:
> > + case SYSTEM_PLL2_200M_CLK:
> > + case SYSTEM_PLL2_166M_CLK:
> > + case SYSTEM_PLL2_125M_CLK:
> > + case SYSTEM_PLL2_100M_CLK:
> > + case SYSTEM_PLL2_50M_CLK:
> > + case SYSTEM_PLL3_CLK:
> > + return decode_intpll(root_src);
> > + case DRAM_PLL1_CLK:
> > + case AUDIO_PLL1_CLK:
> > + case AUDIO_PLL2_CLK:
> > + case VIDEO_PLL_CLK:
> > + return decode_fracpll(root_src);
> > + default:
> > + return 0;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +u32 get_root_clk(enum clk_root_index clock_id)
> > +{
> > + enum clk_root_src root_src;
> > + u32 post_podf, pre_podf, root_src_clk;
> > +
> > + if (clock_root_enabled(clock_id) <= 0)
> > + return 0;
> > +
> > + if (clock_get_prediv(clock_id, &pre_podf) < 0)
> > + return 0;
> > +
> > + if (clock_get_postdiv(clock_id, &post_podf) < 0)
> > + return 0;
> > +
> > + if (clock_get_src(clock_id, &root_src) < 0)
> > + return 0;
> > +
> > + root_src_clk = get_root_src_clk(root_src);
> > +
> > + return root_src_clk / (post_podf + 1) / (pre_podf + 1);
> > +}
> > +
> > +u32 mxc_get_clock(enum mxc_clock clk)
> > +{
> > + u32 val;
> > +
> > + switch (clk) {
> > + case MXC_ARM_CLK:
> > + return get_root_clk(ARM_A53_CLK_ROOT);
> > + case MXC_IPG_CLK:
> > + clock_get_target_val(IPG_CLK_ROOT, &val);
> > + val = val & 0x3;
> > + return get_root_clk(AHB_CLK_ROOT) / 2 / (val + 1);
> > + case MXC_CSPI_CLK:
> > + return get_root_clk(ECSPI1_CLK_ROOT);
> > + case MXC_ESDHC_CLK:
> > + return get_root_clk(USDHC1_CLK_ROOT);
> > + case MXC_ESDHC2_CLK:
> > + return get_root_clk(USDHC2_CLK_ROOT);
> > + case MXC_ESDHC3_CLK:
> > + return get_root_clk(USDHC3_CLK_ROOT);
> > + case MXC_I2C_CLK:
> > + return get_root_clk(I2C1_CLK_ROOT);
> > + case MXC_UART_CLK:
> > + return get_root_clk(UART1_CLK_ROOT);
> > + case MXC_QSPI_CLK:
> > + return get_root_clk(QSPI_CLK_ROOT);
> > + default:
> > + printf("Unsupported mxc_clock %d\n", clk);
> > + break;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +u32 imx_get_uartclk(void)
> > +{
> > + return mxc_get_clock(MXC_UART_CLK);
> > +}
> > +
> > +u32 imx_get_fecclk(void)
> > +{
> > + return get_root_clk(ENET_AXI_CLK_ROOT);
> > +}
> > +
> > +/*
> > + * Dump some clockes.
> > + */
> > +#ifndef CONFIG_SPL_BUILD
> > +int do_mscale_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
> > + char * const argv[])
> > +{
> > + u32 freq;
> > +
> > + freq = decode_intpll(ARM_PLL_CLK);
> > + printf("ARM_PLL %8d MHz\n", freq / 1000000);
> > + freq = decode_intpll(SYSTEM_PLL1_800M_CLK);
> > + printf("SYS_PLL1_800 %8d MHz\n", freq / 1000000);
> > + freq = decode_intpll(SYSTEM_PLL1_400M_CLK);
> > + printf("SYS_PLL1_400 %8d MHz\n", freq / 1000000);
> > + freq = decode_intpll(SYSTEM_PLL1_266M_CLK);
> > + printf("SYS_PLL1_266 %8d MHz\n", freq / 1000000);
> > + freq = decode_intpll(SYSTEM_PLL1_160M_CLK);
> > + printf("SYS_PLL1_160 %8d MHz\n", freq / 1000000);
> > + freq = decode_intpll(SYSTEM_PLL1_133M_CLK);
> > + printf("SYS_PLL1_133 %8d MHz\n", freq / 1000000);
> > + freq = decode_intpll(SYSTEM_PLL1_100M_CLK);
> > + printf("SYS_PLL1_100 %8d MHz\n", freq / 1000000);
> > + freq = decode_intpll(SYSTEM_PLL1_80M_CLK);
> > + printf("SYS_PLL1_80 %8d MHz\n", freq / 1000000);
> > + freq = decode_intpll(SYSTEM_PLL1_40M_CLK);
> > + printf("SYS_PLL1_40 %8d MHz\n", freq / 1000000);
> > + freq = decode_intpll(SYSTEM_PLL2_1000M_CLK);
> > + printf("SYS_PLL2_1000 %8d MHz\n", freq / 1000000);
> > + freq = decode_intpll(SYSTEM_PLL2_500M_CLK);
> > + printf("SYS_PLL2_500 %8d MHz\n", freq / 1000000);
> > + freq = decode_intpll(SYSTEM_PLL2_333M_CLK);
> > + printf("SYS_PLL2_333 %8d MHz\n", freq / 1000000);
> > + freq = decode_intpll(SYSTEM_PLL2_250M_CLK);
> > + printf("SYS_PLL2_250 %8d MHz\n", freq / 1000000);
> > + freq = decode_intpll(SYSTEM_PLL2_200M_CLK);
> > + printf("SYS_PLL2_200 %8d MHz\n", freq / 1000000);
> > + freq = decode_intpll(SYSTEM_PLL2_166M_CLK);
> > + printf("SYS_PLL2_166 %8d MHz\n", freq / 1000000);
> > + freq = decode_intpll(SYSTEM_PLL2_125M_CLK);
> > + printf("SYS_PLL2_125 %8d MHz\n", freq / 1000000);
> > + freq = decode_intpll(SYSTEM_PLL2_100M_CLK);
> > + printf("SYS_PLL2_100 %8d MHz\n", freq / 1000000);
> > + freq = decode_intpll(SYSTEM_PLL2_50M_CLK);
> > + printf("SYS_PLL2_50 %8d MHz\n", freq / 1000000);
> > + freq = decode_intpll(SYSTEM_PLL3_CLK);
> > + printf("SYS_PLL3 %8d MHz\n", freq / 1000000);
> > + freq = mxc_get_clock(MXC_UART_CLK);
> > + printf("UART1 %8d MHz\n", freq / 1000000);
> > + freq = mxc_get_clock(MXC_ESDHC_CLK);
> > + printf("USDHC1 %8d MHz\n", freq / 1000000);
> > + freq = mxc_get_clock(MXC_QSPI_CLK);
> > + printf("QSPI %8d MHz\n", freq / 1000000);
> > +
> > + return 0;
> > +}
> > +
> > +U_BOOT_CMD(
> > + clocks, CONFIG_SYS_MAXARGS, 1, do_mscale_showclocks,
> > + "display clocks",
> > + ""
> > +);
> > +#endif
> > diff --git a/arch/arm/mach-imx/imx8m/clock_slice.c
> > b/arch/arm/mach-imx/imx8m/clock_slice.c index 1a67c626f1..dc2a018e00
> > 100644 --- a/arch/arm/mach-imx/imx8m/clock_slice.c
> > +++ b/arch/arm/mach-imx/imx8m/clock_slice.c
> > @@ -13,6 +13,7 @@
> >
> > static struct ccm_reg *ccm_reg = (struct ccm_reg *)CCM_BASE_ADDR;
> >
> > +#ifdef CONFIG_IMX8MQ
> > static struct clk_root_map root_array[] = {
> > {ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0,
> > {OSC_25M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
> > @@ -474,6 +475,466 @@ static struct clk_root_map root_array[] = {
> > {DRAM_PLL1_CLK}
> > },
> > };
> > +#elif defined(CONFIG_IMX8MM)
> > +static struct clk_root_map root_array[] = {
> > + {ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0,
> > + {OSC_24M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
> > + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
> > + SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL3_CLK}
> > + },
> > + {ARM_M4_CLK_ROOT, CORE_CLOCK_SLICE, 1,
> > + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_250M_CLK,
> > + SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
> > + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
> > + },
> > + {VPU_A53_CLK_ROOT, CORE_CLOCK_SLICE, 2,
> > + {OSC_24M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
> > + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
> > + SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, VPU_PLL_CLK}
> > + },
> > + {GPU3D_CLK_ROOT, CORE_CLOCK_SLICE, 3,
> > + {OSC_24M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
> > + SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
> > + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
> > + },
> > + {GPU2D_CLK_ROOT, CORE_CLOCK_SLICE, 4,
> > + {OSC_24M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
> > + SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
> > + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
> > + },
> > + {MAIN_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 0,
> > + {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL1_800M_CLK,
> > + SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_1000M_CLK,
> > + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL1_100M_CLK}
> > + },
> > + {ENET_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 1,
> > + {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
> > + SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
> > + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
> > + },
> > + {NAND_USDHC_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 2,
> > + {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
> > + SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK,
> > + SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL1_CLK}
> > + },
> > + {VPU_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 3,
> > + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, VPU_PLL_CLK,
> > + AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
> > + SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_100M_CLK}
> > + },
> > + {DISPLAY_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 4,
> > + {OSC_24M_CLK, SYSTEM_PLL2_1000M_CLK,
> SYSTEM_PLL1_800M_CLK,
> > + SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK, AUDIO_PLL2_CLK,
> > + EXT_CLK_1, EXT_CLK_4}
> > + },
> > + {DISPLAY_APB_CLK_ROOT, BUS_CLOCK_SLICE, 5,
> > + {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK,
> > + SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK, AUDIO_PLL2_CLK,
> > + EXT_CLK_1, EXT_CLK_3}
> > + },
> > + {DISPLAY_RTRM_CLK_ROOT, BUS_CLOCK_SLICE, 6,
> > + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_200M_CLK,
> > + SYSTEM_PLL2_1000M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
> > + EXT_CLK_2, EXT_CLK_3}
> > + },
> > + {USB_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 7,
> > + {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
> > + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
> > + EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
> > + },
> > + {GPU_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 8,
> > + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
> > + SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
> > + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
> > + },
> > + {GPU_AHB_CLK_ROOT, BUS_CLOCK_SLICE, 9,
> > + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
> > + SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
> > + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
> > + },
> > + {NOC_CLK_ROOT, BUS_CLOCK_SLICE, 10,
> > + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK,
> > + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK,
> > + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
> > + },
> > + {NOC_APB_CLK_ROOT, BUS_CLOCK_SLICE, 11,
> > + {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL3_CLK,
> > + SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_200M_CLK,
> > + SYSTEM_PLL1_800M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
> > + },
> > + {AHB_CLK_ROOT, AHB_CLOCK_SLICE, 0,
> > + {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_800M_CLK,
> > + SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_125M_CLK,
> > + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
> > + },
> > + {AUDIO_AHB_CLK_ROOT, AHB_CLOCK_SLICE, 1,
> > + {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
> > + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_166M_CLK,
> > + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
> > + },
> > + {MIPI_DSI_ESC_RX_CLK_ROOT, AHB_CLOCK_SLICE, 2,
> > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
> > + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> > + SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
> > + },
> > + {DRAM_ALT_CLK_ROOT, IP_CLOCK_SLICE, 0,
> > + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL1_100M_CLK,
> > + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_1000M_CLK,
> > + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL1_266M_CLK}
> > + },
> > + {DRAM_APB_CLK_ROOT, IP_CLOCK_SLICE, 1,
> > + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
> > + SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
> > + SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
> > + },
> > + {VPU_G1_CLK_ROOT, IP_CLOCK_SLICE, 2,
> > + {OSC_24M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
> > + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_100M_CLK,
> > + SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
> > + },
> > + {VPU_G2_CLK_ROOT, IP_CLOCK_SLICE, 3,
> > + {OSC_24M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
> > + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_100M_CLK,
> > + SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
> > + },
> > + {DISPLAY_DTRC_CLK_ROOT, IP_CLOCK_SLICE, 4,
> > + {OSC_24M_CLK, VIDEO_PLL2_CLK, SYSTEM_PLL1_800M_CLK,
> > + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_160M_CLK,
> > + VIDEO_PLL_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK}
> > + },
> > + {DISPLAY_DC8000_CLK_ROOT, IP_CLOCK_SLICE, 5,
> > + {OSC_24M_CLK, VIDEO_PLL2_CLK, SYSTEM_PLL1_800M_CLK,
> > + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_160M_CLK,
> > + VIDEO_PLL_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK}
> > + },
> > + {PCIE_CTRL_CLK_ROOT, IP_CLOCK_SLICE, 6,
> > + {OSC_24M_CLK, SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
> > + SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
> > + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_333M_CLK,
> > SYSTEM_PLL3_CLK}
> > + },
> > + {PCIE_PHY_CLK_ROOT, IP_CLOCK_SLICE, 7,
> > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_500M_CLK,
> > + EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
> > + SYSTEM_PLL1_400M_CLK}
> > + },
> > + {PCIE_AUX_CLK_ROOT, IP_CLOCK_SLICE, 8,
> > + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_50M_CLK,
> > + SYSTEM_PLL3_CLK, SYSTEM_PLL2_100M_CLK,
> SYSTEM_PLL1_80M_CLK,
> > + SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_200M_CLK}
> > + },
> > + {DC_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 9,
> > + {OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
> > + AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
> > + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
> > + },
> > + {LCDIF_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 10,
> > + {OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
> > + AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
> > + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
> > + },
> > + {SAI1_CLK_ROOT, IP_CLOCK_SLICE, 11,
> > + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
> > + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
> > + OSC_HDMI_CLK, EXT_CLK_1, EXT_CLK_2}
> > + },
> > + {SAI2_CLK_ROOT, IP_CLOCK_SLICE, 12,
> > + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
> > + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
> > + OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
> > + },
> > + {SAI3_CLK_ROOT, IP_CLOCK_SLICE, 13,
> > + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
> > + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
> > + OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
> > + },
> > + {SAI4_CLK_ROOT, IP_CLOCK_SLICE, 14,
> > + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
> > + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
> > + OSC_HDMI_CLK, EXT_CLK_1, EXT_CLK_2}
> > + },
> > + {SAI5_CLK_ROOT, IP_CLOCK_SLICE, 15,
> > + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
> > + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
> > + OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
> > + },
> > + {SAI6_CLK_ROOT, IP_CLOCK_SLICE, 16,
> > + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
> > + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
> > + OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
> > + },
> > + {SPDIF1_CLK_ROOT, IP_CLOCK_SLICE, 17,
> > + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
> > + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
> > + OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
> > + },
> > + {SPDIF2_CLK_ROOT, IP_CLOCK_SLICE, 18,
> > + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
> > + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
> > + OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
> > + },
> > + {ENET_REF_CLK_ROOT, IP_CLOCK_SLICE, 19,
> > + {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_50M_CLK,
> > + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
> > + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, EXT_CLK_4}
> > + },
> > + {ENET_TIMER_CLK_ROOT, IP_CLOCK_SLICE, 20,
> > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK,
> > + EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
> > + VIDEO_PLL_CLK}
> > + },
> > + {ENET_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 21,
> > + {OSC_24M_CLK, SYSTEM_PLL2_50M_CLK, SYSTEM_PLL2_125M_CLK,
> > + SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_500M_CLK,
> > + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
> > + },
> > + {NAND_CLK_ROOT, IP_CLOCK_SLICE, 22,
> > + {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, AUDIO_PLL1_CLK,
> > + SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK,
> > + SYSTEM_PLL2_250M_CLK, VIDEO_PLL_CLK}
> > + },
> > + {QSPI_CLK_ROOT, IP_CLOCK_SLICE, 23,
> > + {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_333M_CLK,
> > + SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK,
> > + SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK,
> > SYSTEM_PLL1_100M_CLK}
> > + },
> > + {USDHC1_CLK_ROOT, IP_CLOCK_SLICE, 24,
> > + {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
> > + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
> > + SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK,
> SYSTEM_PLL1_100M_CLK}
> > + },
> > + {USDHC2_CLK_ROOT, IP_CLOCK_SLICE, 25,
> > + {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
> > + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
> > + SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK,
> SYSTEM_PLL1_100M_CLK}
> > + },
> > + {I2C1_CLK_ROOT, IP_CLOCK_SLICE, 26,
> > + {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
> > + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
> > + AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
> > + },
> > + {I2C2_CLK_ROOT, IP_CLOCK_SLICE, 27,
> > + {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
> > + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
> > + AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
> > + },
> > + {I2C3_CLK_ROOT, IP_CLOCK_SLICE, 28,
> > + {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
> > + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
> > + AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
> > + },
> > + {I2C4_CLK_ROOT, IP_CLOCK_SLICE, 29,
> > + {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
> > + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
> > + AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
> > + },
> > + {UART1_CLK_ROOT, IP_CLOCK_SLICE, 30,
> > + {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
> > + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
> > + EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
> > + },
> > + {UART2_CLK_ROOT, IP_CLOCK_SLICE, 31,
> > + {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
> > + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
> > + EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
> > + },
> > + {UART3_CLK_ROOT, IP_CLOCK_SLICE, 32,
> > + {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
> > + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
> > + EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
> > + },
> > + {UART4_CLK_ROOT, IP_CLOCK_SLICE, 33,
> > + {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
> > + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
> > + EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
> > + },
> > + {USB_CORE_REF_CLK_ROOT, IP_CLOCK_SLICE, 34,
> > + {OSC_24M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
> > + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
> > + EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
> > + },
> > + {USB_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 35,
> > + {OSC_24M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
> > + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
> > + EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
> > + },
> > + {GIC_CLK_ROOT, IP_CLOCK_SLICE, 36,
> > + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
> > + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_800M_CLK,
> > + EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
> > + },
> > + {ECSPI1_CLK_ROOT, IP_CLOCK_SLICE, 37,
> > + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
> > + SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
> > + SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
> > + },
> > + {ECSPI2_CLK_ROOT, IP_CLOCK_SLICE, 38,
> > + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
> > + SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
> > + SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
> > + },
> > + {PWM1_CLK_ROOT, IP_CLOCK_SLICE, 39,
> > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
> > + SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
> > + SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
> > + },
> > + {PWM2_CLK_ROOT, IP_CLOCK_SLICE, 40,
> > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
> > + SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
> > + SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
> > + },
> > + {PWM3_CLK_ROOT, IP_CLOCK_SLICE, 41,
> > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
> > + SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2,
> > + SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
> > + },
> > + {PWM4_CLK_ROOT, IP_CLOCK_SLICE, 42,
> > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
> > + SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2,
> > + SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
> > + },
> > + {GPT1_CLK_ROOT, IP_CLOCK_SLICE, 43,
> > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
> > + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
> > + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
> > + },
> > + {GPT2_CLK_ROOT, IP_CLOCK_SLICE, 44,
> > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
> > + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
> > + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
> > + },
> > + {GPT3_CLK_ROOT, IP_CLOCK_SLICE, 45,
> > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
> > + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
> > + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
> > + },
> > + {GPT4_CLK_ROOT, IP_CLOCK_SLICE, 46,
> > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
> > + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
> > + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
> > + },
> > + {GPT5_CLK_ROOT, IP_CLOCK_SLICE, 47,
> > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
> > + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
> > + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
> > + },
> > + {GPT6_CLK_ROOT, IP_CLOCK_SLICE, 48,
> > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
> > + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
> > + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
> > + },
> > + {TRACE_CLK_ROOT, IP_CLOCK_SLICE, 49,
> > + {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
> > + VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
> > + SYSTEM_PLL3_CLK, EXT_CLK_1, EXT_CLK_3}
> > + },
> > + {WDOG_CLK_ROOT, IP_CLOCK_SLICE, 50,
> > + {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
> > + VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
> > + SYSTEM_PLL3_CLK, SYSTEM_PLL1_80M_CLK,
> SYSTEM_PLL2_166M_CLK}
> > + },
> > + {WRCLK_CLK_ROOT, IP_CLOCK_SLICE, 51,
> > + {OSC_24M_CLK, SYSTEM_PLL1_40M_CLK, VPU_PLL_CLK,
> > + SYSTEM_PLL3_CLK, SYSTEM_PLL2_200M_CLK,
> > + SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_500M_CLK,
> > SYSTEM_PLL1_100M_CLK}
> > + },
> > + {IPP_DO_CLKO1, IP_CLOCK_SLICE, 52,
> > + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, OSC_HDMI_CLK,
> > + SYSTEM_PLL1_200M_CLK, AUDIO_PLL2_CLK,
> > + SYSTEM_PLL2_500M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_80M_CLK}
> > + },
> > + {IPP_DO_CLKO2, IP_CLOCK_SLICE, 53,
> > + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_400M_CLK,
> > + SYSTEM_PLL2_166M_CLK, SYSTEM_PLL3_CLK,
> > + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, OSC_32K_CLK}
> > + },
> > + {MIPI_DSI_CORE_CLK_ROOT, IP_CLOCK_SLICE, 54,
> > + {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
> > + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> > + SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
> > + },
> > + {MIPI_DSI_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 55,
> > + {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_100M_CLK,
> > + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> > + EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
> > + },
> > + {MIPI_DSI_DBI_CLK_ROOT, IP_CLOCK_SLICE, 56,
> > + {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_100M_CLK,
> > + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> > + SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
> > + },
> > + {USDHC3_CLK_ROOT, IP_CLOCK_SLICE, 57,
> > + {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
> > + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
> > + SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK,
> SYSTEM_PLL1_100M_CLK}
> > + },
> > + {MIPI_CSI1_CORE_CLK_ROOT, IP_CLOCK_SLICE, 58,
> > + {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
> > + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> > + SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
> > + },
> > + {MIPI_CSI1_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 59,
> > + {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK,
> > + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> > + EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
> > + },
> > + {MIPI_CSI1_ESC_CLK_ROOT, IP_CLOCK_SLICE, 60,
> > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
> > + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> > + SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
> > + },
> > + {MIPI_CSI2_CORE_CLK_ROOT, IP_CLOCK_SLICE, 61,
> > + {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
> > + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> > + SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
> > + },
> > + {MIPI_CSI2_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 62,
> > + {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK,
> > + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> > + EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
> > + },
> > + {MIPI_CSI2_ESC_CLK_ROOT, IP_CLOCK_SLICE, 63,
> > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
> > + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> > + SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
> > + },
> > + {PCIE2_CTRL_CLK_ROOT, IP_CLOCK_SLICE, 64,
> > + {OSC_24M_CLK, SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
> > + SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
> > + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_333M_CLK,
> > SYSTEM_PLL3_CLK}
> > + },
> > + {PCIE2_PHY_CLK_ROOT, IP_CLOCK_SLICE, 65,
> > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_500M_CLK,
> > + EXT_CLK_1, EXT_CLK_2, EXT_CLK_3,
> > + EXT_CLK_4, SYSTEM_PLL1_400M_CLK}
> > + },
> > + {PCIE2_AUX_CLK_ROOT, IP_CLOCK_SLICE, 66,
> > + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_50M_CLK,
> > + SYSTEM_PLL3_CLK, SYSTEM_PLL2_100M_CLK,
> > + SYSTEM_PLL1_80M_CLK, SYSTEM_PLL1_160M_CLK,
> > SYSTEM_PLL1_200M_CLK}
> > + },
> > + {ECSPI3_CLK_ROOT, IP_CLOCK_SLICE, 67,
> > + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
> > + SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
> > + SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
> > + },
> > + {PDM_CLK_ROOT, IP_CLOCK_SLICE, 68,
> > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK,
> > + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> > + SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK},
> > + },
> > + {VPU_H1_CLK_ROOT, IP_CLOCK_SLICE, 69,
> > + {OSC_24M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
> > + SYSTEM_PLL2_1000M_CLK, AUDIO_PLL2_CLK,
> > + SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
> > + },
> > + {DRAM_SEL_CFG, DRAM_SEL_CLOCK_SLICE, 0,
> > + {DRAM_PLL1_CLK}
> > + },
> > + {CORE_SEL_CFG, CORE_SEL_CLOCK_SLICE, 0,
> > + {DRAM_PLL1_CLK}
> > + },
> > +};
> > +#endif
> >
> > static int select(enum clk_root_index clock_id)
> > {
>
>
>
>
> Best regards,
>
> Lukasz Majewski
>
> --
>
> DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> lukma at denx.de
^ permalink raw reply [flat|nested] 39+ messages in thread* [U-Boot] [PATCH 10/20] imx8m: add clk support for i.MX8MM
2019-01-30 5:46 ` Peng Fan
@ 2019-01-30 6:46 ` Lukasz Majewski
2019-01-30 6:56 ` Peng Fan
0 siblings, 1 reply; 39+ messages in thread
From: Lukasz Majewski @ 2019-01-30 6:46 UTC (permalink / raw)
To: u-boot
Hi Peng,
> Hi Lukasz,
>
> > -----Original Message-----
> > From: Lukasz Majewski [mailto:lukma at denx.de]
> > Sent: 2019年1月30日 6:55
> > To: Peng Fan <peng.fan@nxp.com>
> > Cc: sbabic at denx.de; Fabio Estevam <fabio.estevam@nxp.com>;
> > dl-uboot-imx <uboot-imx@nxp.com>; u-boot at lists.denx.de
> > Subject: Re: [U-Boot] [PATCH 10/20] imx8m: add clk support for
> > i.MX8MM
> >
> > Hi Peng,
> >
> > > Introduce clk implementation for i.MX8MM, including pll
> > > configuration, pll decoding, ccm configuration.
> > >
> > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > ---
> > > arch/arm/include/asm/arch-imx8m/clock.h | 2 +
> > > arch/arm/include/asm/arch-imx8m/clock_imx8mm.h | 387 +++++++++++
> > > arch/arm/mach-imx/imx8m/Makefile | 1 +
> > > arch/arm/mach-imx/imx8m/clock_imx8mm.c | 866
> > > +++++++++++++++++++++++++
> > > arch/arm/mach-imx/imx8m/clock_slice.c | 461
> > +++++++++++++ 5
> > > files changed, 1717 insertions(+) create mode 100644
> > > arch/arm/include/asm/arch-imx8m/clock_imx8mm.h create mode 100644
> > > arch/arm/mach-imx/imx8m/clock_imx8mm.c
> >
> > As fair as I see this approach is not similar to the one from Linux
> > kernel:
> >
> > https://elixir.bootlin.com/linux/v5.0-rc3/source/drivers/clk/imx/clk-imx8mq.
> > c
> > or simpler:
> > https://git.pengutronix.de/cgit/barebox/tree/drivers/clk/imx/clk-imx8mq.c
> >
> > Also Fabio pointed out in the other mail that we shall stick to
> > Linux kernel Common Clock Framework.
> >
> > IMHO we shall add the simple CCF look alike code (I'm going to post
> > imx6q port in a few days).
>
> That will be too complicated for SPL and it will bring more efforts
> when we do pre/post silicon bringup.
If we use OF_PLATDATA to avoid DTB inclusion (and provide necessary
information for the SPL driver) then we may do the trick.
As of now - the problem is that SPL on IMX{568} get bloated very
rapidly when converted to DM/DTS..., but this shall not be the case for
generic EVAL board.
>
> Regards,
> Peng.
>
> >
> > >
> > > diff --git a/arch/arm/include/asm/arch-imx8m/clock.h
> > > b/arch/arm/include/asm/arch-imx8m/clock.h index
> > > 7225c760fe..ead4b8d3dc 100644 ---
> > > a/arch/arm/include/asm/arch-imx8m/clock.h +++
> > > b/arch/arm/include/asm/arch-imx8m/clock.h @@ -7,6 +7,8 @@
> > >
> > > #ifdef CONFIG_IMX8MQ
> > > #include <asm/arch/clock_imx8mq.h>
> > > +#elif defined(CONFIG_IMX8MM)
> > > +#include <asm/arch/clock_imx8mm.h>
> > > #else
> > > #error "Error no clock.h"
> > > #endif
> > > diff --git a/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
> > > b/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h new file mode
> > 100644
> > > index 0000000000..305514a4ec
> > > --- /dev/null
> > > +++ b/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
> > > @@ -0,0 +1,387 @@
> > > +/* SPDX-License-Identifier: GPL-2.0+ */
> > > +/*
> > > + * Copyright 2018-2019 NXP
> > > + *
> > > + * Peng Fan <peng.fan@nxp.com>
> > > + */
> > > +
> > > +#ifndef _ASM_ARCH_IMX8MM_CLOCK_H
> > > +#define _ASM_ARCH_IMX8MM_CLOCK_H
> > > +
> > > +#define PLL_1443X_RATE(_rate, _m, _p, _s, _k)
> > > \
> > > + {
> > > \
> > > + .rate =
> > > (_rate), \
> > > + .mdiv =
> > > (_m), \
> > > + .pdiv =
> > > (_p), \
> > > + .sdiv =
> > > (_s), \
> > > + .kdiv =
> > > (_k), \
> > > + }
> > > +
> > > +#define LOCK_STATUS BIT(31)
> > > +#define LOCK_SEL_MASK BIT(29)
> > > +#define CLKE_MASK BIT(11)
> > > +#define RST_MASK BIT(9)
> > > +#define BYPASS_MASK BIT(4)
> > > +#define MDIV_SHIFT 12
> > > +#define MDIV_MASK GENMASK(21, 12)
> > > +#define PDIV_SHIFT 4
> > > +#define PDIV_MASK GENMASK(9, 4)
> > > +#define SDIV_SHIFT 0
> > > +#define SDIV_MASK GENMASK(2, 0)
> > > +#define KDIV_SHIFT 0
> > > +#define KDIV_MASK GENMASK(15, 0)
> > > +
> > > +struct imx_int_pll_rate_table {
> > > + u32 rate;
> > > + int mdiv;
> > > + int pdiv;
> > > + int sdiv;
> > > + int kdiv;
> > > +};
> > > +
> > > +enum pll_clocks {
> > > + ANATOP_ARM_PLL,
> > > + ANATOP_VPU_PLL,
> > > + ANATOP_GPU_PLL,
> > > + ANATOP_SYSTEM_PLL1,
> > > + ANATOP_SYSTEM_PLL2,
> > > + ANATOP_SYSTEM_PLL3,
> > > + ANATOP_AUDIO_PLL1,
> > > + ANATOP_AUDIO_PLL2,
> > > + ANATOP_VIDEO_PLL,
> > > + ANATOP_DRAM_PLL,
> > > +};
> > > +
> > > +enum clk_root_index {
> > > + ARM_A53_CLK_ROOT = 0,
> > > + ARM_M4_CLK_ROOT = 1,
> > > + VPU_A53_CLK_ROOT = 2,
> > > + GPU3D_CLK_ROOT = 3,
> > > + GPU2D_CLK_ROOT = 4,
> > > + MAIN_AXI_CLK_ROOT = 16,
> > > + ENET_AXI_CLK_ROOT = 17,
> > > + NAND_USDHC_BUS_CLK_ROOT = 18,
> > > + VPU_BUS_CLK_ROOT = 19,
> > > + DISPLAY_AXI_CLK_ROOT = 20,
> > > + DISPLAY_APB_CLK_ROOT = 21,
> > > + DISPLAY_RTRM_CLK_ROOT = 22,
> > > + USB_BUS_CLK_ROOT = 23,
> > > + GPU_AXI_CLK_ROOT = 24,
> > > + GPU_AHB_CLK_ROOT = 25,
> > > + NOC_CLK_ROOT = 26,
> > > + NOC_APB_CLK_ROOT = 27,
> > > + AHB_CLK_ROOT = 32,
> > > + IPG_CLK_ROOT = 33,
> > > + AUDIO_AHB_CLK_ROOT = 34,
> > > + MIPI_DSI_ESC_RX_CLK_ROOT = 36,
> > > + DRAM_SEL_CFG = 48,
> > > + CORE_SEL_CFG = 49,
> > > + DRAM_ALT_CLK_ROOT = 64,
> > > + DRAM_APB_CLK_ROOT = 65,
> > > + VPU_G1_CLK_ROOT = 66,
> > > + VPU_G2_CLK_ROOT = 67,
> > > + DISPLAY_DTRC_CLK_ROOT = 68,
> > > + DISPLAY_DC8000_CLK_ROOT = 69,
> > > + PCIE_CTRL_CLK_ROOT = 70,
> > > + PCIE_PHY_CLK_ROOT = 71,
> > > + PCIE_AUX_CLK_ROOT = 72,
> > > + DC_PIXEL_CLK_ROOT = 73,
> > > + LCDIF_PIXEL_CLK_ROOT = 74,
> > > + SAI1_CLK_ROOT = 75,
> > > + SAI2_CLK_ROOT = 76,
> > > + SAI3_CLK_ROOT = 77,
> > > + SAI4_CLK_ROOT = 78,
> > > + SAI5_CLK_ROOT = 79,
> > > + SAI6_CLK_ROOT = 80,
> > > + SPDIF1_CLK_ROOT = 81,
> > > + SPDIF2_CLK_ROOT = 82,
> > > + ENET_REF_CLK_ROOT = 83,
> > > + ENET_TIMER_CLK_ROOT = 84,
> > > + ENET_PHY_REF_CLK_ROOT = 85,
> > > + NAND_CLK_ROOT = 86,
> > > + QSPI_CLK_ROOT = 87,
> > > + USDHC1_CLK_ROOT = 88,
> > > + USDHC2_CLK_ROOT = 89,
> > > + I2C1_CLK_ROOT = 90,
> > > + I2C2_CLK_ROOT = 91,
> > > + I2C3_CLK_ROOT = 92,
> > > + I2C4_CLK_ROOT = 93,
> > > + UART1_CLK_ROOT = 94,
> > > + UART2_CLK_ROOT = 95,
> > > + UART3_CLK_ROOT = 96,
> > > + UART4_CLK_ROOT = 97,
> > > + USB_CORE_REF_CLK_ROOT = 98,
> > > + USB_PHY_REF_CLK_ROOT = 99,
> > > + GIC_CLK_ROOT = 100,
> > > + ECSPI1_CLK_ROOT = 101,
> > > + ECSPI2_CLK_ROOT = 102,
> > > + PWM1_CLK_ROOT = 103,
> > > + PWM2_CLK_ROOT = 104,
> > > + PWM3_CLK_ROOT = 105,
> > > + PWM4_CLK_ROOT = 106,
> > > + GPT1_CLK_ROOT = 107,
> > > + GPT2_CLK_ROOT = 108,
> > > + GPT3_CLK_ROOT = 109,
> > > + GPT4_CLK_ROOT = 110,
> > > + GPT5_CLK_ROOT = 111,
> > > + GPT6_CLK_ROOT = 112,
> > > + TRACE_CLK_ROOT = 113,
> > > + WDOG_CLK_ROOT = 114,
> > > + WRCLK_CLK_ROOT = 115,
> > > + IPP_DO_CLKO1 = 116,
> > > + IPP_DO_CLKO2 = 117,
> > > + MIPI_DSI_CORE_CLK_ROOT = 118,
> > > + MIPI_DSI_PHY_REF_CLK_ROOT = 119,
> > > + MIPI_DSI_DBI_CLK_ROOT = 120,
> > > + USDHC3_CLK_ROOT = 121,
> > > + MIPI_CSI1_CORE_CLK_ROOT = 122,
> > > + MIPI_CSI1_PHY_REF_CLK_ROOT = 123,
> > > + MIPI_CSI1_ESC_CLK_ROOT = 124,
> > > + MIPI_CSI2_CORE_CLK_ROOT = 125,
> > > + MIPI_CSI2_PHY_REF_CLK_ROOT = 126,
> > > + MIPI_CSI2_ESC_CLK_ROOT = 127,
> > > + PCIE2_CTRL_CLK_ROOT = 128,
> > > + PCIE2_PHY_CLK_ROOT = 129,
> > > + PCIE2_AUX_CLK_ROOT = 130,
> > > + ECSPI3_CLK_ROOT = 131,
> > > + PDM_CLK_ROOT = 132,
> > > + VPU_H1_CLK_ROOT = 133,
> > > + CLK_ROOT_MAX,
> > > +};
> > > +
> > > +enum clk_root_src {
> > > + OSC_24M_CLK,
> > > + ARM_PLL_CLK,
> > > + DRAM_PLL1_CLK,
> > > + VIDEO_PLL2_CLK,
> > > + VPU_PLL_CLK,
> > > + GPU_PLL_CLK,
> > > + SYSTEM_PLL1_800M_CLK,
> > > + SYSTEM_PLL1_400M_CLK,
> > > + SYSTEM_PLL1_266M_CLK,
> > > + SYSTEM_PLL1_200M_CLK,
> > > + SYSTEM_PLL1_160M_CLK,
> > > + SYSTEM_PLL1_133M_CLK,
> > > + SYSTEM_PLL1_100M_CLK,
> > > + SYSTEM_PLL1_80M_CLK,
> > > + SYSTEM_PLL1_40M_CLK,
> > > + SYSTEM_PLL2_1000M_CLK,
> > > + SYSTEM_PLL2_500M_CLK,
> > > + SYSTEM_PLL2_333M_CLK,
> > > + SYSTEM_PLL2_250M_CLK,
> > > + SYSTEM_PLL2_200M_CLK,
> > > + SYSTEM_PLL2_166M_CLK,
> > > + SYSTEM_PLL2_125M_CLK,
> > > + SYSTEM_PLL2_100M_CLK,
> > > + SYSTEM_PLL2_50M_CLK,
> > > + SYSTEM_PLL3_CLK,
> > > + AUDIO_PLL1_CLK,
> > > + AUDIO_PLL2_CLK,
> > > + VIDEO_PLL_CLK,
> > > + OSC_32K_CLK,
> > > + EXT_CLK_1,
> > > + EXT_CLK_2,
> > > + EXT_CLK_3,
> > > + EXT_CLK_4,
> > > + OSC_HDMI_CLK
> > > +};
> > > +
> > > +enum clk_ccgr_index {
> > > + CCGR_DVFS = 0,
> > > + CCGR_ANAMIX = 1,
> > > + CCGR_CPU = 2,
> > > + CCGR_CSU = 3,
> > > + CCGR_DEBUG = 4,
> > > + CCGR_DDR1 = 5,
> > > + CCGR_ECSPI1 = 7,
> > > + CCGR_ECSPI2 = 8,
> > > + CCGR_ECSPI3 = 9,
> > > + CCGR_ENET1 = 10,
> > > + CCGR_GPIO1 = 11,
> > > + CCGR_GPIO2 = 12,
> > > + CCGR_GPIO3 = 13,
> > > + CCGR_GPIO4 = 14,
> > > + CCGR_GPIO5 = 15,
> > > + CCGR_GPT1 = 16,
> > > + CCGR_GPT2 = 17,
> > > + CCGR_GPT3 = 18,
> > > + CCGR_GPT4 = 19,
> > > + CCGR_GPT5 = 20,
> > > + CCGR_GPT6 = 21,
> > > + CCGR_HS = 22,
> > > + CCGR_I2C1 = 23,
> > > + CCGR_I2C2 = 24,
> > > + CCGR_I2C3 = 25,
> > > + CCGR_I2C4 = 26,
> > > + CCGR_IOMUX = 27,
> > > + CCGR_IOMUX1 = 28,
> > > + CCGR_IOMUX2 = 29,
> > > + CCGR_IOMUX3 = 30,
> > > + CCGR_IOMUX4 = 31,
> > > + CCGR_SNVSMIX_IPG_CLK = 32,
> > > + CCGR_MU = 33,
> > > + CCGR_OCOTP = 34,
> > > + CCGR_OCRAM = 35,
> > > + CCGR_OCRAM_S = 36,
> > > + CCGR_PCIE = 37,
> > > + CCGR_PERFMON1 = 38,
> > > + CCGR_PERFMON2 = 39,
> > > + CCGR_PWM1 = 40,
> > > + CCGR_PWM2 = 41,
> > > + CCGR_PWM3 = 42,
> > > + CCGR_PWM4 = 43,
> > > + CCGR_QOS = 44,
> > > + CCGR_QOS_DISPMIX = 45,
> > > + CCGR_QOS_ETHENET = 46,
> > > + CCGR_QSPI = 47,
> > > + CCGR_RAWNAND = 48,
> > > + CCGR_RDC = 49,
> > > + CCGR_ROM = 50,
> > > + CCGR_SAI1 = 51,
> > > + CCGR_SAI2 = 52,
> > > + CCGR_SAI3 = 53,
> > > + CCGR_SAI4 = 54,
> > > + CCGR_SAI5 = 55,
> > > + CCGR_SAI6 = 56,
> > > + CCGR_SCTR = 57,
> > > + CCGR_SDMA1 = 58,
> > > + CCGR_SDMA2 = 59,
> > > + CCGR_SEC_DEBUG = 60,
> > > + CCGR_SEMA1 = 61,
> > > + CCGR_SEMA2 = 62,
> > > + CCGR_SIM_DISPLAY = 63,
> > > + CCGR_SIM_ENET = 64,
> > > + CCGR_SIM_M = 65,
> > > + CCGR_SIM_MAIN = 66,
> > > + CCGR_SIM_S = 67,
> > > + CCGR_SIM_WAKEUP = 68,
> > > + CCGR_SIM_HSIO = 69,
> > > + CCGR_SIM_VPU = 70,
> > > + CCGR_SNVS = 71,
> > > + CCGR_TRACE = 72,
> > > + CCGR_UART1 = 73,
> > > + CCGR_UART2 = 74,
> > > + CCGR_UART3 = 75,
> > > + CCGR_UART4 = 76,
> > > + CCGR_USB_MSCALE_PL301 = 77,
> > > + CCGR_GPU3D = 79,
> > > + CCGR_USDHC1 = 81,
> > > + CCGR_USDHC2 = 82,
> > > + CCGR_WDOG1 = 83,
> > > + CCGR_WDOG2 = 84,
> > > + CCGR_WDOG3 = 85,
> > > + CCGR_VPUG1 = 86,
> > > + CCGR_GPU_BUS = 87,
> > > + CCGR_VPUH1 = 89,
> > > + CCGR_VPUG2 = 90,
> > > + CCGR_PDM = 91,
> > > + CCGR_GIC = 92,
> > > + CCGR_DISPMIX = 93,
> > > + CCGR_USDHC3 = 94,
> > > + CCGR_SDMA3 = 95,
> > > + CCGR_XTAL = 96,
> > > + CCGR_PLL = 97,
> > > + CCGR_TEMP_SENSOR = 98,
> > > + CCGR_VPUMIX_BUS = 99,
> > > + CCGR_GPU2D = 102,
> > > + CCGR_MAX
> > > +};
> > > +
> > > +enum clk_src_index {
> > > + CLK_SRC_CKIL_SYNC_REQ = 0,
> > > + CLK_SRC_ARM_PLL_EN = 1,
> > > + CLK_SRC_GPU_PLL_EN = 2,
> > > + CLK_SRC_VPU_PLL_EN = 3,
> > > + CLK_SRC_DRAM_PLL_EN = 4,
> > > + CLK_SRC_SYSTEM_PLL1_EN = 5,
> > > + CLK_SRC_SYSTEM_PLL2_EN = 6,
> > > + CLK_SRC_SYSTEM_PLL3_EN = 7,
> > > + CLK_SRC_AUDIO_PLL1_EN = 8,
> > > + CLK_SRC_AUDIO_PLL2_EN = 9,
> > > + CLK_SRC_VIDEO_PLL1_EN = 10,
> > > + CLK_SRC_RESERVED = 11,
> > > + CLK_SRC_ARM_PLL = 12,
> > > + CLK_SRC_GPU_PLL = 13,
> > > + CLK_SRC_VPU_PLL = 14,
> > > + CLK_SRC_DRAM_PLL = 15,
> > > + CLK_SRC_SYSTEM_PLL1_800M = 16,
> > > + CLK_SRC_SYSTEM_PLL1_400M = 17,
> > > + CLK_SRC_SYSTEM_PLL1_266M = 18,
> > > + CLK_SRC_SYSTEM_PLL1_200M = 19,
> > > + CLK_SRC_SYSTEM_PLL1_160M = 20,
> > > + CLK_SRC_SYSTEM_PLL1_133M = 21,
> > > + CLK_SRC_SYSTEM_PLL1_100M = 22,
> > > + CLK_SRC_SYSTEM_PLL1_80M = 23,
> > > + CLK_SRC_SYSTEM_PLL1_40M = 24,
> > > + CLK_SRC_SYSTEM_PLL2_1000M = 25,
> > > + CLK_SRC_SYSTEM_PLL2_500M = 26,
> > > + CLK_SRC_SYSTEM_PLL2_333M = 27,
> > > + CLK_SRC_SYSTEM_PLL2_250M = 28,
> > > + CLK_SRC_SYSTEM_PLL2_200M = 29,
> > > + CLK_SRC_SYSTEM_PLL2_166M = 30,
> > > + CLK_SRC_SYSTEM_PLL2_125M = 31,
> > > + CLK_SRC_SYSTEM_PLL2_100M = 32,
> > > + CLK_SRC_SYSTEM_PLL2_50M = 33,
> > > + CLK_SRC_SYSTEM_PLL3 = 34,
> > > + CLK_SRC_AUDIO_PLL1 = 35,
> > > + CLK_SRC_AUDIO_PLL2 = 36,
> > > + CLK_SRC_VIDEO_PLL1 = 37,
> > > +};
> > > +
> > > +#define INTPLL_LOCK_MASK BIT(31)
> > > +#define INTPLL_LOCK_SEL_MASK BIT(29)
> > > +#define INTPLL_EXT_BYPASS_MASK BIT(28)
> > > +#define INTPLL_DIV20_CLKE_MASK BIT(27)
> > > +#define INTPLL_DIV20_CLKE_OVERRIDE_MASK BIT(26)
> > > +#define INTPLL_DIV10_CLKE_MASK BIT(25)
> > > +#define INTPLL_DIV10_CLKE_OVERRIDE_MASK BIT(24)
> > > +#define INTPLL_DIV8_CLKE_MASK BIT(23)
> > > +#define INTPLL_DIV8_CLKE_OVERRIDE_MASK BIT(22)
> > > +#define INTPLL_DIV6_CLKE_MASK BIT(21)
> > > +#define INTPLL_DIV6_CLKE_OVERRIDE_MASK BIT(20)
> > > +#define INTPLL_DIV5_CLKE_MASK BIT(19)
> > > +#define INTPLL_DIV5_CLKE_OVERRIDE_MASK BIT(18)
> > > +#define INTPLL_DIV4_CLKE_MASK BIT(17)
> > > +#define INTPLL_DIV4_CLKE_OVERRIDE_MASK BIT(16)
> > > +#define INTPLL_DIV3_CLKE_MASK BIT(15)
> > > +#define INTPLL_DIV3_CLKE_OVERRIDE_MASK BIT(14)
> > > +#define INTPLL_DIV2_CLKE_MASK BIT(13)
> > > +#define INTPLL_DIV2_CLKE_OVERRIDE_MASK BIT(12)
> > > +#define INTPLL_CLKE_MASK BIT(11)
> > > +#define INTPLL_CLKE_OVERRIDE_MASK BIT(10)
> > > +#define INTPLL_RST_MASK BIT(9)
> > > +#define INTPLL_RST_OVERRIDE_MASK BIT(8)
> > > +#define INTPLL_BYPASS_MASK BIT(4)
> > > +#define INTPLL_PAD_CLK_SEL_MASK
> > > GENMASK(3, 2) +#define
> > > INTPLL_REF_CLK_SEL_MASK GENMASK(1, 0) +
> > > +#define INTPLL_MAIN_DIV_MASK GENMASK(21, 12)
> > > +#define INTPLL_MAIN_DIV_VAL(n) ((n << 12) &
> > > GENMASK(21, 12)) +#define INTPLL_MAIN_DIV_SHIFT 12
> > > +#define INTPLL_PRE_DIV_MASK GENMASK(9, 4)
> > > +#define INTPLL_PRE_DIV_VAL(n) ((n << 4) &
> > > GENMASK(9, 4)) +#define INTPLL_PRE_DIV_SHIFT 4
> > > +#define INTPLL_POST_DIV_MASK GENMASK(2, 0)
> > > +#define INTPLL_POST_DIV_VAL(n) ((n << 0) &
> > > GENMASK(2, 0)) +#define INTPLL_POST_DIV_SHIFT 0
> > > +
> > > +#define INTPLL_LOCK_CON_DLY_MASK GENMASK(5, 4)
> > > +#define INTPLL_LOCK_CON_DLY_SHIFT 4
> > > +#define INTPLL_LOCK_CON_OUT_MASK GENMASK(3, 2)
> > > +#define INTPLL_LOCK_CON_OUT_SHIFT 2
> > > +#define INTPLL_LOCK_CON_IN_MASK GENMASK(1, 0)
> > > +#define INTPLL_LOCK_CON_IN_SHIFT 0
> > > +
> > > +#define INTPLL_LRD_EN_MASK BIT(21)
> > > +#define INTPLL_FOUT_MASK BIT(20)
> > > +#define INTPLL_AFC_SEL_MASK BIT(19)
> > > +#define INTPLL_PBIAS_CTRL_MASK BIT(18)
> > > +#define INTPLL_PBIAS_CTRL_EN_MASK BIT(17)
> > > +#define INTPLL_AFCINIT_SEL_MASK BIT(16)
> > > +#define INTPLL_FSEL_MASK BIT(14)
> > > +#define INTPLL_FEED_EN_MASK BIT(13)
> > > +#define INTPLL_EXTAFC_MASK GENMASK(7, 3)
> > > +#define INTPLL_AFC_EN_MASK BIT(2)
> > > +#define INTPLL_ICP_MASK GENMASK(1, 0)
> > > +
> > > +#endif
> > > diff --git a/arch/arm/mach-imx/imx8m/Makefile
> > > b/arch/arm/mach-imx/imx8m/Makefile index 42a1544c6b..92184f3135
> > 100644
> > > --- a/arch/arm/mach-imx/imx8m/Makefile
> > > +++ b/arch/arm/mach-imx/imx8m/Makefile
> > > @@ -5,3 +5,4 @@
> > > obj-y += lowlevel_init.o
> > > obj-y += clock_slice.o soc.o
> > > obj-$(CONFIG_IMX8MQ) += clock_imx8mq.o
> > > +obj-$(CONFIG_IMX8MM) += clock_imx8mm.o
> > > diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> > > b/arch/arm/mach-imx/imx8m/clock_imx8mm.c new file mode 100644
> > > index 0000000000..beddd2d68b
> > > --- /dev/null
> > > +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> > > @@ -0,0 +1,866 @@
> > > +// SPDX-License-Identifier: GPL-2.0+
> > > +/*
> > > + * Copyright 2018-2019 NXP
> > > + *
> > > + * Peng Fan <peng.fan@nxp.com>
> > > + */
> > > +
> > > +#include <common.h>
> > > +#include <asm/arch/clock.h>
> > > +#include <asm/arch/imx-regs.h>
> > > +#include <asm/arch/sys_proto.h>
> > > +#include <asm/io.h>
> > > +#include <div64.h>
> > > +#include <errno.h>
> > > +
> > > +DECLARE_GLOBAL_DATA_PTR;
> > > +
> > > +static struct anamix_pll *ana_pll = (struct anamix_pll
> > > *)ANATOP_BASE_ADDR; +
> > > +void enable_ocotp_clk(unsigned char enable)
> > > +{
> > > + clock_enable(CCGR_OCOTP, !!enable);
> > > +}
> > > +
> > > +int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
> > > +{
> > > + /* 0 - 3 is valid i2c num */
> > > + if (i2c_num > 3)
> > > + return -EINVAL;
> > > +
> > > + clock_enable(CCGR_I2C1 + i2c_num, !!enable);
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +u32 decode_intpll(enum clk_root_src intpll)
> > > +{
> > > + u32 pll_gnrl_ctl, pll_div_ctl, pll_clke_mask;
> > > + u32 main_div, pre_div, post_div, div;
> > > + u64 freq;
> > > +
> > > + switch (intpll) {
> > > + case ARM_PLL_CLK:
> > > + pll_gnrl_ctl = readl(&ana_pll->arm_pll_gnrl_ctl);
> > > + pll_div_ctl = readl(&ana_pll->arm_pll_div_ctl);
> > > + break;
> > > + case GPU_PLL_CLK:
> > > + pll_gnrl_ctl = readl(&ana_pll->gpu_pll_gnrl_ctl);
> > > + pll_div_ctl = readl(&ana_pll->gpu_pll_div_ctl);
> > > + break;
> > > + case VPU_PLL_CLK:
> > > + pll_gnrl_ctl = readl(&ana_pll->vpu_pll_gnrl_ctl);
> > > + pll_div_ctl = readl(&ana_pll->vpu_pll_div_ctl);
> > > + break;
> > > + case SYSTEM_PLL1_800M_CLK:
> > > + case SYSTEM_PLL1_400M_CLK:
> > > + case SYSTEM_PLL1_266M_CLK:
> > > + case SYSTEM_PLL1_200M_CLK:
> > > + case SYSTEM_PLL1_160M_CLK:
> > > + case SYSTEM_PLL1_133M_CLK:
> > > + case SYSTEM_PLL1_100M_CLK:
> > > + case SYSTEM_PLL1_80M_CLK:
> > > + case SYSTEM_PLL1_40M_CLK:
> > > + pll_gnrl_ctl =
> > > readl(&ana_pll->sys_pll1_gnrl_ctl);
> > > + pll_div_ctl = readl(&ana_pll->sys_pll1_div_ctl);
> > > + break;
> > > + case SYSTEM_PLL2_1000M_CLK:
> > > + case SYSTEM_PLL2_500M_CLK:
> > > + case SYSTEM_PLL2_333M_CLK:
> > > + case SYSTEM_PLL2_250M_CLK:
> > > + case SYSTEM_PLL2_200M_CLK:
> > > + case SYSTEM_PLL2_166M_CLK:
> > > + case SYSTEM_PLL2_125M_CLK:
> > > + case SYSTEM_PLL2_100M_CLK:
> > > + case SYSTEM_PLL2_50M_CLK:
> > > + pll_gnrl_ctl =
> > > readl(&ana_pll->sys_pll2_gnrl_ctl);
> > > + pll_div_ctl = readl(&ana_pll->sys_pll2_div_ctl);
> > > + break;
> > > + case SYSTEM_PLL3_CLK:
> > > + pll_gnrl_ctl =
> > > readl(&ana_pll->sys_pll3_gnrl_ctl);
> > > + pll_div_ctl = readl(&ana_pll->sys_pll3_div_ctl);
> > > + break;
> > > + default:
> > > + return -EINVAL;
> > > + }
> > > +
> > > + /* Only support SYS_XTAL 24M, PAD_CLK not take into
> > > consideration */
> > > + if ((pll_gnrl_ctl & INTPLL_REF_CLK_SEL_MASK) != 0)
> > > + return 0;
> > > +
> > > + if ((pll_gnrl_ctl & INTPLL_RST_MASK) == 0)
> > > + return 0;
> > > +
> > > + /*
> > > + * When BYPASS is equal to 1, PLL enters the bypass mode
> > > + * regardless of the values of RESETB
> > > + */
> > > + if (pll_gnrl_ctl & INTPLL_BYPASS_MASK)
> > > + return 24000000u;
> > > +
> > > + if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) {
> > > + puts("pll not locked\n");
> > > + return 0;
> > > + }
> > > +
> > > + switch (intpll) {
> > > + case ARM_PLL_CLK:
> > > + case GPU_PLL_CLK:
> > > + case VPU_PLL_CLK:
> > > + case SYSTEM_PLL3_CLK:
> > > + case SYSTEM_PLL1_800M_CLK:
> > > + case SYSTEM_PLL2_1000M_CLK:
> > > + pll_clke_mask = INTPLL_CLKE_MASK;
> > > + div = 1;
> > > + break;
> > > +
> > > + case SYSTEM_PLL1_400M_CLK:
> > > + case SYSTEM_PLL2_500M_CLK:
> > > + pll_clke_mask = INTPLL_DIV2_CLKE_MASK;
> > > + div = 2;
> > > + break;
> > > +
> > > + case SYSTEM_PLL1_266M_CLK:
> > > + case SYSTEM_PLL2_333M_CLK:
> > > + pll_clke_mask = INTPLL_DIV3_CLKE_MASK;
> > > + div = 3;
> > > + break;
> > > +
> > > + case SYSTEM_PLL1_200M_CLK:
> > > + case SYSTEM_PLL2_250M_CLK:
> > > + pll_clke_mask = INTPLL_DIV4_CLKE_MASK;
> > > + div = 4;
> > > + break;
> > > +
> > > + case SYSTEM_PLL1_160M_CLK:
> > > + case SYSTEM_PLL2_200M_CLK:
> > > + pll_clke_mask = INTPLL_DIV5_CLKE_MASK;
> > > + div = 5;
> > > + break;
> > > +
> > > + case SYSTEM_PLL1_133M_CLK:
> > > + case SYSTEM_PLL2_166M_CLK:
> > > + pll_clke_mask = INTPLL_DIV6_CLKE_MASK;
> > > + div = 6;
> > > + break;
> > > +
> > > + case SYSTEM_PLL1_100M_CLK:
> > > + case SYSTEM_PLL2_125M_CLK:
> > > + pll_clke_mask = INTPLL_DIV8_CLKE_MASK;
> > > + div = 8;
> > > + break;
> > > +
> > > + case SYSTEM_PLL1_80M_CLK:
> > > + case SYSTEM_PLL2_100M_CLK:
> > > + pll_clke_mask = INTPLL_DIV10_CLKE_MASK;
> > > + div = 10;
> > > + break;
> > > +
> > > + case SYSTEM_PLL1_40M_CLK:
> > > + case SYSTEM_PLL2_50M_CLK:
> > > + pll_clke_mask = INTPLL_DIV20_CLKE_MASK;
> > > + div = 20;
> > > + break;
> > > + default:
> > > + return -EINVAL;
> > > + }
> > > +
> > > + if ((pll_gnrl_ctl & pll_clke_mask) == 0)
> > > + return 0;
> > > +
> > > + main_div = (pll_div_ctl & INTPLL_MAIN_DIV_MASK) >>
> > > + INTPLL_MAIN_DIV_SHIFT;
> > > + pre_div = (pll_div_ctl & INTPLL_PRE_DIV_MASK) >>
> > > + INTPLL_PRE_DIV_SHIFT;
> > > + post_div = (pll_div_ctl & INTPLL_POST_DIV_MASK) >>
> > > + INTPLL_POST_DIV_SHIFT;
> > > +
> > > + /* FFVCO = (m * FFIN) / p, FFOUT = (m * FFIN) / (p *
> > > 2^s) */
> > > + freq = 24000000ULL * main_div;
> > > + return lldiv(freq, pre_div * (1 << post_div) * div);
> > > +}
> > > +
> > > +u32 decode_fracpll(enum clk_root_src frac_pll)
> > > +{
> > > + u32 pll_gnrl_ctl, pll_fdiv_ctl0, pll_fdiv_ctl1;
> > > + u32 main_div, pre_div, post_div, k;
> > > +
> > > + switch (frac_pll) {
> > > + case DRAM_PLL1_CLK:
> > > + pll_gnrl_ctl =
> > > readl(&ana_pll->dram_pll_gnrl_ctl);
> > > + pll_fdiv_ctl0 =
> > > readl(&ana_pll->dram_pll_fdiv_ctl0);
> > > + pll_fdiv_ctl1 =
> > > readl(&ana_pll->dram_pll_fdiv_ctl1);
> > > + break;
> > > + case AUDIO_PLL1_CLK:
> > > + pll_gnrl_ctl =
> > > readl(&ana_pll->audio_pll1_gnrl_ctl);
> > > + pll_fdiv_ctl0 =
> > > readl(&ana_pll->audio_pll1_fdiv_ctl0);
> > > + pll_fdiv_ctl1 =
> > > readl(&ana_pll->audio_pll1_fdiv_ctl1);
> > > + break;
> > > + case AUDIO_PLL2_CLK:
> > > + pll_gnrl_ctl =
> > > readl(&ana_pll->audio_pll2_gnrl_ctl);
> > > + pll_fdiv_ctl0 =
> > > readl(&ana_pll->audio_pll2_fdiv_ctl0);
> > > + pll_fdiv_ctl1 =
> > > readl(&ana_pll->audio_pll2_fdiv_ctl1);
> > > + break;
> > > + case VIDEO_PLL_CLK:
> > > + pll_gnrl_ctl =
> > > readl(&ana_pll->video_pll1_gnrl_ctl);
> > > + pll_fdiv_ctl0 =
> > > readl(&ana_pll->video_pll1_fdiv_ctl0);
> > > + pll_fdiv_ctl1 =
> > > readl(&ana_pll->video_pll1_fdiv_ctl1);
> > > + break;
> > > + default:
> > > + printf("Not supported\n");
> > > + return 0;
> > > + }
> > > +
> > > + /* Only support SYS_XTAL 24M, PAD_CLK not take into
> > > consideration */
> > > + if ((pll_gnrl_ctl & INTPLL_REF_CLK_SEL_MASK) != 0)
> > > + return 0;
> > > +
> > > + if ((pll_gnrl_ctl & INTPLL_RST_MASK) == 0)
> > > + return 0;
> > > + /*
> > > + * When BYPASS is equal to 1, PLL enters the bypass mode
> > > + * regardless of the values of RESETB
> > > + */
> > > + if (pll_gnrl_ctl & INTPLL_BYPASS_MASK)
> > > + return 24000000u;
> > > +
> > > + if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) {
> > > + puts("pll not locked\n");
> > > + return 0;
> > > + }
> > > +
> > > + if (!(pll_gnrl_ctl & INTPLL_CLKE_MASK))
> > > + return 0;
> > > +
> > > + main_div = (pll_fdiv_ctl0 & INTPLL_MAIN_DIV_MASK) >>
> > > + INTPLL_MAIN_DIV_SHIFT;
> > > + pre_div = (pll_fdiv_ctl0 & INTPLL_PRE_DIV_MASK) >>
> > > + INTPLL_PRE_DIV_SHIFT;
> > > + post_div = (pll_fdiv_ctl0 & INTPLL_POST_DIV_MASK) >>
> > > + INTPLL_POST_DIV_SHIFT;
> > > +
> > > + k = pll_fdiv_ctl1 & GENMASK(15, 0);
> > > +
> > > + /*
> > > + * FFOUT = ((m + k / 65536) * FFIN) / (p * 2^s),
> > > + * 1 ≤ p ≤ 63, 64 ≤ m ≤ 1023, 0 ≤ s ≤ 6
> > > + */
> > > + return lldiv((main_div * 65536 + k) * 24000000ULL,
> > > + 65536 * pre_div * (1 << post_div));
> > > +}
> > > +
> > > +static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = {
> > > + PLL_1443X_RATE(800000000U, 300, 9, 0, 0),
> > > + PLL_1443X_RATE(750000000U, 250, 8, 0, 0),
> > > + PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
> > > + PLL_1443X_RATE(600000000U, 300, 3, 2, 0),
> > > + PLL_1443X_RATE(594000000U, 99, 1, 2, 0),
> > > + PLL_1443X_RATE(400000000U, 300, 9, 1, 0),
> > > + PLL_1443X_RATE(266666667U, 400, 9, 2, 0),
> > > + PLL_1443X_RATE(167000000U, 334, 3, 4, 0),
> > > + PLL_1443X_RATE(100000000U, 300, 9, 3, 0),
> > > +};
> > > +
> > > +int fracpll_configure(enum pll_clocks pll, u32 freq)
> > > +{
> > > + int i;
> > > + u32 tmp, div_val;
> > > + void *pll_base;
> > > + struct imx_int_pll_rate_table *rate;
> > > +
> > > + for (i = 0; i < ARRAY_SIZE(imx8mm_fracpll_tbl); i++) {
> > > + if (freq == imx8mm_fracpll_tbl[i].rate)
> > > + break;
> > > + }
> > > +
> > > + if (i == ARRAY_SIZE(imx8mm_fracpll_tbl)) {
> > > + printf("No matched freq table %u\n", freq);
> > > + return -EINVAL;
> > > + }
> > > +
> > > + rate = &imx8mm_fracpll_tbl[i];
> > > +
> > > + switch (pll) {
> > > + case ANATOP_DRAM_PLL:
> > > + setbits_le32(GPC_BASE_ADDR + 0xEC, 1 << 7);
> > > + setbits_le32(GPC_BASE_ADDR + 0xF8, 1 << 5);
> > > + writel(SRC_DDR1_ENABLE_MASK, SRC_BASE_ADDR +
> > > 0x1004); +
> > > + pll_base = &ana_pll->dram_pll_gnrl_ctl;
> > > + break;
> > > + case ANATOP_VIDEO_PLL:
> > > + pll_base = &ana_pll->video_pll1_gnrl_ctl;
> > > + break;
> > > + default:
> > > + return 0;
> > > + }
> > > + /* Bypass clock and set lock to pll output lock */
> > > + tmp = readl(pll_base);
> > > + tmp |= BYPASS_MASK;
> > > + writel(tmp, pll_base);
> > > +
> > > + /* Enable RST */
> > > + tmp &= ~RST_MASK;
> > > + writel(tmp, pll_base);
> > > +
> > > + div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv <<
> > > PDIV_SHIFT) |
> > > + (rate->sdiv << SDIV_SHIFT);
> > > + writel(div_val, pll_base + 4);
> > > + writel(rate->kdiv << KDIV_SHIFT, pll_base + 8);
> > > +
> > > + __udelay(100);
> > > +
> > > + /* Disable RST */
> > > + tmp |= RST_MASK;
> > > + writel(tmp, pll_base);
> > > +
> > > + /* Wait Lock*/
> > > + while (!(readl(pll_base) & LOCK_STATUS))
> > > + ;
> > > +
> > > + /* Bypass */
> > > + tmp &= ~BYPASS_MASK;
> > > + writel(tmp, pll_base);
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +#ifdef CONFIG_SPL_BUILD
> > > +void dram_pll_init(ulong pll_val)
> > > +{
> > > + fracpll_configure(ANATOP_DRAM_PLL, pll_val);
> > > +}
> > > +
> > > +static struct dram_bypass_clk_setting imx8mm_dram_bypass_tbl[] =
> > > {
> > > + DRAM_BYPASS_ROOT_CONFIG(MHZ(100), 2, CLK_ROOT_PRE_DIV1,
> > > 2,
> > > + CLK_ROOT_PRE_DIV2),
> > > + DRAM_BYPASS_ROOT_CONFIG(MHZ(250), 3, CLK_ROOT_PRE_DIV2,
> > > 2,
> > > + CLK_ROOT_PRE_DIV2),
> > > + DRAM_BYPASS_ROOT_CONFIG(MHZ(400), 1, CLK_ROOT_PRE_DIV2,
> > > 3,
> > > + CLK_ROOT_PRE_DIV2),
> > > +};
> > > +
> > > +void dram_enable_bypass(ulong clk_val)
> > > +{
> > > + int i;
> > > + struct dram_bypass_clk_setting *config;
> > > +
> > > + for (i = 0; i < ARRAY_SIZE(imx8mm_dram_bypass_tbl); i++)
> > > {
> > > + if (clk_val == imx8mm_dram_bypass_tbl[i].clk)
> > > + break;
> > > + }
> > > +
> > > + if (i == ARRAY_SIZE(imx8mm_dram_bypass_tbl)) {
> > > + printf("No matched freq table %lu\n", clk_val);
> > > + return;
> > > + }
> > > +
> > > + config = &imx8mm_dram_bypass_tbl[i];
> > > +
> > > + clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
> > > +
> > > CLK_ROOT_SOURCE_SEL(config->alt_root_sel) |
> > > +
> > > CLK_ROOT_PRE_DIV(config->alt_pre_div));
> > > + clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
> > > +
> > > CLK_ROOT_SOURCE_SEL(config->apb_root_sel) |
> > > +
> > > CLK_ROOT_PRE_DIV(config->apb_pre_div));
> > > + clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
> > > + CLK_ROOT_SOURCE_SEL(1));
> > > +}
> > > +
> > > +void dram_disable_bypass(void)
> > > +{
> > > + clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
> > > + CLK_ROOT_SOURCE_SEL(0));
> > > + clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
> > > + CLK_ROOT_SOURCE_SEL(4) |
> > > +
> > > CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV5)); +}
> > > +#endif
> > > +
> > > +int intpll_configure(enum pll_clocks pll, ulong freq)
> > > +{
> > > + void __iomem *pll_gnrl_ctl, __iomem *pll_div_ctl;
> > > + u32 pll_div_ctl_val, pll_clke_masks;
> > > +
> > > + switch (pll) {
> > > + case ANATOP_SYSTEM_PLL1:
> > > + pll_gnrl_ctl = &ana_pll->sys_pll1_gnrl_ctl;
> > > + pll_div_ctl = &ana_pll->sys_pll1_div_ctl;
> > > + pll_clke_masks = INTPLL_DIV20_CLKE_MASK |
> > > + INTPLL_DIV10_CLKE_MASK |
> > > INTPLL_DIV8_CLKE_MASK |
> > > + INTPLL_DIV6_CLKE_MASK |
> > > INTPLL_DIV5_CLKE_MASK |
> > > + INTPLL_DIV4_CLKE_MASK |
> > > INTPLL_DIV3_CLKE_MASK |
> > > + INTPLL_DIV2_CLKE_MASK | INTPLL_CLKE_MASK;
> > > + break;
> > > + case ANATOP_SYSTEM_PLL2:
> > > + pll_gnrl_ctl = &ana_pll->sys_pll2_gnrl_ctl;
> > > + pll_div_ctl = &ana_pll->sys_pll2_div_ctl;
> > > + pll_clke_masks = INTPLL_DIV20_CLKE_MASK |
> > > + INTPLL_DIV10_CLKE_MASK |
> > > INTPLL_DIV8_CLKE_MASK |
> > > + INTPLL_DIV6_CLKE_MASK |
> > > INTPLL_DIV5_CLKE_MASK |
> > > + INTPLL_DIV4_CLKE_MASK |
> > > INTPLL_DIV3_CLKE_MASK |
> > > + INTPLL_DIV2_CLKE_MASK | INTPLL_CLKE_MASK;
> > > + break;
> > > + case ANATOP_SYSTEM_PLL3:
> > > + pll_gnrl_ctl = &ana_pll->sys_pll3_gnrl_ctl;
> > > + pll_div_ctl = &ana_pll->sys_pll3_div_ctl;
> > > + pll_clke_masks = INTPLL_CLKE_MASK;
> > > + break;
> > > + case ANATOP_ARM_PLL:
> > > + pll_gnrl_ctl = &ana_pll->arm_pll_gnrl_ctl;
> > > + pll_div_ctl = &ana_pll->arm_pll_div_ctl;
> > > + pll_clke_masks = INTPLL_CLKE_MASK;
> > > + break;
> > > + case ANATOP_GPU_PLL:
> > > + pll_gnrl_ctl = &ana_pll->gpu_pll_gnrl_ctl;
> > > + pll_div_ctl = &ana_pll->gpu_pll_div_ctl;
> > > + pll_clke_masks = INTPLL_CLKE_MASK;
> > > + break;
> > > + case ANATOP_VPU_PLL:
> > > + pll_gnrl_ctl = &ana_pll->vpu_pll_gnrl_ctl;
> > > + pll_div_ctl = &ana_pll->vpu_pll_div_ctl;
> > > + pll_clke_masks = INTPLL_CLKE_MASK;
> > > + break;
> > > + default:
> > > + return -EINVAL;
> > > + };
> > > +
> > > + switch (freq) {
> > > + case MHZ(750):
> > > + /* 24 * 0xfa / 2 / 2 ^ 2 */
> > > + pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xfa) |
> > > + INTPLL_PRE_DIV_VAL(2) |
> > > INTPLL_POST_DIV_VAL(2);
> > > + break;
> > > + case MHZ(800):
> > > + /* 24 * 0x190 / 3 / 2 ^ 2 */
> > > + pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0x190) |
> > > + INTPLL_PRE_DIV_VAL(3) |
> > > INTPLL_POST_DIV_VAL(2);
> > > + break;
> > > + case MHZ(1000):
> > > + /* 24 * 0xfa / 3 / 2 ^ 1 */
> > > + pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xfa) |
> > > + INTPLL_PRE_DIV_VAL(3) |
> > > INTPLL_POST_DIV_VAL(1);
> > > + break;
> > > + case MHZ(1200):
> > > + /* 24 * 0xc8 / 2 / 2 ^ 1 */
> > > + pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xc8) |
> > > + INTPLL_PRE_DIV_VAL(2) |
> > > INTPLL_POST_DIV_VAL(1);
> > > + break;
> > > + case MHZ(2000):
> > > + /* 24 * 0xfa / 3 / 2 ^ 0 */
> > > + pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xfa) |
> > > + INTPLL_PRE_DIV_VAL(3) |
> > > INTPLL_POST_DIV_VAL(0);
> > > + break;
> > > + default:
> > > + return -EINVAL;
> > > + };
> > > + /* Bypass clock and set lock to pll output lock */
> > > + setbits_le32(pll_gnrl_ctl, INTPLL_BYPASS_MASK |
> > > INTPLL_LOCK_SEL_MASK);
> > > + /* Enable reset */
> > > + clrbits_le32(pll_gnrl_ctl, INTPLL_RST_MASK);
> > > + /* Configure */
> > > + writel(pll_div_ctl_val, pll_div_ctl);
> > > +
> > > + __udelay(100);
> > > +
> > > + /* Disable reset */
> > > + setbits_le32(pll_gnrl_ctl, INTPLL_RST_MASK);
> > > + /* Wait Lock */
> > > + while (!(readl(pll_gnrl_ctl) & INTPLL_LOCK_MASK))
> > > + ;
> > > + /* Clear bypass */
> > > + clrbits_le32(pll_gnrl_ctl, INTPLL_BYPASS_MASK);
> > > + setbits_le32(pll_gnrl_ctl, pll_clke_masks);
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +void init_uart_clk(u32 index)
> > > +{
> > > + /*
> > > + * set uart clock root
> > > + * 24M OSC
> > > + */
> > > + switch (index) {
> > > + case 0:
> > > + clock_enable(CCGR_UART1, 0);
> > > + clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON
> > > |
> > > + CLK_ROOT_SOURCE_SEL(0));
> > > + clock_enable(CCGR_UART1, 1);
> > > + return;
> > > + case 1:
> > > + clock_enable(CCGR_UART2, 0);
> > > + clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON
> > > |
> > > + CLK_ROOT_SOURCE_SEL(0));
> > > + clock_enable(CCGR_UART2, 1);
> > > + return;
> > > + case 2:
> > > + clock_enable(CCGR_UART3, 0);
> > > + clock_set_target_val(UART3_CLK_ROOT, CLK_ROOT_ON
> > > |
> > > + CLK_ROOT_SOURCE_SEL(0));
> > > + clock_enable(CCGR_UART3, 1);
> > > + return;
> > > + case 3:
> > > + clock_enable(CCGR_UART4, 0);
> > > + clock_set_target_val(UART4_CLK_ROOT, CLK_ROOT_ON
> > > |
> > > + CLK_ROOT_SOURCE_SEL(0));
> > > + clock_enable(CCGR_UART4, 1);
> > > + return;
> > > + default:
> > > + printf("Invalid uart index\n");
> > > + return;
> > > + }
> > > +}
> > > +
> > > +void init_wdog_clk(void)
> > > +{
> > > + clock_enable(CCGR_WDOG1, 0);
> > > + clock_enable(CCGR_WDOG2, 0);
> > > + clock_enable(CCGR_WDOG3, 0);
> > > + clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
> > > + CLK_ROOT_SOURCE_SEL(0));
> > > + clock_enable(CCGR_WDOG1, 1);
> > > + clock_enable(CCGR_WDOG2, 1);
> > > + clock_enable(CCGR_WDOG3, 1);
> > > +}
> > > +
> > > +void init_clk_usdhc(u32 index)
> > > +{
> > > + /*
> > > + * set usdhc clock root
> > > + * sys pll1 400M
> > > + */
> > > + switch (index) {
> > > + case 0:
> > > + clock_enable(CCGR_USDHC1, 0);
> > > + clock_set_target_val(USDHC1_CLK_ROOT,
> > > CLK_ROOT_ON |
> > > + CLK_ROOT_SOURCE_SEL(1) |
> > > +
> > > CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
> > > + clock_enable(CCGR_USDHC1, 1);
> > > + return;
> > > + case 1:
> > > + clock_enable(CCGR_USDHC2, 0);
> > > + clock_set_target_val(USDHC2_CLK_ROOT,
> > > CLK_ROOT_ON |
> > > + CLK_ROOT_SOURCE_SEL(1) |
> > > +
> > > CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
> > > + clock_enable(CCGR_USDHC2, 1);
> > > + return;
> > > + case 2:
> > > + clock_enable(CCGR_USDHC3, 0);
> > > + clock_set_target_val(USDHC3_CLK_ROOT,
> > > CLK_ROOT_ON |
> > > + CLK_ROOT_SOURCE_SEL(1) |
> > > +
> > > CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
> > > + clock_enable(CCGR_USDHC3, 1);
> > > + return;
> > > + default:
> > > + printf("Invalid usdhc index\n");
> > > + return;
> > > + }
> > > +}
> > > +
> > > +int clock_init(void)
> > > +{
> > > + u32 val_cfg0;
> > > +
> > > + /* Configure ARM at 1GHz */
> > > + clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
> > > + CLK_ROOT_SOURCE_SEL(0));
> > > +
> > > + intpll_configure(ANATOP_ARM_PLL, MHZ(1200));
> > > +
> > > + clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
> > > + CLK_ROOT_SOURCE_SEL(1) |
> > > +
> > > CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1)); +
> > > + /*
> > > + * According to ANAMIX SPEC
> > > + * sys pll1 fixed at 800MHz
> > > + * sys pll2 fixed at 1GHz
> > > + * Here we only enable the outputs.
> > > + */
> > > + val_cfg0 = readl(&ana_pll->sys_pll1_gnrl_ctl);
> > > + val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK |
> > > + INTPLL_DIV3_CLKE_MASK | INTPLL_DIV4_CLKE_MASK |
> > > + INTPLL_DIV5_CLKE_MASK | INTPLL_DIV6_CLKE_MASK |
> > > + INTPLL_DIV8_CLKE_MASK | INTPLL_DIV10_CLKE_MASK |
> > > + INTPLL_DIV20_CLKE_MASK;
> > > + writel(val_cfg0, &ana_pll->sys_pll1_gnrl_ctl);
> > > +
> > > + val_cfg0 = readl(&ana_pll->sys_pll2_gnrl_ctl);
> > > + val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK |
> > > + INTPLL_DIV3_CLKE_MASK | INTPLL_DIV4_CLKE_MASK |
> > > + INTPLL_DIV5_CLKE_MASK | INTPLL_DIV6_CLKE_MASK |
> > > + INTPLL_DIV8_CLKE_MASK | INTPLL_DIV10_CLKE_MASK |
> > > + INTPLL_DIV20_CLKE_MASK;
> > > + writel(val_cfg0, &ana_pll->sys_pll2_gnrl_ctl);
> > > +
> > > + intpll_configure(ANATOP_SYSTEM_PLL3, MHZ(750));
> > > + clock_set_target_val(NOC_CLK_ROOT, CLK_ROOT_ON |
> > > + CLK_ROOT_SOURCE_SEL(2));
> > > +
> > > + /* config GIC to sys_pll2_100m */
> > > + clock_enable(CCGR_GIC, 0);
> > > + clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON |
> > > + CLK_ROOT_SOURCE_SEL(3));
> > > + clock_enable(CCGR_GIC, 1);
> > > +
> > > + clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT,
> > > CLK_ROOT_ON |
> > > + CLK_ROOT_SOURCE_SEL(1));
> > > +
> > > + clock_enable(CCGR_DDR1, 0);
> > > + clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
> > > + CLK_ROOT_SOURCE_SEL(1));
> > > + clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
> > > + CLK_ROOT_SOURCE_SEL(1));
> > > + clock_enable(CCGR_DDR1, 1);
> > > +
> > > + init_wdog_clk();
> > > +
> > > + clock_enable(CCGR_TEMP_SENSOR, 1);
> > > +
> > > + clock_enable(CCGR_SEC_DEBUG, 1);
> > > +
> > > + return 0;
> > > +};
> > > +
> > > +int set_clk_qspi(void)
> > > +{
> > > + /*
> > > + * set qspi root
> > > + * sys pll1 100M
> > > + */
> > > + clock_enable(CCGR_QSPI, 0);
> > > + clock_set_target_val(QSPI_CLK_ROOT, CLK_ROOT_ON |
> > > + CLK_ROOT_SOURCE_SEL(7));
> > > + clock_enable(CCGR_QSPI, 1);
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +#ifdef CONFIG_FEC_MXC
> > > +int set_clk_enet(enum enet_freq type)
> > > +{
> > > + u32 target;
> > > + u32 enet1_ref;
> > > +
> > > + /* disable the clock first */
> > > + clock_enable(CCGR_ENET1, 0);
> > > + clock_enable(CCGR_SIM_ENET, 0);
> > > +
> > > + switch (type) {
> > > + case ENET_125MHZ:
> > > + enet1_ref =
> > > ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
> > > + break;
> > > + case ENET_50MHZ:
> > > + enet1_ref =
> > > ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
> > > + break;
> > > + case ENET_25MHZ:
> > > + enet1_ref =
> > > ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
> > > + break;
> > > + default:
> > > + return -EINVAL;
> > > + }
> > > +
> > > + /* set enet axi clock 266Mhz */
> > > + target = CLK_ROOT_ON |
> > ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
> > > + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
> > > + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
> > > + clock_set_target_val(ENET_AXI_CLK_ROOT, target);
> > > +
> > > + target = CLK_ROOT_ON | enet1_ref |
> > > + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
> > > + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
> > > + clock_set_target_val(ENET_REF_CLK_ROOT, target);
> > > +
> > > + target = CLK_ROOT_ON |
> > > ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
> > > + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
> > > + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
> > > + clock_set_target_val(ENET_TIMER_CLK_ROOT, target);
> > > +
> > > +#ifdef CONFIG_FEC_MXC_25M_REF_CLK
> > > + target = CLK_ROOT_ON |
> > > +
> > > ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK |
> > > + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
> > > + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
> > > + clock_set_target_val(ENET_PHY_REF_CLK_ROOT, target);
> > > +#endif
> > > + /* enable clock */
> > > + clock_enable(CCGR_SIM_ENET, 1);
> > > + clock_enable(CCGR_ENET1, 1);
> > > +
> > > + return 0;
> > > +}
> > > +#endif
> > > +
> > > +u32 get_root_src_clk(enum clk_root_src root_src)
> > > +{
> > > + switch (root_src) {
> > > + case OSC_24M_CLK:
> > > + return 24000000u;
> > > + case OSC_HDMI_CLK:
> > > + return 26000000u;
> > > + case OSC_32K_CLK:
> > > + return 32000u;
> > > + case ARM_PLL_CLK:
> > > + case GPU_PLL_CLK:
> > > + case VPU_PLL_CLK:
> > > + case SYSTEM_PLL1_800M_CLK:
> > > + case SYSTEM_PLL1_400M_CLK:
> > > + case SYSTEM_PLL1_266M_CLK:
> > > + case SYSTEM_PLL1_200M_CLK:
> > > + case SYSTEM_PLL1_160M_CLK:
> > > + case SYSTEM_PLL1_133M_CLK:
> > > + case SYSTEM_PLL1_100M_CLK:
> > > + case SYSTEM_PLL1_80M_CLK:
> > > + case SYSTEM_PLL1_40M_CLK:
> > > + case SYSTEM_PLL2_1000M_CLK:
> > > + case SYSTEM_PLL2_500M_CLK:
> > > + case SYSTEM_PLL2_333M_CLK:
> > > + case SYSTEM_PLL2_250M_CLK:
> > > + case SYSTEM_PLL2_200M_CLK:
> > > + case SYSTEM_PLL2_166M_CLK:
> > > + case SYSTEM_PLL2_125M_CLK:
> > > + case SYSTEM_PLL2_100M_CLK:
> > > + case SYSTEM_PLL2_50M_CLK:
> > > + case SYSTEM_PLL3_CLK:
> > > + return decode_intpll(root_src);
> > > + case DRAM_PLL1_CLK:
> > > + case AUDIO_PLL1_CLK:
> > > + case AUDIO_PLL2_CLK:
> > > + case VIDEO_PLL_CLK:
> > > + return decode_fracpll(root_src);
> > > + default:
> > > + return 0;
> > > + }
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +u32 get_root_clk(enum clk_root_index clock_id)
> > > +{
> > > + enum clk_root_src root_src;
> > > + u32 post_podf, pre_podf, root_src_clk;
> > > +
> > > + if (clock_root_enabled(clock_id) <= 0)
> > > + return 0;
> > > +
> > > + if (clock_get_prediv(clock_id, &pre_podf) < 0)
> > > + return 0;
> > > +
> > > + if (clock_get_postdiv(clock_id, &post_podf) < 0)
> > > + return 0;
> > > +
> > > + if (clock_get_src(clock_id, &root_src) < 0)
> > > + return 0;
> > > +
> > > + root_src_clk = get_root_src_clk(root_src);
> > > +
> > > + return root_src_clk / (post_podf + 1) / (pre_podf + 1);
> > > +}
> > > +
> > > +u32 mxc_get_clock(enum mxc_clock clk)
> > > +{
> > > + u32 val;
> > > +
> > > + switch (clk) {
> > > + case MXC_ARM_CLK:
> > > + return get_root_clk(ARM_A53_CLK_ROOT);
> > > + case MXC_IPG_CLK:
> > > + clock_get_target_val(IPG_CLK_ROOT, &val);
> > > + val = val & 0x3;
> > > + return get_root_clk(AHB_CLK_ROOT) / 2 / (val +
> > > 1);
> > > + case MXC_CSPI_CLK:
> > > + return get_root_clk(ECSPI1_CLK_ROOT);
> > > + case MXC_ESDHC_CLK:
> > > + return get_root_clk(USDHC1_CLK_ROOT);
> > > + case MXC_ESDHC2_CLK:
> > > + return get_root_clk(USDHC2_CLK_ROOT);
> > > + case MXC_ESDHC3_CLK:
> > > + return get_root_clk(USDHC3_CLK_ROOT);
> > > + case MXC_I2C_CLK:
> > > + return get_root_clk(I2C1_CLK_ROOT);
> > > + case MXC_UART_CLK:
> > > + return get_root_clk(UART1_CLK_ROOT);
> > > + case MXC_QSPI_CLK:
> > > + return get_root_clk(QSPI_CLK_ROOT);
> > > + default:
> > > + printf("Unsupported mxc_clock %d\n", clk);
> > > + break;
> > > + }
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +u32 imx_get_uartclk(void)
> > > +{
> > > + return mxc_get_clock(MXC_UART_CLK);
> > > +}
> > > +
> > > +u32 imx_get_fecclk(void)
> > > +{
> > > + return get_root_clk(ENET_AXI_CLK_ROOT);
> > > +}
> > > +
> > > +/*
> > > + * Dump some clockes.
> > > + */
> > > +#ifndef CONFIG_SPL_BUILD
> > > +int do_mscale_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
> > > + char * const argv[])
> > > +{
> > > + u32 freq;
> > > +
> > > + freq = decode_intpll(ARM_PLL_CLK);
> > > + printf("ARM_PLL %8d MHz\n", freq / 1000000);
> > > + freq = decode_intpll(SYSTEM_PLL1_800M_CLK);
> > > + printf("SYS_PLL1_800 %8d MHz\n", freq / 1000000);
> > > + freq = decode_intpll(SYSTEM_PLL1_400M_CLK);
> > > + printf("SYS_PLL1_400 %8d MHz\n", freq / 1000000);
> > > + freq = decode_intpll(SYSTEM_PLL1_266M_CLK);
> > > + printf("SYS_PLL1_266 %8d MHz\n", freq / 1000000);
> > > + freq = decode_intpll(SYSTEM_PLL1_160M_CLK);
> > > + printf("SYS_PLL1_160 %8d MHz\n", freq / 1000000);
> > > + freq = decode_intpll(SYSTEM_PLL1_133M_CLK);
> > > + printf("SYS_PLL1_133 %8d MHz\n", freq / 1000000);
> > > + freq = decode_intpll(SYSTEM_PLL1_100M_CLK);
> > > + printf("SYS_PLL1_100 %8d MHz\n", freq / 1000000);
> > > + freq = decode_intpll(SYSTEM_PLL1_80M_CLK);
> > > + printf("SYS_PLL1_80 %8d MHz\n", freq / 1000000);
> > > + freq = decode_intpll(SYSTEM_PLL1_40M_CLK);
> > > + printf("SYS_PLL1_40 %8d MHz\n", freq / 1000000);
> > > + freq = decode_intpll(SYSTEM_PLL2_1000M_CLK);
> > > + printf("SYS_PLL2_1000 %8d MHz\n", freq / 1000000);
> > > + freq = decode_intpll(SYSTEM_PLL2_500M_CLK);
> > > + printf("SYS_PLL2_500 %8d MHz\n", freq / 1000000);
> > > + freq = decode_intpll(SYSTEM_PLL2_333M_CLK);
> > > + printf("SYS_PLL2_333 %8d MHz\n", freq / 1000000);
> > > + freq = decode_intpll(SYSTEM_PLL2_250M_CLK);
> > > + printf("SYS_PLL2_250 %8d MHz\n", freq / 1000000);
> > > + freq = decode_intpll(SYSTEM_PLL2_200M_CLK);
> > > + printf("SYS_PLL2_200 %8d MHz\n", freq / 1000000);
> > > + freq = decode_intpll(SYSTEM_PLL2_166M_CLK);
> > > + printf("SYS_PLL2_166 %8d MHz\n", freq / 1000000);
> > > + freq = decode_intpll(SYSTEM_PLL2_125M_CLK);
> > > + printf("SYS_PLL2_125 %8d MHz\n", freq / 1000000);
> > > + freq = decode_intpll(SYSTEM_PLL2_100M_CLK);
> > > + printf("SYS_PLL2_100 %8d MHz\n", freq / 1000000);
> > > + freq = decode_intpll(SYSTEM_PLL2_50M_CLK);
> > > + printf("SYS_PLL2_50 %8d MHz\n", freq / 1000000);
> > > + freq = decode_intpll(SYSTEM_PLL3_CLK);
> > > + printf("SYS_PLL3 %8d MHz\n", freq / 1000000);
> > > + freq = mxc_get_clock(MXC_UART_CLK);
> > > + printf("UART1 %8d MHz\n", freq / 1000000);
> > > + freq = mxc_get_clock(MXC_ESDHC_CLK);
> > > + printf("USDHC1 %8d MHz\n", freq / 1000000);
> > > + freq = mxc_get_clock(MXC_QSPI_CLK);
> > > + printf("QSPI %8d MHz\n", freq / 1000000);
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +U_BOOT_CMD(
> > > + clocks, CONFIG_SYS_MAXARGS, 1,
> > > do_mscale_showclocks,
> > > + "display clocks",
> > > + ""
> > > +);
> > > +#endif
> > > diff --git a/arch/arm/mach-imx/imx8m/clock_slice.c
> > > b/arch/arm/mach-imx/imx8m/clock_slice.c index
> > > 1a67c626f1..dc2a018e00 100644 ---
> > > a/arch/arm/mach-imx/imx8m/clock_slice.c +++
> > > b/arch/arm/mach-imx/imx8m/clock_slice.c @@ -13,6 +13,7 @@
> > >
> > > static struct ccm_reg *ccm_reg = (struct ccm_reg *)CCM_BASE_ADDR;
> > >
> > > +#ifdef CONFIG_IMX8MQ
> > > static struct clk_root_map root_array[] = {
> > > {ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0,
> > > {OSC_25M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
> > > @@ -474,6 +475,466 @@ static struct clk_root_map root_array[] = {
> > > {DRAM_PLL1_CLK}
> > > },
> > > };
> > > +#elif defined(CONFIG_IMX8MM)
> > > +static struct clk_root_map root_array[] = {
> > > + {ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0,
> > > + {OSC_24M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
> > > + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
> > > + SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL3_CLK}
> > > + },
> > > + {ARM_M4_CLK_ROOT, CORE_CLOCK_SLICE, 1,
> > > + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK,
> > > SYSTEM_PLL2_250M_CLK,
> > > + SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
> > > + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
> > > + },
> > > + {VPU_A53_CLK_ROOT, CORE_CLOCK_SLICE, 2,
> > > + {OSC_24M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
> > > + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
> > > + SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, VPU_PLL_CLK}
> > > + },
> > > + {GPU3D_CLK_ROOT, CORE_CLOCK_SLICE, 3,
> > > + {OSC_24M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
> > > + SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
> > > + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
> > > + },
> > > + {GPU2D_CLK_ROOT, CORE_CLOCK_SLICE, 4,
> > > + {OSC_24M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
> > > + SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
> > > + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
> > > + },
> > > + {MAIN_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 0,
> > > + {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK,
> > > SYSTEM_PLL1_800M_CLK,
> > > + SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_1000M_CLK,
> > > + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL1_100M_CLK}
> > > + },
> > > + {ENET_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 1,
> > > + {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK,
> > > SYSTEM_PLL1_800M_CLK,
> > > + SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
> > > + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
> > > + },
> > > + {NAND_USDHC_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 2,
> > > + {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK,
> > > SYSTEM_PLL1_800M_CLK,
> > > + SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK,
> > > + SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL1_CLK}
> > > + },
> > > + {VPU_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 3,
> > > + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, VPU_PLL_CLK,
> > > + AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
> > > + SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_100M_CLK}
> > > + },
> > > + {DISPLAY_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 4,
> > > + {OSC_24M_CLK, SYSTEM_PLL2_1000M_CLK,
> > SYSTEM_PLL1_800M_CLK,
> > > + SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK, AUDIO_PLL2_CLK,
> > > + EXT_CLK_1, EXT_CLK_4}
> > > + },
> > > + {DISPLAY_APB_CLK_ROOT, BUS_CLOCK_SLICE, 5,
> > > + {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK,
> > > SYSTEM_PLL1_800M_CLK,
> > > + SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK, AUDIO_PLL2_CLK,
> > > + EXT_CLK_1, EXT_CLK_3}
> > > + },
> > > + {DISPLAY_RTRM_CLK_ROOT, BUS_CLOCK_SLICE, 6,
> > > + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK,
> > > SYSTEM_PLL2_200M_CLK,
> > > + SYSTEM_PLL2_1000M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
> > > + EXT_CLK_2, EXT_CLK_3}
> > > + },
> > > + {USB_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 7,
> > > + {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK,
> > > SYSTEM_PLL1_800M_CLK,
> > > + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
> > > + EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
> > > + },
> > > + {GPU_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 8,
> > > + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
> > > + SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
> > > + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
> > > + },
> > > + {GPU_AHB_CLK_ROOT, BUS_CLOCK_SLICE, 9,
> > > + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
> > > + SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
> > > + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
> > > + },
> > > + {NOC_CLK_ROOT, BUS_CLOCK_SLICE, 10,
> > > + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK,
> > > + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK,
> > > + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
> > > + },
> > > + {NOC_APB_CLK_ROOT, BUS_CLOCK_SLICE, 11,
> > > + {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL3_CLK,
> > > + SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_200M_CLK,
> > > + SYSTEM_PLL1_800M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
> > > + },
> > > + {AHB_CLK_ROOT, AHB_CLOCK_SLICE, 0,
> > > + {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK,
> > > SYSTEM_PLL1_800M_CLK,
> > > + SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_125M_CLK,
> > > + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
> > > + },
> > > + {AUDIO_AHB_CLK_ROOT, AHB_CLOCK_SLICE, 1,
> > > + {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK,
> > > SYSTEM_PLL1_800M_CLK,
> > > + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_166M_CLK,
> > > + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
> > > + },
> > > + {MIPI_DSI_ESC_RX_CLK_ROOT, AHB_CLOCK_SLICE, 2,
> > > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
> > > + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> > > + SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
> > > + },
> > > + {DRAM_ALT_CLK_ROOT, IP_CLOCK_SLICE, 0,
> > > + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK,
> > > SYSTEM_PLL1_100M_CLK,
> > > + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_1000M_CLK,
> > > + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL1_266M_CLK}
> > > + },
> > > + {DRAM_APB_CLK_ROOT, IP_CLOCK_SLICE, 1,
> > > + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
> > > + SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
> > > + SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
> > > + },
> > > + {VPU_G1_CLK_ROOT, IP_CLOCK_SLICE, 2,
> > > + {OSC_24M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
> > > + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_100M_CLK,
> > > + SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
> > > + },
> > > + {VPU_G2_CLK_ROOT, IP_CLOCK_SLICE, 3,
> > > + {OSC_24M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
> > > + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_100M_CLK,
> > > + SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
> > > + },
> > > + {DISPLAY_DTRC_CLK_ROOT, IP_CLOCK_SLICE, 4,
> > > + {OSC_24M_CLK, VIDEO_PLL2_CLK, SYSTEM_PLL1_800M_CLK,
> > > + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_160M_CLK,
> > > + VIDEO_PLL_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK}
> > > + },
> > > + {DISPLAY_DC8000_CLK_ROOT, IP_CLOCK_SLICE, 5,
> > > + {OSC_24M_CLK, VIDEO_PLL2_CLK, SYSTEM_PLL1_800M_CLK,
> > > + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_160M_CLK,
> > > + VIDEO_PLL_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK}
> > > + },
> > > + {PCIE_CTRL_CLK_ROOT, IP_CLOCK_SLICE, 6,
> > > + {OSC_24M_CLK, SYSTEM_PLL2_250M_CLK,
> > > SYSTEM_PLL2_200M_CLK,
> > > + SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
> > > + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_333M_CLK,
> > > SYSTEM_PLL3_CLK}
> > > + },
> > > + {PCIE_PHY_CLK_ROOT, IP_CLOCK_SLICE, 7,
> > > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK,
> > > SYSTEM_PLL2_500M_CLK,
> > > + EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
> > > + SYSTEM_PLL1_400M_CLK}
> > > + },
> > > + {PCIE_AUX_CLK_ROOT, IP_CLOCK_SLICE, 8,
> > > + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_50M_CLK,
> > > + SYSTEM_PLL3_CLK, SYSTEM_PLL2_100M_CLK,
> > SYSTEM_PLL1_80M_CLK,
> > > + SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_200M_CLK}
> > > + },
> > > + {DC_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 9,
> > > + {OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
> > > + AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
> > > + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
> > > + },
> > > + {LCDIF_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 10,
> > > + {OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
> > > + AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
> > > + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
> > > + },
> > > + {SAI1_CLK_ROOT, IP_CLOCK_SLICE, 11,
> > > + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
> > > + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
> > > + OSC_HDMI_CLK, EXT_CLK_1, EXT_CLK_2}
> > > + },
> > > + {SAI2_CLK_ROOT, IP_CLOCK_SLICE, 12,
> > > + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
> > > + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
> > > + OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
> > > + },
> > > + {SAI3_CLK_ROOT, IP_CLOCK_SLICE, 13,
> > > + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
> > > + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
> > > + OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
> > > + },
> > > + {SAI4_CLK_ROOT, IP_CLOCK_SLICE, 14,
> > > + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
> > > + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
> > > + OSC_HDMI_CLK, EXT_CLK_1, EXT_CLK_2}
> > > + },
> > > + {SAI5_CLK_ROOT, IP_CLOCK_SLICE, 15,
> > > + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
> > > + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
> > > + OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
> > > + },
> > > + {SAI6_CLK_ROOT, IP_CLOCK_SLICE, 16,
> > > + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
> > > + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
> > > + OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
> > > + },
> > > + {SPDIF1_CLK_ROOT, IP_CLOCK_SLICE, 17,
> > > + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
> > > + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
> > > + OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
> > > + },
> > > + {SPDIF2_CLK_ROOT, IP_CLOCK_SLICE, 18,
> > > + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
> > > + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
> > > + OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
> > > + },
> > > + {ENET_REF_CLK_ROOT, IP_CLOCK_SLICE, 19,
> > > + {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_50M_CLK,
> > > + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
> > > + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, EXT_CLK_4}
> > > + },
> > > + {ENET_TIMER_CLK_ROOT, IP_CLOCK_SLICE, 20,
> > > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK,
> > > + EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
> > > + VIDEO_PLL_CLK}
> > > + },
> > > + {ENET_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 21,
> > > + {OSC_24M_CLK, SYSTEM_PLL2_50M_CLK, SYSTEM_PLL2_125M_CLK,
> > > + SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_500M_CLK,
> > > + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
> > > + },
> > > + {NAND_CLK_ROOT, IP_CLOCK_SLICE, 22,
> > > + {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, AUDIO_PLL1_CLK,
> > > + SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK,
> > > + SYSTEM_PLL2_250M_CLK, VIDEO_PLL_CLK}
> > > + },
> > > + {QSPI_CLK_ROOT, IP_CLOCK_SLICE, 23,
> > > + {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK,
> > > SYSTEM_PLL2_333M_CLK,
> > > + SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK,
> > > + SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK,
> > > SYSTEM_PLL1_100M_CLK}
> > > + },
> > > + {USDHC1_CLK_ROOT, IP_CLOCK_SLICE, 24,
> > > + {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK,
> > > SYSTEM_PLL1_800M_CLK,
> > > + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
> > > + SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK,
> > SYSTEM_PLL1_100M_CLK}
> > > + },
> > > + {USDHC2_CLK_ROOT, IP_CLOCK_SLICE, 25,
> > > + {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK,
> > > SYSTEM_PLL1_800M_CLK,
> > > + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
> > > + SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK,
> > SYSTEM_PLL1_100M_CLK}
> > > + },
> > > + {I2C1_CLK_ROOT, IP_CLOCK_SLICE, 26,
> > > + {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
> > > + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
> > > + AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
> > > + },
> > > + {I2C2_CLK_ROOT, IP_CLOCK_SLICE, 27,
> > > + {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
> > > + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
> > > + AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
> > > + },
> > > + {I2C3_CLK_ROOT, IP_CLOCK_SLICE, 28,
> > > + {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
> > > + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
> > > + AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
> > > + },
> > > + {I2C4_CLK_ROOT, IP_CLOCK_SLICE, 29,
> > > + {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
> > > + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
> > > + AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
> > > + },
> > > + {UART1_CLK_ROOT, IP_CLOCK_SLICE, 30,
> > > + {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
> > > + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
> > > + EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
> > > + },
> > > + {UART2_CLK_ROOT, IP_CLOCK_SLICE, 31,
> > > + {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
> > > + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
> > > + EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
> > > + },
> > > + {UART3_CLK_ROOT, IP_CLOCK_SLICE, 32,
> > > + {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
> > > + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
> > > + EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
> > > + },
> > > + {UART4_CLK_ROOT, IP_CLOCK_SLICE, 33,
> > > + {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
> > > + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
> > > + EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
> > > + },
> > > + {USB_CORE_REF_CLK_ROOT, IP_CLOCK_SLICE, 34,
> > > + {OSC_24M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
> > > + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
> > > + EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
> > > + },
> > > + {USB_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 35,
> > > + {OSC_24M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
> > > + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
> > > + EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
> > > + },
> > > + {GIC_CLK_ROOT, IP_CLOCK_SLICE, 36,
> > > + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
> > > + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_800M_CLK,
> > > + EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
> > > + },
> > > + {ECSPI1_CLK_ROOT, IP_CLOCK_SLICE, 37,
> > > + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
> > > + SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
> > > + SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
> > > + },
> > > + {ECSPI2_CLK_ROOT, IP_CLOCK_SLICE, 38,
> > > + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
> > > + SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
> > > + SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
> > > + },
> > > + {PWM1_CLK_ROOT, IP_CLOCK_SLICE, 39,
> > > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK,
> > > SYSTEM_PLL1_160M_CLK,
> > > + SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
> > > + SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
> > > + },
> > > + {PWM2_CLK_ROOT, IP_CLOCK_SLICE, 40,
> > > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK,
> > > SYSTEM_PLL1_160M_CLK,
> > > + SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
> > > + SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
> > > + },
> > > + {PWM3_CLK_ROOT, IP_CLOCK_SLICE, 41,
> > > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK,
> > > SYSTEM_PLL1_160M_CLK,
> > > + SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2,
> > > + SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
> > > + },
> > > + {PWM4_CLK_ROOT, IP_CLOCK_SLICE, 42,
> > > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK,
> > > SYSTEM_PLL1_160M_CLK,
> > > + SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2,
> > > + SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
> > > + },
> > > + {GPT1_CLK_ROOT, IP_CLOCK_SLICE, 43,
> > > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK,
> > > SYSTEM_PLL1_400M_CLK,
> > > + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
> > > + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
> > > + },
> > > + {GPT2_CLK_ROOT, IP_CLOCK_SLICE, 44,
> > > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK,
> > > SYSTEM_PLL1_400M_CLK,
> > > + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
> > > + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
> > > + },
> > > + {GPT3_CLK_ROOT, IP_CLOCK_SLICE, 45,
> > > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK,
> > > SYSTEM_PLL1_400M_CLK,
> > > + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
> > > + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
> > > + },
> > > + {GPT4_CLK_ROOT, IP_CLOCK_SLICE, 46,
> > > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK,
> > > SYSTEM_PLL1_400M_CLK,
> > > + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
> > > + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
> > > + },
> > > + {GPT5_CLK_ROOT, IP_CLOCK_SLICE, 47,
> > > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK,
> > > SYSTEM_PLL1_400M_CLK,
> > > + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
> > > + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
> > > + },
> > > + {GPT6_CLK_ROOT, IP_CLOCK_SLICE, 48,
> > > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK,
> > > SYSTEM_PLL1_400M_CLK,
> > > + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
> > > + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
> > > + },
> > > + {TRACE_CLK_ROOT, IP_CLOCK_SLICE, 49,
> > > + {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK,
> > > SYSTEM_PLL1_160M_CLK,
> > > + VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
> > > + SYSTEM_PLL3_CLK, EXT_CLK_1, EXT_CLK_3}
> > > + },
> > > + {WDOG_CLK_ROOT, IP_CLOCK_SLICE, 50,
> > > + {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK,
> > > SYSTEM_PLL1_160M_CLK,
> > > + VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
> > > + SYSTEM_PLL3_CLK, SYSTEM_PLL1_80M_CLK,
> > SYSTEM_PLL2_166M_CLK}
> > > + },
> > > + {WRCLK_CLK_ROOT, IP_CLOCK_SLICE, 51,
> > > + {OSC_24M_CLK, SYSTEM_PLL1_40M_CLK, VPU_PLL_CLK,
> > > + SYSTEM_PLL3_CLK, SYSTEM_PLL2_200M_CLK,
> > > + SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_500M_CLK,
> > > SYSTEM_PLL1_100M_CLK}
> > > + },
> > > + {IPP_DO_CLKO1, IP_CLOCK_SLICE, 52,
> > > + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, OSC_HDMI_CLK,
> > > + SYSTEM_PLL1_200M_CLK, AUDIO_PLL2_CLK,
> > > + SYSTEM_PLL2_500M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_80M_CLK}
> > > + },
> > > + {IPP_DO_CLKO2, IP_CLOCK_SLICE, 53,
> > > + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK,
> > > SYSTEM_PLL1_400M_CLK,
> > > + SYSTEM_PLL2_166M_CLK, SYSTEM_PLL3_CLK,
> > > + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, OSC_32K_CLK}
> > > + },
> > > + {MIPI_DSI_CORE_CLK_ROOT, IP_CLOCK_SLICE, 54,
> > > + {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK,
> > > SYSTEM_PLL2_250M_CLK,
> > > + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> > > + SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
> > > + },
> > > + {MIPI_DSI_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 55,
> > > + {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK,
> > > SYSTEM_PLL2_100M_CLK,
> > > + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> > > + EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
> > > + },
> > > + {MIPI_DSI_DBI_CLK_ROOT, IP_CLOCK_SLICE, 56,
> > > + {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK,
> > > SYSTEM_PLL2_100M_CLK,
> > > + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> > > + SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
> > > + },
> > > + {USDHC3_CLK_ROOT, IP_CLOCK_SLICE, 57,
> > > + {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK,
> > > SYSTEM_PLL1_800M_CLK,
> > > + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
> > > + SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK,
> > SYSTEM_PLL1_100M_CLK}
> > > + },
> > > + {MIPI_CSI1_CORE_CLK_ROOT, IP_CLOCK_SLICE, 58,
> > > + {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK,
> > > SYSTEM_PLL2_250M_CLK,
> > > + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> > > + SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
> > > + },
> > > + {MIPI_CSI1_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 59,
> > > + {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK,
> > > SYSTEM_PLL2_100M_CLK,
> > > + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> > > + EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
> > > + },
> > > + {MIPI_CSI1_ESC_CLK_ROOT, IP_CLOCK_SLICE, 60,
> > > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
> > > + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> > > + SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
> > > + },
> > > + {MIPI_CSI2_CORE_CLK_ROOT, IP_CLOCK_SLICE, 61,
> > > + {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK,
> > > SYSTEM_PLL2_250M_CLK,
> > > + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> > > + SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
> > > + },
> > > + {MIPI_CSI2_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 62,
> > > + {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK,
> > > SYSTEM_PLL2_100M_CLK,
> > > + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> > > + EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
> > > + },
> > > + {MIPI_CSI2_ESC_CLK_ROOT, IP_CLOCK_SLICE, 63,
> > > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
> > > + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> > > + SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
> > > + },
> > > + {PCIE2_CTRL_CLK_ROOT, IP_CLOCK_SLICE, 64,
> > > + {OSC_24M_CLK, SYSTEM_PLL2_250M_CLK,
> > > SYSTEM_PLL2_200M_CLK,
> > > + SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
> > > + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_333M_CLK,
> > > SYSTEM_PLL3_CLK}
> > > + },
> > > + {PCIE2_PHY_CLK_ROOT, IP_CLOCK_SLICE, 65,
> > > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK,
> > > SYSTEM_PLL2_500M_CLK,
> > > + EXT_CLK_1, EXT_CLK_2, EXT_CLK_3,
> > > + EXT_CLK_4, SYSTEM_PLL1_400M_CLK}
> > > + },
> > > + {PCIE2_AUX_CLK_ROOT, IP_CLOCK_SLICE, 66,
> > > + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_50M_CLK,
> > > + SYSTEM_PLL3_CLK, SYSTEM_PLL2_100M_CLK,
> > > + SYSTEM_PLL1_80M_CLK, SYSTEM_PLL1_160M_CLK,
> > > SYSTEM_PLL1_200M_CLK}
> > > + },
> > > + {ECSPI3_CLK_ROOT, IP_CLOCK_SLICE, 67,
> > > + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
> > > + SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
> > > + SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
> > > + },
> > > + {PDM_CLK_ROOT, IP_CLOCK_SLICE, 68,
> > > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK,
> > > + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> > > + SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK},
> > > + },
> > > + {VPU_H1_CLK_ROOT, IP_CLOCK_SLICE, 69,
> > > + {OSC_24M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
> > > + SYSTEM_PLL2_1000M_CLK, AUDIO_PLL2_CLK,
> > > + SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
> > > + },
> > > + {DRAM_SEL_CFG, DRAM_SEL_CLOCK_SLICE, 0,
> > > + {DRAM_PLL1_CLK}
> > > + },
> > > + {CORE_SEL_CFG, CORE_SEL_CLOCK_SLICE, 0,
> > > + {DRAM_PLL1_CLK}
> > > + },
> > > +};
> > > +#endif
> > >
> > > static int select(enum clk_root_index clock_id)
> > > {
> >
> >
> >
> >
> > Best regards,
> >
> > Lukasz Majewski
> >
> > --
> >
> > DENX Software Engineering GmbH, Managing Director: Wolfgang
> > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell,
> > Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> > lukma at denx.de
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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^ permalink raw reply [flat|nested] 39+ messages in thread* [U-Boot] [PATCH 10/20] imx8m: add clk support for i.MX8MM
2019-01-30 6:46 ` Lukasz Majewski
@ 2019-01-30 6:56 ` Peng Fan
2019-01-30 8:22 ` Lukasz Majewski
0 siblings, 1 reply; 39+ messages in thread
From: Peng Fan @ 2019-01-30 6:56 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: Lukasz Majewski [mailto:lukma at denx.de]
> Sent: 2019年1月30日 14:47
> To: Peng Fan <peng.fan@nxp.com>
> Cc: sbabic at denx.de; Fabio Estevam <fabio.estevam@nxp.com>;
> dl-uboot-imx <uboot-imx@nxp.com>; u-boot at lists.denx.de
> Subject: Re: [U-Boot] [PATCH 10/20] imx8m: add clk support for i.MX8MM
>
> Hi Peng,
>
> > Hi Lukasz,
> >
> > > -----Original Message-----
> > > From: Lukasz Majewski [mailto:lukma at denx.de]
> > > Sent: 2019年1月30日 6:55
> > > To: Peng Fan <peng.fan@nxp.com>
> > > Cc: sbabic at denx.de; Fabio Estevam <fabio.estevam@nxp.com>;
> > > dl-uboot-imx <uboot-imx@nxp.com>; u-boot at lists.denx.de
> > > Subject: Re: [U-Boot] [PATCH 10/20] imx8m: add clk support for
> > > i.MX8MM
> > >
> > > Hi Peng,
> > >
> > > > Introduce clk implementation for i.MX8MM, including pll
> > > > configuration, pll decoding, ccm configuration.
> > > >
> > > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > > ---
> > > > arch/arm/include/asm/arch-imx8m/clock.h | 2 +
> > > > arch/arm/include/asm/arch-imx8m/clock_imx8mm.h | 387
> +++++++++++
> > > > arch/arm/mach-imx/imx8m/Makefile | 1 +
> > > > arch/arm/mach-imx/imx8m/clock_imx8mm.c | 866
> > > > +++++++++++++++++++++++++
> > > > arch/arm/mach-imx/imx8m/clock_slice.c | 461
> > > +++++++++++++ 5
> > > > files changed, 1717 insertions(+) create mode 100644
> > > > arch/arm/include/asm/arch-imx8m/clock_imx8mm.h create mode
> 100644
> > > > arch/arm/mach-imx/imx8m/clock_imx8mm.c
> > >
> > > As fair as I see this approach is not similar to the one from Linux
> > > kernel:
> > >
> > >
> https://elixir.bootlin.com/linux/v5.0-rc3/source/drivers/clk/imx/clk-imx8mq.
> > > c
> > > or simpler:
> > >
> https://git.pengutronix.de/cgit/barebox/tree/drivers/clk/imx/clk-imx8mq.c
> > >
> > > Also Fabio pointed out in the other mail that we shall stick to
> > > Linux kernel Common Clock Framework.
> > >
> > > IMHO we shall add the simple CCF look alike code (I'm going to post
> > > imx6q port in a few days).
> >
> > That will be too complicated for SPL and it will bring more efforts
> > when we do pre/post silicon bringup.
>
> If we use OF_PLATDATA to avoid DTB inclusion (and provide necessary
> information for the SPL driver) then we may do the trick.
>
> As of now - the problem is that SPL on IMX{568} get bloated very
> rapidly when converted to DM/DTS..., but this shall not be the case for
> generic EVAL board.
Ok. I'll wait for your work about CCF, then check whether that could
be used on i.MX8MM. On some platform, there are limited SRAM,
hope we not goes into use TPL.
Thanks,
Peng.
>
> >
> > Regards,
> > Peng.
> >
> > >
> > > >
> > > > diff --git a/arch/arm/include/asm/arch-imx8m/clock.h
> > > > b/arch/arm/include/asm/arch-imx8m/clock.h index
> > > > 7225c760fe..ead4b8d3dc 100644 ---
> > > > a/arch/arm/include/asm/arch-imx8m/clock.h +++
> > > > b/arch/arm/include/asm/arch-imx8m/clock.h @@ -7,6 +7,8 @@
> > > >
> > > > #ifdef CONFIG_IMX8MQ
> > > > #include <asm/arch/clock_imx8mq.h>
> > > > +#elif defined(CONFIG_IMX8MM)
> > > > +#include <asm/arch/clock_imx8mm.h>
> > > > #else
> > > > #error "Error no clock.h"
> > > > #endif
> > > > diff --git a/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
> > > > b/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h new file mode
> > > 100644
> > > > index 0000000000..305514a4ec
> > > > --- /dev/null
> > > > +++ b/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
> > > > @@ -0,0 +1,387 @@
> > > > +/* SPDX-License-Identifier: GPL-2.0+ */
> > > > +/*
> > > > + * Copyright 2018-2019 NXP
> > > > + *
> > > > + * Peng Fan <peng.fan@nxp.com>
> > > > + */
> > > > +
> > > > +#ifndef _ASM_ARCH_IMX8MM_CLOCK_H
> > > > +#define _ASM_ARCH_IMX8MM_CLOCK_H
> > > > +
> > > > +#define PLL_1443X_RATE(_rate, _m, _p, _s, _k)
> > > > \
> > > > + {
> > > > \
> > > > + .rate =
> > > > (_rate), \
> > > > + .mdiv =
> > > > (_m), \
> > > > + .pdiv =
> > > > (_p), \
> > > > + .sdiv =
> > > > (_s), \
> > > > + .kdiv =
> > > > (_k), \
> > > > + }
> > > > +
> > > > +#define LOCK_STATUS BIT(31)
> > > > +#define LOCK_SEL_MASK BIT(29)
> > > > +#define CLKE_MASK BIT(11)
> > > > +#define RST_MASK BIT(9)
> > > > +#define BYPASS_MASK BIT(4)
> > > > +#define MDIV_SHIFT 12
> > > > +#define MDIV_MASK GENMASK(21, 12)
> > > > +#define PDIV_SHIFT 4
> > > > +#define PDIV_MASK GENMASK(9, 4)
> > > > +#define SDIV_SHIFT 0
> > > > +#define SDIV_MASK GENMASK(2, 0)
> > > > +#define KDIV_SHIFT 0
> > > > +#define KDIV_MASK GENMASK(15, 0)
> > > > +
> > > > +struct imx_int_pll_rate_table {
> > > > + u32 rate;
> > > > + int mdiv;
> > > > + int pdiv;
> > > > + int sdiv;
> > > > + int kdiv;
> > > > +};
> > > > +
> > > > +enum pll_clocks {
> > > > + ANATOP_ARM_PLL,
> > > > + ANATOP_VPU_PLL,
> > > > + ANATOP_GPU_PLL,
> > > > + ANATOP_SYSTEM_PLL1,
> > > > + ANATOP_SYSTEM_PLL2,
> > > > + ANATOP_SYSTEM_PLL3,
> > > > + ANATOP_AUDIO_PLL1,
> > > > + ANATOP_AUDIO_PLL2,
> > > > + ANATOP_VIDEO_PLL,
> > > > + ANATOP_DRAM_PLL,
> > > > +};
> > > > +
> > > > +enum clk_root_index {
> > > > + ARM_A53_CLK_ROOT = 0,
> > > > + ARM_M4_CLK_ROOT = 1,
> > > > + VPU_A53_CLK_ROOT = 2,
> > > > + GPU3D_CLK_ROOT = 3,
> > > > + GPU2D_CLK_ROOT = 4,
> > > > + MAIN_AXI_CLK_ROOT = 16,
> > > > + ENET_AXI_CLK_ROOT = 17,
> > > > + NAND_USDHC_BUS_CLK_ROOT = 18,
> > > > + VPU_BUS_CLK_ROOT = 19,
> > > > + DISPLAY_AXI_CLK_ROOT = 20,
> > > > + DISPLAY_APB_CLK_ROOT = 21,
> > > > + DISPLAY_RTRM_CLK_ROOT = 22,
> > > > + USB_BUS_CLK_ROOT = 23,
> > > > + GPU_AXI_CLK_ROOT = 24,
> > > > + GPU_AHB_CLK_ROOT = 25,
> > > > + NOC_CLK_ROOT = 26,
> > > > + NOC_APB_CLK_ROOT = 27,
> > > > + AHB_CLK_ROOT = 32,
> > > > + IPG_CLK_ROOT = 33,
> > > > + AUDIO_AHB_CLK_ROOT = 34,
> > > > + MIPI_DSI_ESC_RX_CLK_ROOT = 36,
> > > > + DRAM_SEL_CFG = 48,
> > > > + CORE_SEL_CFG = 49,
> > > > + DRAM_ALT_CLK_ROOT = 64,
> > > > + DRAM_APB_CLK_ROOT = 65,
> > > > + VPU_G1_CLK_ROOT = 66,
> > > > + VPU_G2_CLK_ROOT = 67,
> > > > + DISPLAY_DTRC_CLK_ROOT = 68,
> > > > + DISPLAY_DC8000_CLK_ROOT = 69,
> > > > + PCIE_CTRL_CLK_ROOT = 70,
> > > > + PCIE_PHY_CLK_ROOT = 71,
> > > > + PCIE_AUX_CLK_ROOT = 72,
> > > > + DC_PIXEL_CLK_ROOT = 73,
> > > > + LCDIF_PIXEL_CLK_ROOT = 74,
> > > > + SAI1_CLK_ROOT = 75,
> > > > + SAI2_CLK_ROOT = 76,
> > > > + SAI3_CLK_ROOT = 77,
> > > > + SAI4_CLK_ROOT = 78,
> > > > + SAI5_CLK_ROOT = 79,
> > > > + SAI6_CLK_ROOT = 80,
> > > > + SPDIF1_CLK_ROOT = 81,
> > > > + SPDIF2_CLK_ROOT = 82,
> > > > + ENET_REF_CLK_ROOT = 83,
> > > > + ENET_TIMER_CLK_ROOT = 84,
> > > > + ENET_PHY_REF_CLK_ROOT = 85,
> > > > + NAND_CLK_ROOT = 86,
> > > > + QSPI_CLK_ROOT = 87,
> > > > + USDHC1_CLK_ROOT = 88,
> > > > + USDHC2_CLK_ROOT = 89,
> > > > + I2C1_CLK_ROOT = 90,
> > > > + I2C2_CLK_ROOT = 91,
> > > > + I2C3_CLK_ROOT = 92,
> > > > + I2C4_CLK_ROOT = 93,
> > > > + UART1_CLK_ROOT = 94,
> > > > + UART2_CLK_ROOT = 95,
> > > > + UART3_CLK_ROOT = 96,
> > > > + UART4_CLK_ROOT = 97,
> > > > + USB_CORE_REF_CLK_ROOT = 98,
> > > > + USB_PHY_REF_CLK_ROOT = 99,
> > > > + GIC_CLK_ROOT = 100,
> > > > + ECSPI1_CLK_ROOT = 101,
> > > > + ECSPI2_CLK_ROOT = 102,
> > > > + PWM1_CLK_ROOT = 103,
> > > > + PWM2_CLK_ROOT = 104,
> > > > + PWM3_CLK_ROOT = 105,
> > > > + PWM4_CLK_ROOT = 106,
> > > > + GPT1_CLK_ROOT = 107,
> > > > + GPT2_CLK_ROOT = 108,
> > > > + GPT3_CLK_ROOT = 109,
> > > > + GPT4_CLK_ROOT = 110,
> > > > + GPT5_CLK_ROOT = 111,
> > > > + GPT6_CLK_ROOT = 112,
> > > > + TRACE_CLK_ROOT = 113,
> > > > + WDOG_CLK_ROOT = 114,
> > > > + WRCLK_CLK_ROOT = 115,
> > > > + IPP_DO_CLKO1 = 116,
> > > > + IPP_DO_CLKO2 = 117,
> > > > + MIPI_DSI_CORE_CLK_ROOT = 118,
> > > > + MIPI_DSI_PHY_REF_CLK_ROOT = 119,
> > > > + MIPI_DSI_DBI_CLK_ROOT = 120,
> > > > + USDHC3_CLK_ROOT = 121,
> > > > + MIPI_CSI1_CORE_CLK_ROOT = 122,
> > > > + MIPI_CSI1_PHY_REF_CLK_ROOT = 123,
> > > > + MIPI_CSI1_ESC_CLK_ROOT = 124,
> > > > + MIPI_CSI2_CORE_CLK_ROOT = 125,
> > > > + MIPI_CSI2_PHY_REF_CLK_ROOT = 126,
> > > > + MIPI_CSI2_ESC_CLK_ROOT = 127,
> > > > + PCIE2_CTRL_CLK_ROOT = 128,
> > > > + PCIE2_PHY_CLK_ROOT = 129,
> > > > + PCIE2_AUX_CLK_ROOT = 130,
> > > > + ECSPI3_CLK_ROOT = 131,
> > > > + PDM_CLK_ROOT = 132,
> > > > + VPU_H1_CLK_ROOT = 133,
> > > > + CLK_ROOT_MAX,
> > > > +};
> > > > +
> > > > +enum clk_root_src {
> > > > + OSC_24M_CLK,
> > > > + ARM_PLL_CLK,
> > > > + DRAM_PLL1_CLK,
> > > > + VIDEO_PLL2_CLK,
> > > > + VPU_PLL_CLK,
> > > > + GPU_PLL_CLK,
> > > > + SYSTEM_PLL1_800M_CLK,
> > > > + SYSTEM_PLL1_400M_CLK,
> > > > + SYSTEM_PLL1_266M_CLK,
> > > > + SYSTEM_PLL1_200M_CLK,
> > > > + SYSTEM_PLL1_160M_CLK,
> > > > + SYSTEM_PLL1_133M_CLK,
> > > > + SYSTEM_PLL1_100M_CLK,
> > > > + SYSTEM_PLL1_80M_CLK,
> > > > + SYSTEM_PLL1_40M_CLK,
> > > > + SYSTEM_PLL2_1000M_CLK,
> > > > + SYSTEM_PLL2_500M_CLK,
> > > > + SYSTEM_PLL2_333M_CLK,
> > > > + SYSTEM_PLL2_250M_CLK,
> > > > + SYSTEM_PLL2_200M_CLK,
> > > > + SYSTEM_PLL2_166M_CLK,
> > > > + SYSTEM_PLL2_125M_CLK,
> > > > + SYSTEM_PLL2_100M_CLK,
> > > > + SYSTEM_PLL2_50M_CLK,
> > > > + SYSTEM_PLL3_CLK,
> > > > + AUDIO_PLL1_CLK,
> > > > + AUDIO_PLL2_CLK,
> > > > + VIDEO_PLL_CLK,
> > > > + OSC_32K_CLK,
> > > > + EXT_CLK_1,
> > > > + EXT_CLK_2,
> > > > + EXT_CLK_3,
> > > > + EXT_CLK_4,
> > > > + OSC_HDMI_CLK
> > > > +};
> > > > +
> > > > +enum clk_ccgr_index {
> > > > + CCGR_DVFS = 0,
> > > > + CCGR_ANAMIX = 1,
> > > > + CCGR_CPU = 2,
> > > > + CCGR_CSU = 3,
> > > > + CCGR_DEBUG = 4,
> > > > + CCGR_DDR1 = 5,
> > > > + CCGR_ECSPI1 = 7,
> > > > + CCGR_ECSPI2 = 8,
> > > > + CCGR_ECSPI3 = 9,
> > > > + CCGR_ENET1 = 10,
> > > > + CCGR_GPIO1 = 11,
> > > > + CCGR_GPIO2 = 12,
> > > > + CCGR_GPIO3 = 13,
> > > > + CCGR_GPIO4 = 14,
> > > > + CCGR_GPIO5 = 15,
> > > > + CCGR_GPT1 = 16,
> > > > + CCGR_GPT2 = 17,
> > > > + CCGR_GPT3 = 18,
> > > > + CCGR_GPT4 = 19,
> > > > + CCGR_GPT5 = 20,
> > > > + CCGR_GPT6 = 21,
> > > > + CCGR_HS = 22,
> > > > + CCGR_I2C1 = 23,
> > > > + CCGR_I2C2 = 24,
> > > > + CCGR_I2C3 = 25,
> > > > + CCGR_I2C4 = 26,
> > > > + CCGR_IOMUX = 27,
> > > > + CCGR_IOMUX1 = 28,
> > > > + CCGR_IOMUX2 = 29,
> > > > + CCGR_IOMUX3 = 30,
> > > > + CCGR_IOMUX4 = 31,
> > > > + CCGR_SNVSMIX_IPG_CLK = 32,
> > > > + CCGR_MU = 33,
> > > > + CCGR_OCOTP = 34,
> > > > + CCGR_OCRAM = 35,
> > > > + CCGR_OCRAM_S = 36,
> > > > + CCGR_PCIE = 37,
> > > > + CCGR_PERFMON1 = 38,
> > > > + CCGR_PERFMON2 = 39,
> > > > + CCGR_PWM1 = 40,
> > > > + CCGR_PWM2 = 41,
> > > > + CCGR_PWM3 = 42,
> > > > + CCGR_PWM4 = 43,
> > > > + CCGR_QOS = 44,
> > > > + CCGR_QOS_DISPMIX = 45,
> > > > + CCGR_QOS_ETHENET = 46,
> > > > + CCGR_QSPI = 47,
> > > > + CCGR_RAWNAND = 48,
> > > > + CCGR_RDC = 49,
> > > > + CCGR_ROM = 50,
> > > > + CCGR_SAI1 = 51,
> > > > + CCGR_SAI2 = 52,
> > > > + CCGR_SAI3 = 53,
> > > > + CCGR_SAI4 = 54,
> > > > + CCGR_SAI5 = 55,
> > > > + CCGR_SAI6 = 56,
> > > > + CCGR_SCTR = 57,
> > > > + CCGR_SDMA1 = 58,
> > > > + CCGR_SDMA2 = 59,
> > > > + CCGR_SEC_DEBUG = 60,
> > > > + CCGR_SEMA1 = 61,
> > > > + CCGR_SEMA2 = 62,
> > > > + CCGR_SIM_DISPLAY = 63,
> > > > + CCGR_SIM_ENET = 64,
> > > > + CCGR_SIM_M = 65,
> > > > + CCGR_SIM_MAIN = 66,
> > > > + CCGR_SIM_S = 67,
> > > > + CCGR_SIM_WAKEUP = 68,
> > > > + CCGR_SIM_HSIO = 69,
> > > > + CCGR_SIM_VPU = 70,
> > > > + CCGR_SNVS = 71,
> > > > + CCGR_TRACE = 72,
> > > > + CCGR_UART1 = 73,
> > > > + CCGR_UART2 = 74,
> > > > + CCGR_UART3 = 75,
> > > > + CCGR_UART4 = 76,
> > > > + CCGR_USB_MSCALE_PL301 = 77,
> > > > + CCGR_GPU3D = 79,
> > > > + CCGR_USDHC1 = 81,
> > > > + CCGR_USDHC2 = 82,
> > > > + CCGR_WDOG1 = 83,
> > > > + CCGR_WDOG2 = 84,
> > > > + CCGR_WDOG3 = 85,
> > > > + CCGR_VPUG1 = 86,
> > > > + CCGR_GPU_BUS = 87,
> > > > + CCGR_VPUH1 = 89,
> > > > + CCGR_VPUG2 = 90,
> > > > + CCGR_PDM = 91,
> > > > + CCGR_GIC = 92,
> > > > + CCGR_DISPMIX = 93,
> > > > + CCGR_USDHC3 = 94,
> > > > + CCGR_SDMA3 = 95,
> > > > + CCGR_XTAL = 96,
> > > > + CCGR_PLL = 97,
> > > > + CCGR_TEMP_SENSOR = 98,
> > > > + CCGR_VPUMIX_BUS = 99,
> > > > + CCGR_GPU2D = 102,
> > > > + CCGR_MAX
> > > > +};
> > > > +
> > > > +enum clk_src_index {
> > > > + CLK_SRC_CKIL_SYNC_REQ = 0,
> > > > + CLK_SRC_ARM_PLL_EN = 1,
> > > > + CLK_SRC_GPU_PLL_EN = 2,
> > > > + CLK_SRC_VPU_PLL_EN = 3,
> > > > + CLK_SRC_DRAM_PLL_EN = 4,
> > > > + CLK_SRC_SYSTEM_PLL1_EN = 5,
> > > > + CLK_SRC_SYSTEM_PLL2_EN = 6,
> > > > + CLK_SRC_SYSTEM_PLL3_EN = 7,
> > > > + CLK_SRC_AUDIO_PLL1_EN = 8,
> > > > + CLK_SRC_AUDIO_PLL2_EN = 9,
> > > > + CLK_SRC_VIDEO_PLL1_EN = 10,
> > > > + CLK_SRC_RESERVED = 11,
> > > > + CLK_SRC_ARM_PLL = 12,
> > > > + CLK_SRC_GPU_PLL = 13,
> > > > + CLK_SRC_VPU_PLL = 14,
> > > > + CLK_SRC_DRAM_PLL = 15,
> > > > + CLK_SRC_SYSTEM_PLL1_800M = 16,
> > > > + CLK_SRC_SYSTEM_PLL1_400M = 17,
> > > > + CLK_SRC_SYSTEM_PLL1_266M = 18,
> > > > + CLK_SRC_SYSTEM_PLL1_200M = 19,
> > > > + CLK_SRC_SYSTEM_PLL1_160M = 20,
> > > > + CLK_SRC_SYSTEM_PLL1_133M = 21,
> > > > + CLK_SRC_SYSTEM_PLL1_100M = 22,
> > > > + CLK_SRC_SYSTEM_PLL1_80M = 23,
> > > > + CLK_SRC_SYSTEM_PLL1_40M = 24,
> > > > + CLK_SRC_SYSTEM_PLL2_1000M = 25,
> > > > + CLK_SRC_SYSTEM_PLL2_500M = 26,
> > > > + CLK_SRC_SYSTEM_PLL2_333M = 27,
> > > > + CLK_SRC_SYSTEM_PLL2_250M = 28,
> > > > + CLK_SRC_SYSTEM_PLL2_200M = 29,
> > > > + CLK_SRC_SYSTEM_PLL2_166M = 30,
> > > > + CLK_SRC_SYSTEM_PLL2_125M = 31,
> > > > + CLK_SRC_SYSTEM_PLL2_100M = 32,
> > > > + CLK_SRC_SYSTEM_PLL2_50M = 33,
> > > > + CLK_SRC_SYSTEM_PLL3 = 34,
> > > > + CLK_SRC_AUDIO_PLL1 = 35,
> > > > + CLK_SRC_AUDIO_PLL2 = 36,
> > > > + CLK_SRC_VIDEO_PLL1 = 37,
> > > > +};
> > > > +
> > > > +#define INTPLL_LOCK_MASK BIT(31)
> > > > +#define INTPLL_LOCK_SEL_MASK BIT(29)
> > > > +#define INTPLL_EXT_BYPASS_MASK BIT(28)
> > > > +#define INTPLL_DIV20_CLKE_MASK BIT(27)
> > > > +#define INTPLL_DIV20_CLKE_OVERRIDE_MASK BIT(26)
> > > > +#define INTPLL_DIV10_CLKE_MASK BIT(25)
> > > > +#define INTPLL_DIV10_CLKE_OVERRIDE_MASK BIT(24)
> > > > +#define INTPLL_DIV8_CLKE_MASK BIT(23)
> > > > +#define INTPLL_DIV8_CLKE_OVERRIDE_MASK BIT(22)
> > > > +#define INTPLL_DIV6_CLKE_MASK BIT(21)
> > > > +#define INTPLL_DIV6_CLKE_OVERRIDE_MASK BIT(20)
> > > > +#define INTPLL_DIV5_CLKE_MASK BIT(19)
> > > > +#define INTPLL_DIV5_CLKE_OVERRIDE_MASK BIT(18)
> > > > +#define INTPLL_DIV4_CLKE_MASK BIT(17)
> > > > +#define INTPLL_DIV4_CLKE_OVERRIDE_MASK BIT(16)
> > > > +#define INTPLL_DIV3_CLKE_MASK BIT(15)
> > > > +#define INTPLL_DIV3_CLKE_OVERRIDE_MASK BIT(14)
> > > > +#define INTPLL_DIV2_CLKE_MASK BIT(13)
> > > > +#define INTPLL_DIV2_CLKE_OVERRIDE_MASK BIT(12)
> > > > +#define INTPLL_CLKE_MASK BIT(11)
> > > > +#define INTPLL_CLKE_OVERRIDE_MASK BIT(10)
> > > > +#define INTPLL_RST_MASK BIT(9)
> > > > +#define INTPLL_RST_OVERRIDE_MASK BIT(8)
> > > > +#define INTPLL_BYPASS_MASK BIT(4)
> > > > +#define INTPLL_PAD_CLK_SEL_MASK
> > > > GENMASK(3, 2) +#define
> > > > INTPLL_REF_CLK_SEL_MASK GENMASK(1, 0) +
> > > > +#define INTPLL_MAIN_DIV_MASK GENMASK(21, 12)
> > > > +#define INTPLL_MAIN_DIV_VAL(n) ((n << 12) &
> > > > GENMASK(21, 12)) +#define INTPLL_MAIN_DIV_SHIFT 12
> > > > +#define INTPLL_PRE_DIV_MASK GENMASK(9, 4)
> > > > +#define INTPLL_PRE_DIV_VAL(n) ((n << 4) &
> > > > GENMASK(9, 4)) +#define INTPLL_PRE_DIV_SHIFT 4
> > > > +#define INTPLL_POST_DIV_MASK GENMASK(2, 0)
> > > > +#define INTPLL_POST_DIV_VAL(n) ((n << 0) &
> > > > GENMASK(2, 0)) +#define INTPLL_POST_DIV_SHIFT 0
> > > > +
> > > > +#define INTPLL_LOCK_CON_DLY_MASK GENMASK(5, 4)
> > > > +#define INTPLL_LOCK_CON_DLY_SHIFT 4
> > > > +#define INTPLL_LOCK_CON_OUT_MASK GENMASK(3, 2)
> > > > +#define INTPLL_LOCK_CON_OUT_SHIFT 2
> > > > +#define INTPLL_LOCK_CON_IN_MASK GENMASK(1, 0)
> > > > +#define INTPLL_LOCK_CON_IN_SHIFT 0
> > > > +
> > > > +#define INTPLL_LRD_EN_MASK BIT(21)
> > > > +#define INTPLL_FOUT_MASK BIT(20)
> > > > +#define INTPLL_AFC_SEL_MASK BIT(19)
> > > > +#define INTPLL_PBIAS_CTRL_MASK BIT(18)
> > > > +#define INTPLL_PBIAS_CTRL_EN_MASK BIT(17)
> > > > +#define INTPLL_AFCINIT_SEL_MASK BIT(16)
> > > > +#define INTPLL_FSEL_MASK BIT(14)
> > > > +#define INTPLL_FEED_EN_MASK BIT(13)
> > > > +#define INTPLL_EXTAFC_MASK GENMASK(7, 3)
> > > > +#define INTPLL_AFC_EN_MASK BIT(2)
> > > > +#define INTPLL_ICP_MASK GENMASK(1, 0)
> > > > +
> > > > +#endif
> > > > diff --git a/arch/arm/mach-imx/imx8m/Makefile
> > > > b/arch/arm/mach-imx/imx8m/Makefile index 42a1544c6b..92184f3135
> > > 100644
> > > > --- a/arch/arm/mach-imx/imx8m/Makefile
> > > > +++ b/arch/arm/mach-imx/imx8m/Makefile
> > > > @@ -5,3 +5,4 @@
> > > > obj-y += lowlevel_init.o
> > > > obj-y += clock_slice.o soc.o
> > > > obj-$(CONFIG_IMX8MQ) += clock_imx8mq.o
> > > > +obj-$(CONFIG_IMX8MM) += clock_imx8mm.o
> > > > diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> > > > b/arch/arm/mach-imx/imx8m/clock_imx8mm.c new file mode 100644
> > > > index 0000000000..beddd2d68b
> > > > --- /dev/null
> > > > +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> > > > @@ -0,0 +1,866 @@
> > > > +// SPDX-License-Identifier: GPL-2.0+
> > > > +/*
> > > > + * Copyright 2018-2019 NXP
> > > > + *
> > > > + * Peng Fan <peng.fan@nxp.com>
> > > > + */
> > > > +
> > > > +#include <common.h>
> > > > +#include <asm/arch/clock.h>
> > > > +#include <asm/arch/imx-regs.h>
> > > > +#include <asm/arch/sys_proto.h>
> > > > +#include <asm/io.h>
> > > > +#include <div64.h>
> > > > +#include <errno.h>
> > > > +
> > > > +DECLARE_GLOBAL_DATA_PTR;
> > > > +
> > > > +static struct anamix_pll *ana_pll = (struct anamix_pll
> > > > *)ANATOP_BASE_ADDR; +
> > > > +void enable_ocotp_clk(unsigned char enable)
> > > > +{
> > > > + clock_enable(CCGR_OCOTP, !!enable);
> > > > +}
> > > > +
> > > > +int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
> > > > +{
> > > > + /* 0 - 3 is valid i2c num */
> > > > + if (i2c_num > 3)
> > > > + return -EINVAL;
> > > > +
> > > > + clock_enable(CCGR_I2C1 + i2c_num, !!enable);
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > +u32 decode_intpll(enum clk_root_src intpll)
> > > > +{
> > > > + u32 pll_gnrl_ctl, pll_div_ctl, pll_clke_mask;
> > > > + u32 main_div, pre_div, post_div, div;
> > > > + u64 freq;
> > > > +
> > > > + switch (intpll) {
> > > > + case ARM_PLL_CLK:
> > > > + pll_gnrl_ctl = readl(&ana_pll->arm_pll_gnrl_ctl);
> > > > + pll_div_ctl = readl(&ana_pll->arm_pll_div_ctl);
> > > > + break;
> > > > + case GPU_PLL_CLK:
> > > > + pll_gnrl_ctl = readl(&ana_pll->gpu_pll_gnrl_ctl);
> > > > + pll_div_ctl = readl(&ana_pll->gpu_pll_div_ctl);
> > > > + break;
> > > > + case VPU_PLL_CLK:
> > > > + pll_gnrl_ctl = readl(&ana_pll->vpu_pll_gnrl_ctl);
> > > > + pll_div_ctl = readl(&ana_pll->vpu_pll_div_ctl);
> > > > + break;
> > > > + case SYSTEM_PLL1_800M_CLK:
> > > > + case SYSTEM_PLL1_400M_CLK:
> > > > + case SYSTEM_PLL1_266M_CLK:
> > > > + case SYSTEM_PLL1_200M_CLK:
> > > > + case SYSTEM_PLL1_160M_CLK:
> > > > + case SYSTEM_PLL1_133M_CLK:
> > > > + case SYSTEM_PLL1_100M_CLK:
> > > > + case SYSTEM_PLL1_80M_CLK:
> > > > + case SYSTEM_PLL1_40M_CLK:
> > > > + pll_gnrl_ctl =
> > > > readl(&ana_pll->sys_pll1_gnrl_ctl);
> > > > + pll_div_ctl = readl(&ana_pll->sys_pll1_div_ctl);
> > > > + break;
> > > > + case SYSTEM_PLL2_1000M_CLK:
> > > > + case SYSTEM_PLL2_500M_CLK:
> > > > + case SYSTEM_PLL2_333M_CLK:
> > > > + case SYSTEM_PLL2_250M_CLK:
> > > > + case SYSTEM_PLL2_200M_CLK:
> > > > + case SYSTEM_PLL2_166M_CLK:
> > > > + case SYSTEM_PLL2_125M_CLK:
> > > > + case SYSTEM_PLL2_100M_CLK:
> > > > + case SYSTEM_PLL2_50M_CLK:
> > > > + pll_gnrl_ctl =
> > > > readl(&ana_pll->sys_pll2_gnrl_ctl);
> > > > + pll_div_ctl = readl(&ana_pll->sys_pll2_div_ctl);
> > > > + break;
> > > > + case SYSTEM_PLL3_CLK:
> > > > + pll_gnrl_ctl =
> > > > readl(&ana_pll->sys_pll3_gnrl_ctl);
> > > > + pll_div_ctl = readl(&ana_pll->sys_pll3_div_ctl);
> > > > + break;
> > > > + default:
> > > > + return -EINVAL;
> > > > + }
> > > > +
> > > > + /* Only support SYS_XTAL 24M, PAD_CLK not take into
> > > > consideration */
> > > > + if ((pll_gnrl_ctl & INTPLL_REF_CLK_SEL_MASK) != 0)
> > > > + return 0;
> > > > +
> > > > + if ((pll_gnrl_ctl & INTPLL_RST_MASK) == 0)
> > > > + return 0;
> > > > +
> > > > + /*
> > > > + * When BYPASS is equal to 1, PLL enters the bypass mode
> > > > + * regardless of the values of RESETB
> > > > + */
> > > > + if (pll_gnrl_ctl & INTPLL_BYPASS_MASK)
> > > > + return 24000000u;
> > > > +
> > > > + if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) {
> > > > + puts("pll not locked\n");
> > > > + return 0;
> > > > + }
> > > > +
> > > > + switch (intpll) {
> > > > + case ARM_PLL_CLK:
> > > > + case GPU_PLL_CLK:
> > > > + case VPU_PLL_CLK:
> > > > + case SYSTEM_PLL3_CLK:
> > > > + case SYSTEM_PLL1_800M_CLK:
> > > > + case SYSTEM_PLL2_1000M_CLK:
> > > > + pll_clke_mask = INTPLL_CLKE_MASK;
> > > > + div = 1;
> > > > + break;
> > > > +
> > > > + case SYSTEM_PLL1_400M_CLK:
> > > > + case SYSTEM_PLL2_500M_CLK:
> > > > + pll_clke_mask = INTPLL_DIV2_CLKE_MASK;
> > > > + div = 2;
> > > > + break;
> > > > +
> > > > + case SYSTEM_PLL1_266M_CLK:
> > > > + case SYSTEM_PLL2_333M_CLK:
> > > > + pll_clke_mask = INTPLL_DIV3_CLKE_MASK;
> > > > + div = 3;
> > > > + break;
> > > > +
> > > > + case SYSTEM_PLL1_200M_CLK:
> > > > + case SYSTEM_PLL2_250M_CLK:
> > > > + pll_clke_mask = INTPLL_DIV4_CLKE_MASK;
> > > > + div = 4;
> > > > + break;
> > > > +
> > > > + case SYSTEM_PLL1_160M_CLK:
> > > > + case SYSTEM_PLL2_200M_CLK:
> > > > + pll_clke_mask = INTPLL_DIV5_CLKE_MASK;
> > > > + div = 5;
> > > > + break;
> > > > +
> > > > + case SYSTEM_PLL1_133M_CLK:
> > > > + case SYSTEM_PLL2_166M_CLK:
> > > > + pll_clke_mask = INTPLL_DIV6_CLKE_MASK;
> > > > + div = 6;
> > > > + break;
> > > > +
> > > > + case SYSTEM_PLL1_100M_CLK:
> > > > + case SYSTEM_PLL2_125M_CLK:
> > > > + pll_clke_mask = INTPLL_DIV8_CLKE_MASK;
> > > > + div = 8;
> > > > + break;
> > > > +
> > > > + case SYSTEM_PLL1_80M_CLK:
> > > > + case SYSTEM_PLL2_100M_CLK:
> > > > + pll_clke_mask = INTPLL_DIV10_CLKE_MASK;
> > > > + div = 10;
> > > > + break;
> > > > +
> > > > + case SYSTEM_PLL1_40M_CLK:
> > > > + case SYSTEM_PLL2_50M_CLK:
> > > > + pll_clke_mask = INTPLL_DIV20_CLKE_MASK;
> > > > + div = 20;
> > > > + break;
> > > > + default:
> > > > + return -EINVAL;
> > > > + }
> > > > +
> > > > + if ((pll_gnrl_ctl & pll_clke_mask) == 0)
> > > > + return 0;
> > > > +
> > > > + main_div = (pll_div_ctl & INTPLL_MAIN_DIV_MASK) >>
> > > > + INTPLL_MAIN_DIV_SHIFT;
> > > > + pre_div = (pll_div_ctl & INTPLL_PRE_DIV_MASK) >>
> > > > + INTPLL_PRE_DIV_SHIFT;
> > > > + post_div = (pll_div_ctl & INTPLL_POST_DIV_MASK) >>
> > > > + INTPLL_POST_DIV_SHIFT;
> > > > +
> > > > + /* FFVCO = (m * FFIN) / p, FFOUT = (m * FFIN) / (p *
> > > > 2^s) */
> > > > + freq = 24000000ULL * main_div;
> > > > + return lldiv(freq, pre_div * (1 << post_div) * div);
> > > > +}
> > > > +
> > > > +u32 decode_fracpll(enum clk_root_src frac_pll)
> > > > +{
> > > > + u32 pll_gnrl_ctl, pll_fdiv_ctl0, pll_fdiv_ctl1;
> > > > + u32 main_div, pre_div, post_div, k;
> > > > +
> > > > + switch (frac_pll) {
> > > > + case DRAM_PLL1_CLK:
> > > > + pll_gnrl_ctl =
> > > > readl(&ana_pll->dram_pll_gnrl_ctl);
> > > > + pll_fdiv_ctl0 =
> > > > readl(&ana_pll->dram_pll_fdiv_ctl0);
> > > > + pll_fdiv_ctl1 =
> > > > readl(&ana_pll->dram_pll_fdiv_ctl1);
> > > > + break;
> > > > + case AUDIO_PLL1_CLK:
> > > > + pll_gnrl_ctl =
> > > > readl(&ana_pll->audio_pll1_gnrl_ctl);
> > > > + pll_fdiv_ctl0 =
> > > > readl(&ana_pll->audio_pll1_fdiv_ctl0);
> > > > + pll_fdiv_ctl1 =
> > > > readl(&ana_pll->audio_pll1_fdiv_ctl1);
> > > > + break;
> > > > + case AUDIO_PLL2_CLK:
> > > > + pll_gnrl_ctl =
> > > > readl(&ana_pll->audio_pll2_gnrl_ctl);
> > > > + pll_fdiv_ctl0 =
> > > > readl(&ana_pll->audio_pll2_fdiv_ctl0);
> > > > + pll_fdiv_ctl1 =
> > > > readl(&ana_pll->audio_pll2_fdiv_ctl1);
> > > > + break;
> > > > + case VIDEO_PLL_CLK:
> > > > + pll_gnrl_ctl =
> > > > readl(&ana_pll->video_pll1_gnrl_ctl);
> > > > + pll_fdiv_ctl0 =
> > > > readl(&ana_pll->video_pll1_fdiv_ctl0);
> > > > + pll_fdiv_ctl1 =
> > > > readl(&ana_pll->video_pll1_fdiv_ctl1);
> > > > + break;
> > > > + default:
> > > > + printf("Not supported\n");
> > > > + return 0;
> > > > + }
> > > > +
> > > > + /* Only support SYS_XTAL 24M, PAD_CLK not take into
> > > > consideration */
> > > > + if ((pll_gnrl_ctl & INTPLL_REF_CLK_SEL_MASK) != 0)
> > > > + return 0;
> > > > +
> > > > + if ((pll_gnrl_ctl & INTPLL_RST_MASK) == 0)
> > > > + return 0;
> > > > + /*
> > > > + * When BYPASS is equal to 1, PLL enters the bypass mode
> > > > + * regardless of the values of RESETB
> > > > + */
> > > > + if (pll_gnrl_ctl & INTPLL_BYPASS_MASK)
> > > > + return 24000000u;
> > > > +
> > > > + if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) {
> > > > + puts("pll not locked\n");
> > > > + return 0;
> > > > + }
> > > > +
> > > > + if (!(pll_gnrl_ctl & INTPLL_CLKE_MASK))
> > > > + return 0;
> > > > +
> > > > + main_div = (pll_fdiv_ctl0 & INTPLL_MAIN_DIV_MASK) >>
> > > > + INTPLL_MAIN_DIV_SHIFT;
> > > > + pre_div = (pll_fdiv_ctl0 & INTPLL_PRE_DIV_MASK) >>
> > > > + INTPLL_PRE_DIV_SHIFT;
> > > > + post_div = (pll_fdiv_ctl0 & INTPLL_POST_DIV_MASK) >>
> > > > + INTPLL_POST_DIV_SHIFT;
> > > > +
> > > > + k = pll_fdiv_ctl1 & GENMASK(15, 0);
> > > > +
> > > > + /*
> > > > + * FFOUT = ((m + k / 65536) * FFIN) / (p * 2^s),
> > > > + * 1 ≤ p ≤ 63, 64 ≤ m ≤ 1023, 0 ≤ s ≤ 6
> > > > + */
> > > > + return lldiv((main_div * 65536 + k) * 24000000ULL,
> > > > + 65536 * pre_div * (1 << post_div));
> > > > +}
> > > > +
> > > > +static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = {
> > > > + PLL_1443X_RATE(800000000U, 300, 9, 0, 0),
> > > > + PLL_1443X_RATE(750000000U, 250, 8, 0, 0),
> > > > + PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
> > > > + PLL_1443X_RATE(600000000U, 300, 3, 2, 0),
> > > > + PLL_1443X_RATE(594000000U, 99, 1, 2, 0),
> > > > + PLL_1443X_RATE(400000000U, 300, 9, 1, 0),
> > > > + PLL_1443X_RATE(266666667U, 400, 9, 2, 0),
> > > > + PLL_1443X_RATE(167000000U, 334, 3, 4, 0),
> > > > + PLL_1443X_RATE(100000000U, 300, 9, 3, 0),
> > > > +};
> > > > +
> > > > +int fracpll_configure(enum pll_clocks pll, u32 freq)
> > > > +{
> > > > + int i;
> > > > + u32 tmp, div_val;
> > > > + void *pll_base;
> > > > + struct imx_int_pll_rate_table *rate;
> > > > +
> > > > + for (i = 0; i < ARRAY_SIZE(imx8mm_fracpll_tbl); i++) {
> > > > + if (freq == imx8mm_fracpll_tbl[i].rate)
> > > > + break;
> > > > + }
> > > > +
> > > > + if (i == ARRAY_SIZE(imx8mm_fracpll_tbl)) {
> > > > + printf("No matched freq table %u\n", freq);
> > > > + return -EINVAL;
> > > > + }
> > > > +
> > > > + rate = &imx8mm_fracpll_tbl[i];
> > > > +
> > > > + switch (pll) {
> > > > + case ANATOP_DRAM_PLL:
> > > > + setbits_le32(GPC_BASE_ADDR + 0xEC, 1 << 7);
> > > > + setbits_le32(GPC_BASE_ADDR + 0xF8, 1 << 5);
> > > > + writel(SRC_DDR1_ENABLE_MASK, SRC_BASE_ADDR +
> > > > 0x1004); +
> > > > + pll_base = &ana_pll->dram_pll_gnrl_ctl;
> > > > + break;
> > > > + case ANATOP_VIDEO_PLL:
> > > > + pll_base = &ana_pll->video_pll1_gnrl_ctl;
> > > > + break;
> > > > + default:
> > > > + return 0;
> > > > + }
> > > > + /* Bypass clock and set lock to pll output lock */
> > > > + tmp = readl(pll_base);
> > > > + tmp |= BYPASS_MASK;
> > > > + writel(tmp, pll_base);
> > > > +
> > > > + /* Enable RST */
> > > > + tmp &= ~RST_MASK;
> > > > + writel(tmp, pll_base);
> > > > +
> > > > + div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv <<
> > > > PDIV_SHIFT) |
> > > > + (rate->sdiv << SDIV_SHIFT);
> > > > + writel(div_val, pll_base + 4);
> > > > + writel(rate->kdiv << KDIV_SHIFT, pll_base + 8);
> > > > +
> > > > + __udelay(100);
> > > > +
> > > > + /* Disable RST */
> > > > + tmp |= RST_MASK;
> > > > + writel(tmp, pll_base);
> > > > +
> > > > + /* Wait Lock*/
> > > > + while (!(readl(pll_base) & LOCK_STATUS))
> > > > + ;
> > > > +
> > > > + /* Bypass */
> > > > + tmp &= ~BYPASS_MASK;
> > > > + writel(tmp, pll_base);
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > +#ifdef CONFIG_SPL_BUILD
> > > > +void dram_pll_init(ulong pll_val)
> > > > +{
> > > > + fracpll_configure(ANATOP_DRAM_PLL, pll_val);
> > > > +}
> > > > +
> > > > +static struct dram_bypass_clk_setting imx8mm_dram_bypass_tbl[] =
> > > > {
> > > > + DRAM_BYPASS_ROOT_CONFIG(MHZ(100), 2, CLK_ROOT_PRE_DIV1,
> > > > 2,
> > > > + CLK_ROOT_PRE_DIV2),
> > > > + DRAM_BYPASS_ROOT_CONFIG(MHZ(250), 3, CLK_ROOT_PRE_DIV2,
> > > > 2,
> > > > + CLK_ROOT_PRE_DIV2),
> > > > + DRAM_BYPASS_ROOT_CONFIG(MHZ(400), 1, CLK_ROOT_PRE_DIV2,
> > > > 3,
> > > > + CLK_ROOT_PRE_DIV2),
> > > > +};
> > > > +
> > > > +void dram_enable_bypass(ulong clk_val)
> > > > +{
> > > > + int i;
> > > > + struct dram_bypass_clk_setting *config;
> > > > +
> > > > + for (i = 0; i < ARRAY_SIZE(imx8mm_dram_bypass_tbl); i++)
> > > > {
> > > > + if (clk_val == imx8mm_dram_bypass_tbl[i].clk)
> > > > + break;
> > > > + }
> > > > +
> > > > + if (i == ARRAY_SIZE(imx8mm_dram_bypass_tbl)) {
> > > > + printf("No matched freq table %lu\n", clk_val);
> > > > + return;
> > > > + }
> > > > +
> > > > + config = &imx8mm_dram_bypass_tbl[i];
> > > > +
> > > > + clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
> > > > +
> > > > CLK_ROOT_SOURCE_SEL(config->alt_root_sel) |
> > > > +
> > > > CLK_ROOT_PRE_DIV(config->alt_pre_div));
> > > > + clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
> > > > +
> > > > CLK_ROOT_SOURCE_SEL(config->apb_root_sel) |
> > > > +
> > > > CLK_ROOT_PRE_DIV(config->apb_pre_div));
> > > > + clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
> > > > + CLK_ROOT_SOURCE_SEL(1));
> > > > +}
> > > > +
> > > > +void dram_disable_bypass(void)
> > > > +{
> > > > + clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
> > > > + CLK_ROOT_SOURCE_SEL(0));
> > > > + clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
> > > > + CLK_ROOT_SOURCE_SEL(4) |
> > > > +
> > > > CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV5)); +}
> > > > +#endif
> > > > +
> > > > +int intpll_configure(enum pll_clocks pll, ulong freq)
> > > > +{
> > > > + void __iomem *pll_gnrl_ctl, __iomem *pll_div_ctl;
> > > > + u32 pll_div_ctl_val, pll_clke_masks;
> > > > +
> > > > + switch (pll) {
> > > > + case ANATOP_SYSTEM_PLL1:
> > > > + pll_gnrl_ctl = &ana_pll->sys_pll1_gnrl_ctl;
> > > > + pll_div_ctl = &ana_pll->sys_pll1_div_ctl;
> > > > + pll_clke_masks = INTPLL_DIV20_CLKE_MASK |
> > > > + INTPLL_DIV10_CLKE_MASK |
> > > > INTPLL_DIV8_CLKE_MASK |
> > > > + INTPLL_DIV6_CLKE_MASK |
> > > > INTPLL_DIV5_CLKE_MASK |
> > > > + INTPLL_DIV4_CLKE_MASK |
> > > > INTPLL_DIV3_CLKE_MASK |
> > > > + INTPLL_DIV2_CLKE_MASK | INTPLL_CLKE_MASK;
> > > > + break;
> > > > + case ANATOP_SYSTEM_PLL2:
> > > > + pll_gnrl_ctl = &ana_pll->sys_pll2_gnrl_ctl;
> > > > + pll_div_ctl = &ana_pll->sys_pll2_div_ctl;
> > > > + pll_clke_masks = INTPLL_DIV20_CLKE_MASK |
> > > > + INTPLL_DIV10_CLKE_MASK |
> > > > INTPLL_DIV8_CLKE_MASK |
> > > > + INTPLL_DIV6_CLKE_MASK |
> > > > INTPLL_DIV5_CLKE_MASK |
> > > > + INTPLL_DIV4_CLKE_MASK |
> > > > INTPLL_DIV3_CLKE_MASK |
> > > > + INTPLL_DIV2_CLKE_MASK | INTPLL_CLKE_MASK;
> > > > + break;
> > > > + case ANATOP_SYSTEM_PLL3:
> > > > + pll_gnrl_ctl = &ana_pll->sys_pll3_gnrl_ctl;
> > > > + pll_div_ctl = &ana_pll->sys_pll3_div_ctl;
> > > > + pll_clke_masks = INTPLL_CLKE_MASK;
> > > > + break;
> > > > + case ANATOP_ARM_PLL:
> > > > + pll_gnrl_ctl = &ana_pll->arm_pll_gnrl_ctl;
> > > > + pll_div_ctl = &ana_pll->arm_pll_div_ctl;
> > > > + pll_clke_masks = INTPLL_CLKE_MASK;
> > > > + break;
> > > > + case ANATOP_GPU_PLL:
> > > > + pll_gnrl_ctl = &ana_pll->gpu_pll_gnrl_ctl;
> > > > + pll_div_ctl = &ana_pll->gpu_pll_div_ctl;
> > > > + pll_clke_masks = INTPLL_CLKE_MASK;
> > > > + break;
> > > > + case ANATOP_VPU_PLL:
> > > > + pll_gnrl_ctl = &ana_pll->vpu_pll_gnrl_ctl;
> > > > + pll_div_ctl = &ana_pll->vpu_pll_div_ctl;
> > > > + pll_clke_masks = INTPLL_CLKE_MASK;
> > > > + break;
> > > > + default:
> > > > + return -EINVAL;
> > > > + };
> > > > +
> > > > + switch (freq) {
> > > > + case MHZ(750):
> > > > + /* 24 * 0xfa / 2 / 2 ^ 2 */
> > > > + pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xfa) |
> > > > + INTPLL_PRE_DIV_VAL(2) |
> > > > INTPLL_POST_DIV_VAL(2);
> > > > + break;
> > > > + case MHZ(800):
> > > > + /* 24 * 0x190 / 3 / 2 ^ 2 */
> > > > + pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0x190) |
> > > > + INTPLL_PRE_DIV_VAL(3) |
> > > > INTPLL_POST_DIV_VAL(2);
> > > > + break;
> > > > + case MHZ(1000):
> > > > + /* 24 * 0xfa / 3 / 2 ^ 1 */
> > > > + pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xfa) |
> > > > + INTPLL_PRE_DIV_VAL(3) |
> > > > INTPLL_POST_DIV_VAL(1);
> > > > + break;
> > > > + case MHZ(1200):
> > > > + /* 24 * 0xc8 / 2 / 2 ^ 1 */
> > > > + pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xc8) |
> > > > + INTPLL_PRE_DIV_VAL(2) |
> > > > INTPLL_POST_DIV_VAL(1);
> > > > + break;
> > > > + case MHZ(2000):
> > > > + /* 24 * 0xfa / 3 / 2 ^ 0 */
> > > > + pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xfa) |
> > > > + INTPLL_PRE_DIV_VAL(3) |
> > > > INTPLL_POST_DIV_VAL(0);
> > > > + break;
> > > > + default:
> > > > + return -EINVAL;
> > > > + };
> > > > + /* Bypass clock and set lock to pll output lock */
> > > > + setbits_le32(pll_gnrl_ctl, INTPLL_BYPASS_MASK |
> > > > INTPLL_LOCK_SEL_MASK);
> > > > + /* Enable reset */
> > > > + clrbits_le32(pll_gnrl_ctl, INTPLL_RST_MASK);
> > > > + /* Configure */
> > > > + writel(pll_div_ctl_val, pll_div_ctl);
> > > > +
> > > > + __udelay(100);
> > > > +
> > > > + /* Disable reset */
> > > > + setbits_le32(pll_gnrl_ctl, INTPLL_RST_MASK);
> > > > + /* Wait Lock */
> > > > + while (!(readl(pll_gnrl_ctl) & INTPLL_LOCK_MASK))
> > > > + ;
> > > > + /* Clear bypass */
> > > > + clrbits_le32(pll_gnrl_ctl, INTPLL_BYPASS_MASK);
> > > > + setbits_le32(pll_gnrl_ctl, pll_clke_masks);
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > +void init_uart_clk(u32 index)
> > > > +{
> > > > + /*
> > > > + * set uart clock root
> > > > + * 24M OSC
> > > > + */
> > > > + switch (index) {
> > > > + case 0:
> > > > + clock_enable(CCGR_UART1, 0);
> > > > + clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON
> > > > |
> > > > + CLK_ROOT_SOURCE_SEL(0));
> > > > + clock_enable(CCGR_UART1, 1);
> > > > + return;
> > > > + case 1:
> > > > + clock_enable(CCGR_UART2, 0);
> > > > + clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON
> > > > |
> > > > + CLK_ROOT_SOURCE_SEL(0));
> > > > + clock_enable(CCGR_UART2, 1);
> > > > + return;
> > > > + case 2:
> > > > + clock_enable(CCGR_UART3, 0);
> > > > + clock_set_target_val(UART3_CLK_ROOT, CLK_ROOT_ON
> > > > |
> > > > + CLK_ROOT_SOURCE_SEL(0));
> > > > + clock_enable(CCGR_UART3, 1);
> > > > + return;
> > > > + case 3:
> > > > + clock_enable(CCGR_UART4, 0);
> > > > + clock_set_target_val(UART4_CLK_ROOT, CLK_ROOT_ON
> > > > |
> > > > + CLK_ROOT_SOURCE_SEL(0));
> > > > + clock_enable(CCGR_UART4, 1);
> > > > + return;
> > > > + default:
> > > > + printf("Invalid uart index\n");
> > > > + return;
> > > > + }
> > > > +}
> > > > +
> > > > +void init_wdog_clk(void)
> > > > +{
> > > > + clock_enable(CCGR_WDOG1, 0);
> > > > + clock_enable(CCGR_WDOG2, 0);
> > > > + clock_enable(CCGR_WDOG3, 0);
> > > > + clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
> > > > + CLK_ROOT_SOURCE_SEL(0));
> > > > + clock_enable(CCGR_WDOG1, 1);
> > > > + clock_enable(CCGR_WDOG2, 1);
> > > > + clock_enable(CCGR_WDOG3, 1);
> > > > +}
> > > > +
> > > > +void init_clk_usdhc(u32 index)
> > > > +{
> > > > + /*
> > > > + * set usdhc clock root
> > > > + * sys pll1 400M
> > > > + */
> > > > + switch (index) {
> > > > + case 0:
> > > > + clock_enable(CCGR_USDHC1, 0);
> > > > + clock_set_target_val(USDHC1_CLK_ROOT,
> > > > CLK_ROOT_ON |
> > > > + CLK_ROOT_SOURCE_SEL(1) |
> > > > +
> > > > CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
> > > > + clock_enable(CCGR_USDHC1, 1);
> > > > + return;
> > > > + case 1:
> > > > + clock_enable(CCGR_USDHC2, 0);
> > > > + clock_set_target_val(USDHC2_CLK_ROOT,
> > > > CLK_ROOT_ON |
> > > > + CLK_ROOT_SOURCE_SEL(1) |
> > > > +
> > > > CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
> > > > + clock_enable(CCGR_USDHC2, 1);
> > > > + return;
> > > > + case 2:
> > > > + clock_enable(CCGR_USDHC3, 0);
> > > > + clock_set_target_val(USDHC3_CLK_ROOT,
> > > > CLK_ROOT_ON |
> > > > + CLK_ROOT_SOURCE_SEL(1) |
> > > > +
> > > > CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
> > > > + clock_enable(CCGR_USDHC3, 1);
> > > > + return;
> > > > + default:
> > > > + printf("Invalid usdhc index\n");
> > > > + return;
> > > > + }
> > > > +}
> > > > +
> > > > +int clock_init(void)
> > > > +{
> > > > + u32 val_cfg0;
> > > > +
> > > > + /* Configure ARM at 1GHz */
> > > > + clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
> > > > + CLK_ROOT_SOURCE_SEL(0));
> > > > +
> > > > + intpll_configure(ANATOP_ARM_PLL, MHZ(1200));
> > > > +
> > > > + clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
> > > > + CLK_ROOT_SOURCE_SEL(1) |
> > > > +
> > > > CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1)); +
> > > > + /*
> > > > + * According to ANAMIX SPEC
> > > > + * sys pll1 fixed at 800MHz
> > > > + * sys pll2 fixed at 1GHz
> > > > + * Here we only enable the outputs.
> > > > + */
> > > > + val_cfg0 = readl(&ana_pll->sys_pll1_gnrl_ctl);
> > > > + val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK |
> > > > + INTPLL_DIV3_CLKE_MASK | INTPLL_DIV4_CLKE_MASK |
> > > > + INTPLL_DIV5_CLKE_MASK | INTPLL_DIV6_CLKE_MASK |
> > > > + INTPLL_DIV8_CLKE_MASK | INTPLL_DIV10_CLKE_MASK |
> > > > + INTPLL_DIV20_CLKE_MASK;
> > > > + writel(val_cfg0, &ana_pll->sys_pll1_gnrl_ctl);
> > > > +
> > > > + val_cfg0 = readl(&ana_pll->sys_pll2_gnrl_ctl);
> > > > + val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK |
> > > > + INTPLL_DIV3_CLKE_MASK | INTPLL_DIV4_CLKE_MASK |
> > > > + INTPLL_DIV5_CLKE_MASK | INTPLL_DIV6_CLKE_MASK |
> > > > + INTPLL_DIV8_CLKE_MASK | INTPLL_DIV10_CLKE_MASK |
> > > > + INTPLL_DIV20_CLKE_MASK;
> > > > + writel(val_cfg0, &ana_pll->sys_pll2_gnrl_ctl);
> > > > +
> > > > + intpll_configure(ANATOP_SYSTEM_PLL3, MHZ(750));
> > > > + clock_set_target_val(NOC_CLK_ROOT, CLK_ROOT_ON |
> > > > + CLK_ROOT_SOURCE_SEL(2));
> > > > +
> > > > + /* config GIC to sys_pll2_100m */
> > > > + clock_enable(CCGR_GIC, 0);
> > > > + clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON |
> > > > + CLK_ROOT_SOURCE_SEL(3));
> > > > + clock_enable(CCGR_GIC, 1);
> > > > +
> > > > + clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT,
> > > > CLK_ROOT_ON |
> > > > + CLK_ROOT_SOURCE_SEL(1));
> > > > +
> > > > + clock_enable(CCGR_DDR1, 0);
> > > > + clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
> > > > + CLK_ROOT_SOURCE_SEL(1));
> > > > + clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
> > > > + CLK_ROOT_SOURCE_SEL(1));
> > > > + clock_enable(CCGR_DDR1, 1);
> > > > +
> > > > + init_wdog_clk();
> > > > +
> > > > + clock_enable(CCGR_TEMP_SENSOR, 1);
> > > > +
> > > > + clock_enable(CCGR_SEC_DEBUG, 1);
> > > > +
> > > > + return 0;
> > > > +};
> > > > +
> > > > +int set_clk_qspi(void)
> > > > +{
> > > > + /*
> > > > + * set qspi root
> > > > + * sys pll1 100M
> > > > + */
> > > > + clock_enable(CCGR_QSPI, 0);
> > > > + clock_set_target_val(QSPI_CLK_ROOT, CLK_ROOT_ON |
> > > > + CLK_ROOT_SOURCE_SEL(7));
> > > > + clock_enable(CCGR_QSPI, 1);
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > +#ifdef CONFIG_FEC_MXC
> > > > +int set_clk_enet(enum enet_freq type)
> > > > +{
> > > > + u32 target;
> > > > + u32 enet1_ref;
> > > > +
> > > > + /* disable the clock first */
> > > > + clock_enable(CCGR_ENET1, 0);
> > > > + clock_enable(CCGR_SIM_ENET, 0);
> > > > +
> > > > + switch (type) {
> > > > + case ENET_125MHZ:
> > > > + enet1_ref =
> > > > ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
> > > > + break;
> > > > + case ENET_50MHZ:
> > > > + enet1_ref =
> > > > ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
> > > > + break;
> > > > + case ENET_25MHZ:
> > > > + enet1_ref =
> > > > ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
> > > > + break;
> > > > + default:
> > > > + return -EINVAL;
> > > > + }
> > > > +
> > > > + /* set enet axi clock 266Mhz */
> > > > + target = CLK_ROOT_ON |
> > > ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
> > > > + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
> > > > + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
> > > > + clock_set_target_val(ENET_AXI_CLK_ROOT, target);
> > > > +
> > > > + target = CLK_ROOT_ON | enet1_ref |
> > > > + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
> > > > + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
> > > > + clock_set_target_val(ENET_REF_CLK_ROOT, target);
> > > > +
> > > > + target = CLK_ROOT_ON |
> > > > ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
> > > > + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
> > > > + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
> > > > + clock_set_target_val(ENET_TIMER_CLK_ROOT, target);
> > > > +
> > > > +#ifdef CONFIG_FEC_MXC_25M_REF_CLK
> > > > + target = CLK_ROOT_ON |
> > > > +
> > > > ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK |
> > > > + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
> > > > + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
> > > > + clock_set_target_val(ENET_PHY_REF_CLK_ROOT, target);
> > > > +#endif
> > > > + /* enable clock */
> > > > + clock_enable(CCGR_SIM_ENET, 1);
> > > > + clock_enable(CCGR_ENET1, 1);
> > > > +
> > > > + return 0;
> > > > +}
> > > > +#endif
> > > > +
> > > > +u32 get_root_src_clk(enum clk_root_src root_src)
> > > > +{
> > > > + switch (root_src) {
> > > > + case OSC_24M_CLK:
> > > > + return 24000000u;
> > > > + case OSC_HDMI_CLK:
> > > > + return 26000000u;
> > > > + case OSC_32K_CLK:
> > > > + return 32000u;
> > > > + case ARM_PLL_CLK:
> > > > + case GPU_PLL_CLK:
> > > > + case VPU_PLL_CLK:
> > > > + case SYSTEM_PLL1_800M_CLK:
> > > > + case SYSTEM_PLL1_400M_CLK:
> > > > + case SYSTEM_PLL1_266M_CLK:
> > > > + case SYSTEM_PLL1_200M_CLK:
> > > > + case SYSTEM_PLL1_160M_CLK:
> > > > + case SYSTEM_PLL1_133M_CLK:
> > > > + case SYSTEM_PLL1_100M_CLK:
> > > > + case SYSTEM_PLL1_80M_CLK:
> > > > + case SYSTEM_PLL1_40M_CLK:
> > > > + case SYSTEM_PLL2_1000M_CLK:
> > > > + case SYSTEM_PLL2_500M_CLK:
> > > > + case SYSTEM_PLL2_333M_CLK:
> > > > + case SYSTEM_PLL2_250M_CLK:
> > > > + case SYSTEM_PLL2_200M_CLK:
> > > > + case SYSTEM_PLL2_166M_CLK:
> > > > + case SYSTEM_PLL2_125M_CLK:
> > > > + case SYSTEM_PLL2_100M_CLK:
> > > > + case SYSTEM_PLL2_50M_CLK:
> > > > + case SYSTEM_PLL3_CLK:
> > > > + return decode_intpll(root_src);
> > > > + case DRAM_PLL1_CLK:
> > > > + case AUDIO_PLL1_CLK:
> > > > + case AUDIO_PLL2_CLK:
> > > > + case VIDEO_PLL_CLK:
> > > > + return decode_fracpll(root_src);
> > > > + default:
> > > > + return 0;
> > > > + }
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > +u32 get_root_clk(enum clk_root_index clock_id)
> > > > +{
> > > > + enum clk_root_src root_src;
> > > > + u32 post_podf, pre_podf, root_src_clk;
> > > > +
> > > > + if (clock_root_enabled(clock_id) <= 0)
> > > > + return 0;
> > > > +
> > > > + if (clock_get_prediv(clock_id, &pre_podf) < 0)
> > > > + return 0;
> > > > +
> > > > + if (clock_get_postdiv(clock_id, &post_podf) < 0)
> > > > + return 0;
> > > > +
> > > > + if (clock_get_src(clock_id, &root_src) < 0)
> > > > + return 0;
> > > > +
> > > > + root_src_clk = get_root_src_clk(root_src);
> > > > +
> > > > + return root_src_clk / (post_podf + 1) / (pre_podf + 1);
> > > > +}
> > > > +
> > > > +u32 mxc_get_clock(enum mxc_clock clk)
> > > > +{
> > > > + u32 val;
> > > > +
> > > > + switch (clk) {
> > > > + case MXC_ARM_CLK:
> > > > + return get_root_clk(ARM_A53_CLK_ROOT);
> > > > + case MXC_IPG_CLK:
> > > > + clock_get_target_val(IPG_CLK_ROOT, &val);
> > > > + val = val & 0x3;
> > > > + return get_root_clk(AHB_CLK_ROOT) / 2 / (val +
> > > > 1);
> > > > + case MXC_CSPI_CLK:
> > > > + return get_root_clk(ECSPI1_CLK_ROOT);
> > > > + case MXC_ESDHC_CLK:
> > > > + return get_root_clk(USDHC1_CLK_ROOT);
> > > > + case MXC_ESDHC2_CLK:
> > > > + return get_root_clk(USDHC2_CLK_ROOT);
> > > > + case MXC_ESDHC3_CLK:
> > > > + return get_root_clk(USDHC3_CLK_ROOT);
> > > > + case MXC_I2C_CLK:
> > > > + return get_root_clk(I2C1_CLK_ROOT);
> > > > + case MXC_UART_CLK:
> > > > + return get_root_clk(UART1_CLK_ROOT);
> > > > + case MXC_QSPI_CLK:
> > > > + return get_root_clk(QSPI_CLK_ROOT);
> > > > + default:
> > > > + printf("Unsupported mxc_clock %d\n", clk);
> > > > + break;
> > > > + }
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > +u32 imx_get_uartclk(void)
> > > > +{
> > > > + return mxc_get_clock(MXC_UART_CLK);
> > > > +}
> > > > +
> > > > +u32 imx_get_fecclk(void)
> > > > +{
> > > > + return get_root_clk(ENET_AXI_CLK_ROOT);
> > > > +}
> > > > +
> > > > +/*
> > > > + * Dump some clockes.
> > > > + */
> > > > +#ifndef CONFIG_SPL_BUILD
> > > > +int do_mscale_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
> > > > + char * const argv[])
> > > > +{
> > > > + u32 freq;
> > > > +
> > > > + freq = decode_intpll(ARM_PLL_CLK);
> > > > + printf("ARM_PLL %8d MHz\n", freq / 1000000);
> > > > + freq = decode_intpll(SYSTEM_PLL1_800M_CLK);
> > > > + printf("SYS_PLL1_800 %8d MHz\n", freq / 1000000);
> > > > + freq = decode_intpll(SYSTEM_PLL1_400M_CLK);
> > > > + printf("SYS_PLL1_400 %8d MHz\n", freq / 1000000);
> > > > + freq = decode_intpll(SYSTEM_PLL1_266M_CLK);
> > > > + printf("SYS_PLL1_266 %8d MHz\n", freq / 1000000);
> > > > + freq = decode_intpll(SYSTEM_PLL1_160M_CLK);
> > > > + printf("SYS_PLL1_160 %8d MHz\n", freq / 1000000);
> > > > + freq = decode_intpll(SYSTEM_PLL1_133M_CLK);
> > > > + printf("SYS_PLL1_133 %8d MHz\n", freq / 1000000);
> > > > + freq = decode_intpll(SYSTEM_PLL1_100M_CLK);
> > > > + printf("SYS_PLL1_100 %8d MHz\n", freq / 1000000);
> > > > + freq = decode_intpll(SYSTEM_PLL1_80M_CLK);
> > > > + printf("SYS_PLL1_80 %8d MHz\n", freq / 1000000);
> > > > + freq = decode_intpll(SYSTEM_PLL1_40M_CLK);
> > > > + printf("SYS_PLL1_40 %8d MHz\n", freq / 1000000);
> > > > + freq = decode_intpll(SYSTEM_PLL2_1000M_CLK);
> > > > + printf("SYS_PLL2_1000 %8d MHz\n", freq / 1000000);
> > > > + freq = decode_intpll(SYSTEM_PLL2_500M_CLK);
> > > > + printf("SYS_PLL2_500 %8d MHz\n", freq / 1000000);
> > > > + freq = decode_intpll(SYSTEM_PLL2_333M_CLK);
> > > > + printf("SYS_PLL2_333 %8d MHz\n", freq / 1000000);
> > > > + freq = decode_intpll(SYSTEM_PLL2_250M_CLK);
> > > > + printf("SYS_PLL2_250 %8d MHz\n", freq / 1000000);
> > > > + freq = decode_intpll(SYSTEM_PLL2_200M_CLK);
> > > > + printf("SYS_PLL2_200 %8d MHz\n", freq / 1000000);
> > > > + freq = decode_intpll(SYSTEM_PLL2_166M_CLK);
> > > > + printf("SYS_PLL2_166 %8d MHz\n", freq / 1000000);
> > > > + freq = decode_intpll(SYSTEM_PLL2_125M_CLK);
> > > > + printf("SYS_PLL2_125 %8d MHz\n", freq / 1000000);
> > > > + freq = decode_intpll(SYSTEM_PLL2_100M_CLK);
> > > > + printf("SYS_PLL2_100 %8d MHz\n", freq / 1000000);
> > > > + freq = decode_intpll(SYSTEM_PLL2_50M_CLK);
> > > > + printf("SYS_PLL2_50 %8d MHz\n", freq / 1000000);
> > > > + freq = decode_intpll(SYSTEM_PLL3_CLK);
> > > > + printf("SYS_PLL3 %8d MHz\n", freq / 1000000);
> > > > + freq = mxc_get_clock(MXC_UART_CLK);
> > > > + printf("UART1 %8d MHz\n", freq / 1000000);
> > > > + freq = mxc_get_clock(MXC_ESDHC_CLK);
> > > > + printf("USDHC1 %8d MHz\n", freq / 1000000);
> > > > + freq = mxc_get_clock(MXC_QSPI_CLK);
> > > > + printf("QSPI %8d MHz\n", freq / 1000000);
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > +U_BOOT_CMD(
> > > > + clocks, CONFIG_SYS_MAXARGS, 1,
> > > > do_mscale_showclocks,
> > > > + "display clocks",
> > > > + ""
> > > > +);
> > > > +#endif
> > > > diff --git a/arch/arm/mach-imx/imx8m/clock_slice.c
> > > > b/arch/arm/mach-imx/imx8m/clock_slice.c index
> > > > 1a67c626f1..dc2a018e00 100644 ---
> > > > a/arch/arm/mach-imx/imx8m/clock_slice.c +++
> > > > b/arch/arm/mach-imx/imx8m/clock_slice.c @@ -13,6 +13,7 @@
> > > >
> > > > static struct ccm_reg *ccm_reg = (struct ccm_reg
> *)CCM_BASE_ADDR;
> > > >
> > > > +#ifdef CONFIG_IMX8MQ
> > > > static struct clk_root_map root_array[] = {
> > > > {ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0,
> > > > {OSC_25M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
> > > > @@ -474,6 +475,466 @@ static struct clk_root_map root_array[] = {
> > > > {DRAM_PLL1_CLK}
> > > > },
> > > > };
> > > > +#elif defined(CONFIG_IMX8MM)
> > > > +static struct clk_root_map root_array[] = {
> > > > + {ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0,
> > > > + {OSC_24M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
> > > > + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
> > > > + SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK,
> SYSTEM_PLL3_CLK}
> > > > + },
> > > > + {ARM_M4_CLK_ROOT, CORE_CLOCK_SLICE, 1,
> > > > + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK,
> > > > SYSTEM_PLL2_250M_CLK,
> > > > + SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
> > > > + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
> > > > + },
> > > > + {VPU_A53_CLK_ROOT, CORE_CLOCK_SLICE, 2,
> > > > + {OSC_24M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
> > > > + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
> > > > + SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, VPU_PLL_CLK}
> > > > + },
> > > > + {GPU3D_CLK_ROOT, CORE_CLOCK_SLICE, 3,
> > > > + {OSC_24M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
> > > > + SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
> > > > + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
> > > > + },
> > > > + {GPU2D_CLK_ROOT, CORE_CLOCK_SLICE, 4,
> > > > + {OSC_24M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
> > > > + SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
> > > > + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
> > > > + },
> > > > + {MAIN_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 0,
> > > > + {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK,
> > > > SYSTEM_PLL1_800M_CLK,
> > > > + SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_1000M_CLK,
> > > > + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL1_100M_CLK}
> > > > + },
> > > > + {ENET_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 1,
> > > > + {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK,
> > > > SYSTEM_PLL1_800M_CLK,
> > > > + SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
> > > > + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
> > > > + },
> > > > + {NAND_USDHC_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 2,
> > > > + {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK,
> > > > SYSTEM_PLL1_800M_CLK,
> > > > + SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK,
> > > > + SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK,
> AUDIO_PLL1_CLK}
> > > > + },
> > > > + {VPU_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 3,
> > > > + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, VPU_PLL_CLK,
> > > > + AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK,
> SYSTEM_PLL2_1000M_CLK,
> > > > + SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_100M_CLK}
> > > > + },
> > > > + {DISPLAY_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 4,
> > > > + {OSC_24M_CLK, SYSTEM_PLL2_1000M_CLK,
> > > SYSTEM_PLL1_800M_CLK,
> > > > + SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK, AUDIO_PLL2_CLK,
> > > > + EXT_CLK_1, EXT_CLK_4}
> > > > + },
> > > > + {DISPLAY_APB_CLK_ROOT, BUS_CLOCK_SLICE, 5,
> > > > + {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK,
> > > > SYSTEM_PLL1_800M_CLK,
> > > > + SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK, AUDIO_PLL2_CLK,
> > > > + EXT_CLK_1, EXT_CLK_3}
> > > > + },
> > > > + {DISPLAY_RTRM_CLK_ROOT, BUS_CLOCK_SLICE, 6,
> > > > + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK,
> > > > SYSTEM_PLL2_200M_CLK,
> > > > + SYSTEM_PLL2_1000M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
> > > > + EXT_CLK_2, EXT_CLK_3}
> > > > + },
> > > > + {USB_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 7,
> > > > + {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK,
> > > > SYSTEM_PLL1_800M_CLK,
> > > > + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
> > > > + EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
> > > > + },
> > > > + {GPU_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 8,
> > > > + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
> > > > + SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
> > > > + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
> > > > + },
> > > > + {GPU_AHB_CLK_ROOT, BUS_CLOCK_SLICE, 9,
> > > > + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
> > > > + SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
> > > > + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
> > > > + },
> > > > + {NOC_CLK_ROOT, BUS_CLOCK_SLICE, 10,
> > > > + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK,
> > > > + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK,
> > > > + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
> > > > + },
> > > > + {NOC_APB_CLK_ROOT, BUS_CLOCK_SLICE, 11,
> > > > + {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL3_CLK,
> > > > + SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_200M_CLK,
> > > > + SYSTEM_PLL1_800M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
> > > > + },
> > > > + {AHB_CLK_ROOT, AHB_CLOCK_SLICE, 0,
> > > > + {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK,
> > > > SYSTEM_PLL1_800M_CLK,
> > > > + SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_125M_CLK,
> > > > + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
> > > > + },
> > > > + {AUDIO_AHB_CLK_ROOT, AHB_CLOCK_SLICE, 1,
> > > > + {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK,
> > > > SYSTEM_PLL1_800M_CLK,
> > > > + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_166M_CLK,
> > > > + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
> > > > + },
> > > > + {MIPI_DSI_ESC_RX_CLK_ROOT, AHB_CLOCK_SLICE, 2,
> > > > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK,
> SYSTEM_PLL1_80M_CLK,
> > > > + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> > > > + SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
> > > > + },
> > > > + {DRAM_ALT_CLK_ROOT, IP_CLOCK_SLICE, 0,
> > > > + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK,
> > > > SYSTEM_PLL1_100M_CLK,
> > > > + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_1000M_CLK,
> > > > + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK,
> SYSTEM_PLL1_266M_CLK}
> > > > + },
> > > > + {DRAM_APB_CLK_ROOT, IP_CLOCK_SLICE, 1,
> > > > + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK,
> SYSTEM_PLL1_40M_CLK,
> > > > + SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
> > > > + SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK,
> AUDIO_PLL2_CLK}
> > > > + },
> > > > + {VPU_G1_CLK_ROOT, IP_CLOCK_SLICE, 2,
> > > > + {OSC_24M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
> > > > + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_100M_CLK,
> > > > + SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK,
> AUDIO_PLL1_CLK}
> > > > + },
> > > > + {VPU_G2_CLK_ROOT, IP_CLOCK_SLICE, 3,
> > > > + {OSC_24M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
> > > > + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_100M_CLK,
> > > > + SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK,
> AUDIO_PLL1_CLK}
> > > > + },
> > > > + {DISPLAY_DTRC_CLK_ROOT, IP_CLOCK_SLICE, 4,
> > > > + {OSC_24M_CLK, VIDEO_PLL2_CLK, SYSTEM_PLL1_800M_CLK,
> > > > + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_160M_CLK,
> > > > + VIDEO_PLL_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK}
> > > > + },
> > > > + {DISPLAY_DC8000_CLK_ROOT, IP_CLOCK_SLICE, 5,
> > > > + {OSC_24M_CLK, VIDEO_PLL2_CLK, SYSTEM_PLL1_800M_CLK,
> > > > + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_160M_CLK,
> > > > + VIDEO_PLL_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK}
> > > > + },
> > > > + {PCIE_CTRL_CLK_ROOT, IP_CLOCK_SLICE, 6,
> > > > + {OSC_24M_CLK, SYSTEM_PLL2_250M_CLK,
> > > > SYSTEM_PLL2_200M_CLK,
> > > > + SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
> > > > + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_333M_CLK,
> > > > SYSTEM_PLL3_CLK}
> > > > + },
> > > > + {PCIE_PHY_CLK_ROOT, IP_CLOCK_SLICE, 7,
> > > > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK,
> > > > SYSTEM_PLL2_500M_CLK,
> > > > + EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
> > > > + SYSTEM_PLL1_400M_CLK}
> > > > + },
> > > > + {PCIE_AUX_CLK_ROOT, IP_CLOCK_SLICE, 8,
> > > > + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK,
> SYSTEM_PLL2_50M_CLK,
> > > > + SYSTEM_PLL3_CLK, SYSTEM_PLL2_100M_CLK,
> > > SYSTEM_PLL1_80M_CLK,
> > > > + SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_200M_CLK}
> > > > + },
> > > > + {DC_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 9,
> > > > + {OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
> > > > + AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
> > > > + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
> > > > + },
> > > > + {LCDIF_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 10,
> > > > + {OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
> > > > + AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
> > > > + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
> > > > + },
> > > > + {SAI1_CLK_ROOT, IP_CLOCK_SLICE, 11,
> > > > + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
> > > > + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
> > > > + OSC_HDMI_CLK, EXT_CLK_1, EXT_CLK_2}
> > > > + },
> > > > + {SAI2_CLK_ROOT, IP_CLOCK_SLICE, 12,
> > > > + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
> > > > + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
> > > > + OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
> > > > + },
> > > > + {SAI3_CLK_ROOT, IP_CLOCK_SLICE, 13,
> > > > + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
> > > > + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
> > > > + OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
> > > > + },
> > > > + {SAI4_CLK_ROOT, IP_CLOCK_SLICE, 14,
> > > > + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
> > > > + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
> > > > + OSC_HDMI_CLK, EXT_CLK_1, EXT_CLK_2}
> > > > + },
> > > > + {SAI5_CLK_ROOT, IP_CLOCK_SLICE, 15,
> > > > + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
> > > > + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
> > > > + OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
> > > > + },
> > > > + {SAI6_CLK_ROOT, IP_CLOCK_SLICE, 16,
> > > > + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
> > > > + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
> > > > + OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
> > > > + },
> > > > + {SPDIF1_CLK_ROOT, IP_CLOCK_SLICE, 17,
> > > > + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
> > > > + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
> > > > + OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
> > > > + },
> > > > + {SPDIF2_CLK_ROOT, IP_CLOCK_SLICE, 18,
> > > > + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
> > > > + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
> > > > + OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
> > > > + },
> > > > + {ENET_REF_CLK_ROOT, IP_CLOCK_SLICE, 19,
> > > > + {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK,
> SYSTEM_PLL2_50M_CLK,
> > > > + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
> > > > + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, EXT_CLK_4}
> > > > + },
> > > > + {ENET_TIMER_CLK_ROOT, IP_CLOCK_SLICE, 20,
> > > > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK,
> > > > + EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
> > > > + VIDEO_PLL_CLK}
> > > > + },
> > > > + {ENET_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 21,
> > > > + {OSC_24M_CLK, SYSTEM_PLL2_50M_CLK,
> SYSTEM_PLL2_125M_CLK,
> > > > + SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_500M_CLK,
> > > > + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
> > > > + },
> > > > + {NAND_CLK_ROOT, IP_CLOCK_SLICE, 22,
> > > > + {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, AUDIO_PLL1_CLK,
> > > > + SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK,
> SYSTEM_PLL3_CLK,
> > > > + SYSTEM_PLL2_250M_CLK, VIDEO_PLL_CLK}
> > > > + },
> > > > + {QSPI_CLK_ROOT, IP_CLOCK_SLICE, 23,
> > > > + {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK,
> > > > SYSTEM_PLL2_333M_CLK,
> > > > + SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK,
> > > > + SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK,
> > > > SYSTEM_PLL1_100M_CLK}
> > > > + },
> > > > + {USDHC1_CLK_ROOT, IP_CLOCK_SLICE, 24,
> > > > + {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK,
> > > > SYSTEM_PLL1_800M_CLK,
> > > > + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
> > > > + SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK,
> > > SYSTEM_PLL1_100M_CLK}
> > > > + },
> > > > + {USDHC2_CLK_ROOT, IP_CLOCK_SLICE, 25,
> > > > + {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK,
> > > > SYSTEM_PLL1_800M_CLK,
> > > > + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
> > > > + SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK,
> > > SYSTEM_PLL1_100M_CLK}
> > > > + },
> > > > + {I2C1_CLK_ROOT, IP_CLOCK_SLICE, 26,
> > > > + {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK,
> SYSTEM_PLL2_50M_CLK,
> > > > + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
> > > > + AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
> > > > + },
> > > > + {I2C2_CLK_ROOT, IP_CLOCK_SLICE, 27,
> > > > + {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK,
> SYSTEM_PLL2_50M_CLK,
> > > > + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
> > > > + AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
> > > > + },
> > > > + {I2C3_CLK_ROOT, IP_CLOCK_SLICE, 28,
> > > > + {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK,
> SYSTEM_PLL2_50M_CLK,
> > > > + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
> > > > + AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
> > > > + },
> > > > + {I2C4_CLK_ROOT, IP_CLOCK_SLICE, 29,
> > > > + {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK,
> SYSTEM_PLL2_50M_CLK,
> > > > + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
> > > > + AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
> > > > + },
> > > > + {UART1_CLK_ROOT, IP_CLOCK_SLICE, 30,
> > > > + {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK,
> SYSTEM_PLL2_200M_CLK,
> > > > + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
> > > > + EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
> > > > + },
> > > > + {UART2_CLK_ROOT, IP_CLOCK_SLICE, 31,
> > > > + {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK,
> SYSTEM_PLL2_200M_CLK,
> > > > + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
> > > > + EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
> > > > + },
> > > > + {UART3_CLK_ROOT, IP_CLOCK_SLICE, 32,
> > > > + {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK,
> SYSTEM_PLL2_200M_CLK,
> > > > + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
> > > > + EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
> > > > + },
> > > > + {UART4_CLK_ROOT, IP_CLOCK_SLICE, 33,
> > > > + {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK,
> SYSTEM_PLL2_200M_CLK,
> > > > + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
> > > > + EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
> > > > + },
> > > > + {USB_CORE_REF_CLK_ROOT, IP_CLOCK_SLICE, 34,
> > > > + {OSC_24M_CLK, SYSTEM_PLL1_100M_CLK,
> SYSTEM_PLL1_40M_CLK,
> > > > + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
> > > > + EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
> > > > + },
> > > > + {USB_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 35,
> > > > + {OSC_24M_CLK, SYSTEM_PLL1_100M_CLK,
> SYSTEM_PLL1_40M_CLK,
> > > > + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
> > > > + EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
> > > > + },
> > > > + {GIC_CLK_ROOT, IP_CLOCK_SLICE, 36,
> > > > + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK,
> SYSTEM_PLL1_40M_CLK,
> > > > + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_800M_CLK,
> > > > + EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
> > > > + },
> > > > + {ECSPI1_CLK_ROOT, IP_CLOCK_SLICE, 37,
> > > > + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK,
> SYSTEM_PLL1_40M_CLK,
> > > > + SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
> > > > + SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK,
> AUDIO_PLL2_CLK}
> > > > + },
> > > > + {ECSPI2_CLK_ROOT, IP_CLOCK_SLICE, 38,
> > > > + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK,
> SYSTEM_PLL1_40M_CLK,
> > > > + SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
> > > > + SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK,
> AUDIO_PLL2_CLK}
> > > > + },
> > > > + {PWM1_CLK_ROOT, IP_CLOCK_SLICE, 39,
> > > > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK,
> > > > SYSTEM_PLL1_160M_CLK,
> > > > + SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
> > > > + SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
> > > > + },
> > > > + {PWM2_CLK_ROOT, IP_CLOCK_SLICE, 40,
> > > > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK,
> > > > SYSTEM_PLL1_160M_CLK,
> > > > + SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
> > > > + SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
> > > > + },
> > > > + {PWM3_CLK_ROOT, IP_CLOCK_SLICE, 41,
> > > > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK,
> > > > SYSTEM_PLL1_160M_CLK,
> > > > + SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2,
> > > > + SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
> > > > + },
> > > > + {PWM4_CLK_ROOT, IP_CLOCK_SLICE, 42,
> > > > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK,
> > > > SYSTEM_PLL1_160M_CLK,
> > > > + SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2,
> > > > + SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
> > > > + },
> > > > + {GPT1_CLK_ROOT, IP_CLOCK_SLICE, 43,
> > > > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK,
> > > > SYSTEM_PLL1_400M_CLK,
> > > > + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
> > > > + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
> > > > + },
> > > > + {GPT2_CLK_ROOT, IP_CLOCK_SLICE, 44,
> > > > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK,
> > > > SYSTEM_PLL1_400M_CLK,
> > > > + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
> > > > + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
> > > > + },
> > > > + {GPT3_CLK_ROOT, IP_CLOCK_SLICE, 45,
> > > > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK,
> > > > SYSTEM_PLL1_400M_CLK,
> > > > + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
> > > > + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
> > > > + },
> > > > + {GPT4_CLK_ROOT, IP_CLOCK_SLICE, 46,
> > > > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK,
> > > > SYSTEM_PLL1_400M_CLK,
> > > > + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
> > > > + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
> > > > + },
> > > > + {GPT5_CLK_ROOT, IP_CLOCK_SLICE, 47,
> > > > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK,
> > > > SYSTEM_PLL1_400M_CLK,
> > > > + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
> > > > + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
> > > > + },
> > > > + {GPT6_CLK_ROOT, IP_CLOCK_SLICE, 48,
> > > > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK,
> > > > SYSTEM_PLL1_400M_CLK,
> > > > + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
> > > > + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
> > > > + },
> > > > + {TRACE_CLK_ROOT, IP_CLOCK_SLICE, 49,
> > > > + {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK,
> > > > SYSTEM_PLL1_160M_CLK,
> > > > + VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
> > > > + SYSTEM_PLL3_CLK, EXT_CLK_1, EXT_CLK_3}
> > > > + },
> > > > + {WDOG_CLK_ROOT, IP_CLOCK_SLICE, 50,
> > > > + {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK,
> > > > SYSTEM_PLL1_160M_CLK,
> > > > + VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
> > > > + SYSTEM_PLL3_CLK, SYSTEM_PLL1_80M_CLK,
> > > SYSTEM_PLL2_166M_CLK}
> > > > + },
> > > > + {WRCLK_CLK_ROOT, IP_CLOCK_SLICE, 51,
> > > > + {OSC_24M_CLK, SYSTEM_PLL1_40M_CLK, VPU_PLL_CLK,
> > > > + SYSTEM_PLL3_CLK, SYSTEM_PLL2_200M_CLK,
> > > > + SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_500M_CLK,
> > > > SYSTEM_PLL1_100M_CLK}
> > > > + },
> > > > + {IPP_DO_CLKO1, IP_CLOCK_SLICE, 52,
> > > > + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, OSC_HDMI_CLK,
> > > > + SYSTEM_PLL1_200M_CLK, AUDIO_PLL2_CLK,
> > > > + SYSTEM_PLL2_500M_CLK, VPU_PLL_CLK,
> SYSTEM_PLL1_80M_CLK}
> > > > + },
> > > > + {IPP_DO_CLKO2, IP_CLOCK_SLICE, 53,
> > > > + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK,
> > > > SYSTEM_PLL1_400M_CLK,
> > > > + SYSTEM_PLL2_166M_CLK, SYSTEM_PLL3_CLK,
> > > > + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, OSC_32K_CLK}
> > > > + },
> > > > + {MIPI_DSI_CORE_CLK_ROOT, IP_CLOCK_SLICE, 54,
> > > > + {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK,
> > > > SYSTEM_PLL2_250M_CLK,
> > > > + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> > > > + SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
> > > > + },
> > > > + {MIPI_DSI_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 55,
> > > > + {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK,
> > > > SYSTEM_PLL2_100M_CLK,
> > > > + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> > > > + EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
> > > > + },
> > > > + {MIPI_DSI_DBI_CLK_ROOT, IP_CLOCK_SLICE, 56,
> > > > + {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK,
> > > > SYSTEM_PLL2_100M_CLK,
> > > > + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> > > > + SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
> > > > + },
> > > > + {USDHC3_CLK_ROOT, IP_CLOCK_SLICE, 57,
> > > > + {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK,
> > > > SYSTEM_PLL1_800M_CLK,
> > > > + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
> > > > + SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK,
> > > SYSTEM_PLL1_100M_CLK}
> > > > + },
> > > > + {MIPI_CSI1_CORE_CLK_ROOT, IP_CLOCK_SLICE, 58,
> > > > + {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK,
> > > > SYSTEM_PLL2_250M_CLK,
> > > > + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> > > > + SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
> > > > + },
> > > > + {MIPI_CSI1_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 59,
> > > > + {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK,
> > > > SYSTEM_PLL2_100M_CLK,
> > > > + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> > > > + EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
> > > > + },
> > > > + {MIPI_CSI1_ESC_CLK_ROOT, IP_CLOCK_SLICE, 60,
> > > > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK,
> SYSTEM_PLL1_80M_CLK,
> > > > + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> > > > + SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
> > > > + },
> > > > + {MIPI_CSI2_CORE_CLK_ROOT, IP_CLOCK_SLICE, 61,
> > > > + {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK,
> > > > SYSTEM_PLL2_250M_CLK,
> > > > + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> > > > + SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
> > > > + },
> > > > + {MIPI_CSI2_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 62,
> > > > + {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK,
> > > > SYSTEM_PLL2_100M_CLK,
> > > > + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> > > > + EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
> > > > + },
> > > > + {MIPI_CSI2_ESC_CLK_ROOT, IP_CLOCK_SLICE, 63,
> > > > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK,
> SYSTEM_PLL1_80M_CLK,
> > > > + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> > > > + SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
> > > > + },
> > > > + {PCIE2_CTRL_CLK_ROOT, IP_CLOCK_SLICE, 64,
> > > > + {OSC_24M_CLK, SYSTEM_PLL2_250M_CLK,
> > > > SYSTEM_PLL2_200M_CLK,
> > > > + SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
> > > > + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_333M_CLK,
> > > > SYSTEM_PLL3_CLK}
> > > > + },
> > > > + {PCIE2_PHY_CLK_ROOT, IP_CLOCK_SLICE, 65,
> > > > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK,
> > > > SYSTEM_PLL2_500M_CLK,
> > > > + EXT_CLK_1, EXT_CLK_2, EXT_CLK_3,
> > > > + EXT_CLK_4, SYSTEM_PLL1_400M_CLK}
> > > > + },
> > > > + {PCIE2_AUX_CLK_ROOT, IP_CLOCK_SLICE, 66,
> > > > + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK,
> SYSTEM_PLL2_50M_CLK,
> > > > + SYSTEM_PLL3_CLK, SYSTEM_PLL2_100M_CLK,
> > > > + SYSTEM_PLL1_80M_CLK, SYSTEM_PLL1_160M_CLK,
> > > > SYSTEM_PLL1_200M_CLK}
> > > > + },
> > > > + {ECSPI3_CLK_ROOT, IP_CLOCK_SLICE, 67,
> > > > + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK,
> SYSTEM_PLL1_40M_CLK,
> > > > + SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
> > > > + SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK,
> AUDIO_PLL2_CLK}
> > > > + },
> > > > + {PDM_CLK_ROOT, IP_CLOCK_SLICE, 68,
> > > > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK,
> > > > + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> > > > + SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK},
> > > > + },
> > > > + {VPU_H1_CLK_ROOT, IP_CLOCK_SLICE, 69,
> > > > + {OSC_24M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
> > > > + SYSTEM_PLL2_1000M_CLK, AUDIO_PLL2_CLK,
> > > > + SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK,
> AUDIO_PLL1_CLK}
> > > > + },
> > > > + {DRAM_SEL_CFG, DRAM_SEL_CLOCK_SLICE, 0,
> > > > + {DRAM_PLL1_CLK}
> > > > + },
> > > > + {CORE_SEL_CFG, CORE_SEL_CLOCK_SLICE, 0,
> > > > + {DRAM_PLL1_CLK}
> > > > + },
> > > > +};
> > > > +#endif
> > > >
> > > > static int select(enum clk_root_index clock_id)
> > > > {
> > >
> > >
> > >
> > >
> > > Best regards,
> > >
> > > Lukasz Majewski
> > >
> > > --
> > >
> > > DENX Software Engineering GmbH, Managing Director: Wolfgang
> > > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell,
> > > Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> > > lukma at denx.de
>
>
>
>
> Best regards,
>
> Lukasz Majewski
>
> --
>
> DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> lukma at denx.de
^ permalink raw reply [flat|nested] 39+ messages in thread* [U-Boot] [PATCH 10/20] imx8m: add clk support for i.MX8MM
2019-01-30 6:56 ` Peng Fan
@ 2019-01-30 8:22 ` Lukasz Majewski
0 siblings, 0 replies; 39+ messages in thread
From: Lukasz Majewski @ 2019-01-30 8:22 UTC (permalink / raw)
To: u-boot
Hi Peng,
> > -----Original Message-----
> > From: Lukasz Majewski [mailto:lukma at denx.de]
> > Sent: 2019年1月30日 14:47
> > To: Peng Fan <peng.fan@nxp.com>
> > Cc: sbabic at denx.de; Fabio Estevam <fabio.estevam@nxp.com>;
> > dl-uboot-imx <uboot-imx@nxp.com>; u-boot at lists.denx.de
> > Subject: Re: [U-Boot] [PATCH 10/20] imx8m: add clk support for
> > i.MX8MM
> >
> > Hi Peng,
> >
> > > Hi Lukasz,
> > >
> > > > -----Original Message-----
> > > > From: Lukasz Majewski [mailto:lukma at denx.de]
> > > > Sent: 2019年1月30日 6:55
> > > > To: Peng Fan <peng.fan@nxp.com>
> > > > Cc: sbabic at denx.de; Fabio Estevam <fabio.estevam@nxp.com>;
> > > > dl-uboot-imx <uboot-imx@nxp.com>; u-boot at lists.denx.de
> > > > Subject: Re: [U-Boot] [PATCH 10/20] imx8m: add clk support for
> > > > i.MX8MM
> > > >
> > > > Hi Peng,
> > > >
> > > > > Introduce clk implementation for i.MX8MM, including pll
> > > > > configuration, pll decoding, ccm configuration.
> > > > >
> > > > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > > > ---
> > > > > arch/arm/include/asm/arch-imx8m/clock.h | 2 +
> > > > > arch/arm/include/asm/arch-imx8m/clock_imx8mm.h | 387
> > +++++++++++
> > > > > arch/arm/mach-imx/imx8m/Makefile | 1 +
> > > > > arch/arm/mach-imx/imx8m/clock_imx8mm.c | 866
> > > > > +++++++++++++++++++++++++
> > > > > arch/arm/mach-imx/imx8m/clock_slice.c | 461
> > > > +++++++++++++ 5
> > > > > files changed, 1717 insertions(+) create mode 100644
> > > > > arch/arm/include/asm/arch-imx8m/clock_imx8mm.h create mode
> > 100644
> > > > > arch/arm/mach-imx/imx8m/clock_imx8mm.c
> > > >
> > > > As fair as I see this approach is not similar to the one from
> > > > Linux kernel:
> > > >
> > > >
> > https://elixir.bootlin.com/linux/v5.0-rc3/source/drivers/clk/imx/clk-imx8mq.
> > > > c
> > > > or simpler:
> > > >
> > https://git.pengutronix.de/cgit/barebox/tree/drivers/clk/imx/clk-imx8mq.c
> > > >
> > > > Also Fabio pointed out in the other mail that we shall stick to
> > > > Linux kernel Common Clock Framework.
> > > >
> > > > IMHO we shall add the simple CCF look alike code (I'm going to
> > > > post imx6q port in a few days).
> > >
> > > That will be too complicated for SPL and it will bring more
> > > efforts when we do pre/post silicon bringup.
> >
> > If we use OF_PLATDATA to avoid DTB inclusion (and provide necessary
> > information for the SPL driver) then we may do the trick.
> >
> > As of now - the problem is that SPL on IMX{568} get bloated very
> > rapidly when converted to DM/DTS..., but this shall not be the case
> > for generic EVAL board.
>
> Ok. I'll wait for your work about CCF, then check whether that could
> be used on i.MX8MM. On some platform, there are limited SRAM,
IMX6Q has a lot of OCRAM, so SPL will fit.
What is the smallest SRAM size for IMX8MM?
There are other options to trim the SPL - like reduced eMMC support,
reduced FitImage, reduced printf, etc.
> hope we not goes into use TPL.
I would also prefer to avoid TPL by any means.
>
> Thanks,
> Peng.
>
> >
> > >
> > > Regards,
> > > Peng.
> > >
> > > >
> > > > >
> > > > > diff --git a/arch/arm/include/asm/arch-imx8m/clock.h
> > > > > b/arch/arm/include/asm/arch-imx8m/clock.h index
> > > > > 7225c760fe..ead4b8d3dc 100644 ---
> > > > > a/arch/arm/include/asm/arch-imx8m/clock.h +++
> > > > > b/arch/arm/include/asm/arch-imx8m/clock.h @@ -7,6 +7,8 @@
> > > > >
> > > > > #ifdef CONFIG_IMX8MQ
> > > > > #include <asm/arch/clock_imx8mq.h>
> > > > > +#elif defined(CONFIG_IMX8MM)
> > > > > +#include <asm/arch/clock_imx8mm.h>
> > > > > #else
> > > > > #error "Error no clock.h"
> > > > > #endif
> > > > > diff --git a/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
> > > > > b/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h new file
> > > > > mode
> > > > 100644
> > > > > index 0000000000..305514a4ec
> > > > > --- /dev/null
> > > > > +++ b/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
> > > > > @@ -0,0 +1,387 @@
> > > > > +/* SPDX-License-Identifier: GPL-2.0+ */
> > > > > +/*
> > > > > + * Copyright 2018-2019 NXP
> > > > > + *
> > > > > + * Peng Fan <peng.fan@nxp.com>
> > > > > + */
> > > > > +
> > > > > +#ifndef _ASM_ARCH_IMX8MM_CLOCK_H
> > > > > +#define _ASM_ARCH_IMX8MM_CLOCK_H
> > > > > +
> > > > > +#define PLL_1443X_RATE(_rate, _m, _p, _s, _k)
> > > > > \
> > > > > + {
> > > > > \
> > > > > + .rate =
> > > > > (_rate), \
> > > > > + .mdiv =
> > > > > (_m), \
> > > > > + .pdiv =
> > > > > (_p), \
> > > > > + .sdiv =
> > > > > (_s), \
> > > > > + .kdiv =
> > > > > (_k), \
> > > > > + }
> > > > > +
> > > > > +#define LOCK_STATUS BIT(31)
> > > > > +#define LOCK_SEL_MASK BIT(29)
> > > > > +#define CLKE_MASK BIT(11)
> > > > > +#define RST_MASK BIT(9)
> > > > > +#define BYPASS_MASK BIT(4)
> > > > > +#define MDIV_SHIFT 12
> > > > > +#define MDIV_MASK GENMASK(21, 12)
> > > > > +#define PDIV_SHIFT 4
> > > > > +#define PDIV_MASK GENMASK(9, 4)
> > > > > +#define SDIV_SHIFT 0
> > > > > +#define SDIV_MASK GENMASK(2, 0)
> > > > > +#define KDIV_SHIFT 0
> > > > > +#define KDIV_MASK GENMASK(15, 0)
> > > > > +
> > > > > +struct imx_int_pll_rate_table {
> > > > > + u32 rate;
> > > > > + int mdiv;
> > > > > + int pdiv;
> > > > > + int sdiv;
> > > > > + int kdiv;
> > > > > +};
> > > > > +
> > > > > +enum pll_clocks {
> > > > > + ANATOP_ARM_PLL,
> > > > > + ANATOP_VPU_PLL,
> > > > > + ANATOP_GPU_PLL,
> > > > > + ANATOP_SYSTEM_PLL1,
> > > > > + ANATOP_SYSTEM_PLL2,
> > > > > + ANATOP_SYSTEM_PLL3,
> > > > > + ANATOP_AUDIO_PLL1,
> > > > > + ANATOP_AUDIO_PLL2,
> > > > > + ANATOP_VIDEO_PLL,
> > > > > + ANATOP_DRAM_PLL,
> > > > > +};
> > > > > +
> > > > > +enum clk_root_index {
> > > > > + ARM_A53_CLK_ROOT = 0,
> > > > > + ARM_M4_CLK_ROOT = 1,
> > > > > + VPU_A53_CLK_ROOT = 2,
> > > > > + GPU3D_CLK_ROOT = 3,
> > > > > + GPU2D_CLK_ROOT = 4,
> > > > > + MAIN_AXI_CLK_ROOT = 16,
> > > > > + ENET_AXI_CLK_ROOT = 17,
> > > > > + NAND_USDHC_BUS_CLK_ROOT = 18,
> > > > > + VPU_BUS_CLK_ROOT = 19,
> > > > > + DISPLAY_AXI_CLK_ROOT = 20,
> > > > > + DISPLAY_APB_CLK_ROOT = 21,
> > > > > + DISPLAY_RTRM_CLK_ROOT = 22,
> > > > > + USB_BUS_CLK_ROOT = 23,
> > > > > + GPU_AXI_CLK_ROOT = 24,
> > > > > + GPU_AHB_CLK_ROOT = 25,
> > > > > + NOC_CLK_ROOT = 26,
> > > > > + NOC_APB_CLK_ROOT = 27,
> > > > > + AHB_CLK_ROOT = 32,
> > > > > + IPG_CLK_ROOT = 33,
> > > > > + AUDIO_AHB_CLK_ROOT = 34,
> > > > > + MIPI_DSI_ESC_RX_CLK_ROOT = 36,
> > > > > + DRAM_SEL_CFG = 48,
> > > > > + CORE_SEL_CFG = 49,
> > > > > + DRAM_ALT_CLK_ROOT = 64,
> > > > > + DRAM_APB_CLK_ROOT = 65,
> > > > > + VPU_G1_CLK_ROOT = 66,
> > > > > + VPU_G2_CLK_ROOT = 67,
> > > > > + DISPLAY_DTRC_CLK_ROOT = 68,
> > > > > + DISPLAY_DC8000_CLK_ROOT = 69,
> > > > > + PCIE_CTRL_CLK_ROOT = 70,
> > > > > + PCIE_PHY_CLK_ROOT = 71,
> > > > > + PCIE_AUX_CLK_ROOT = 72,
> > > > > + DC_PIXEL_CLK_ROOT = 73,
> > > > > + LCDIF_PIXEL_CLK_ROOT = 74,
> > > > > + SAI1_CLK_ROOT = 75,
> > > > > + SAI2_CLK_ROOT = 76,
> > > > > + SAI3_CLK_ROOT = 77,
> > > > > + SAI4_CLK_ROOT = 78,
> > > > > + SAI5_CLK_ROOT = 79,
> > > > > + SAI6_CLK_ROOT = 80,
> > > > > + SPDIF1_CLK_ROOT = 81,
> > > > > + SPDIF2_CLK_ROOT = 82,
> > > > > + ENET_REF_CLK_ROOT = 83,
> > > > > + ENET_TIMER_CLK_ROOT = 84,
> > > > > + ENET_PHY_REF_CLK_ROOT = 85,
> > > > > + NAND_CLK_ROOT = 86,
> > > > > + QSPI_CLK_ROOT = 87,
> > > > > + USDHC1_CLK_ROOT = 88,
> > > > > + USDHC2_CLK_ROOT = 89,
> > > > > + I2C1_CLK_ROOT = 90,
> > > > > + I2C2_CLK_ROOT = 91,
> > > > > + I2C3_CLK_ROOT = 92,
> > > > > + I2C4_CLK_ROOT = 93,
> > > > > + UART1_CLK_ROOT = 94,
> > > > > + UART2_CLK_ROOT = 95,
> > > > > + UART3_CLK_ROOT = 96,
> > > > > + UART4_CLK_ROOT = 97,
> > > > > + USB_CORE_REF_CLK_ROOT = 98,
> > > > > + USB_PHY_REF_CLK_ROOT = 99,
> > > > > + GIC_CLK_ROOT = 100,
> > > > > + ECSPI1_CLK_ROOT = 101,
> > > > > + ECSPI2_CLK_ROOT = 102,
> > > > > + PWM1_CLK_ROOT = 103,
> > > > > + PWM2_CLK_ROOT = 104,
> > > > > + PWM3_CLK_ROOT = 105,
> > > > > + PWM4_CLK_ROOT = 106,
> > > > > + GPT1_CLK_ROOT = 107,
> > > > > + GPT2_CLK_ROOT = 108,
> > > > > + GPT3_CLK_ROOT = 109,
> > > > > + GPT4_CLK_ROOT = 110,
> > > > > + GPT5_CLK_ROOT = 111,
> > > > > + GPT6_CLK_ROOT = 112,
> > > > > + TRACE_CLK_ROOT = 113,
> > > > > + WDOG_CLK_ROOT = 114,
> > > > > + WRCLK_CLK_ROOT = 115,
> > > > > + IPP_DO_CLKO1 = 116,
> > > > > + IPP_DO_CLKO2 = 117,
> > > > > + MIPI_DSI_CORE_CLK_ROOT = 118,
> > > > > + MIPI_DSI_PHY_REF_CLK_ROOT = 119,
> > > > > + MIPI_DSI_DBI_CLK_ROOT = 120,
> > > > > + USDHC3_CLK_ROOT = 121,
> > > > > + MIPI_CSI1_CORE_CLK_ROOT = 122,
> > > > > + MIPI_CSI1_PHY_REF_CLK_ROOT = 123,
> > > > > + MIPI_CSI1_ESC_CLK_ROOT = 124,
> > > > > + MIPI_CSI2_CORE_CLK_ROOT = 125,
> > > > > + MIPI_CSI2_PHY_REF_CLK_ROOT = 126,
> > > > > + MIPI_CSI2_ESC_CLK_ROOT = 127,
> > > > > + PCIE2_CTRL_CLK_ROOT = 128,
> > > > > + PCIE2_PHY_CLK_ROOT = 129,
> > > > > + PCIE2_AUX_CLK_ROOT = 130,
> > > > > + ECSPI3_CLK_ROOT = 131,
> > > > > + PDM_CLK_ROOT = 132,
> > > > > + VPU_H1_CLK_ROOT = 133,
> > > > > + CLK_ROOT_MAX,
> > > > > +};
> > > > > +
> > > > > +enum clk_root_src {
> > > > > + OSC_24M_CLK,
> > > > > + ARM_PLL_CLK,
> > > > > + DRAM_PLL1_CLK,
> > > > > + VIDEO_PLL2_CLK,
> > > > > + VPU_PLL_CLK,
> > > > > + GPU_PLL_CLK,
> > > > > + SYSTEM_PLL1_800M_CLK,
> > > > > + SYSTEM_PLL1_400M_CLK,
> > > > > + SYSTEM_PLL1_266M_CLK,
> > > > > + SYSTEM_PLL1_200M_CLK,
> > > > > + SYSTEM_PLL1_160M_CLK,
> > > > > + SYSTEM_PLL1_133M_CLK,
> > > > > + SYSTEM_PLL1_100M_CLK,
> > > > > + SYSTEM_PLL1_80M_CLK,
> > > > > + SYSTEM_PLL1_40M_CLK,
> > > > > + SYSTEM_PLL2_1000M_CLK,
> > > > > + SYSTEM_PLL2_500M_CLK,
> > > > > + SYSTEM_PLL2_333M_CLK,
> > > > > + SYSTEM_PLL2_250M_CLK,
> > > > > + SYSTEM_PLL2_200M_CLK,
> > > > > + SYSTEM_PLL2_166M_CLK,
> > > > > + SYSTEM_PLL2_125M_CLK,
> > > > > + SYSTEM_PLL2_100M_CLK,
> > > > > + SYSTEM_PLL2_50M_CLK,
> > > > > + SYSTEM_PLL3_CLK,
> > > > > + AUDIO_PLL1_CLK,
> > > > > + AUDIO_PLL2_CLK,
> > > > > + VIDEO_PLL_CLK,
> > > > > + OSC_32K_CLK,
> > > > > + EXT_CLK_1,
> > > > > + EXT_CLK_2,
> > > > > + EXT_CLK_3,
> > > > > + EXT_CLK_4,
> > > > > + OSC_HDMI_CLK
> > > > > +};
> > > > > +
> > > > > +enum clk_ccgr_index {
> > > > > + CCGR_DVFS = 0,
> > > > > + CCGR_ANAMIX = 1,
> > > > > + CCGR_CPU = 2,
> > > > > + CCGR_CSU = 3,
> > > > > + CCGR_DEBUG = 4,
> > > > > + CCGR_DDR1 = 5,
> > > > > + CCGR_ECSPI1 = 7,
> > > > > + CCGR_ECSPI2 = 8,
> > > > > + CCGR_ECSPI3 = 9,
> > > > > + CCGR_ENET1 = 10,
> > > > > + CCGR_GPIO1 = 11,
> > > > > + CCGR_GPIO2 = 12,
> > > > > + CCGR_GPIO3 = 13,
> > > > > + CCGR_GPIO4 = 14,
> > > > > + CCGR_GPIO5 = 15,
> > > > > + CCGR_GPT1 = 16,
> > > > > + CCGR_GPT2 = 17,
> > > > > + CCGR_GPT3 = 18,
> > > > > + CCGR_GPT4 = 19,
> > > > > + CCGR_GPT5 = 20,
> > > > > + CCGR_GPT6 = 21,
> > > > > + CCGR_HS = 22,
> > > > > + CCGR_I2C1 = 23,
> > > > > + CCGR_I2C2 = 24,
> > > > > + CCGR_I2C3 = 25,
> > > > > + CCGR_I2C4 = 26,
> > > > > + CCGR_IOMUX = 27,
> > > > > + CCGR_IOMUX1 = 28,
> > > > > + CCGR_IOMUX2 = 29,
> > > > > + CCGR_IOMUX3 = 30,
> > > > > + CCGR_IOMUX4 = 31,
> > > > > + CCGR_SNVSMIX_IPG_CLK = 32,
> > > > > + CCGR_MU = 33,
> > > > > + CCGR_OCOTP = 34,
> > > > > + CCGR_OCRAM = 35,
> > > > > + CCGR_OCRAM_S = 36,
> > > > > + CCGR_PCIE = 37,
> > > > > + CCGR_PERFMON1 = 38,
> > > > > + CCGR_PERFMON2 = 39,
> > > > > + CCGR_PWM1 = 40,
> > > > > + CCGR_PWM2 = 41,
> > > > > + CCGR_PWM3 = 42,
> > > > > + CCGR_PWM4 = 43,
> > > > > + CCGR_QOS = 44,
> > > > > + CCGR_QOS_DISPMIX = 45,
> > > > > + CCGR_QOS_ETHENET = 46,
> > > > > + CCGR_QSPI = 47,
> > > > > + CCGR_RAWNAND = 48,
> > > > > + CCGR_RDC = 49,
> > > > > + CCGR_ROM = 50,
> > > > > + CCGR_SAI1 = 51,
> > > > > + CCGR_SAI2 = 52,
> > > > > + CCGR_SAI3 = 53,
> > > > > + CCGR_SAI4 = 54,
> > > > > + CCGR_SAI5 = 55,
> > > > > + CCGR_SAI6 = 56,
> > > > > + CCGR_SCTR = 57,
> > > > > + CCGR_SDMA1 = 58,
> > > > > + CCGR_SDMA2 = 59,
> > > > > + CCGR_SEC_DEBUG = 60,
> > > > > + CCGR_SEMA1 = 61,
> > > > > + CCGR_SEMA2 = 62,
> > > > > + CCGR_SIM_DISPLAY = 63,
> > > > > + CCGR_SIM_ENET = 64,
> > > > > + CCGR_SIM_M = 65,
> > > > > + CCGR_SIM_MAIN = 66,
> > > > > + CCGR_SIM_S = 67,
> > > > > + CCGR_SIM_WAKEUP = 68,
> > > > > + CCGR_SIM_HSIO = 69,
> > > > > + CCGR_SIM_VPU = 70,
> > > > > + CCGR_SNVS = 71,
> > > > > + CCGR_TRACE = 72,
> > > > > + CCGR_UART1 = 73,
> > > > > + CCGR_UART2 = 74,
> > > > > + CCGR_UART3 = 75,
> > > > > + CCGR_UART4 = 76,
> > > > > + CCGR_USB_MSCALE_PL301 = 77,
> > > > > + CCGR_GPU3D = 79,
> > > > > + CCGR_USDHC1 = 81,
> > > > > + CCGR_USDHC2 = 82,
> > > > > + CCGR_WDOG1 = 83,
> > > > > + CCGR_WDOG2 = 84,
> > > > > + CCGR_WDOG3 = 85,
> > > > > + CCGR_VPUG1 = 86,
> > > > > + CCGR_GPU_BUS = 87,
> > > > > + CCGR_VPUH1 = 89,
> > > > > + CCGR_VPUG2 = 90,
> > > > > + CCGR_PDM = 91,
> > > > > + CCGR_GIC = 92,
> > > > > + CCGR_DISPMIX = 93,
> > > > > + CCGR_USDHC3 = 94,
> > > > > + CCGR_SDMA3 = 95,
> > > > > + CCGR_XTAL = 96,
> > > > > + CCGR_PLL = 97,
> > > > > + CCGR_TEMP_SENSOR = 98,
> > > > > + CCGR_VPUMIX_BUS = 99,
> > > > > + CCGR_GPU2D = 102,
> > > > > + CCGR_MAX
> > > > > +};
> > > > > +
> > > > > +enum clk_src_index {
> > > > > + CLK_SRC_CKIL_SYNC_REQ = 0,
> > > > > + CLK_SRC_ARM_PLL_EN = 1,
> > > > > + CLK_SRC_GPU_PLL_EN = 2,
> > > > > + CLK_SRC_VPU_PLL_EN = 3,
> > > > > + CLK_SRC_DRAM_PLL_EN = 4,
> > > > > + CLK_SRC_SYSTEM_PLL1_EN = 5,
> > > > > + CLK_SRC_SYSTEM_PLL2_EN = 6,
> > > > > + CLK_SRC_SYSTEM_PLL3_EN = 7,
> > > > > + CLK_SRC_AUDIO_PLL1_EN = 8,
> > > > > + CLK_SRC_AUDIO_PLL2_EN = 9,
> > > > > + CLK_SRC_VIDEO_PLL1_EN = 10,
> > > > > + CLK_SRC_RESERVED = 11,
> > > > > + CLK_SRC_ARM_PLL = 12,
> > > > > + CLK_SRC_GPU_PLL = 13,
> > > > > + CLK_SRC_VPU_PLL = 14,
> > > > > + CLK_SRC_DRAM_PLL = 15,
> > > > > + CLK_SRC_SYSTEM_PLL1_800M = 16,
> > > > > + CLK_SRC_SYSTEM_PLL1_400M = 17,
> > > > > + CLK_SRC_SYSTEM_PLL1_266M = 18,
> > > > > + CLK_SRC_SYSTEM_PLL1_200M = 19,
> > > > > + CLK_SRC_SYSTEM_PLL1_160M = 20,
> > > > > + CLK_SRC_SYSTEM_PLL1_133M = 21,
> > > > > + CLK_SRC_SYSTEM_PLL1_100M = 22,
> > > > > + CLK_SRC_SYSTEM_PLL1_80M = 23,
> > > > > + CLK_SRC_SYSTEM_PLL1_40M = 24,
> > > > > + CLK_SRC_SYSTEM_PLL2_1000M = 25,
> > > > > + CLK_SRC_SYSTEM_PLL2_500M = 26,
> > > > > + CLK_SRC_SYSTEM_PLL2_333M = 27,
> > > > > + CLK_SRC_SYSTEM_PLL2_250M = 28,
> > > > > + CLK_SRC_SYSTEM_PLL2_200M = 29,
> > > > > + CLK_SRC_SYSTEM_PLL2_166M = 30,
> > > > > + CLK_SRC_SYSTEM_PLL2_125M = 31,
> > > > > + CLK_SRC_SYSTEM_PLL2_100M = 32,
> > > > > + CLK_SRC_SYSTEM_PLL2_50M = 33,
> > > > > + CLK_SRC_SYSTEM_PLL3 = 34,
> > > > > + CLK_SRC_AUDIO_PLL1 = 35,
> > > > > + CLK_SRC_AUDIO_PLL2 = 36,
> > > > > + CLK_SRC_VIDEO_PLL1 = 37,
> > > > > +};
> > > > > +
> > > > > +#define INTPLL_LOCK_MASK BIT(31)
> > > > > +#define INTPLL_LOCK_SEL_MASK BIT(29)
> > > > > +#define INTPLL_EXT_BYPASS_MASK BIT(28)
> > > > > +#define INTPLL_DIV20_CLKE_MASK BIT(27)
> > > > > +#define INTPLL_DIV20_CLKE_OVERRIDE_MASK
> > > > > BIT(26) +#define
> > > > > INTPLL_DIV10_CLKE_MASK BIT(25)
> > > > > +#define INTPLL_DIV10_CLKE_OVERRIDE_MASK
> > > > > BIT(24) +#define INTPLL_DIV8_CLKE_MASK
> > > > > BIT(23) +#define
> > > > > INTPLL_DIV8_CLKE_OVERRIDE_MASK BIT(22)
> > > > > +#define INTPLL_DIV6_CLKE_MASK BIT(21)
> > > > > +#define INTPLL_DIV6_CLKE_OVERRIDE_MASK
> > > > > BIT(20) +#define INTPLL_DIV5_CLKE_MASK
> > > > > BIT(19) +#define
> > > > > INTPLL_DIV5_CLKE_OVERRIDE_MASK BIT(18)
> > > > > +#define INTPLL_DIV4_CLKE_MASK BIT(17)
> > > > > +#define INTPLL_DIV4_CLKE_OVERRIDE_MASK
> > > > > BIT(16) +#define INTPLL_DIV3_CLKE_MASK
> > > > > BIT(15) +#define
> > > > > INTPLL_DIV3_CLKE_OVERRIDE_MASK BIT(14)
> > > > > +#define INTPLL_DIV2_CLKE_MASK BIT(13)
> > > > > +#define INTPLL_DIV2_CLKE_OVERRIDE_MASK
> > > > > BIT(12) +#define INTPLL_CLKE_MASK
> > > > > BIT(11) +#define INTPLL_CLKE_OVERRIDE_MASK
> > > > > BIT(10) +#define
> > > > > INTPLL_RST_MASK BIT(9)
> > > > > +#define INTPLL_RST_OVERRIDE_MASK BIT(8)
> > > > > +#define INTPLL_BYPASS_MASK BIT(4)
> > > > > +#define INTPLL_PAD_CLK_SEL_MASK GENMASK(3, 2) +#define
> > > > > INTPLL_REF_CLK_SEL_MASK GENMASK(1, 0)
> > > > > + +#define INTPLL_MAIN_DIV_MASK GENMASK(21,
> > > > > 12) +#define INTPLL_MAIN_DIV_VAL(n) ((n << 12)
> > > > > & GENMASK(21, 12)) +#define
> > > > > INTPLL_MAIN_DIV_SHIFT 12 +#define
> > > > > INTPLL_PRE_DIV_MASK GENMASK(9, 4) +#define
> > > > > INTPLL_PRE_DIV_VAL(n) ((n << 4) & GENMASK(9,
> > > > > 4)) +#define INTPLL_PRE_DIV_SHIFT 4 +#define
> > > > > INTPLL_POST_DIV_MASK GENMASK(2, 0) +#define
> > > > > INTPLL_POST_DIV_VAL(n) ((n << 0) & GENMASK(2,
> > > > > 0)) +#define INTPLL_POST_DIV_SHIFT 0 +
> > > > > +#define INTPLL_LOCK_CON_DLY_MASK GENMASK(5, 4)
> > > > > +#define INTPLL_LOCK_CON_DLY_SHIFT 4 +#define
> > > > > INTPLL_LOCK_CON_OUT_MASK GENMASK(3, 2) +#define
> > > > > INTPLL_LOCK_CON_OUT_SHIFT 2 +#define
> > > > > INTPLL_LOCK_CON_IN_MASK GENMASK(1, 0) +#define
> > > > > INTPLL_LOCK_CON_IN_SHIFT 0 + +#define
> > > > > INTPLL_LRD_EN_MASK BIT(21) +#define
> > > > > INTPLL_FOUT_MASK BIT(20) +#define
> > > > > INTPLL_AFC_SEL_MASK BIT(19) +#define
> > > > > INTPLL_PBIAS_CTRL_MASK BIT(18) +#define
> > > > > INTPLL_PBIAS_CTRL_EN_MASK BIT(17) +#define
> > > > > INTPLL_AFCINIT_SEL_MASK BIT(16) +#define
> > > > > INTPLL_FSEL_MASK BIT(14) +#define
> > > > > INTPLL_FEED_EN_MASK BIT(13) +#define
> > > > > INTPLL_EXTAFC_MASK GENMASK(7, 3) +#define
> > > > > INTPLL_AFC_EN_MASK BIT(2) +#define
> > > > > INTPLL_ICP_MASK GENMASK(1, 0) +
> > > > > +#endif diff --git a/arch/arm/mach-imx/imx8m/Makefile
> > > > > b/arch/arm/mach-imx/imx8m/Makefile index
> > > > > 42a1544c6b..92184f3135
> > > > 100644
> > > > > --- a/arch/arm/mach-imx/imx8m/Makefile
> > > > > +++ b/arch/arm/mach-imx/imx8m/Makefile
> > > > > @@ -5,3 +5,4 @@
> > > > > obj-y += lowlevel_init.o
> > > > > obj-y += clock_slice.o soc.o
> > > > > obj-$(CONFIG_IMX8MQ) += clock_imx8mq.o
> > > > > +obj-$(CONFIG_IMX8MM) += clock_imx8mm.o
> > > > > diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> > > > > b/arch/arm/mach-imx/imx8m/clock_imx8mm.c new file mode 100644
> > > > > index 0000000000..beddd2d68b
> > > > > --- /dev/null
> > > > > +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> > > > > @@ -0,0 +1,866 @@
> > > > > +// SPDX-License-Identifier: GPL-2.0+
> > > > > +/*
> > > > > + * Copyright 2018-2019 NXP
> > > > > + *
> > > > > + * Peng Fan <peng.fan@nxp.com>
> > > > > + */
> > > > > +
> > > > > +#include <common.h>
> > > > > +#include <asm/arch/clock.h>
> > > > > +#include <asm/arch/imx-regs.h>
> > > > > +#include <asm/arch/sys_proto.h>
> > > > > +#include <asm/io.h>
> > > > > +#include <div64.h>
> > > > > +#include <errno.h>
> > > > > +
> > > > > +DECLARE_GLOBAL_DATA_PTR;
> > > > > +
> > > > > +static struct anamix_pll *ana_pll = (struct anamix_pll
> > > > > *)ANATOP_BASE_ADDR; +
> > > > > +void enable_ocotp_clk(unsigned char enable)
> > > > > +{
> > > > > + clock_enable(CCGR_OCOTP, !!enable);
> > > > > +}
> > > > > +
> > > > > +int enable_i2c_clk(unsigned char enable, unsigned int
> > > > > i2c_num) +{
> > > > > + /* 0 - 3 is valid i2c num */
> > > > > + if (i2c_num > 3)
> > > > > + return -EINVAL;
> > > > > +
> > > > > + clock_enable(CCGR_I2C1 + i2c_num, !!enable);
> > > > > +
> > > > > + return 0;
> > > > > +}
> > > > > +
> > > > > +u32 decode_intpll(enum clk_root_src intpll)
> > > > > +{
> > > > > + u32 pll_gnrl_ctl, pll_div_ctl, pll_clke_mask;
> > > > > + u32 main_div, pre_div, post_div, div;
> > > > > + u64 freq;
> > > > > +
> > > > > + switch (intpll) {
> > > > > + case ARM_PLL_CLK:
> > > > > + pll_gnrl_ctl =
> > > > > readl(&ana_pll->arm_pll_gnrl_ctl);
> > > > > + pll_div_ctl =
> > > > > readl(&ana_pll->arm_pll_div_ctl);
> > > > > + break;
> > > > > + case GPU_PLL_CLK:
> > > > > + pll_gnrl_ctl =
> > > > > readl(&ana_pll->gpu_pll_gnrl_ctl);
> > > > > + pll_div_ctl =
> > > > > readl(&ana_pll->gpu_pll_div_ctl);
> > > > > + break;
> > > > > + case VPU_PLL_CLK:
> > > > > + pll_gnrl_ctl =
> > > > > readl(&ana_pll->vpu_pll_gnrl_ctl);
> > > > > + pll_div_ctl =
> > > > > readl(&ana_pll->vpu_pll_div_ctl);
> > > > > + break;
> > > > > + case SYSTEM_PLL1_800M_CLK:
> > > > > + case SYSTEM_PLL1_400M_CLK:
> > > > > + case SYSTEM_PLL1_266M_CLK:
> > > > > + case SYSTEM_PLL1_200M_CLK:
> > > > > + case SYSTEM_PLL1_160M_CLK:
> > > > > + case SYSTEM_PLL1_133M_CLK:
> > > > > + case SYSTEM_PLL1_100M_CLK:
> > > > > + case SYSTEM_PLL1_80M_CLK:
> > > > > + case SYSTEM_PLL1_40M_CLK:
> > > > > + pll_gnrl_ctl =
> > > > > readl(&ana_pll->sys_pll1_gnrl_ctl);
> > > > > + pll_div_ctl =
> > > > > readl(&ana_pll->sys_pll1_div_ctl);
> > > > > + break;
> > > > > + case SYSTEM_PLL2_1000M_CLK:
> > > > > + case SYSTEM_PLL2_500M_CLK:
> > > > > + case SYSTEM_PLL2_333M_CLK:
> > > > > + case SYSTEM_PLL2_250M_CLK:
> > > > > + case SYSTEM_PLL2_200M_CLK:
> > > > > + case SYSTEM_PLL2_166M_CLK:
> > > > > + case SYSTEM_PLL2_125M_CLK:
> > > > > + case SYSTEM_PLL2_100M_CLK:
> > > > > + case SYSTEM_PLL2_50M_CLK:
> > > > > + pll_gnrl_ctl =
> > > > > readl(&ana_pll->sys_pll2_gnrl_ctl);
> > > > > + pll_div_ctl =
> > > > > readl(&ana_pll->sys_pll2_div_ctl);
> > > > > + break;
> > > > > + case SYSTEM_PLL3_CLK:
> > > > > + pll_gnrl_ctl =
> > > > > readl(&ana_pll->sys_pll3_gnrl_ctl);
> > > > > + pll_div_ctl =
> > > > > readl(&ana_pll->sys_pll3_div_ctl);
> > > > > + break;
> > > > > + default:
> > > > > + return -EINVAL;
> > > > > + }
> > > > > +
> > > > > + /* Only support SYS_XTAL 24M, PAD_CLK not take into
> > > > > consideration */
> > > > > + if ((pll_gnrl_ctl & INTPLL_REF_CLK_SEL_MASK) != 0)
> > > > > + return 0;
> > > > > +
> > > > > + if ((pll_gnrl_ctl & INTPLL_RST_MASK) == 0)
> > > > > + return 0;
> > > > > +
> > > > > + /*
> > > > > + * When BYPASS is equal to 1, PLL enters the bypass
> > > > > mode
> > > > > + * regardless of the values of RESETB
> > > > > + */
> > > > > + if (pll_gnrl_ctl & INTPLL_BYPASS_MASK)
> > > > > + return 24000000u;
> > > > > +
> > > > > + if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) {
> > > > > + puts("pll not locked\n");
> > > > > + return 0;
> > > > > + }
> > > > > +
> > > > > + switch (intpll) {
> > > > > + case ARM_PLL_CLK:
> > > > > + case GPU_PLL_CLK:
> > > > > + case VPU_PLL_CLK:
> > > > > + case SYSTEM_PLL3_CLK:
> > > > > + case SYSTEM_PLL1_800M_CLK:
> > > > > + case SYSTEM_PLL2_1000M_CLK:
> > > > > + pll_clke_mask = INTPLL_CLKE_MASK;
> > > > > + div = 1;
> > > > > + break;
> > > > > +
> > > > > + case SYSTEM_PLL1_400M_CLK:
> > > > > + case SYSTEM_PLL2_500M_CLK:
> > > > > + pll_clke_mask = INTPLL_DIV2_CLKE_MASK;
> > > > > + div = 2;
> > > > > + break;
> > > > > +
> > > > > + case SYSTEM_PLL1_266M_CLK:
> > > > > + case SYSTEM_PLL2_333M_CLK:
> > > > > + pll_clke_mask = INTPLL_DIV3_CLKE_MASK;
> > > > > + div = 3;
> > > > > + break;
> > > > > +
> > > > > + case SYSTEM_PLL1_200M_CLK:
> > > > > + case SYSTEM_PLL2_250M_CLK:
> > > > > + pll_clke_mask = INTPLL_DIV4_CLKE_MASK;
> > > > > + div = 4;
> > > > > + break;
> > > > > +
> > > > > + case SYSTEM_PLL1_160M_CLK:
> > > > > + case SYSTEM_PLL2_200M_CLK:
> > > > > + pll_clke_mask = INTPLL_DIV5_CLKE_MASK;
> > > > > + div = 5;
> > > > > + break;
> > > > > +
> > > > > + case SYSTEM_PLL1_133M_CLK:
> > > > > + case SYSTEM_PLL2_166M_CLK:
> > > > > + pll_clke_mask = INTPLL_DIV6_CLKE_MASK;
> > > > > + div = 6;
> > > > > + break;
> > > > > +
> > > > > + case SYSTEM_PLL1_100M_CLK:
> > > > > + case SYSTEM_PLL2_125M_CLK:
> > > > > + pll_clke_mask = INTPLL_DIV8_CLKE_MASK;
> > > > > + div = 8;
> > > > > + break;
> > > > > +
> > > > > + case SYSTEM_PLL1_80M_CLK:
> > > > > + case SYSTEM_PLL2_100M_CLK:
> > > > > + pll_clke_mask = INTPLL_DIV10_CLKE_MASK;
> > > > > + div = 10;
> > > > > + break;
> > > > > +
> > > > > + case SYSTEM_PLL1_40M_CLK:
> > > > > + case SYSTEM_PLL2_50M_CLK:
> > > > > + pll_clke_mask = INTPLL_DIV20_CLKE_MASK;
> > > > > + div = 20;
> > > > > + break;
> > > > > + default:
> > > > > + return -EINVAL;
> > > > > + }
> > > > > +
> > > > > + if ((pll_gnrl_ctl & pll_clke_mask) == 0)
> > > > > + return 0;
> > > > > +
> > > > > + main_div = (pll_div_ctl & INTPLL_MAIN_DIV_MASK) >>
> > > > > + INTPLL_MAIN_DIV_SHIFT;
> > > > > + pre_div = (pll_div_ctl & INTPLL_PRE_DIV_MASK) >>
> > > > > + INTPLL_PRE_DIV_SHIFT;
> > > > > + post_div = (pll_div_ctl & INTPLL_POST_DIV_MASK) >>
> > > > > + INTPLL_POST_DIV_SHIFT;
> > > > > +
> > > > > + /* FFVCO = (m * FFIN) / p, FFOUT = (m * FFIN) / (p *
> > > > > 2^s) */
> > > > > + freq = 24000000ULL * main_div;
> > > > > + return lldiv(freq, pre_div * (1 << post_div) * div);
> > > > > +}
> > > > > +
> > > > > +u32 decode_fracpll(enum clk_root_src frac_pll)
> > > > > +{
> > > > > + u32 pll_gnrl_ctl, pll_fdiv_ctl0, pll_fdiv_ctl1;
> > > > > + u32 main_div, pre_div, post_div, k;
> > > > > +
> > > > > + switch (frac_pll) {
> > > > > + case DRAM_PLL1_CLK:
> > > > > + pll_gnrl_ctl =
> > > > > readl(&ana_pll->dram_pll_gnrl_ctl);
> > > > > + pll_fdiv_ctl0 =
> > > > > readl(&ana_pll->dram_pll_fdiv_ctl0);
> > > > > + pll_fdiv_ctl1 =
> > > > > readl(&ana_pll->dram_pll_fdiv_ctl1);
> > > > > + break;
> > > > > + case AUDIO_PLL1_CLK:
> > > > > + pll_gnrl_ctl =
> > > > > readl(&ana_pll->audio_pll1_gnrl_ctl);
> > > > > + pll_fdiv_ctl0 =
> > > > > readl(&ana_pll->audio_pll1_fdiv_ctl0);
> > > > > + pll_fdiv_ctl1 =
> > > > > readl(&ana_pll->audio_pll1_fdiv_ctl1);
> > > > > + break;
> > > > > + case AUDIO_PLL2_CLK:
> > > > > + pll_gnrl_ctl =
> > > > > readl(&ana_pll->audio_pll2_gnrl_ctl);
> > > > > + pll_fdiv_ctl0 =
> > > > > readl(&ana_pll->audio_pll2_fdiv_ctl0);
> > > > > + pll_fdiv_ctl1 =
> > > > > readl(&ana_pll->audio_pll2_fdiv_ctl1);
> > > > > + break;
> > > > > + case VIDEO_PLL_CLK:
> > > > > + pll_gnrl_ctl =
> > > > > readl(&ana_pll->video_pll1_gnrl_ctl);
> > > > > + pll_fdiv_ctl0 =
> > > > > readl(&ana_pll->video_pll1_fdiv_ctl0);
> > > > > + pll_fdiv_ctl1 =
> > > > > readl(&ana_pll->video_pll1_fdiv_ctl1);
> > > > > + break;
> > > > > + default:
> > > > > + printf("Not supported\n");
> > > > > + return 0;
> > > > > + }
> > > > > +
> > > > > + /* Only support SYS_XTAL 24M, PAD_CLK not take into
> > > > > consideration */
> > > > > + if ((pll_gnrl_ctl & INTPLL_REF_CLK_SEL_MASK) != 0)
> > > > > + return 0;
> > > > > +
> > > > > + if ((pll_gnrl_ctl & INTPLL_RST_MASK) == 0)
> > > > > + return 0;
> > > > > + /*
> > > > > + * When BYPASS is equal to 1, PLL enters the bypass
> > > > > mode
> > > > > + * regardless of the values of RESETB
> > > > > + */
> > > > > + if (pll_gnrl_ctl & INTPLL_BYPASS_MASK)
> > > > > + return 24000000u;
> > > > > +
> > > > > + if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) {
> > > > > + puts("pll not locked\n");
> > > > > + return 0;
> > > > > + }
> > > > > +
> > > > > + if (!(pll_gnrl_ctl & INTPLL_CLKE_MASK))
> > > > > + return 0;
> > > > > +
> > > > > + main_div = (pll_fdiv_ctl0 & INTPLL_MAIN_DIV_MASK) >>
> > > > > + INTPLL_MAIN_DIV_SHIFT;
> > > > > + pre_div = (pll_fdiv_ctl0 & INTPLL_PRE_DIV_MASK) >>
> > > > > + INTPLL_PRE_DIV_SHIFT;
> > > > > + post_div = (pll_fdiv_ctl0 & INTPLL_POST_DIV_MASK) >>
> > > > > + INTPLL_POST_DIV_SHIFT;
> > > > > +
> > > > > + k = pll_fdiv_ctl1 & GENMASK(15, 0);
> > > > > +
> > > > > + /*
> > > > > + * FFOUT = ((m + k / 65536) * FFIN) / (p * 2^s),
> > > > > + * 1 ≤ p ≤ 63, 64 ≤ m ≤ 1023, 0 ≤ s ≤ 6
> > > > > + */
> > > > > + return lldiv((main_div * 65536 + k) * 24000000ULL,
> > > > > + 65536 * pre_div * (1 << post_div));
> > > > > +}
> > > > > +
> > > > > +static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = {
> > > > > + PLL_1443X_RATE(800000000U, 300, 9, 0, 0),
> > > > > + PLL_1443X_RATE(750000000U, 250, 8, 0, 0),
> > > > > + PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
> > > > > + PLL_1443X_RATE(600000000U, 300, 3, 2, 0),
> > > > > + PLL_1443X_RATE(594000000U, 99, 1, 2, 0),
> > > > > + PLL_1443X_RATE(400000000U, 300, 9, 1, 0),
> > > > > + PLL_1443X_RATE(266666667U, 400, 9, 2, 0),
> > > > > + PLL_1443X_RATE(167000000U, 334, 3, 4, 0),
> > > > > + PLL_1443X_RATE(100000000U, 300, 9, 3, 0),
> > > > > +};
> > > > > +
> > > > > +int fracpll_configure(enum pll_clocks pll, u32 freq)
> > > > > +{
> > > > > + int i;
> > > > > + u32 tmp, div_val;
> > > > > + void *pll_base;
> > > > > + struct imx_int_pll_rate_table *rate;
> > > > > +
> > > > > + for (i = 0; i < ARRAY_SIZE(imx8mm_fracpll_tbl); i++)
> > > > > {
> > > > > + if (freq == imx8mm_fracpll_tbl[i].rate)
> > > > > + break;
> > > > > + }
> > > > > +
> > > > > + if (i == ARRAY_SIZE(imx8mm_fracpll_tbl)) {
> > > > > + printf("No matched freq table %u\n", freq);
> > > > > + return -EINVAL;
> > > > > + }
> > > > > +
> > > > > + rate = &imx8mm_fracpll_tbl[i];
> > > > > +
> > > > > + switch (pll) {
> > > > > + case ANATOP_DRAM_PLL:
> > > > > + setbits_le32(GPC_BASE_ADDR + 0xEC, 1 << 7);
> > > > > + setbits_le32(GPC_BASE_ADDR + 0xF8, 1 << 5);
> > > > > + writel(SRC_DDR1_ENABLE_MASK, SRC_BASE_ADDR +
> > > > > 0x1004); +
> > > > > + pll_base = &ana_pll->dram_pll_gnrl_ctl;
> > > > > + break;
> > > > > + case ANATOP_VIDEO_PLL:
> > > > > + pll_base = &ana_pll->video_pll1_gnrl_ctl;
> > > > > + break;
> > > > > + default:
> > > > > + return 0;
> > > > > + }
> > > > > + /* Bypass clock and set lock to pll output lock */
> > > > > + tmp = readl(pll_base);
> > > > > + tmp |= BYPASS_MASK;
> > > > > + writel(tmp, pll_base);
> > > > > +
> > > > > + /* Enable RST */
> > > > > + tmp &= ~RST_MASK;
> > > > > + writel(tmp, pll_base);
> > > > > +
> > > > > + div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv <<
> > > > > PDIV_SHIFT) |
> > > > > + (rate->sdiv << SDIV_SHIFT);
> > > > > + writel(div_val, pll_base + 4);
> > > > > + writel(rate->kdiv << KDIV_SHIFT, pll_base + 8);
> > > > > +
> > > > > + __udelay(100);
> > > > > +
> > > > > + /* Disable RST */
> > > > > + tmp |= RST_MASK;
> > > > > + writel(tmp, pll_base);
> > > > > +
> > > > > + /* Wait Lock*/
> > > > > + while (!(readl(pll_base) & LOCK_STATUS))
> > > > > + ;
> > > > > +
> > > > > + /* Bypass */
> > > > > + tmp &= ~BYPASS_MASK;
> > > > > + writel(tmp, pll_base);
> > > > > +
> > > > > + return 0;
> > > > > +}
> > > > > +
> > > > > +#ifdef CONFIG_SPL_BUILD
> > > > > +void dram_pll_init(ulong pll_val)
> > > > > +{
> > > > > + fracpll_configure(ANATOP_DRAM_PLL, pll_val);
> > > > > +}
> > > > > +
> > > > > +static struct dram_bypass_clk_setting
> > > > > imx8mm_dram_bypass_tbl[] = {
> > > > > + DRAM_BYPASS_ROOT_CONFIG(MHZ(100), 2,
> > > > > CLK_ROOT_PRE_DIV1, 2,
> > > > > + CLK_ROOT_PRE_DIV2),
> > > > > + DRAM_BYPASS_ROOT_CONFIG(MHZ(250), 3,
> > > > > CLK_ROOT_PRE_DIV2, 2,
> > > > > + CLK_ROOT_PRE_DIV2),
> > > > > + DRAM_BYPASS_ROOT_CONFIG(MHZ(400), 1,
> > > > > CLK_ROOT_PRE_DIV2, 3,
> > > > > + CLK_ROOT_PRE_DIV2),
> > > > > +};
> > > > > +
> > > > > +void dram_enable_bypass(ulong clk_val)
> > > > > +{
> > > > > + int i;
> > > > > + struct dram_bypass_clk_setting *config;
> > > > > +
> > > > > + for (i = 0; i < ARRAY_SIZE(imx8mm_dram_bypass_tbl);
> > > > > i++) {
> > > > > + if (clk_val == imx8mm_dram_bypass_tbl[i].clk)
> > > > > + break;
> > > > > + }
> > > > > +
> > > > > + if (i == ARRAY_SIZE(imx8mm_dram_bypass_tbl)) {
> > > > > + printf("No matched freq table %lu\n",
> > > > > clk_val);
> > > > > + return;
> > > > > + }
> > > > > +
> > > > > + config = &imx8mm_dram_bypass_tbl[i];
> > > > > +
> > > > > + clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
> > > > > +
> > > > > CLK_ROOT_SOURCE_SEL(config->alt_root_sel) |
> > > > > +
> > > > > CLK_ROOT_PRE_DIV(config->alt_pre_div));
> > > > > + clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
> > > > > +
> > > > > CLK_ROOT_SOURCE_SEL(config->apb_root_sel) |
> > > > > +
> > > > > CLK_ROOT_PRE_DIV(config->apb_pre_div));
> > > > > + clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
> > > > > + CLK_ROOT_SOURCE_SEL(1));
> > > > > +}
> > > > > +
> > > > > +void dram_disable_bypass(void)
> > > > > +{
> > > > > + clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
> > > > > + CLK_ROOT_SOURCE_SEL(0));
> > > > > + clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
> > > > > + CLK_ROOT_SOURCE_SEL(4) |
> > > > > +
> > > > > CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV5)); +}
> > > > > +#endif
> > > > > +
> > > > > +int intpll_configure(enum pll_clocks pll, ulong freq)
> > > > > +{
> > > > > + void __iomem *pll_gnrl_ctl, __iomem *pll_div_ctl;
> > > > > + u32 pll_div_ctl_val, pll_clke_masks;
> > > > > +
> > > > > + switch (pll) {
> > > > > + case ANATOP_SYSTEM_PLL1:
> > > > > + pll_gnrl_ctl = &ana_pll->sys_pll1_gnrl_ctl;
> > > > > + pll_div_ctl = &ana_pll->sys_pll1_div_ctl;
> > > > > + pll_clke_masks = INTPLL_DIV20_CLKE_MASK |
> > > > > + INTPLL_DIV10_CLKE_MASK |
> > > > > INTPLL_DIV8_CLKE_MASK |
> > > > > + INTPLL_DIV6_CLKE_MASK |
> > > > > INTPLL_DIV5_CLKE_MASK |
> > > > > + INTPLL_DIV4_CLKE_MASK |
> > > > > INTPLL_DIV3_CLKE_MASK |
> > > > > + INTPLL_DIV2_CLKE_MASK |
> > > > > INTPLL_CLKE_MASK;
> > > > > + break;
> > > > > + case ANATOP_SYSTEM_PLL2:
> > > > > + pll_gnrl_ctl = &ana_pll->sys_pll2_gnrl_ctl;
> > > > > + pll_div_ctl = &ana_pll->sys_pll2_div_ctl;
> > > > > + pll_clke_masks = INTPLL_DIV20_CLKE_MASK |
> > > > > + INTPLL_DIV10_CLKE_MASK |
> > > > > INTPLL_DIV8_CLKE_MASK |
> > > > > + INTPLL_DIV6_CLKE_MASK |
> > > > > INTPLL_DIV5_CLKE_MASK |
> > > > > + INTPLL_DIV4_CLKE_MASK |
> > > > > INTPLL_DIV3_CLKE_MASK |
> > > > > + INTPLL_DIV2_CLKE_MASK |
> > > > > INTPLL_CLKE_MASK;
> > > > > + break;
> > > > > + case ANATOP_SYSTEM_PLL3:
> > > > > + pll_gnrl_ctl = &ana_pll->sys_pll3_gnrl_ctl;
> > > > > + pll_div_ctl = &ana_pll->sys_pll3_div_ctl;
> > > > > + pll_clke_masks = INTPLL_CLKE_MASK;
> > > > > + break;
> > > > > + case ANATOP_ARM_PLL:
> > > > > + pll_gnrl_ctl = &ana_pll->arm_pll_gnrl_ctl;
> > > > > + pll_div_ctl = &ana_pll->arm_pll_div_ctl;
> > > > > + pll_clke_masks = INTPLL_CLKE_MASK;
> > > > > + break;
> > > > > + case ANATOP_GPU_PLL:
> > > > > + pll_gnrl_ctl = &ana_pll->gpu_pll_gnrl_ctl;
> > > > > + pll_div_ctl = &ana_pll->gpu_pll_div_ctl;
> > > > > + pll_clke_masks = INTPLL_CLKE_MASK;
> > > > > + break;
> > > > > + case ANATOP_VPU_PLL:
> > > > > + pll_gnrl_ctl = &ana_pll->vpu_pll_gnrl_ctl;
> > > > > + pll_div_ctl = &ana_pll->vpu_pll_div_ctl;
> > > > > + pll_clke_masks = INTPLL_CLKE_MASK;
> > > > > + break;
> > > > > + default:
> > > > > + return -EINVAL;
> > > > > + };
> > > > > +
> > > > > + switch (freq) {
> > > > > + case MHZ(750):
> > > > > + /* 24 * 0xfa / 2 / 2 ^ 2 */
> > > > > + pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xfa) |
> > > > > + INTPLL_PRE_DIV_VAL(2) |
> > > > > INTPLL_POST_DIV_VAL(2);
> > > > > + break;
> > > > > + case MHZ(800):
> > > > > + /* 24 * 0x190 / 3 / 2 ^ 2 */
> > > > > + pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0x190)
> > > > > |
> > > > > + INTPLL_PRE_DIV_VAL(3) |
> > > > > INTPLL_POST_DIV_VAL(2);
> > > > > + break;
> > > > > + case MHZ(1000):
> > > > > + /* 24 * 0xfa / 3 / 2 ^ 1 */
> > > > > + pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xfa) |
> > > > > + INTPLL_PRE_DIV_VAL(3) |
> > > > > INTPLL_POST_DIV_VAL(1);
> > > > > + break;
> > > > > + case MHZ(1200):
> > > > > + /* 24 * 0xc8 / 2 / 2 ^ 1 */
> > > > > + pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xc8) |
> > > > > + INTPLL_PRE_DIV_VAL(2) |
> > > > > INTPLL_POST_DIV_VAL(1);
> > > > > + break;
> > > > > + case MHZ(2000):
> > > > > + /* 24 * 0xfa / 3 / 2 ^ 0 */
> > > > > + pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xfa) |
> > > > > + INTPLL_PRE_DIV_VAL(3) |
> > > > > INTPLL_POST_DIV_VAL(0);
> > > > > + break;
> > > > > + default:
> > > > > + return -EINVAL;
> > > > > + };
> > > > > + /* Bypass clock and set lock to pll output lock */
> > > > > + setbits_le32(pll_gnrl_ctl, INTPLL_BYPASS_MASK |
> > > > > INTPLL_LOCK_SEL_MASK);
> > > > > + /* Enable reset */
> > > > > + clrbits_le32(pll_gnrl_ctl, INTPLL_RST_MASK);
> > > > > + /* Configure */
> > > > > + writel(pll_div_ctl_val, pll_div_ctl);
> > > > > +
> > > > > + __udelay(100);
> > > > > +
> > > > > + /* Disable reset */
> > > > > + setbits_le32(pll_gnrl_ctl, INTPLL_RST_MASK);
> > > > > + /* Wait Lock */
> > > > > + while (!(readl(pll_gnrl_ctl) & INTPLL_LOCK_MASK))
> > > > > + ;
> > > > > + /* Clear bypass */
> > > > > + clrbits_le32(pll_gnrl_ctl, INTPLL_BYPASS_MASK);
> > > > > + setbits_le32(pll_gnrl_ctl, pll_clke_masks);
> > > > > +
> > > > > + return 0;
> > > > > +}
> > > > > +
> > > > > +void init_uart_clk(u32 index)
> > > > > +{
> > > > > + /*
> > > > > + * set uart clock root
> > > > > + * 24M OSC
> > > > > + */
> > > > > + switch (index) {
> > > > > + case 0:
> > > > > + clock_enable(CCGR_UART1, 0);
> > > > > + clock_set_target_val(UART1_CLK_ROOT,
> > > > > CLK_ROOT_ON |
> > > > > + CLK_ROOT_SOURCE_SEL(0));
> > > > > + clock_enable(CCGR_UART1, 1);
> > > > > + return;
> > > > > + case 1:
> > > > > + clock_enable(CCGR_UART2, 0);
> > > > > + clock_set_target_val(UART2_CLK_ROOT,
> > > > > CLK_ROOT_ON |
> > > > > + CLK_ROOT_SOURCE_SEL(0));
> > > > > + clock_enable(CCGR_UART2, 1);
> > > > > + return;
> > > > > + case 2:
> > > > > + clock_enable(CCGR_UART3, 0);
> > > > > + clock_set_target_val(UART3_CLK_ROOT,
> > > > > CLK_ROOT_ON |
> > > > > + CLK_ROOT_SOURCE_SEL(0));
> > > > > + clock_enable(CCGR_UART3, 1);
> > > > > + return;
> > > > > + case 3:
> > > > > + clock_enable(CCGR_UART4, 0);
> > > > > + clock_set_target_val(UART4_CLK_ROOT,
> > > > > CLK_ROOT_ON |
> > > > > + CLK_ROOT_SOURCE_SEL(0));
> > > > > + clock_enable(CCGR_UART4, 1);
> > > > > + return;
> > > > > + default:
> > > > > + printf("Invalid uart index\n");
> > > > > + return;
> > > > > + }
> > > > > +}
> > > > > +
> > > > > +void init_wdog_clk(void)
> > > > > +{
> > > > > + clock_enable(CCGR_WDOG1, 0);
> > > > > + clock_enable(CCGR_WDOG2, 0);
> > > > > + clock_enable(CCGR_WDOG3, 0);
> > > > > + clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
> > > > > + CLK_ROOT_SOURCE_SEL(0));
> > > > > + clock_enable(CCGR_WDOG1, 1);
> > > > > + clock_enable(CCGR_WDOG2, 1);
> > > > > + clock_enable(CCGR_WDOG3, 1);
> > > > > +}
> > > > > +
> > > > > +void init_clk_usdhc(u32 index)
> > > > > +{
> > > > > + /*
> > > > > + * set usdhc clock root
> > > > > + * sys pll1 400M
> > > > > + */
> > > > > + switch (index) {
> > > > > + case 0:
> > > > > + clock_enable(CCGR_USDHC1, 0);
> > > > > + clock_set_target_val(USDHC1_CLK_ROOT,
> > > > > CLK_ROOT_ON |
> > > > > + CLK_ROOT_SOURCE_SEL(1) |
> > > > > +
> > > > > CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
> > > > > + clock_enable(CCGR_USDHC1, 1);
> > > > > + return;
> > > > > + case 1:
> > > > > + clock_enable(CCGR_USDHC2, 0);
> > > > > + clock_set_target_val(USDHC2_CLK_ROOT,
> > > > > CLK_ROOT_ON |
> > > > > + CLK_ROOT_SOURCE_SEL(1) |
> > > > > +
> > > > > CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
> > > > > + clock_enable(CCGR_USDHC2, 1);
> > > > > + return;
> > > > > + case 2:
> > > > > + clock_enable(CCGR_USDHC3, 0);
> > > > > + clock_set_target_val(USDHC3_CLK_ROOT,
> > > > > CLK_ROOT_ON |
> > > > > + CLK_ROOT_SOURCE_SEL(1) |
> > > > > +
> > > > > CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
> > > > > + clock_enable(CCGR_USDHC3, 1);
> > > > > + return;
> > > > > + default:
> > > > > + printf("Invalid usdhc index\n");
> > > > > + return;
> > > > > + }
> > > > > +}
> > > > > +
> > > > > +int clock_init(void)
> > > > > +{
> > > > > + u32 val_cfg0;
> > > > > +
> > > > > + /* Configure ARM at 1GHz */
> > > > > + clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
> > > > > + CLK_ROOT_SOURCE_SEL(0));
> > > > > +
> > > > > + intpll_configure(ANATOP_ARM_PLL, MHZ(1200));
> > > > > +
> > > > > + clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
> > > > > + CLK_ROOT_SOURCE_SEL(1) |
> > > > > +
> > > > > CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1)); +
> > > > > + /*
> > > > > + * According to ANAMIX SPEC
> > > > > + * sys pll1 fixed at 800MHz
> > > > > + * sys pll2 fixed at 1GHz
> > > > > + * Here we only enable the outputs.
> > > > > + */
> > > > > + val_cfg0 = readl(&ana_pll->sys_pll1_gnrl_ctl);
> > > > > + val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK
> > > > > |
> > > > > + INTPLL_DIV3_CLKE_MASK |
> > > > > INTPLL_DIV4_CLKE_MASK |
> > > > > + INTPLL_DIV5_CLKE_MASK |
> > > > > INTPLL_DIV6_CLKE_MASK |
> > > > > + INTPLL_DIV8_CLKE_MASK |
> > > > > INTPLL_DIV10_CLKE_MASK |
> > > > > + INTPLL_DIV20_CLKE_MASK;
> > > > > + writel(val_cfg0, &ana_pll->sys_pll1_gnrl_ctl);
> > > > > +
> > > > > + val_cfg0 = readl(&ana_pll->sys_pll2_gnrl_ctl);
> > > > > + val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK
> > > > > |
> > > > > + INTPLL_DIV3_CLKE_MASK |
> > > > > INTPLL_DIV4_CLKE_MASK |
> > > > > + INTPLL_DIV5_CLKE_MASK |
> > > > > INTPLL_DIV6_CLKE_MASK |
> > > > > + INTPLL_DIV8_CLKE_MASK |
> > > > > INTPLL_DIV10_CLKE_MASK |
> > > > > + INTPLL_DIV20_CLKE_MASK;
> > > > > + writel(val_cfg0, &ana_pll->sys_pll2_gnrl_ctl);
> > > > > +
> > > > > + intpll_configure(ANATOP_SYSTEM_PLL3, MHZ(750));
> > > > > + clock_set_target_val(NOC_CLK_ROOT, CLK_ROOT_ON |
> > > > > + CLK_ROOT_SOURCE_SEL(2));
> > > > > +
> > > > > + /* config GIC to sys_pll2_100m */
> > > > > + clock_enable(CCGR_GIC, 0);
> > > > > + clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON |
> > > > > + CLK_ROOT_SOURCE_SEL(3));
> > > > > + clock_enable(CCGR_GIC, 1);
> > > > > +
> > > > > + clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT,
> > > > > CLK_ROOT_ON |
> > > > > + CLK_ROOT_SOURCE_SEL(1));
> > > > > +
> > > > > + clock_enable(CCGR_DDR1, 0);
> > > > > + clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
> > > > > + CLK_ROOT_SOURCE_SEL(1));
> > > > > + clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
> > > > > + CLK_ROOT_SOURCE_SEL(1));
> > > > > + clock_enable(CCGR_DDR1, 1);
> > > > > +
> > > > > + init_wdog_clk();
> > > > > +
> > > > > + clock_enable(CCGR_TEMP_SENSOR, 1);
> > > > > +
> > > > > + clock_enable(CCGR_SEC_DEBUG, 1);
> > > > > +
> > > > > + return 0;
> > > > > +};
> > > > > +
> > > > > +int set_clk_qspi(void)
> > > > > +{
> > > > > + /*
> > > > > + * set qspi root
> > > > > + * sys pll1 100M
> > > > > + */
> > > > > + clock_enable(CCGR_QSPI, 0);
> > > > > + clock_set_target_val(QSPI_CLK_ROOT, CLK_ROOT_ON |
> > > > > + CLK_ROOT_SOURCE_SEL(7));
> > > > > + clock_enable(CCGR_QSPI, 1);
> > > > > +
> > > > > + return 0;
> > > > > +}
> > > > > +
> > > > > +#ifdef CONFIG_FEC_MXC
> > > > > +int set_clk_enet(enum enet_freq type)
> > > > > +{
> > > > > + u32 target;
> > > > > + u32 enet1_ref;
> > > > > +
> > > > > + /* disable the clock first */
> > > > > + clock_enable(CCGR_ENET1, 0);
> > > > > + clock_enable(CCGR_SIM_ENET, 0);
> > > > > +
> > > > > + switch (type) {
> > > > > + case ENET_125MHZ:
> > > > > + enet1_ref =
> > > > > ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
> > > > > + break;
> > > > > + case ENET_50MHZ:
> > > > > + enet1_ref =
> > > > > ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
> > > > > + break;
> > > > > + case ENET_25MHZ:
> > > > > + enet1_ref =
> > > > > ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
> > > > > + break;
> > > > > + default:
> > > > > + return -EINVAL;
> > > > > + }
> > > > > +
> > > > > + /* set enet axi clock 266Mhz */
> > > > > + target = CLK_ROOT_ON |
> > > > ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
> > > > > + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
> > > > > + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
> > > > > + clock_set_target_val(ENET_AXI_CLK_ROOT, target);
> > > > > +
> > > > > + target = CLK_ROOT_ON | enet1_ref |
> > > > > + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
> > > > > + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
> > > > > + clock_set_target_val(ENET_REF_CLK_ROOT, target);
> > > > > +
> > > > > + target = CLK_ROOT_ON |
> > > > > ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
> > > > > + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
> > > > > + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
> > > > > + clock_set_target_val(ENET_TIMER_CLK_ROOT, target);
> > > > > +
> > > > > +#ifdef CONFIG_FEC_MXC_25M_REF_CLK
> > > > > + target = CLK_ROOT_ON |
> > > > > +
> > > > > ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK |
> > > > > + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
> > > > > + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
> > > > > + clock_set_target_val(ENET_PHY_REF_CLK_ROOT, target);
> > > > > +#endif
> > > > > + /* enable clock */
> > > > > + clock_enable(CCGR_SIM_ENET, 1);
> > > > > + clock_enable(CCGR_ENET1, 1);
> > > > > +
> > > > > + return 0;
> > > > > +}
> > > > > +#endif
> > > > > +
> > > > > +u32 get_root_src_clk(enum clk_root_src root_src)
> > > > > +{
> > > > > + switch (root_src) {
> > > > > + case OSC_24M_CLK:
> > > > > + return 24000000u;
> > > > > + case OSC_HDMI_CLK:
> > > > > + return 26000000u;
> > > > > + case OSC_32K_CLK:
> > > > > + return 32000u;
> > > > > + case ARM_PLL_CLK:
> > > > > + case GPU_PLL_CLK:
> > > > > + case VPU_PLL_CLK:
> > > > > + case SYSTEM_PLL1_800M_CLK:
> > > > > + case SYSTEM_PLL1_400M_CLK:
> > > > > + case SYSTEM_PLL1_266M_CLK:
> > > > > + case SYSTEM_PLL1_200M_CLK:
> > > > > + case SYSTEM_PLL1_160M_CLK:
> > > > > + case SYSTEM_PLL1_133M_CLK:
> > > > > + case SYSTEM_PLL1_100M_CLK:
> > > > > + case SYSTEM_PLL1_80M_CLK:
> > > > > + case SYSTEM_PLL1_40M_CLK:
> > > > > + case SYSTEM_PLL2_1000M_CLK:
> > > > > + case SYSTEM_PLL2_500M_CLK:
> > > > > + case SYSTEM_PLL2_333M_CLK:
> > > > > + case SYSTEM_PLL2_250M_CLK:
> > > > > + case SYSTEM_PLL2_200M_CLK:
> > > > > + case SYSTEM_PLL2_166M_CLK:
> > > > > + case SYSTEM_PLL2_125M_CLK:
> > > > > + case SYSTEM_PLL2_100M_CLK:
> > > > > + case SYSTEM_PLL2_50M_CLK:
> > > > > + case SYSTEM_PLL3_CLK:
> > > > > + return decode_intpll(root_src);
> > > > > + case DRAM_PLL1_CLK:
> > > > > + case AUDIO_PLL1_CLK:
> > > > > + case AUDIO_PLL2_CLK:
> > > > > + case VIDEO_PLL_CLK:
> > > > > + return decode_fracpll(root_src);
> > > > > + default:
> > > > > + return 0;
> > > > > + }
> > > > > +
> > > > > + return 0;
> > > > > +}
> > > > > +
> > > > > +u32 get_root_clk(enum clk_root_index clock_id)
> > > > > +{
> > > > > + enum clk_root_src root_src;
> > > > > + u32 post_podf, pre_podf, root_src_clk;
> > > > > +
> > > > > + if (clock_root_enabled(clock_id) <= 0)
> > > > > + return 0;
> > > > > +
> > > > > + if (clock_get_prediv(clock_id, &pre_podf) < 0)
> > > > > + return 0;
> > > > > +
> > > > > + if (clock_get_postdiv(clock_id, &post_podf) < 0)
> > > > > + return 0;
> > > > > +
> > > > > + if (clock_get_src(clock_id, &root_src) < 0)
> > > > > + return 0;
> > > > > +
> > > > > + root_src_clk = get_root_src_clk(root_src);
> > > > > +
> > > > > + return root_src_clk / (post_podf + 1) / (pre_podf +
> > > > > 1); +}
> > > > > +
> > > > > +u32 mxc_get_clock(enum mxc_clock clk)
> > > > > +{
> > > > > + u32 val;
> > > > > +
> > > > > + switch (clk) {
> > > > > + case MXC_ARM_CLK:
> > > > > + return get_root_clk(ARM_A53_CLK_ROOT);
> > > > > + case MXC_IPG_CLK:
> > > > > + clock_get_target_val(IPG_CLK_ROOT, &val);
> > > > > + val = val & 0x3;
> > > > > + return get_root_clk(AHB_CLK_ROOT) / 2 / (val
> > > > > + 1);
> > > > > + case MXC_CSPI_CLK:
> > > > > + return get_root_clk(ECSPI1_CLK_ROOT);
> > > > > + case MXC_ESDHC_CLK:
> > > > > + return get_root_clk(USDHC1_CLK_ROOT);
> > > > > + case MXC_ESDHC2_CLK:
> > > > > + return get_root_clk(USDHC2_CLK_ROOT);
> > > > > + case MXC_ESDHC3_CLK:
> > > > > + return get_root_clk(USDHC3_CLK_ROOT);
> > > > > + case MXC_I2C_CLK:
> > > > > + return get_root_clk(I2C1_CLK_ROOT);
> > > > > + case MXC_UART_CLK:
> > > > > + return get_root_clk(UART1_CLK_ROOT);
> > > > > + case MXC_QSPI_CLK:
> > > > > + return get_root_clk(QSPI_CLK_ROOT);
> > > > > + default:
> > > > > + printf("Unsupported mxc_clock %d\n", clk);
> > > > > + break;
> > > > > + }
> > > > > +
> > > > > + return 0;
> > > > > +}
> > > > > +
> > > > > +u32 imx_get_uartclk(void)
> > > > > +{
> > > > > + return mxc_get_clock(MXC_UART_CLK);
> > > > > +}
> > > > > +
> > > > > +u32 imx_get_fecclk(void)
> > > > > +{
> > > > > + return get_root_clk(ENET_AXI_CLK_ROOT);
> > > > > +}
> > > > > +
> > > > > +/*
> > > > > + * Dump some clockes.
> > > > > + */
> > > > > +#ifndef CONFIG_SPL_BUILD
> > > > > +int do_mscale_showclocks(cmd_tbl_t *cmdtp, int flag, int
> > > > > argc,
> > > > > + char * const argv[])
> > > > > +{
> > > > > + u32 freq;
> > > > > +
> > > > > + freq = decode_intpll(ARM_PLL_CLK);
> > > > > + printf("ARM_PLL %8d MHz\n", freq / 1000000);
> > > > > + freq = decode_intpll(SYSTEM_PLL1_800M_CLK);
> > > > > + printf("SYS_PLL1_800 %8d MHz\n", freq / 1000000);
> > > > > + freq = decode_intpll(SYSTEM_PLL1_400M_CLK);
> > > > > + printf("SYS_PLL1_400 %8d MHz\n", freq / 1000000);
> > > > > + freq = decode_intpll(SYSTEM_PLL1_266M_CLK);
> > > > > + printf("SYS_PLL1_266 %8d MHz\n", freq / 1000000);
> > > > > + freq = decode_intpll(SYSTEM_PLL1_160M_CLK);
> > > > > + printf("SYS_PLL1_160 %8d MHz\n", freq / 1000000);
> > > > > + freq = decode_intpll(SYSTEM_PLL1_133M_CLK);
> > > > > + printf("SYS_PLL1_133 %8d MHz\n", freq / 1000000);
> > > > > + freq = decode_intpll(SYSTEM_PLL1_100M_CLK);
> > > > > + printf("SYS_PLL1_100 %8d MHz\n", freq / 1000000);
> > > > > + freq = decode_intpll(SYSTEM_PLL1_80M_CLK);
> > > > > + printf("SYS_PLL1_80 %8d MHz\n", freq / 1000000);
> > > > > + freq = decode_intpll(SYSTEM_PLL1_40M_CLK);
> > > > > + printf("SYS_PLL1_40 %8d MHz\n", freq / 1000000);
> > > > > + freq = decode_intpll(SYSTEM_PLL2_1000M_CLK);
> > > > > + printf("SYS_PLL2_1000 %8d MHz\n", freq / 1000000);
> > > > > + freq = decode_intpll(SYSTEM_PLL2_500M_CLK);
> > > > > + printf("SYS_PLL2_500 %8d MHz\n", freq / 1000000);
> > > > > + freq = decode_intpll(SYSTEM_PLL2_333M_CLK);
> > > > > + printf("SYS_PLL2_333 %8d MHz\n", freq / 1000000);
> > > > > + freq = decode_intpll(SYSTEM_PLL2_250M_CLK);
> > > > > + printf("SYS_PLL2_250 %8d MHz\n", freq / 1000000);
> > > > > + freq = decode_intpll(SYSTEM_PLL2_200M_CLK);
> > > > > + printf("SYS_PLL2_200 %8d MHz\n", freq / 1000000);
> > > > > + freq = decode_intpll(SYSTEM_PLL2_166M_CLK);
> > > > > + printf("SYS_PLL2_166 %8d MHz\n", freq / 1000000);
> > > > > + freq = decode_intpll(SYSTEM_PLL2_125M_CLK);
> > > > > + printf("SYS_PLL2_125 %8d MHz\n", freq / 1000000);
> > > > > + freq = decode_intpll(SYSTEM_PLL2_100M_CLK);
> > > > > + printf("SYS_PLL2_100 %8d MHz\n", freq / 1000000);
> > > > > + freq = decode_intpll(SYSTEM_PLL2_50M_CLK);
> > > > > + printf("SYS_PLL2_50 %8d MHz\n", freq / 1000000);
> > > > > + freq = decode_intpll(SYSTEM_PLL3_CLK);
> > > > > + printf("SYS_PLL3 %8d MHz\n", freq / 1000000);
> > > > > + freq = mxc_get_clock(MXC_UART_CLK);
> > > > > + printf("UART1 %8d MHz\n", freq / 1000000);
> > > > > + freq = mxc_get_clock(MXC_ESDHC_CLK);
> > > > > + printf("USDHC1 %8d MHz\n", freq / 1000000);
> > > > > + freq = mxc_get_clock(MXC_QSPI_CLK);
> > > > > + printf("QSPI %8d MHz\n", freq / 1000000);
> > > > > +
> > > > > + return 0;
> > > > > +}
> > > > > +
> > > > > +U_BOOT_CMD(
> > > > > + clocks, CONFIG_SYS_MAXARGS, 1,
> > > > > do_mscale_showclocks,
> > > > > + "display clocks",
> > > > > + ""
> > > > > +);
> > > > > +#endif
> > > > > diff --git a/arch/arm/mach-imx/imx8m/clock_slice.c
> > > > > b/arch/arm/mach-imx/imx8m/clock_slice.c index
> > > > > 1a67c626f1..dc2a018e00 100644 ---
> > > > > a/arch/arm/mach-imx/imx8m/clock_slice.c +++
> > > > > b/arch/arm/mach-imx/imx8m/clock_slice.c @@ -13,6 +13,7 @@
> > > > >
> > > > > static struct ccm_reg *ccm_reg = (struct ccm_reg
> > *)CCM_BASE_ADDR;
> > > > >
> > > > > +#ifdef CONFIG_IMX8MQ
> > > > > static struct clk_root_map root_array[] = {
> > > > > {ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0,
> > > > > {OSC_25M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
> > > > > @@ -474,6 +475,466 @@ static struct clk_root_map root_array[]
> > > > > = { {DRAM_PLL1_CLK}
> > > > > },
> > > > > };
> > > > > +#elif defined(CONFIG_IMX8MM)
> > > > > +static struct clk_root_map root_array[] = {
> > > > > + {ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0,
> > > > > + {OSC_24M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
> > > > > + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
> > > > > + SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK,
> > SYSTEM_PLL3_CLK}
> > > > > + },
> > > > > + {ARM_M4_CLK_ROOT, CORE_CLOCK_SLICE, 1,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK,
> > > > > SYSTEM_PLL2_250M_CLK,
> > > > > + SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
> > > > > + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
> > > > > + },
> > > > > + {VPU_A53_CLK_ROOT, CORE_CLOCK_SLICE, 2,
> > > > > + {OSC_24M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
> > > > > + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
> > > > > + SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, VPU_PLL_CLK}
> > > > > + },
> > > > > + {GPU3D_CLK_ROOT, CORE_CLOCK_SLICE, 3,
> > > > > + {OSC_24M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
> > > > > + SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
> > > > > + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
> > > > > + },
> > > > > + {GPU2D_CLK_ROOT, CORE_CLOCK_SLICE, 4,
> > > > > + {OSC_24M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
> > > > > + SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
> > > > > + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
> > > > > + },
> > > > > + {MAIN_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 0,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK,
> > > > > SYSTEM_PLL1_800M_CLK,
> > > > > + SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_1000M_CLK,
> > > > > + AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
> > > > > SYSTEM_PLL1_100M_CLK}
> > > > > + },
> > > > > + {ENET_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 1,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK,
> > > > > SYSTEM_PLL1_800M_CLK,
> > > > > + SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
> > > > > + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
> > > > > + },
> > > > > + {NAND_USDHC_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 2,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK,
> > > > > SYSTEM_PLL1_800M_CLK,
> > > > > + SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK,
> > > > > + SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK,
> > AUDIO_PLL1_CLK}
> > > > > + },
> > > > > + {VPU_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 3,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, VPU_PLL_CLK,
> > > > > + AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK,
> > SYSTEM_PLL2_1000M_CLK,
> > > > > + SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_100M_CLK}
> > > > > + },
> > > > > + {DISPLAY_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 4,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL2_1000M_CLK,
> > > > SYSTEM_PLL1_800M_CLK,
> > > > > + SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK,
> > > > > AUDIO_PLL2_CLK,
> > > > > + EXT_CLK_1, EXT_CLK_4}
> > > > > + },
> > > > > + {DISPLAY_APB_CLK_ROOT, BUS_CLOCK_SLICE, 5,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK,
> > > > > SYSTEM_PLL1_800M_CLK,
> > > > > + SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK,
> > > > > AUDIO_PLL2_CLK,
> > > > > + EXT_CLK_1, EXT_CLK_3}
> > > > > + },
> > > > > + {DISPLAY_RTRM_CLK_ROOT, BUS_CLOCK_SLICE, 6,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK,
> > > > > SYSTEM_PLL2_200M_CLK,
> > > > > + SYSTEM_PLL2_1000M_CLK, AUDIO_PLL1_CLK,
> > > > > VIDEO_PLL_CLK,
> > > > > + EXT_CLK_2, EXT_CLK_3}
> > > > > + },
> > > > > + {USB_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 7,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK,
> > > > > SYSTEM_PLL1_800M_CLK,
> > > > > + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
> > > > > + EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
> > > > > + },
> > > > > + {GPU_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 8,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
> > > > > + SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
> > > > > + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
> > > > > + },
> > > > > + {GPU_AHB_CLK_ROOT, BUS_CLOCK_SLICE, 9,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
> > > > > + SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
> > > > > + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
> > > > > + },
> > > > > + {NOC_CLK_ROOT, BUS_CLOCK_SLICE, 10,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK,
> > > > > + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK,
> > > > > + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
> > > > > + },
> > > > > + {NOC_APB_CLK_ROOT, BUS_CLOCK_SLICE, 11,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL3_CLK,
> > > > > + SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_200M_CLK,
> > > > > + SYSTEM_PLL1_800M_CLK, AUDIO_PLL1_CLK,
> > > > > VIDEO_PLL_CLK}
> > > > > + },
> > > > > + {AHB_CLK_ROOT, AHB_CLOCK_SLICE, 0,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK,
> > > > > SYSTEM_PLL1_800M_CLK,
> > > > > + SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_125M_CLK,
> > > > > + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
> > > > > + },
> > > > > + {AUDIO_AHB_CLK_ROOT, AHB_CLOCK_SLICE, 1,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK,
> > > > > SYSTEM_PLL1_800M_CLK,
> > > > > + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_166M_CLK,
> > > > > + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
> > > > > + },
> > > > > + {MIPI_DSI_ESC_RX_CLK_ROOT, AHB_CLOCK_SLICE, 2,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK,
> > SYSTEM_PLL1_80M_CLK,
> > > > > + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> > > > > + SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
> > > > > + },
> > > > > + {DRAM_ALT_CLK_ROOT, IP_CLOCK_SLICE, 0,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK,
> > > > > SYSTEM_PLL1_100M_CLK,
> > > > > + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_1000M_CLK,
> > > > > + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK,
> > SYSTEM_PLL1_266M_CLK}
> > > > > + },
> > > > > + {DRAM_APB_CLK_ROOT, IP_CLOCK_SLICE, 1,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK,
> > SYSTEM_PLL1_40M_CLK,
> > > > > + SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
> > > > > + SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK,
> > AUDIO_PLL2_CLK}
> > > > > + },
> > > > > + {VPU_G1_CLK_ROOT, IP_CLOCK_SLICE, 2,
> > > > > + {OSC_24M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
> > > > > + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_100M_CLK,
> > > > > + SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK,
> > AUDIO_PLL1_CLK}
> > > > > + },
> > > > > + {VPU_G2_CLK_ROOT, IP_CLOCK_SLICE, 3,
> > > > > + {OSC_24M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
> > > > > + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_100M_CLK,
> > > > > + SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK,
> > AUDIO_PLL1_CLK}
> > > > > + },
> > > > > + {DISPLAY_DTRC_CLK_ROOT, IP_CLOCK_SLICE, 4,
> > > > > + {OSC_24M_CLK, VIDEO_PLL2_CLK, SYSTEM_PLL1_800M_CLK,
> > > > > + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_160M_CLK,
> > > > > + VIDEO_PLL_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK}
> > > > > + },
> > > > > + {DISPLAY_DC8000_CLK_ROOT, IP_CLOCK_SLICE, 5,
> > > > > + {OSC_24M_CLK, VIDEO_PLL2_CLK, SYSTEM_PLL1_800M_CLK,
> > > > > + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_160M_CLK,
> > > > > + VIDEO_PLL_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK}
> > > > > + },
> > > > > + {PCIE_CTRL_CLK_ROOT, IP_CLOCK_SLICE, 6,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL2_250M_CLK,
> > > > > SYSTEM_PLL2_200M_CLK,
> > > > > + SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
> > > > > + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_333M_CLK,
> > > > > SYSTEM_PLL3_CLK}
> > > > > + },
> > > > > + {PCIE_PHY_CLK_ROOT, IP_CLOCK_SLICE, 7,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK,
> > > > > SYSTEM_PLL2_500M_CLK,
> > > > > + EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
> > > > > + SYSTEM_PLL1_400M_CLK}
> > > > > + },
> > > > > + {PCIE_AUX_CLK_ROOT, IP_CLOCK_SLICE, 8,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK,
> > SYSTEM_PLL2_50M_CLK,
> > > > > + SYSTEM_PLL3_CLK, SYSTEM_PLL2_100M_CLK,
> > > > SYSTEM_PLL1_80M_CLK,
> > > > > + SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_200M_CLK}
> > > > > + },
> > > > > + {DC_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 9,
> > > > > + {OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
> > > > > + AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
> > > > > + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
> > > > > + },
> > > > > + {LCDIF_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 10,
> > > > > + {OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
> > > > > + AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
> > > > > + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
> > > > > + },
> > > > > + {SAI1_CLK_ROOT, IP_CLOCK_SLICE, 11,
> > > > > + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
> > > > > + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
> > > > > + OSC_HDMI_CLK, EXT_CLK_1, EXT_CLK_2}
> > > > > + },
> > > > > + {SAI2_CLK_ROOT, IP_CLOCK_SLICE, 12,
> > > > > + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
> > > > > + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
> > > > > + OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
> > > > > + },
> > > > > + {SAI3_CLK_ROOT, IP_CLOCK_SLICE, 13,
> > > > > + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
> > > > > + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
> > > > > + OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
> > > > > + },
> > > > > + {SAI4_CLK_ROOT, IP_CLOCK_SLICE, 14,
> > > > > + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
> > > > > + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
> > > > > + OSC_HDMI_CLK, EXT_CLK_1, EXT_CLK_2}
> > > > > + },
> > > > > + {SAI5_CLK_ROOT, IP_CLOCK_SLICE, 15,
> > > > > + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
> > > > > + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
> > > > > + OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
> > > > > + },
> > > > > + {SAI6_CLK_ROOT, IP_CLOCK_SLICE, 16,
> > > > > + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
> > > > > + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
> > > > > + OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
> > > > > + },
> > > > > + {SPDIF1_CLK_ROOT, IP_CLOCK_SLICE, 17,
> > > > > + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
> > > > > + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
> > > > > + OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
> > > > > + },
> > > > > + {SPDIF2_CLK_ROOT, IP_CLOCK_SLICE, 18,
> > > > > + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
> > > > > + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
> > > > > + OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
> > > > > + },
> > > > > + {ENET_REF_CLK_ROOT, IP_CLOCK_SLICE, 19,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK,
> > SYSTEM_PLL2_50M_CLK,
> > > > > + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
> > > > > + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, EXT_CLK_4}
> > > > > + },
> > > > > + {ENET_TIMER_CLK_ROOT, IP_CLOCK_SLICE, 20,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK,
> > > > > + EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
> > > > > + VIDEO_PLL_CLK}
> > > > > + },
> > > > > + {ENET_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 21,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL2_50M_CLK,
> > SYSTEM_PLL2_125M_CLK,
> > > > > + SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_500M_CLK,
> > > > > + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
> > > > > + },
> > > > > + {NAND_CLK_ROOT, IP_CLOCK_SLICE, 22,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, AUDIO_PLL1_CLK,
> > > > > + SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK,
> > SYSTEM_PLL3_CLK,
> > > > > + SYSTEM_PLL2_250M_CLK, VIDEO_PLL_CLK}
> > > > > + },
> > > > > + {QSPI_CLK_ROOT, IP_CLOCK_SLICE, 23,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK,
> > > > > SYSTEM_PLL2_333M_CLK,
> > > > > + SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK,
> > > > > + SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK,
> > > > > SYSTEM_PLL1_100M_CLK}
> > > > > + },
> > > > > + {USDHC1_CLK_ROOT, IP_CLOCK_SLICE, 24,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK,
> > > > > SYSTEM_PLL1_800M_CLK,
> > > > > + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
> > > > > + SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK,
> > > > SYSTEM_PLL1_100M_CLK}
> > > > > + },
> > > > > + {USDHC2_CLK_ROOT, IP_CLOCK_SLICE, 25,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK,
> > > > > SYSTEM_PLL1_800M_CLK,
> > > > > + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
> > > > > + SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK,
> > > > SYSTEM_PLL1_100M_CLK}
> > > > > + },
> > > > > + {I2C1_CLK_ROOT, IP_CLOCK_SLICE, 26,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK,
> > SYSTEM_PLL2_50M_CLK,
> > > > > + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
> > > > > + AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
> > > > > + },
> > > > > + {I2C2_CLK_ROOT, IP_CLOCK_SLICE, 27,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK,
> > SYSTEM_PLL2_50M_CLK,
> > > > > + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
> > > > > + AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
> > > > > + },
> > > > > + {I2C3_CLK_ROOT, IP_CLOCK_SLICE, 28,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK,
> > SYSTEM_PLL2_50M_CLK,
> > > > > + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
> > > > > + AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
> > > > > + },
> > > > > + {I2C4_CLK_ROOT, IP_CLOCK_SLICE, 29,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK,
> > SYSTEM_PLL2_50M_CLK,
> > > > > + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
> > > > > + AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
> > > > > + },
> > > > > + {UART1_CLK_ROOT, IP_CLOCK_SLICE, 30,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK,
> > SYSTEM_PLL2_200M_CLK,
> > > > > + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
> > > > > + EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
> > > > > + },
> > > > > + {UART2_CLK_ROOT, IP_CLOCK_SLICE, 31,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK,
> > SYSTEM_PLL2_200M_CLK,
> > > > > + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
> > > > > + EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
> > > > > + },
> > > > > + {UART3_CLK_ROOT, IP_CLOCK_SLICE, 32,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK,
> > SYSTEM_PLL2_200M_CLK,
> > > > > + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
> > > > > + EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
> > > > > + },
> > > > > + {UART4_CLK_ROOT, IP_CLOCK_SLICE, 33,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK,
> > SYSTEM_PLL2_200M_CLK,
> > > > > + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
> > > > > + EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
> > > > > + },
> > > > > + {USB_CORE_REF_CLK_ROOT, IP_CLOCK_SLICE, 34,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL1_100M_CLK,
> > SYSTEM_PLL1_40M_CLK,
> > > > > + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
> > > > > + EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
> > > > > + },
> > > > > + {USB_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 35,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL1_100M_CLK,
> > SYSTEM_PLL1_40M_CLK,
> > > > > + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
> > > > > + EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
> > > > > + },
> > > > > + {GIC_CLK_ROOT, IP_CLOCK_SLICE, 36,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK,
> > SYSTEM_PLL1_40M_CLK,
> > > > > + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_800M_CLK,
> > > > > + EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
> > > > > + },
> > > > > + {ECSPI1_CLK_ROOT, IP_CLOCK_SLICE, 37,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK,
> > SYSTEM_PLL1_40M_CLK,
> > > > > + SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
> > > > > + SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK,
> > AUDIO_PLL2_CLK}
> > > > > + },
> > > > > + {ECSPI2_CLK_ROOT, IP_CLOCK_SLICE, 38,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK,
> > SYSTEM_PLL1_40M_CLK,
> > > > > + SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
> > > > > + SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK,
> > AUDIO_PLL2_CLK}
> > > > > + },
> > > > > + {PWM1_CLK_ROOT, IP_CLOCK_SLICE, 39,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK,
> > > > > SYSTEM_PLL1_160M_CLK,
> > > > > + SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
> > > > > + SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
> > > > > + },
> > > > > + {PWM2_CLK_ROOT, IP_CLOCK_SLICE, 40,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK,
> > > > > SYSTEM_PLL1_160M_CLK,
> > > > > + SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
> > > > > + SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
> > > > > + },
> > > > > + {PWM3_CLK_ROOT, IP_CLOCK_SLICE, 41,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK,
> > > > > SYSTEM_PLL1_160M_CLK,
> > > > > + SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2,
> > > > > + SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
> > > > > + },
> > > > > + {PWM4_CLK_ROOT, IP_CLOCK_SLICE, 42,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK,
> > > > > SYSTEM_PLL1_160M_CLK,
> > > > > + SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2,
> > > > > + SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
> > > > > + },
> > > > > + {GPT1_CLK_ROOT, IP_CLOCK_SLICE, 43,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK,
> > > > > SYSTEM_PLL1_400M_CLK,
> > > > > + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
> > > > > + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
> > > > > + },
> > > > > + {GPT2_CLK_ROOT, IP_CLOCK_SLICE, 44,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK,
> > > > > SYSTEM_PLL1_400M_CLK,
> > > > > + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
> > > > > + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
> > > > > + },
> > > > > + {GPT3_CLK_ROOT, IP_CLOCK_SLICE, 45,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK,
> > > > > SYSTEM_PLL1_400M_CLK,
> > > > > + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
> > > > > + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
> > > > > + },
> > > > > + {GPT4_CLK_ROOT, IP_CLOCK_SLICE, 46,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK,
> > > > > SYSTEM_PLL1_400M_CLK,
> > > > > + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
> > > > > + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
> > > > > + },
> > > > > + {GPT5_CLK_ROOT, IP_CLOCK_SLICE, 47,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK,
> > > > > SYSTEM_PLL1_400M_CLK,
> > > > > + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
> > > > > + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
> > > > > + },
> > > > > + {GPT6_CLK_ROOT, IP_CLOCK_SLICE, 48,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK,
> > > > > SYSTEM_PLL1_400M_CLK,
> > > > > + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
> > > > > + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
> > > > > + },
> > > > > + {TRACE_CLK_ROOT, IP_CLOCK_SLICE, 49,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK,
> > > > > SYSTEM_PLL1_160M_CLK,
> > > > > + VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
> > > > > + SYSTEM_PLL3_CLK, EXT_CLK_1, EXT_CLK_3}
> > > > > + },
> > > > > + {WDOG_CLK_ROOT, IP_CLOCK_SLICE, 50,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK,
> > > > > SYSTEM_PLL1_160M_CLK,
> > > > > + VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
> > > > > + SYSTEM_PLL3_CLK, SYSTEM_PLL1_80M_CLK,
> > > > SYSTEM_PLL2_166M_CLK}
> > > > > + },
> > > > > + {WRCLK_CLK_ROOT, IP_CLOCK_SLICE, 51,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL1_40M_CLK, VPU_PLL_CLK,
> > > > > + SYSTEM_PLL3_CLK, SYSTEM_PLL2_200M_CLK,
> > > > > + SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_500M_CLK,
> > > > > SYSTEM_PLL1_100M_CLK}
> > > > > + },
> > > > > + {IPP_DO_CLKO1, IP_CLOCK_SLICE, 52,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, OSC_HDMI_CLK,
> > > > > + SYSTEM_PLL1_200M_CLK, AUDIO_PLL2_CLK,
> > > > > + SYSTEM_PLL2_500M_CLK, VPU_PLL_CLK,
> > SYSTEM_PLL1_80M_CLK}
> > > > > + },
> > > > > + {IPP_DO_CLKO2, IP_CLOCK_SLICE, 53,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK,
> > > > > SYSTEM_PLL1_400M_CLK,
> > > > > + SYSTEM_PLL2_166M_CLK, SYSTEM_PLL3_CLK,
> > > > > + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, OSC_32K_CLK}
> > > > > + },
> > > > > + {MIPI_DSI_CORE_CLK_ROOT, IP_CLOCK_SLICE, 54,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK,
> > > > > SYSTEM_PLL2_250M_CLK,
> > > > > + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> > > > > + SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
> > > > > + },
> > > > > + {MIPI_DSI_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 55,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK,
> > > > > SYSTEM_PLL2_100M_CLK,
> > > > > + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> > > > > + EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
> > > > > + },
> > > > > + {MIPI_DSI_DBI_CLK_ROOT, IP_CLOCK_SLICE, 56,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK,
> > > > > SYSTEM_PLL2_100M_CLK,
> > > > > + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> > > > > + SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
> > > > > + },
> > > > > + {USDHC3_CLK_ROOT, IP_CLOCK_SLICE, 57,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK,
> > > > > SYSTEM_PLL1_800M_CLK,
> > > > > + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
> > > > > + SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK,
> > > > SYSTEM_PLL1_100M_CLK}
> > > > > + },
> > > > > + {MIPI_CSI1_CORE_CLK_ROOT, IP_CLOCK_SLICE, 58,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK,
> > > > > SYSTEM_PLL2_250M_CLK,
> > > > > + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> > > > > + SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
> > > > > + },
> > > > > + {MIPI_CSI1_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 59,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK,
> > > > > SYSTEM_PLL2_100M_CLK,
> > > > > + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> > > > > + EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
> > > > > + },
> > > > > + {MIPI_CSI1_ESC_CLK_ROOT, IP_CLOCK_SLICE, 60,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK,
> > SYSTEM_PLL1_80M_CLK,
> > > > > + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> > > > > + SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
> > > > > + },
> > > > > + {MIPI_CSI2_CORE_CLK_ROOT, IP_CLOCK_SLICE, 61,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK,
> > > > > SYSTEM_PLL2_250M_CLK,
> > > > > + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> > > > > + SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
> > > > > + },
> > > > > + {MIPI_CSI2_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 62,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK,
> > > > > SYSTEM_PLL2_100M_CLK,
> > > > > + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> > > > > + EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
> > > > > + },
> > > > > + {MIPI_CSI2_ESC_CLK_ROOT, IP_CLOCK_SLICE, 63,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK,
> > SYSTEM_PLL1_80M_CLK,
> > > > > + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> > > > > + SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
> > > > > + },
> > > > > + {PCIE2_CTRL_CLK_ROOT, IP_CLOCK_SLICE, 64,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL2_250M_CLK,
> > > > > SYSTEM_PLL2_200M_CLK,
> > > > > + SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
> > > > > + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_333M_CLK,
> > > > > SYSTEM_PLL3_CLK}
> > > > > + },
> > > > > + {PCIE2_PHY_CLK_ROOT, IP_CLOCK_SLICE, 65,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK,
> > > > > SYSTEM_PLL2_500M_CLK,
> > > > > + EXT_CLK_1, EXT_CLK_2, EXT_CLK_3,
> > > > > + EXT_CLK_4, SYSTEM_PLL1_400M_CLK}
> > > > > + },
> > > > > + {PCIE2_AUX_CLK_ROOT, IP_CLOCK_SLICE, 66,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK,
> > SYSTEM_PLL2_50M_CLK,
> > > > > + SYSTEM_PLL3_CLK, SYSTEM_PLL2_100M_CLK,
> > > > > + SYSTEM_PLL1_80M_CLK, SYSTEM_PLL1_160M_CLK,
> > > > > SYSTEM_PLL1_200M_CLK}
> > > > > + },
> > > > > + {ECSPI3_CLK_ROOT, IP_CLOCK_SLICE, 67,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK,
> > SYSTEM_PLL1_40M_CLK,
> > > > > + SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
> > > > > + SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK,
> > AUDIO_PLL2_CLK}
> > > > > + },
> > > > > + {PDM_CLK_ROOT, IP_CLOCK_SLICE, 68,
> > > > > + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK,
> > > > > + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
> > > > > + SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK},
> > > > > + },
> > > > > + {VPU_H1_CLK_ROOT, IP_CLOCK_SLICE, 69,
> > > > > + {OSC_24M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
> > > > > + SYSTEM_PLL2_1000M_CLK, AUDIO_PLL2_CLK,
> > > > > + SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK,
> > AUDIO_PLL1_CLK}
> > > > > + },
> > > > > + {DRAM_SEL_CFG, DRAM_SEL_CLOCK_SLICE, 0,
> > > > > + {DRAM_PLL1_CLK}
> > > > > + },
> > > > > + {CORE_SEL_CFG, CORE_SEL_CLOCK_SLICE, 0,
> > > > > + {DRAM_PLL1_CLK}
> > > > > + },
> > > > > +};
> > > > > +#endif
> > > > >
> > > > > static int select(enum clk_root_index clock_id)
> > > > > {
> > > >
> > > >
> > > >
> > > >
> > > > Best regards,
> > > >
> > > > Lukasz Majewski
> > > >
> > > > --
> > > >
> > > > DENX Software Engineering GmbH, Managing Director: Wolfgang
> > > > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194
> > > > Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax:
> > > > (+49)-8142-66989-80 Email: lukma at denx.de
> >
> >
> >
> >
> > Best regards,
> >
> > Lukasz Majewski
> >
> > --
> >
> > DENX Software Engineering GmbH, Managing Director: Wolfgang
> > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell,
> > Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> > lukma at denx.de
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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* [U-Boot] [PATCH 11/20] imx8m: add pin header for i.MX8MM
2019-01-28 9:39 [U-Boot] [PATCH 00/20] imx: add i.MX8MM support Peng Fan
` (9 preceding siblings ...)
2019-01-28 9:39 ` [U-Boot] [PATCH 10/20] imx8m: add clk support for i.MX8MM Peng Fan
@ 2019-01-28 9:39 ` Peng Fan
2019-01-28 9:39 ` [U-Boot] [PATCH 12/20] imx: add i.MX8MM PE property Peng Fan
` (8 subsequent siblings)
19 siblings, 0 replies; 39+ messages in thread
From: Peng Fan @ 2019-01-28 9:39 UTC (permalink / raw)
To: u-boot
Add pin header file for i.MX8MM
To IMX8MM_PAD_NAND_WE_B_USDHC3_CLK, IOMUX_CONFIG_SION needs to be
selected.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/include/asm/arch-imx8m/imx8mm_pins.h | 691 ++++++++++++++++++++++++++
1 file changed, 691 insertions(+)
create mode 100644 arch/arm/include/asm/arch-imx8m/imx8mm_pins.h
diff --git a/arch/arm/include/asm/arch-imx8m/imx8mm_pins.h b/arch/arm/include/asm/arch-imx8m/imx8mm_pins.h
new file mode 100644
index 0000000000..210e96e1db
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8m/imx8mm_pins.h
@@ -0,0 +1,691 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018-2019 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX8MM_PINS_H__
+#define __ASM_ARCH_IMX8MM_PINS_H__
+
+#include <asm/mach-imx/iomux-v3.h>
+
+enum {
+ IMX8MM_PAD_GPIO1_IO00_GPIO1_IO0 = IOMUX_PAD(0x0290, 0x0028, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT = IOMUX_PAD(0x0290, 0x0028, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO00_XTALOSC_REF_CLK_32K = IOMUX_PAD(0x0290, 0x0028, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO00_CCM_EXT_CLK1 = IOMUX_PAD(0x0290, 0x0028, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO01_GPIO1_IO1 = IOMUX_PAD(0x0294, 0x002C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO01_PWM1_OUT = IOMUX_PAD(0x0294, 0x002C, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO01_XTALOSC_REF_CLK_24M = IOMUX_PAD(0x0294, 0x002C, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO01_CCM_EXT_CLK2 = IOMUX_PAD(0x0294, 0x002C, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO02_GPIO1_IO2 = IOMUX_PAD(0x0298, 0x0030, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B = IOMUX_PAD(0x0298, 0x0030, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_ANY = IOMUX_PAD(0x0298, 0x0030, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO03_GPIO1_IO3 = IOMUX_PAD(0x029C, 0x0034, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO03_USDHC1_VSELECT = IOMUX_PAD(0x029C, 0x0034, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO03_SDMA1_EXT_EVENT0 = IOMUX_PAD(0x029C, 0x0034, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO04_GPIO1_IO4 = IOMUX_PAD(0x02A0, 0x0038, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO04_USDHC2_VSELECT = IOMUX_PAD(0x02A0, 0x0038, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO04_SDMA1_EXT_EVENT1 = IOMUX_PAD(0x02A0, 0x0038, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO05_GPIO1_IO5 = IOMUX_PAD(0x02A4, 0x003C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO05_ARM_PLATFORM_M4_NMI = IOMUX_PAD(0x02A4, 0x003C, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO05_CCM_PMIC_READY = IOMUX_PAD(0x02A4, 0x003C, 5, 0x04BC, 0, 0),
+ IMX8MM_PAD_GPIO1_IO05_SRC_INT_BOOT = IOMUX_PAD(0x02A4, 0x003C, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO06_GPIO1_IO6 = IOMUX_PAD(0x02A8, 0x0040, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO06_ENET1_MDC = IOMUX_PAD(0x02A8, 0x0040, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO06_USDHC1_CD_B = IOMUX_PAD(0x02A8, 0x0040, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO06_CCM_EXT_CLK3 = IOMUX_PAD(0x02A8, 0x0040, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO07_GPIO1_IO7 = IOMUX_PAD(0x02AC, 0x0044, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO07_ENET1_MDIO = IOMUX_PAD(0x02AC, 0x0044, 1, 0x04C0, 0, 0),
+ IMX8MM_PAD_GPIO1_IO07_USDHC1_WP = IOMUX_PAD(0x02AC, 0x0044, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO07_CCM_EXT_CLK4 = IOMUX_PAD(0x02AC, 0x0044, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO08_GPIO1_IO8 = IOMUX_PAD(0x02B0, 0x0048, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO08_ENET1_1588_EVENT0_IN = IOMUX_PAD(0x02B0, 0x0048, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO08_USDHC2_RESET_B = IOMUX_PAD(0x02B0, 0x0048, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO08_CCM_WAIT = IOMUX_PAD(0x02B0, 0x0048, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO09_GPIO1_IO9 = IOMUX_PAD(0x02B4, 0x004C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO09_ENET1_1588_EVENT0_OUT = IOMUX_PAD(0x02B4, 0x004C, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO09_USDHC3_RESET_B = IOMUX_PAD(0x02B4, 0x004C, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO09_SDMA2_EXT_EVENT0 = IOMUX_PAD(0x02B4, 0x004C, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO09_CCM_STOP = IOMUX_PAD(0x02B4, 0x004C, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO10_GPIO1_IO10 = IOMUX_PAD(0x02B8, 0x0050, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO10_USB1_OTG_ID = IOMUX_PAD(0x02B8, 0x0050, 1, 0x0000, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO11_GPIO1_IO11 = IOMUX_PAD(0x02BC, 0x0054, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO11_USB2_OTG_ID = IOMUX_PAD(0x02BC, 0x0054, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO11_USDHC3_VSELECT = IOMUX_PAD(0x02BC, 0x0054, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO11_CCM_PMIC_READY = IOMUX_PAD(0x02BC, 0x0054, 5, 0x04BC, 1, 0),
+ IMX8MM_PAD_GPIO1_IO11_CCM_OUT0 = IOMUX_PAD(0x02BC, 0x0054, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO12_GPIO1_IO12 = IOMUX_PAD(0x02C0, 0x0058, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO12_USB1_OTG_PWR = IOMUX_PAD(0x02C0, 0x0058, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO12_SDMA2_EXT_EVENT1 = IOMUX_PAD(0x02C0, 0x0058, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO12_CCM_OUT1 = IOMUX_PAD(0x02C0, 0x0058, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO13_GPIO1_IO13 = IOMUX_PAD(0x02C4, 0x005C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO13_USB1_OTG_OC = IOMUX_PAD(0x02C4, 0x005C, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO13_PWM2_OUT = IOMUX_PAD(0x02C4, 0x005C, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO13_CCM_OUT2 = IOMUX_PAD(0x02C4, 0x005C, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO14_GPIO1_IO14 = IOMUX_PAD(0x02C8, 0x0060, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO14_USB2_OTG_PWR = IOMUX_PAD(0x02C8, 0x0060, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO14_USDHC3_CD_B = IOMUX_PAD(0x02C8, 0x0060, 4, 0x0544, 2, 0),
+ IMX8MM_PAD_GPIO1_IO14_PWM3_OUT = IOMUX_PAD(0x02C8, 0x0060, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO14_CCM_CLKO1 = IOMUX_PAD(0x02C8, 0x0060, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO15_GPIO1_IO15 = IOMUX_PAD(0x02CC, 0x0064, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO15_USB2_OTG_OC = IOMUX_PAD(0x02CC, 0x0064, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO15_USDHC3_WP = IOMUX_PAD(0x02CC, 0x0064, 4, 0x0548, 2, 0),
+ IMX8MM_PAD_GPIO1_IO15_PWM4_OUT = IOMUX_PAD(0x02CC, 0x0064, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO15_CCM_CLKO2 = IOMUX_PAD(0x02CC, 0x0064, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ENET_MDC_ENET1_MDC = IOMUX_PAD(0x02D0, 0x0068, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ENET_MDC_GPIO1_IO16 = IOMUX_PAD(0x02D0, 0x0068, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ENET_MDIO_ENET1_MDIO = IOMUX_PAD(0x02D4, 0x006C, 0, 0x04C0, 1, 0),
+ IMX8MM_PAD_ENET_MDIO_GPIO1_IO17 = IOMUX_PAD(0x02D4, 0x006C, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ENET_TD3_ENET1_RGMII_TD3 = IOMUX_PAD(0x02D8, 0x0070, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ENET_TD3_GPIO1_IO18 = IOMUX_PAD(0x02D8, 0x0070, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ENET_TD2_ENET1_RGMII_TD2 = IOMUX_PAD(0x02DC, 0x0074, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ENET_TD2_ENET1_TX_CLK = IOMUX_PAD(0x02DC, 0x0074, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_ENET_TD2_CCM_ENET_REF_CLK_ROOT = IOMUX_PAD(0x02DC, 0x0074, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_ENET_TD2_GPIO1_IO19 = IOMUX_PAD(0x02DC, 0x0074, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ENET_TD1_ENET1_RGMII_TD1 = IOMUX_PAD(0x02E0, 0x0078, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ENET_TD1_GPIO1_IO20 = IOMUX_PAD(0x02E0, 0x0078, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ENET_TD0_ENET1_RGMII_TD0 = IOMUX_PAD(0x02E4, 0x007C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ENET_TD0_GPIO1_IO21 = IOMUX_PAD(0x02E4, 0x007C, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ENET_TX_CTL_ENET1_RGMII_TX_CTL = IOMUX_PAD(0x02E8, 0x0080, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ENET_TX_CTL_GPIO1_IO22 = IOMUX_PAD(0x02E8, 0x0080, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ENET_TXC_ENET1_RGMII_TXC = IOMUX_PAD(0x02EC, 0x0084, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ENET_TXC_ENET1_TX_ER = IOMUX_PAD(0x02EC, 0x0084, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_ENET_TXC_GPIO1_IO23 = IOMUX_PAD(0x02EC, 0x0084, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ENET_RX_CTL_ENET1_RGMII_RX_CTL = IOMUX_PAD(0x02F0, 0x0088, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ENET_RX_CTL_GPIO1_IO24 = IOMUX_PAD(0x02F0, 0x0088, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ENET_RXC_ENET1_RGMII_RXC = IOMUX_PAD(0x02F4, 0x008C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ENET_RXC_ENET1_RX_ER = IOMUX_PAD(0x02F4, 0x008C, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_ENET_RXC_GPIO1_IO25 = IOMUX_PAD(0x02F4, 0x008C, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ENET_RD0_ENET1_RGMII_RD0 = IOMUX_PAD(0x02F8, 0x0090, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ENET_RD0_GPIO1_IO26 = IOMUX_PAD(0x02F8, 0x0090, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ENET_RD1_ENET1_RGMII_RD1 = IOMUX_PAD(0x02FC, 0x0094, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ENET_RD1_GPIO1_IO27 = IOMUX_PAD(0x02FC, 0x0094, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ENET_RD2_ENET1_RGMII_RD2 = IOMUX_PAD(0x0300, 0x0098, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ENET_RD2_GPIO1_IO28 = IOMUX_PAD(0x0300, 0x0098, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ENET_RD3_ENET1_RGMII_RD3 = IOMUX_PAD(0x0304, 0x009C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ENET_RD3_GPIO1_IO29 = IOMUX_PAD(0x0304, 0x009C, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD1_CLK_USDHC1_CLK = IOMUX_PAD(0x0308, 0x00A0, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD1_CLK_GPIO2_IO0 = IOMUX_PAD(0x0308, 0x00A0, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD1_CMD_USDHC1_CMD = IOMUX_PAD(0x030C, 0x00A4, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD1_CMD_GPIO2_IO1 = IOMUX_PAD(0x030C, 0x00A4, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD1_DATA0_USDHC1_DATA0 = IOMUX_PAD(0x0310, 0x00A8, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD1_DATA0_GPIO2_IO2 = IOMUX_PAD(0x0310, 0x00A8, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD1_DATA1_USDHC1_DATA1 = IOMUX_PAD(0x0314, 0x00AC, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD1_DATA1_GPIO2_IO3 = IOMUX_PAD(0x0314, 0x00AC, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD1_DATA2_USDHC1_DATA2 = IOMUX_PAD(0x0318, 0x00B0, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD1_DATA2_GPIO2_IO4 = IOMUX_PAD(0x0318, 0x00B0, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD1_DATA3_USDHC1_DATA3 = IOMUX_PAD(0x031C, 0x00B4, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD1_DATA3_GPIO2_IO5 = IOMUX_PAD(0x031C, 0x00B4, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD1_DATA4_USDHC1_DATA4 = IOMUX_PAD(0x0320, 0x00B8, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD1_DATA4_GPIO2_IO6 = IOMUX_PAD(0x0320, 0x00B8, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD1_DATA5_USDHC1_DATA5 = IOMUX_PAD(0x0324, 0x00BC, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD1_DATA5_GPIO2_IO7 = IOMUX_PAD(0x0324, 0x00BC, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD1_DATA6_USDHC1_DATA6 = IOMUX_PAD(0x0328, 0x00C0, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD1_DATA6_GPIO2_IO8 = IOMUX_PAD(0x0328, 0x00C0, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD1_DATA7_USDHC1_DATA7 = IOMUX_PAD(0x032C, 0x00C4, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD1_DATA7_GPIO2_IO9 = IOMUX_PAD(0x032C, 0x00C4, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD1_RESET_B_USDHC1_RESET_B = IOMUX_PAD(0x0330, 0x00C8, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD1_RESET_B_GPIO2_IO10 = IOMUX_PAD(0x0330, 0x00C8, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD1_STROBE_USDHC1_STROBE = IOMUX_PAD(0x0334, 0x00CC, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD1_STROBE_GPIO2_IO11 = IOMUX_PAD(0x0334, 0x00CC, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD2_CD_B_USDHC2_CD_B = IOMUX_PAD(0x0338, 0x00D0, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD2_CD_B_GPIO2_IO12 = IOMUX_PAD(0x0338, 0x00D0, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD2_CLK_USDHC2_CLK = IOMUX_PAD(0x033C, 0x00D4, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD2_CLK_GPIO2_IO13 = IOMUX_PAD(0x033C, 0x00D4, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SD2_CLK_CCM_OBSERVE0 = IOMUX_PAD(0x033C, 0x00D4, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD2_CMD_USDHC2_CMD = IOMUX_PAD(0x0340, 0x00D8, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD2_CMD_GPIO2_IO14 = IOMUX_PAD(0x0340, 0x00D8, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SD2_CMD_CCM_OBSERVE1 = IOMUX_PAD(0x0340, 0x00D8, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD2_DATA0_USDHC2_DATA0 = IOMUX_PAD(0x0344, 0x00DC, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD2_DATA0_GPIO2_IO15 = IOMUX_PAD(0x0344, 0x00DC, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SD2_DATA0_CCM_OBSERVE2 = IOMUX_PAD(0x0344, 0x00DC, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD2_DATA1_USDHC2_DATA1 = IOMUX_PAD(0x0348, 0x00E0, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD2_DATA1_GPIO2_IO16 = IOMUX_PAD(0x0348, 0x00E0, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SD2_DATA1_CCM_WAIT = IOMUX_PAD(0x0348, 0x00E0, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD2_DATA2_USDHC2_DATA2 = IOMUX_PAD(0x034C, 0x00E4, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD2_DATA2_GPIO2_IO17 = IOMUX_PAD(0x034C, 0x00E4, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SD2_DATA2_CCM_STOP = IOMUX_PAD(0x034C, 0x00E4, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 = IOMUX_PAD(0x0350, 0x00E8, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD2_DATA3_GPIO2_IO18 = IOMUX_PAD(0x0350, 0x00E8, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SD2_DATA3_SRC_EARLY_RESET = IOMUX_PAD(0x0350, 0x00E8, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD2_RESET_B_USDHC2_RESET_B = IOMUX_PAD(0x0354, 0x00EC, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD2_RESET_B_GPIO2_IO19 = IOMUX_PAD(0x0354, 0x00EC, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SD2_RESET_B_SRC_SYSTEM_RESET = IOMUX_PAD(0x0354, 0x00EC, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD2_WP_USDHC2_WP = IOMUX_PAD(0x0358, 0x00F0, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD2_WP_GPIO2_IO20 = IOMUX_PAD(0x0358, 0x00F0, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_ALE_RAWNAND_ALE = IOMUX_PAD(0x035C, 0x00F4, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_ALE_QSPI_A_SCLK = IOMUX_PAD(0x035C, 0x00F4, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_ALE_GPIO3_IO0 = IOMUX_PAD(0x035C, 0x00F4, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_CE0_B_RAWNAND_CE0_B = IOMUX_PAD(0x0360, 0x00F8, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_CE0_B_QSPI_A_SS0_B = IOMUX_PAD(0x0360, 0x00F8, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_CE0_B_GPIO3_IO1 = IOMUX_PAD(0x0360, 0x00F8, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_CE1_B_RAWNAND_CE1_B = IOMUX_PAD(0x0364, 0x00FC, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_CE1_B_QSPI_A_SS1_B = IOMUX_PAD(0x0364, 0x00FC, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_CE1_B_USDHC3_STROBE = IOMUX_PAD(0x0364, 0x00FC, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_CE1_B_GPIO3_IO2 = IOMUX_PAD(0x0364, 0x00FC, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_CE2_B_RAWNAND_CE2_B = IOMUX_PAD(0x0368, 0x0100, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_CE2_B_QSPI_B_SS0_B = IOMUX_PAD(0x0368, 0x0100, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_CE2_B_USDHC3_DATA5 = IOMUX_PAD(0x0368, 0x0100, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_CE2_B_GPIO3_IO3 = IOMUX_PAD(0x0368, 0x0100, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_CE3_B_RAWNAND_CE3_B = IOMUX_PAD(0x036C, 0x0104, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_CE3_B_QSPI_B_SS1_B = IOMUX_PAD(0x036C, 0x0104, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_CE3_B_USDHC3_DATA6 = IOMUX_PAD(0x036C, 0x0104, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_CE3_B_GPIO3_IO4 = IOMUX_PAD(0x036C, 0x0104, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_CLE_RAWNAND_CLE = IOMUX_PAD(0x0370, 0x0108, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_CLE_QSPI_B_SCLK = IOMUX_PAD(0x0370, 0x0108, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_CLE_USDHC3_DATA7 = IOMUX_PAD(0x0370, 0x0108, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_CLE_GPIO3_IO5 = IOMUX_PAD(0x0370, 0x0108, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_DATA00_RAWNAND_DATA00 = IOMUX_PAD(0x0374, 0x010C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA00_QSPI_A_DATA0 = IOMUX_PAD(0x0374, 0x010C, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA00_GPIO3_IO6 = IOMUX_PAD(0x0374, 0x010C, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_DATA01_RAWNAND_DATA01 = IOMUX_PAD(0x0378, 0x0110, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA01_QSPI_A_DATA1 = IOMUX_PAD(0x0378, 0x0110, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA01_GPIO3_IO7 = IOMUX_PAD(0x0378, 0x0110, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_DATA02_RAWNAND_DATA02 = IOMUX_PAD(0x037C, 0x0114, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA02_QSPI_A_DATA2 = IOMUX_PAD(0x037C, 0x0114, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA02_USDHC3_CD_B = IOMUX_PAD(0x037C, 0x0114, 2, 0x0544, 0, 0),
+ IMX8MM_PAD_NAND_DATA02_GPIO3_IO8 = IOMUX_PAD(0x037C, 0x0114, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_DATA03_RAWNAND_DATA03 = IOMUX_PAD(0x0380, 0x0118, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA03_QSPI_A_DATA3 = IOMUX_PAD(0x0380, 0x0118, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA03_USDHC3_WP = IOMUX_PAD(0x0380, 0x0118, 2, 0x0548, 0, 0),
+ IMX8MM_PAD_NAND_DATA03_GPIO3_IO9 = IOMUX_PAD(0x0380, 0x0118, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_DATA04_RAWNAND_DATA04 = IOMUX_PAD(0x0384, 0x011C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA04_QSPI_B_DATA0 = IOMUX_PAD(0x0384, 0x011C, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA04_USDHC3_DATA0 = IOMUX_PAD(0x0384, 0x011C, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA04_GPIO3_IO10 = IOMUX_PAD(0x0384, 0x011C, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_DATA05_RAWNAND_DATA05 = IOMUX_PAD(0x0388, 0x0120, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA05_QSPI_B_DATA1 = IOMUX_PAD(0x0388, 0x0120, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA05_USDHC3_DATA1 = IOMUX_PAD(0x0388, 0x0120, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA05_GPIO3_IO11 = IOMUX_PAD(0x0388, 0x0120, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_DATA06_RAWNAND_DATA06 = IOMUX_PAD(0x038C, 0x0124, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA06_QSPI_B_DATA2 = IOMUX_PAD(0x038C, 0x0124, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA06_USDHC3_DATA2 = IOMUX_PAD(0x038C, 0x0124, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA06_GPIO3_IO12 = IOMUX_PAD(0x038C, 0x0124, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_DATA07_RAWNAND_DATA07 = IOMUX_PAD(0x0390, 0x0128, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA07_QSPI_B_DATA3 = IOMUX_PAD(0x0390, 0x0128, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA07_USDHC3_DATA3 = IOMUX_PAD(0x0390, 0x0128, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA07_GPIO3_IO13 = IOMUX_PAD(0x0390, 0x0128, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_DQS_RAWNAND_DQS = IOMUX_PAD(0x0394, 0x012C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DQS_QSPI_A_DQS = IOMUX_PAD(0x0394, 0x012C, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DQS_GPIO3_IO14 = IOMUX_PAD(0x0394, 0x012C, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_RE_B_RAWNAND_RE_B = IOMUX_PAD(0x0398, 0x0130, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_RE_B_QSPI_B_DQS = IOMUX_PAD(0x0398, 0x0130, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_RE_B_USDHC3_DATA4 = IOMUX_PAD(0x0398, 0x0130, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_RE_B_GPIO3_IO15 = IOMUX_PAD(0x0398, 0x0130, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_READY_B_RAWNAND_READY_B = IOMUX_PAD(0x039C, 0x0134, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_READY_B_USDHC3_RESET_B = IOMUX_PAD(0x039C, 0x0134, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_READY_B_GPIO3_IO16 = IOMUX_PAD(0x039C, 0x0134, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_WE_B_RAWNAND_WE_B = IOMUX_PAD(0x03A0, 0x0138, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_WE_B_USDHC3_CLK = IOMUX_PAD(0x03A0, 0x0138, 2 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_WE_B_GPIO3_IO17 = IOMUX_PAD(0x03A0, 0x0138, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_WP_B_RAWNAND_WP_B = IOMUX_PAD(0x03A4, 0x013C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_WP_B_USDHC3_CMD = IOMUX_PAD(0x03A4, 0x013C, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_WP_B_GPIO3_IO18 = IOMUX_PAD(0x03A4, 0x013C, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI5_RXFS_SAI5_RX_SYNC = IOMUX_PAD(0x03A8, 0x0140, 0, 0x04E4, 0, 0),
+ IMX8MM_PAD_SAI5_RXFS_SAI1_TX_DATA0 = IOMUX_PAD(0x03A8, 0x0140, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI5_RXFS_GPIO3_IO19 = IOMUX_PAD(0x03A8, 0x0140, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI5_RXC_SAI5_RX_BCLK = IOMUX_PAD(0x03AC, 0x0144, 0, 0x04D0, 0, 0),
+ IMX8MM_PAD_SAI5_RXC_SAI1_TX_DATA1 = IOMUX_PAD(0x03AC, 0x0144, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI5_RXC_PDM_CLK = IOMUX_PAD(0x03AC, 0x0144, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI5_RXC_GPIO3_IO20 = IOMUX_PAD(0x03AC, 0x0144, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI5_RXD0_SAI5_RX_DATA0 = IOMUX_PAD(0x03B0, 0x0148, 0, 0x04D4, 0, 0),
+ IMX8MM_PAD_SAI5_RXD0_SAI1_TX_DATA2 = IOMUX_PAD(0x03B0, 0x0148, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI5_RXD0_PDM_BIT_STREAM0 = IOMUX_PAD(0x03B0, 0x0148, 4, 0x0534, 0, 0),
+ IMX8MM_PAD_SAI5_RXD0_GPIO3_IO21 = IOMUX_PAD(0x03B0, 0x0148, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI5_RXD1_SAI5_RX_DATA1 = IOMUX_PAD(0x03B4, 0x014C, 0, 0x04D8, 0, 0),
+ IMX8MM_PAD_SAI5_RXD1_SAI1_TX_DATA3 = IOMUX_PAD(0x03B4, 0x014C, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI5_RXD1_SAI1_TX_SYNC = IOMUX_PAD(0x03B4, 0x014C, 2, 0x04CC, 0, 0),
+ IMX8MM_PAD_SAI5_RXD1_SAI5_TX_SYNC = IOMUX_PAD(0x03B4, 0x014C, 3, 0x04EC, 0, 0),
+ IMX8MM_PAD_SAI5_RXD1_PDM_BIT_STREAM1 = IOMUX_PAD(0x03B4, 0x014C, 4, 0x0538, 0, 0),
+ IMX8MM_PAD_SAI5_RXD1_GPIO3_IO22 = IOMUX_PAD(0x03B4, 0x014C, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI5_RXD2_SAI5_RX_DATA2 = IOMUX_PAD(0x03B8, 0x0150, 0, 0x04DC, 0, 0),
+ IMX8MM_PAD_SAI5_RXD2_SAI1_TX_DATA4 = IOMUX_PAD(0x03B8, 0x0150, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI5_RXD2_SAI1_TX_SYNC = IOMUX_PAD(0x03B8, 0x0150, 2, 0x04CC, 1, 0),
+ IMX8MM_PAD_SAI5_RXD2_SAI5_TX_BCLK = IOMUX_PAD(0x03B8, 0x0150, 3, 0x04E8, 0, 0),
+ IMX8MM_PAD_SAI5_RXD2_PDM_BIT_STREAM2 = IOMUX_PAD(0x03B8, 0x0150, 4, 0x053C, 0, 0),
+ IMX8MM_PAD_SAI5_RXD2_GPIO3_IO23 = IOMUX_PAD(0x03B8, 0x0150, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI5_RXD3_SAI5_RX_DATA3 = IOMUX_PAD(0x03BC, 0x0154, 0, 0x04E0, 0, 0),
+ IMX8MM_PAD_SAI5_RXD3_SAI1_TX_DATA5 = IOMUX_PAD(0x03BC, 0x0154, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI5_RXD3_SAI1_TX_SYNC = IOMUX_PAD(0x03BC, 0x0154, 2, 0x04CC, 2, 0),
+ IMX8MM_PAD_SAI5_RXD3_SAI5_TX_DATA0 = IOMUX_PAD(0x03BC, 0x0154, 3, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI5_RXD3_PDM_BIT_STREAM3 = IOMUX_PAD(0x03BC, 0x0154, 4, 0x0540, 0, 0),
+ IMX8MM_PAD_SAI5_RXD3_GPIO3_IO24 = IOMUX_PAD(0x03BC, 0x0154, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI5_MCLK_SAI5_MCLK = IOMUX_PAD(0x03C0, 0x0158, 0, 0x052C, 0, 0),
+ IMX8MM_PAD_SAI5_MCLK_SAI1_TX_BCLK = IOMUX_PAD(0x03C0, 0x0158, 1, 0x04C8, 0, 0),
+ IMX8MM_PAD_SAI5_MCLK_GPIO3_IO25 = IOMUX_PAD(0x03C0, 0x0158, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI5_MCLK_SRC_TESTER_ACK = IOMUX_PAD(0x03C0, 0x0158, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_RXFS_SAI1_RX_SYNC = IOMUX_PAD(0x03C4, 0x015C, 0, 0x04C4, 0, 0),
+ IMX8MM_PAD_SAI1_RXFS_SAI5_RX_SYNC = IOMUX_PAD(0x03C4, 0x015C, 1, 0x04E4, 1, 0),
+ IMX8MM_PAD_SAI1_RXFS_ARM_PLATFORM_TRACE_CLK = IOMUX_PAD(0x03C4, 0x015C, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXFS_GPIO4_IO0 = IOMUX_PAD(0x03C4, 0x015C, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_RXC_SAI1_RX_BCLK = IOMUX_PAD(0x03C8, 0x0160, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXC_SAI5_RX_BCLK = IOMUX_PAD(0x03C8, 0x0160, 1, 0x04D0, 1, 0),
+ IMX8MM_PAD_SAI1_RXC_ARM_PLATFORM_TRACE_CTL = IOMUX_PAD(0x03C8, 0x0160, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXC_GPIO4_IO1 = IOMUX_PAD(0x03C8, 0x0160, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_RXD0_SAI1_RX_DATA0 = IOMUX_PAD(0x03CC, 0x0164, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD0_SAI5_RX_DATA0 = IOMUX_PAD(0x03CC, 0x0164, 1, 0x04D4, 1, 0),
+ IMX8MM_PAD_SAI1_RXD0_SAI1_TX_DATA1 = IOMUX_PAD(0x03CC, 0x0164, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD0_PDM_BIT_STREAM0 = IOMUX_PAD(0x03CC, 0x0164, 3, 0x0534, 1, 0),
+ IMX8MM_PAD_SAI1_RXD0_ARM_PLATFORM_TRACE0 = IOMUX_PAD(0x03CC, 0x0164, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD0_GPIO4_IO2 = IOMUX_PAD(0x03CC, 0x0164, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD0_SRC_BOOT_CFG0 = IOMUX_PAD(0x03CC, 0x0164, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_RXD1_SAI1_RX_DATA1 = IOMUX_PAD(0x03D0, 0x0168, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD1_SAI5_RX_DATA1 = IOMUX_PAD(0x03D0, 0x0168, 1, 0x04D8, 1, 0),
+ IMX8MM_PAD_SAI1_RXD1_PDM_BIT_STREAM1 = IOMUX_PAD(0x03D0, 0x0168, 3, 0x0538, 1, 0),
+ IMX8MM_PAD_SAI1_RXD1_ARM_PLATFORM_TRACE1 = IOMUX_PAD(0x03D0, 0x0168, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD1_GPIO4_IO3 = IOMUX_PAD(0x03D0, 0x0168, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD1_SRC_BOOT_CFG1 = IOMUX_PAD(0x03D0, 0x0168, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_RXD2_SAI1_RX_DATA2 = IOMUX_PAD(0x03D4, 0x016C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD2_SAI5_RX_DATA2 = IOMUX_PAD(0x03D4, 0x016C, 1, 0x04DC, 1, 0),
+ IMX8MM_PAD_SAI1_RXD2_PDM_BIT_STREAM2 = IOMUX_PAD(0x03D4, 0x016C, 3, 0x053C, 1, 0),
+ IMX8MM_PAD_SAI1_RXD2_ARM_PLATFORM_TRACE2 = IOMUX_PAD(0x03D4, 0x016C, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD2_GPIO4_IO4 = IOMUX_PAD(0x03D4, 0x016C, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD2_SRC_BOOT_CFG2 = IOMUX_PAD(0x03D4, 0x016C, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_RXD3_SAI1_RX_DATA3 = IOMUX_PAD(0x03D8, 0x0170, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD3_SAI5_RX_DATA3 = IOMUX_PAD(0x03D8, 0x0170, 1, 0x04E0, 1, 0),
+ IMX8MM_PAD_SAI1_RXD3_PDM_BIT_STREAM3 = IOMUX_PAD(0x03D8, 0x0170, 3, 0x0540, 1, 0),
+ IMX8MM_PAD_SAI1_RXD3_ARM_PLATFORM_TRACE3 = IOMUX_PAD(0x03D8, 0x0170, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD3_GPIO4_IO5 = IOMUX_PAD(0x03D8, 0x0170, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD3_SRC_BOOT_CFG3 = IOMUX_PAD(0x03D8, 0x0170, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_RXD4_SAI1_RX_DATA4 = IOMUX_PAD(0x03DC, 0x0174, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD4_SAI6_TX_BCLK = IOMUX_PAD(0x03DC, 0x0174, 1, 0x051C, 0, 0),
+ IMX8MM_PAD_SAI1_RXD4_SAI6_RX_BCLK = IOMUX_PAD(0x03DC, 0x0174, 2, 0x0510, 0, 0),
+ IMX8MM_PAD_SAI1_RXD4_ARM_PLATFORM_TRACE4 = IOMUX_PAD(0x03DC, 0x0174, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD4_GPIO4_IO6 = IOMUX_PAD(0x03DC, 0x0174, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD4_SRC_BOOT_CFG4 = IOMUX_PAD(0x03DC, 0x0174, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_RXD5_SAI1_RX_DATA5 = IOMUX_PAD(0x03E0, 0x0178, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD5_SAI6_TX_DATA0 = IOMUX_PAD(0x03E0, 0x0178, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD5_SAI6_RX_DATA0 = IOMUX_PAD(0x03E0, 0x0178, 2, 0x0514, 0, 0),
+ IMX8MM_PAD_SAI1_RXD5_SAI1_RX_SYNC = IOMUX_PAD(0x03E0, 0x0178, 3, 0x04C4, 1, 0),
+ IMX8MM_PAD_SAI1_RXD5_ARM_PLATFORM_TRACE5 = IOMUX_PAD(0x03E0, 0x0178, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD5_GPIO4_IO7 = IOMUX_PAD(0x03E0, 0x0178, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD5_SRC_BOOT_CFG5 = IOMUX_PAD(0x03E0, 0x0178, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_RXD6_SAI1_RX_DATA6 = IOMUX_PAD(0x03E4, 0x017C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD6_SAI6_TX_SYNC = IOMUX_PAD(0x03E4, 0x017C, 1, 0x0520, 0, 0),
+ IMX8MM_PAD_SAI1_RXD6_SAI6_RX_SYNC = IOMUX_PAD(0x03E4, 0x017C, 2, 0x0518, 0, 0),
+ IMX8MM_PAD_SAI1_RXD6_ARM_PLATFORM_TRACE6 = IOMUX_PAD(0x03E4, 0x017C, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD6_GPIO4_IO8 = IOMUX_PAD(0x03E4, 0x017C, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD6_SRC_BOOT_CFG6 = IOMUX_PAD(0x03E4, 0x017C, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_RXD7_SAI1_RX_DATA7 = IOMUX_PAD(0x03E8, 0x0180, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD7_SAI6_MCLK = IOMUX_PAD(0x03E8, 0x0180, 1, 0x0530, 0, 0),
+ IMX8MM_PAD_SAI1_RXD7_SAI1_TX_SYNC = IOMUX_PAD(0x03E8, 0x0180, 2, 0x04CC, 4, 0),
+ IMX8MM_PAD_SAI1_RXD7_SAI1_TX_DATA4 = IOMUX_PAD(0x03E8, 0x0180, 3, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD7_ARM_PLATFORM_TRACE7 = IOMUX_PAD(0x03E8, 0x0180, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD7_GPIO4_IO9 = IOMUX_PAD(0x03E8, 0x0180, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD7_SRC_BOOT_CFG7 = IOMUX_PAD(0x03E8, 0x0180, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_TXFS_SAI1_TX_SYNC = IOMUX_PAD(0x03EC, 0x0184, 0, 0x04CC, 3, 0),
+ IMX8MM_PAD_SAI1_TXFS_SAI5_TX_SYNC = IOMUX_PAD(0x03EC, 0x0184, 1, 0x04EC, 1, 0),
+ IMX8MM_PAD_SAI1_TXFS_ARM_PLATFORM_EVENTO = IOMUX_PAD(0x03EC, 0x0184, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXFS_GPIO4_IO10 = IOMUX_PAD(0x03EC, 0x0184, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_TXC_SAI1_TX_BCLK = IOMUX_PAD(0x03F0, 0x0188, 0, 0x04C8, 1, 0),
+ IMX8MM_PAD_SAI1_TXC_SAI5_TX_BCLK = IOMUX_PAD(0x03F0, 0x0188, 1, 0x04E8, 1, 0),
+ IMX8MM_PAD_SAI1_TXC_ARM_PLATFORM_EVENTI = IOMUX_PAD(0x03F0, 0x0188, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXC_GPIO4_IO11 = IOMUX_PAD(0x03F0, 0x0188, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_TXD0_SAI1_TX_DATA0 = IOMUX_PAD(0x03F4, 0x018C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD0_SAI5_TX_DATA0 = IOMUX_PAD(0x03F4, 0x018C, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD0_ARM_PLATFORM_TRACE8 = IOMUX_PAD(0x03F4, 0x018C, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD0_GPIO4_IO12 = IOMUX_PAD(0x03F4, 0x018C, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD0_SRC_BOOT_CFG8 = IOMUX_PAD(0x03F4, 0x018C, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_TXD1_SAI1_TX_DATA1 = IOMUX_PAD(0x03F8, 0x0190, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD1_SAI5_TX_DATA1 = IOMUX_PAD(0x03F8, 0x0190, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD1_ARM_PLATFORM_TRACE9 = IOMUX_PAD(0x03F8, 0x0190, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD1_GPIO4_IO13 = IOMUX_PAD(0x03F8, 0x0190, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD1_SRC_BOOT_CFG9 = IOMUX_PAD(0x03F8, 0x0190, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_TXD2_SAI1_TX_DATA2 = IOMUX_PAD(0x03FC, 0x0194, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD2_SAI5_TX_DATA2 = IOMUX_PAD(0x03FC, 0x0194, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD2_ARM_PLATFORM_TRACE10 = IOMUX_PAD(0x03FC, 0x0194, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD2_GPIO4_IO14 = IOMUX_PAD(0x03FC, 0x0194, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD2_SRC_BOOT_CFG10 = IOMUX_PAD(0x03FC, 0x0194, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_TXD3_SAI1_TX_DATA3 = IOMUX_PAD(0x0400, 0x0198, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD3_SAI5_TX_DATA3 = IOMUX_PAD(0x0400, 0x0198, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD3_ARM_PLATFORM_TRACE11 = IOMUX_PAD(0x0400, 0x0198, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD3_GPIO4_IO15 = IOMUX_PAD(0x0400, 0x0198, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD3_SRC_BOOT_CFG11 = IOMUX_PAD(0x0400, 0x0198, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_TXD4_SAI1_TX_DATA4 = IOMUX_PAD(0x0404, 0x019C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD4_SAI6_RX_BCLK = IOMUX_PAD(0x0404, 0x019C, 1, 0x0510, 1, 0),
+ IMX8MM_PAD_SAI1_TXD4_SAI6_TX_BCLK = IOMUX_PAD(0x0404, 0x019C, 2, 0x051C, 1, 0),
+ IMX8MM_PAD_SAI1_TXD4_ARM_PLATFORM_TRACE12 = IOMUX_PAD(0x0404, 0x019C, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD4_GPIO4_IO16 = IOMUX_PAD(0x0404, 0x019C, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD4_SRC_BOOT_CFG12 = IOMUX_PAD(0x0404, 0x019C, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_TXD5_SAI1_TX_DATA5 = IOMUX_PAD(0x0408, 0x01A0, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD5_SAI6_RX_DATA0 = IOMUX_PAD(0x0408, 0x01A0, 1, 0x0514, 1, 0),
+ IMX8MM_PAD_SAI1_TXD5_SAI6_TX_DATA0 = IOMUX_PAD(0x0408, 0x01A0, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD5_ARM_PLATFORM_TRACE13 = IOMUX_PAD(0x0408, 0x01A0, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD5_GPIO4_IO17 = IOMUX_PAD(0x0408, 0x01A0, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD5_SRC_BOOT_CFG13 = IOMUX_PAD(0x0408, 0x01A0, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_TXD6_SAI1_TX_DATA6 = IOMUX_PAD(0x040C, 0x01A4, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD6_SAI6_RX_SYNC = IOMUX_PAD(0x040C, 0x01A4, 1, 0x0518, 1, 0),
+ IMX8MM_PAD_SAI1_TXD6_SAI6_TX_SYNC = IOMUX_PAD(0x040C, 0x01A4, 2, 0x0520, 1, 0),
+ IMX8MM_PAD_SAI1_TXD6_ARM_PLATFORM_TRACE14 = IOMUX_PAD(0x040C, 0x01A4, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD6_GPIO4_IO18 = IOMUX_PAD(0x040C, 0x01A4, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD6_SRC_BOOT_CFG14 = IOMUX_PAD(0x040C, 0x01A4, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_TXD7_SAI1_TX_DATA7 = IOMUX_PAD(0x0410, 0x01A8, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD7_SAI6_MCLK = IOMUX_PAD(0x0410, 0x01A8, 1, 0x0530, 1, 0),
+ IMX8MM_PAD_SAI1_TXD7_PDM_CLK = IOMUX_PAD(0x0410, 0x01A8, 3, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD7_ARM_PLATFORM_TRACE15 = IOMUX_PAD(0x0410, 0x01A8, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD7_GPIO4_IO19 = IOMUX_PAD(0x0410, 0x01A8, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD7_SRC_BOOT_CFG15 = IOMUX_PAD(0x0410, 0x01A8, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_MCLK_SAI1_MCLK = IOMUX_PAD(0x0414, 0x01AC, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_MCLK_SAI5_MCLK = IOMUX_PAD(0x0414, 0x01AC, 1, 0x052C, 1, 0),
+ IMX8MM_PAD_SAI1_MCLK_SAI1_TX_BCLK = IOMUX_PAD(0x0414, 0x01AC, 2, 0x04C8, 2, 0),
+ IMX8MM_PAD_SAI1_MCLK_PDM_CLK = IOMUX_PAD(0x0414, 0x01AC, 3, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_MCLK_GPIO4_IO20 = IOMUX_PAD(0x0414, 0x01AC, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI2_RXFS_SAI2_RX_SYNC = IOMUX_PAD(0x0418, 0x01B0, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_RXFS_SAI5_TX_SYNC = IOMUX_PAD(0x0418, 0x01B0, 1, 0x04EC, 2, 0),
+ IMX8MM_PAD_SAI2_RXFS_SAI5_TX_DATA1 = IOMUX_PAD(0x0418, 0x01B0, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_RXFS_SAI2_RX_DATA1 = IOMUX_PAD(0x0418, 0x01B0, 3, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_RXFS_UART1_TX = IOMUX_PAD(0x0418, 0x01B0, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_RXFS_UART1_RX = IOMUX_PAD(0x0418, 0x01B0, 4, 0x04F4, 2, 0),
+ IMX8MM_PAD_SAI2_RXFS_GPIO4_IO21 = IOMUX_PAD(0x0418, 0x01B0, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI2_RXC_SAI2_RX_BCLK = IOMUX_PAD(0x041C, 0x01B4, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_RXC_SAI5_TX_BCLK = IOMUX_PAD(0x041C, 0x01B4, 1, 0x04E8, 2, 0),
+ IMX8MM_PAD_SAI2_RXC_UART1_RX = IOMUX_PAD(0x041C, 0x01B4, 4, 0x04F4, 3, 0),
+ IMX8MM_PAD_SAI2_RXC_UART1_TX = IOMUX_PAD(0x041C, 0x01B4, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_RXC_GPIO4_IO22 = IOMUX_PAD(0x041C, 0x01B4, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI2_RXD0_SAI2_RX_DATA0 = IOMUX_PAD(0x0420, 0x01B8, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_RXD0_SAI5_TX_DATA0 = IOMUX_PAD(0x0420, 0x01B8, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_RXD0_UART1_RTS_B = IOMUX_PAD(0x0420, 0x01B8, 4, 0x04F0, 2, 0),
+ IMX8MM_PAD_SAI2_RXD0_UART1_CTS_B = IOMUX_PAD(0x0420, 0x01B8, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_RXD0_GPIO4_IO23 = IOMUX_PAD(0x0420, 0x01B8, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI2_TXFS_SAI2_TX_SYNC = IOMUX_PAD(0x0424, 0x01BC, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_TXFS_SAI5_TX_DATA1 = IOMUX_PAD(0x0424, 0x01BC, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_TXFS_SAI2_TX_DATA1 = IOMUX_PAD(0x0424, 0x01BC, 3, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_TXFS_UART1_CTS_B = IOMUX_PAD(0x0424, 0x01BC, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_TXFS_UART1_RTS_B = IOMUX_PAD(0x0424, 0x01BC, 4, 0x04F0, 3, 0),
+ IMX8MM_PAD_SAI2_TXFS_GPIO4_IO24 = IOMUX_PAD(0x0424, 0x01BC, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI2_TXC_SAI2_TX_BCLK = IOMUX_PAD(0x0428, 0x01C0, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_TXC_SAI5_TX_DATA2 = IOMUX_PAD(0x0428, 0x01C0, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_TXC_GPIO4_IO25 = IOMUX_PAD(0x0428, 0x01C0, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI2_TXD0_SAI2_TX_DATA0 = IOMUX_PAD(0x042C, 0x01C4, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_TXD0_SAI5_TX_DATA3 = IOMUX_PAD(0x042C, 0x01C4, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_TXD0_GPIO4_IO26 = IOMUX_PAD(0x042C, 0x01C4, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI2_MCLK_SAI2_MCLK = IOMUX_PAD(0x0430, 0x01C8, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_MCLK_SAI5_MCLK = IOMUX_PAD(0x0430, 0x01C8, 1, 0x052C, 2, 0),
+ IMX8MM_PAD_SAI2_MCLK_GPIO4_IO27 = IOMUX_PAD(0x0430, 0x01C8, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI3_RXFS_SAI3_RX_SYNC = IOMUX_PAD(0x0434, 0x01CC, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_RXFS_GPT1_CAPTURE1 = IOMUX_PAD(0x0434, 0x01CC, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_RXFS_SAI5_RX_SYNC = IOMUX_PAD(0x0434, 0x01CC, 2, 0x04E4, 2, 0),
+ IMX8MM_PAD_SAI3_RXFS_SAI3_RX_DATA1 = IOMUX_PAD(0x0434, 0x01CC, 3, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_RXFS_GPIO4_IO28 = IOMUX_PAD(0x0434, 0x01CC, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI3_RXC_SAI3_RX_BCLK = IOMUX_PAD(0x0438, 0x01D0, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_RXC_GPT1_CLK = IOMUX_PAD(0x0438, 0x01D0, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_RXC_SAI5_RX_BCLK = IOMUX_PAD(0x0438, 0x01D0, 2, 0x04D0, 2, 0),
+ IMX8MM_PAD_SAI3_RXC_UART2_CTS_B = IOMUX_PAD(0x0438, 0x01D0, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_RXC_UART2_RTS_B = IOMUX_PAD(0x0438, 0x01D0, 4, 0x04F8, 2, 0),
+ IMX8MM_PAD_SAI3_RXC_GPIO4_IO29 = IOMUX_PAD(0x0438, 0x01D0, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI3_RXD_SAI3_RX_DATA0 = IOMUX_PAD(0x043C, 0x01D4, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_RXD_GPT1_COMPARE1 = IOMUX_PAD(0x043C, 0x01D4, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_RXD_SAI5_RX_DATA0 = IOMUX_PAD(0x043C, 0x01D4, 2, 0x04D4, 2, 0),
+ IMX8MM_PAD_SAI3_RXD_UART2_RTS_B = IOMUX_PAD(0x043C, 0x01D4, 4, 0x04F8, 3, 0),
+ IMX8MM_PAD_SAI3_RXD_UART2_CTS_B = IOMUX_PAD(0x043C, 0x01D4, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_RXD_GPIO4_IO30 = IOMUX_PAD(0x043C, 0x01D4, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI3_TXFS_SAI3_TX_SYNC = IOMUX_PAD(0x0440, 0x01D8, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_TXFS_GPT1_CAPTURE2 = IOMUX_PAD(0x0440, 0x01D8, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_TXFS_SAI5_RX_DATA1 = IOMUX_PAD(0x0440, 0x01D8, 2, 0x04D8, 2, 0),
+ IMX8MM_PAD_SAI3_TXFS_SAI3_TX_DATA1 = IOMUX_PAD(0x0440, 0x01D8, 3, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_TXFS_UART2_RX = IOMUX_PAD(0x0440, 0x01D8, 4, 0x04FC, 2, 0),
+ IMX8MM_PAD_SAI3_TXFS_UART2_TX = IOMUX_PAD(0x0440, 0x01D8, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_TXFS_GPIO4_IO31 = IOMUX_PAD(0x0440, 0x01D8, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI3_TXC_SAI3_TX_BCLK = IOMUX_PAD(0x0444, 0x01DC, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_TXC_GPT1_COMPARE2 = IOMUX_PAD(0x0444, 0x01DC, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_TXC_SAI5_RX_DATA2 = IOMUX_PAD(0x0444, 0x01DC, 2, 0x04DC, 2, 0),
+ IMX8MM_PAD_SAI3_TXC_UART2_TX = IOMUX_PAD(0x0444, 0x01DC, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_TXC_UART2_RX = IOMUX_PAD(0x0444, 0x01DC, 4, 0x04FC, 3, 0),
+ IMX8MM_PAD_SAI3_TXC_GPIO5_IO0 = IOMUX_PAD(0x0444, 0x01DC, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI3_TXD_SAI3_TX_DATA0 = IOMUX_PAD(0x0448, 0x01E0, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_TXD_GPT1_COMPARE3 = IOMUX_PAD(0x0448, 0x01E0, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_TXD_SAI5_RX_DATA3 = IOMUX_PAD(0x0448, 0x01E0, 2, 0x04E0, 2, 0),
+ IMX8MM_PAD_SAI3_TXD_GPIO5_IO1 = IOMUX_PAD(0x0448, 0x01E0, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI3_MCLK_SAI3_MCLK = IOMUX_PAD(0x044C, 0x01E4, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_MCLK_PWM4_OUT = IOMUX_PAD(0x044C, 0x01E4, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_MCLK_SAI5_MCLK = IOMUX_PAD(0x044C, 0x01E4, 2, 0x052C, 3, 0),
+ IMX8MM_PAD_SAI3_MCLK_GPIO5_IO2 = IOMUX_PAD(0x044C, 0x01E4, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SPDIF_TX_SPDIF1_OUT = IOMUX_PAD(0x0450, 0x01E8, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SPDIF_TX_PWM3_OUT = IOMUX_PAD(0x0450, 0x01E8, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SPDIF_TX_GPIO5_IO3 = IOMUX_PAD(0x0450, 0x01E8, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SPDIF_RX_SPDIF1_IN = IOMUX_PAD(0x0454, 0x01EC, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SPDIF_RX_PWM2_OUT = IOMUX_PAD(0x0454, 0x01EC, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SPDIF_RX_GPIO5_IO4 = IOMUX_PAD(0x0454, 0x01EC, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SPDIF_EXT_CLK_SPDIF1_EXT_CLK = IOMUX_PAD(0x0458, 0x01F0, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SPDIF_EXT_CLK_PWM1_OUT = IOMUX_PAD(0x0458, 0x01F0, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SPDIF_EXT_CLK_GPIO5_IO5 = IOMUX_PAD(0x0458, 0x01F0, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ECSPI1_SCLK_ECSPI1_SCLK = IOMUX_PAD(0x045C, 0x01F4, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ECSPI1_SCLK_UART3_RX = IOMUX_PAD(0x045C, 0x01F4, 1, 0x0504, 0, 0),
+ IMX8MM_PAD_ECSPI1_SCLK_UART3_TX = IOMUX_PAD(0x045C, 0x01F4, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_ECSPI1_SCLK_GPIO5_IO6 = IOMUX_PAD(0x045C, 0x01F4, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ECSPI1_MOSI_ECSPI1_MOSI = IOMUX_PAD(0x0460, 0x01F8, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ECSPI1_MOSI_UART3_TX = IOMUX_PAD(0x0460, 0x01F8, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_ECSPI1_MOSI_UART3_RX = IOMUX_PAD(0x0460, 0x01F8, 1, 0x0504, 1, 0),
+ IMX8MM_PAD_ECSPI1_MOSI_GPIO5_IO7 = IOMUX_PAD(0x0460, 0x01F8, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ECSPI1_MISO_ECSPI1_MISO = IOMUX_PAD(0x0464, 0x01FC, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ECSPI1_MISO_UART3_CTS_B = IOMUX_PAD(0x0464, 0x01FC, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_ECSPI1_MISO_UART3_RTS_B = IOMUX_PAD(0x0464, 0x01FC, 1, 0x0500, 0, 0),
+ IMX8MM_PAD_ECSPI1_MISO_GPIO5_IO8 = IOMUX_PAD(0x0464, 0x01FC, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ECSPI1_SS0_ECSPI1_SS0 = IOMUX_PAD(0x0468, 0x0200, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ECSPI1_SS0_UART3_RTS_B = IOMUX_PAD(0x0468, 0x0200, 1, 0x0500, 1, 0),
+ IMX8MM_PAD_ECSPI1_SS0_UART3_CTS_B = IOMUX_PAD(0x0468, 0x0200, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_ECSPI1_SS0_GPIO5_IO9 = IOMUX_PAD(0x0468, 0x0200, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ECSPI2_SCLK_ECSPI2_SCLK = IOMUX_PAD(0x046C, 0x0204, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ECSPI2_SCLK_UART4_RX = IOMUX_PAD(0x046C, 0x0204, 1, 0x050C, 0, 0),
+ IMX8MM_PAD_ECSPI2_SCLK_UART4_TX = IOMUX_PAD(0x046C, 0x0204, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_ECSPI2_SCLK_GPIO5_IO10 = IOMUX_PAD(0x046C, 0x0204, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ECSPI2_MOSI_ECSPI2_MOSI = IOMUX_PAD(0x0470, 0x0208, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ECSPI2_MOSI_UART4_TX = IOMUX_PAD(0x0470, 0x0208, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_ECSPI2_MOSI_UART4_RX = IOMUX_PAD(0x0470, 0x0208, 1, 0x050C, 1, 0),
+ IMX8MM_PAD_ECSPI2_MOSI_GPIO5_IO11 = IOMUX_PAD(0x0470, 0x0208, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ECSPI2_MISO_ECSPI2_MISO = IOMUX_PAD(0x0474, 0x020C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ECSPI2_MISO_UART4_CTS_B = IOMUX_PAD(0x0474, 0x020C, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_ECSPI2_MISO_UART4_RTS_B = IOMUX_PAD(0x0474, 0x020C, 1, 0x0508, 0, 0),
+ IMX8MM_PAD_ECSPI2_MISO_GPIO5_IO12 = IOMUX_PAD(0x0474, 0x020C, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ECSPI2_SS0_ECSPI2_SS0 = IOMUX_PAD(0x0478, 0x0210, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ECSPI2_SS0_UART4_RTS_B = IOMUX_PAD(0x0478, 0x0210, 1, 0x0508, 1, 0),
+ IMX8MM_PAD_ECSPI2_SS0_UART4_CTS_B = IOMUX_PAD(0x0478, 0x0210, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_ECSPI2_SS0_GPIO5_IO13 = IOMUX_PAD(0x0478, 0x0210, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_I2C1_SCL_I2C1_SCL = IOMUX_PAD(0x047C, 0x0214, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+ IMX8MM_PAD_I2C1_SCL_ENET1_MDC = IOMUX_PAD(0x047C, 0x0214, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_I2C1_SCL_GPIO5_IO14 = IOMUX_PAD(0x047C, 0x0214, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_I2C1_SDA_I2C1_SDA = IOMUX_PAD(0x0480, 0x0218, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+ IMX8MM_PAD_I2C1_SDA_ENET1_MDIO = IOMUX_PAD(0x0480, 0x0218, 1, 0x04C0, 2, 0),
+ IMX8MM_PAD_I2C1_SDA_GPIO5_IO15 = IOMUX_PAD(0x0480, 0x0218, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_I2C2_SCL_I2C2_SCL = IOMUX_PAD(0x0484, 0x021C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_I2C2_SCL_ENET1_1588_EVENT1_IN = IOMUX_PAD(0x0484, 0x021C, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_I2C2_SCL_USDHC3_CD_B = IOMUX_PAD(0x0484, 0x021C, 2, 0x0544, 1, 0),
+ IMX8MM_PAD_I2C2_SCL_GPIO5_IO16 = IOMUX_PAD(0x0484, 0x021C, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_I2C2_SDA_I2C2_SDA = IOMUX_PAD(0x0488, 0x0220, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_I2C2_SDA_ENET1_1588_EVENT1_OUT = IOMUX_PAD(0x0488, 0x0220, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_I2C2_SDA_USDHC3_WP = IOMUX_PAD(0x0488, 0x0220, 2, 0x0548, 1, 0),
+ IMX8MM_PAD_I2C2_SDA_GPIO5_IO17 = IOMUX_PAD(0x0488, 0x0220, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_I2C3_SCL_I2C3_SCL = IOMUX_PAD(0x048C, 0x0224, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_I2C3_SCL_PWM4_OUT = IOMUX_PAD(0x048C, 0x0224, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_I2C3_SCL_GPT2_CLK = IOMUX_PAD(0x048C, 0x0224, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_I2C3_SCL_GPIO5_IO18 = IOMUX_PAD(0x048C, 0x0224, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_I2C3_SDA_I2C3_SDA = IOMUX_PAD(0x0490, 0x0228, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_I2C3_SDA_PWM3_OUT = IOMUX_PAD(0x0490, 0x0228, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_I2C3_SDA_GPT3_CLK = IOMUX_PAD(0x0490, 0x0228, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_I2C3_SDA_GPIO5_IO19 = IOMUX_PAD(0x0490, 0x0228, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_I2C4_SCL_I2C4_SCL = IOMUX_PAD(0x0494, 0x022C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_I2C4_SCL_PWM2_OUT = IOMUX_PAD(0x0494, 0x022C, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_I2C4_SCL_PCIE1_CLKREQ_B = IOMUX_PAD(0x0494, 0x022C, 2, 0x0524, 0, 0),
+ IMX8MM_PAD_I2C4_SCL_GPIO5_IO20 = IOMUX_PAD(0x0494, 0x022C, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_I2C4_SDA_I2C4_SDA = IOMUX_PAD(0x0498, 0x0230, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_I2C4_SDA_PWM1_OUT = IOMUX_PAD(0x0498, 0x0230, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_I2C4_SDA_GPIO5_IO21 = IOMUX_PAD(0x0498, 0x0230, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_UART1_RXD_UART1_RX = IOMUX_PAD(0x049C, 0x0234, 0, 0x04F4, 0, 0),
+ IMX8MM_PAD_UART1_RXD_UART1_TX = IOMUX_PAD(0x049C, 0x0234, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_UART1_RXD_ECSPI3_SCLK = IOMUX_PAD(0x049C, 0x0234, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_UART1_RXD_GPIO5_IO22 = IOMUX_PAD(0x049C, 0x0234, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_UART1_TXD_UART1_TX = IOMUX_PAD(0x04A0, 0x0238, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_UART1_TXD_UART1_RX = IOMUX_PAD(0x04A0, 0x0238, 0, 0x04F4, 1, 0),
+ IMX8MM_PAD_UART1_TXD_ECSPI3_MOSI = IOMUX_PAD(0x04A0, 0x0238, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_UART1_TXD_GPIO5_IO23 = IOMUX_PAD(0x04A0, 0x0238, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_UART2_RXD_UART2_RX = IOMUX_PAD(0x04A4, 0x023C, 0, 0x04FC, 0, 0),
+ IMX8MM_PAD_UART2_RXD_UART2_TX = IOMUX_PAD(0x04A4, 0x023C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_UART2_RXD_ECSPI3_MISO = IOMUX_PAD(0x04A4, 0x023C, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_UART2_RXD_GPIO5_IO24 = IOMUX_PAD(0x04A4, 0x023C, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_UART2_TXD_UART2_TX = IOMUX_PAD(0x04A8, 0x0240, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_UART2_TXD_UART2_RX = IOMUX_PAD(0x04A8, 0x0240, 0, 0x04FC, 1, 0),
+ IMX8MM_PAD_UART2_TXD_ECSPI3_SS0 = IOMUX_PAD(0x04A8, 0x0240, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_UART2_TXD_GPIO5_IO25 = IOMUX_PAD(0x04A8, 0x0240, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_UART3_RXD_UART3_RX = IOMUX_PAD(0x04AC, 0x0244, 0, 0x0504, 2, 0),
+ IMX8MM_PAD_UART3_RXD_UART3_TX = IOMUX_PAD(0x04AC, 0x0244, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_UART3_RXD_UART1_CTS_B = IOMUX_PAD(0x04AC, 0x0244, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_UART3_RXD_UART1_RTS_B = IOMUX_PAD(0x04AC, 0x0244, 1, 0x04F0, 0, 0),
+ IMX8MM_PAD_UART3_RXD_USDHC3_RESET_B = IOMUX_PAD(0x04AC, 0x0244, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_UART3_RXD_GPIO5_IO26 = IOMUX_PAD(0x04AC, 0x0244, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_UART3_TXD_UART3_TX = IOMUX_PAD(0x04B0, 0x0248, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_UART3_TXD_UART3_RX = IOMUX_PAD(0x04B0, 0x0248, 0, 0x0504, 3, 0),
+ IMX8MM_PAD_UART3_TXD_UART1_RTS_B = IOMUX_PAD(0x04B0, 0x0248, 1, 0x04F0, 1, 0),
+ IMX8MM_PAD_UART3_TXD_UART1_CTS_B = IOMUX_PAD(0x04B0, 0x0248, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_UART3_TXD_USDHC3_VSELECT = IOMUX_PAD(0x04B0, 0x0248, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_UART3_TXD_GPIO5_IO27 = IOMUX_PAD(0x04B0, 0x0248, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_UART4_RXD_UART4_RX = IOMUX_PAD(0x04B4, 0x024C, 0, 0x050C, 2, 0),
+ IMX8MM_PAD_UART4_RXD_UART4_TX = IOMUX_PAD(0x04B4, 0x024C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_UART4_RXD_UART2_CTS_B = IOMUX_PAD(0x04B4, 0x024C, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_UART4_RXD_UART2_RTS_B = IOMUX_PAD(0x04B4, 0x024C, 1, 0x04F8, 0, 0),
+ IMX8MM_PAD_UART4_RXD_PCIE1_CLKREQ_B = IOMUX_PAD(0x04B4, 0x024C, 2, 0x0524, 1, 0),
+ IMX8MM_PAD_UART4_RXD_GPIO5_IO28 = IOMUX_PAD(0x04B4, 0x024C, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_UART4_TXD_UART4_TX = IOMUX_PAD(0x04B8, 0x0250, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_UART4_TXD_UART4_RX = IOMUX_PAD(0x04B8, 0x0250, 0, 0x050C, 3, 0),
+ IMX8MM_PAD_UART4_TXD_UART2_RTS_B = IOMUX_PAD(0x04B8, 0x0250, 1, 0x04F8, 1, 0),
+ IMX8MM_PAD_UART4_TXD_UART2_CTS_B = IOMUX_PAD(0x04B8, 0x0250, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_UART4_TXD_GPIO5_IO29 = IOMUX_PAD(0x04B8, 0x0250, 5, 0x0000, 0, 0),
+};
+#endif
--
2.14.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* [U-Boot] [PATCH 12/20] imx: add i.MX8MM PE property
2019-01-28 9:39 [U-Boot] [PATCH 00/20] imx: add i.MX8MM support Peng Fan
` (10 preceding siblings ...)
2019-01-28 9:39 ` [U-Boot] [PATCH 11/20] imx8m: add pin header " Peng Fan
@ 2019-01-28 9:39 ` Peng Fan
2019-01-28 9:39 ` [U-Boot] [PATCH 13/20] imx8m: Fix MMU table issue for OPTEE memory Peng Fan
` (7 subsequent siblings)
19 siblings, 0 replies; 39+ messages in thread
From: Peng Fan @ 2019-01-28 9:39 UTC (permalink / raw)
To: u-boot
i.MX8MM does not have LVTTL, it has a PE property
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/include/asm/mach-imx/iomux-v3.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/include/asm/mach-imx/iomux-v3.h b/arch/arm/include/asm/mach-imx/iomux-v3.h
index b899a4ff6f..720e8f7043 100644
--- a/arch/arm/include/asm/mach-imx/iomux-v3.h
+++ b/arch/arm/include/asm/mach-imx/iomux-v3.h
@@ -104,7 +104,11 @@ typedef u64 iomux_v3_cfg_t;
#define PAD_CTL_ODE (0x1 << 5)
#define PAD_CTL_PUE (0x1 << 6)
#define PAD_CTL_HYS (0x1 << 7)
+#ifdef CONFIG_IMX8MM
+#define PAD_CTL_PE (0x1 << 8)
+#else
#define PAD_CTL_LVTTL (0x1 << 8)
+#endif
#elif defined CONFIG_MX7
--
2.14.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* [U-Boot] [PATCH 13/20] imx8m: Fix MMU table issue for OPTEE memory
2019-01-28 9:39 [U-Boot] [PATCH 00/20] imx: add i.MX8MM support Peng Fan
` (11 preceding siblings ...)
2019-01-28 9:39 ` [U-Boot] [PATCH 12/20] imx: add i.MX8MM PE property Peng Fan
@ 2019-01-28 9:39 ` Peng Fan
2019-01-28 9:39 ` [U-Boot] [PATCH 14/20] imx8m: set BYPASS ID SWAP to avoid AXI bus errors Peng Fan
` (6 subsequent siblings)
19 siblings, 0 replies; 39+ messages in thread
From: Peng Fan @ 2019-01-28 9:39 UTC (permalink / raw)
To: u-boot
When running with OPTEE, the MMU table in u-boot does not remove the OPTEE
memory from its settings. So ARM speculative prefetch in u-boot may access
that OPTEE memory. Due to trust zone is enabled by OPTEE and that memory
is set to secure access, then the speculative prefetch will fail and cause
various memory issue in u-boot.
The fail address register and int_status register in trustzone has logged
that speculative access from u-boot.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/mach-imx/imx8m/soc.c | 20 ++++++++++++++++++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 4160a75918..5634bfb96a 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -112,16 +112,18 @@ static struct mm_region imx8m_mem_map[] = {
/* DRAM1 */
.virt = 0x40000000UL,
.phys = 0x40000000UL,
- .size = 0xC0000000UL,
+ .size = PHYS_SDRAM_SIZE,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE
+#ifdef PHYS_SDRAM_2_SIZE
}, {
/* DRAM2 */
.virt = 0x100000000UL,
.phys = 0x100000000UL,
- .size = 0x040000000UL,
+ .size = PHYS_SDRAM_2_SIZE,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE
+#endif
}, {
/* List terminator */
0,
@@ -130,6 +132,20 @@ static struct mm_region imx8m_mem_map[] = {
struct mm_region *mem_map = imx8m_mem_map;
+void enable_caches(void)
+{
+ /*
+ * If OPTEE runs, remove OPTEE memory from MMU table to
+ * avoid speculative prefetch. OPTEE runs at the top of
+ * the first memory bank
+ */
+ if (rom_pointer[1])
+ imx8m_mem_map[5].size -= rom_pointer[1];
+
+ icache_enable();
+ dcache_enable();
+}
+
static u32 get_cpu_variant_type(u32 type)
{
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
--
2.14.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* [U-Boot] [PATCH 14/20] imx8m: set BYPASS ID SWAP to avoid AXI bus errors
2019-01-28 9:39 [U-Boot] [PATCH 00/20] imx: add i.MX8MM support Peng Fan
` (12 preceding siblings ...)
2019-01-28 9:39 ` [U-Boot] [PATCH 13/20] imx8m: Fix MMU table issue for OPTEE memory Peng Fan
@ 2019-01-28 9:39 ` Peng Fan
2019-01-28 9:40 ` [U-Boot] [PATCH 15/20] imx8m: Configure trustzone region 0 for non-secure access Peng Fan
` (5 subsequent siblings)
19 siblings, 0 replies; 39+ messages in thread
From: Peng Fan @ 2019-01-28 9:39 UTC (permalink / raw)
To: u-boot
set the BYPASS ID SWAP bit (GPR10 bit 1) in order for GPU not to
generated AXI bus errors with TZC380 enabled.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/mach-imx/imx8m/soc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 5634bfb96a..f4239d3357 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -55,6 +55,8 @@ void enable_tzc380(void)
/* Enable TZASC and lock setting */
setbits_le32(&gpr->gpr[10], GPR_TZASC_EN);
setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
+ if (IS_ENABLED(CONFIG_IMX8MM))
+ setbits_le32(&gpr->gpr[10], BIT(1));
}
void set_wdog_reset(struct wdog_regs *wdog)
--
2.14.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* [U-Boot] [PATCH 15/20] imx8m: Configure trustzone region 0 for non-secure access
2019-01-28 9:39 [U-Boot] [PATCH 00/20] imx: add i.MX8MM support Peng Fan
` (13 preceding siblings ...)
2019-01-28 9:39 ` [U-Boot] [PATCH 14/20] imx8m: set BYPASS ID SWAP to avoid AXI bus errors Peng Fan
@ 2019-01-28 9:40 ` Peng Fan
2019-01-28 9:40 ` [U-Boot] [PATCH 16/20] imx8m: fix sd to mmc1 and emmc to mmc2 for i.MX8MM Peng Fan
` (4 subsequent siblings)
19 siblings, 0 replies; 39+ messages in thread
From: Peng Fan @ 2019-01-28 9:40 UTC (permalink / raw)
To: u-boot
From: Ye Li <ye.li@nxp.com>
Set trustzone region 0 to allow both non-secure and secure access
when trust zone is enabled. We found USB controller fails to access
DDR if the default region 0 is secure access only.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/mach-imx/imx8m/soc.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index f4239d3357..98388003bc 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -57,6 +57,12 @@ void enable_tzc380(void)
setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
if (IS_ENABLED(CONFIG_IMX8MM))
setbits_le32(&gpr->gpr[10], BIT(1));
+ /*
+ * set Region 0 attribute to allow secure and non-secure
+ * read/write permission. Found some masters like usb dwc3
+ * controllers can't work with secure memory.
+ */
+ writel(0xf0000000, TZASC_BASE_ADDR + 0x108);
}
void set_wdog_reset(struct wdog_regs *wdog)
--
2.14.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* [U-Boot] [PATCH 16/20] imx8m: fix sd to mmc1 and emmc to mmc2 for i.MX8MM
2019-01-28 9:39 [U-Boot] [PATCH 00/20] imx: add i.MX8MM support Peng Fan
` (14 preceding siblings ...)
2019-01-28 9:40 ` [U-Boot] [PATCH 15/20] imx8m: Configure trustzone region 0 for non-secure access Peng Fan
@ 2019-01-28 9:40 ` Peng Fan
2019-01-29 22:57 ` Lukasz Majewski
2019-01-28 9:40 ` [U-Boot] [PATCH 17/20] imx8m: soc: enable SCTR clock before timer init Peng Fan
` (3 subsequent siblings)
19 siblings, 1 reply; 39+ messages in thread
From: Peng Fan @ 2019-01-28 9:40 UTC (permalink / raw)
To: u-boot
Since the SD is usdhc2 and eMMC is usdhc3, this cause mapping problem
for spl_boot_device. So far hard coded them to correct MMC index, so
that SD and eMMC boot can work.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/mach-imx/spl.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c
index ebd8ff9290..0048832be8 100644
--- a/arch/arm/mach-imx/spl.c
+++ b/arch/arm/mach-imx/spl.c
@@ -147,9 +147,18 @@ u32 spl_boot_device(void)
case SD1_BOOT:
case MMC1_BOOT:
return BOOT_DEVICE_MMC1;
+#if defined(CONFIG_IMX8MM)
+ case SD2_BOOT:
+ case MMC2_BOOT:
+ return BOOT_DEVICE_MMC1;
+ case SD3_BOOT:
+ case MMC3_BOOT:
+ return BOOT_DEVICE_MMC2;
+#else
case SD2_BOOT:
case MMC2_BOOT:
return BOOT_DEVICE_MMC2;
+#endif
#endif
case NAND_BOOT:
return BOOT_DEVICE_NAND;
--
2.14.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* [U-Boot] [PATCH 16/20] imx8m: fix sd to mmc1 and emmc to mmc2 for i.MX8MM
2019-01-28 9:40 ` [U-Boot] [PATCH 16/20] imx8m: fix sd to mmc1 and emmc to mmc2 for i.MX8MM Peng Fan
@ 2019-01-29 22:57 ` Lukasz Majewski
2019-01-29 23:01 ` Fabio Estevam
2019-01-30 5:47 ` Peng Fan
0 siblings, 2 replies; 39+ messages in thread
From: Lukasz Majewski @ 2019-01-29 22:57 UTC (permalink / raw)
To: u-boot
Hi Peng,
> Since the SD is usdhc2 and eMMC is usdhc3,
Is this true on all IMX8M boards? Or is it only on the development kit
you do have?
My point is that this shall be setup by DTS aliases or maybe by Kconfig
option.
> this cause mapping problem
> for spl_boot_device. So far hard coded them to correct MMC index, so
> that SD and eMMC boot can work.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> arch/arm/mach-imx/spl.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c
> index ebd8ff9290..0048832be8 100644
> --- a/arch/arm/mach-imx/spl.c
> +++ b/arch/arm/mach-imx/spl.c
> @@ -147,9 +147,18 @@ u32 spl_boot_device(void)
> case SD1_BOOT:
> case MMC1_BOOT:
> return BOOT_DEVICE_MMC1;
> +#if defined(CONFIG_IMX8MM)
> + case SD2_BOOT:
> + case MMC2_BOOT:
> + return BOOT_DEVICE_MMC1;
> + case SD3_BOOT:
> + case MMC3_BOOT:
> + return BOOT_DEVICE_MMC2;
> +#else
> case SD2_BOOT:
> case MMC2_BOOT:
> return BOOT_DEVICE_MMC2;
> +#endif
> #endif
> case NAND_BOOT:
> return BOOT_DEVICE_NAND;
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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^ permalink raw reply [flat|nested] 39+ messages in thread
* [U-Boot] [PATCH 16/20] imx8m: fix sd to mmc1 and emmc to mmc2 for i.MX8MM
2019-01-29 22:57 ` Lukasz Majewski
@ 2019-01-29 23:01 ` Fabio Estevam
2019-01-30 5:47 ` Peng Fan
1 sibling, 0 replies; 39+ messages in thread
From: Fabio Estevam @ 2019-01-29 23:01 UTC (permalink / raw)
To: u-boot
On Tue, Jan 29, 2019 at 8:58 PM Lukasz Majewski <lukma@denx.de> wrote:
> Is this true on all IMX8M boards? Or is it only on the development kit
> you do have?
>
> My point is that this shall be setup by DTS aliases or maybe by Kconfig
> option.
Yes, it seems that setting up the alias in the board dts should do the trick.
^ permalink raw reply [flat|nested] 39+ messages in thread
* [U-Boot] [PATCH 16/20] imx8m: fix sd to mmc1 and emmc to mmc2 for i.MX8MM
2019-01-29 22:57 ` Lukasz Majewski
2019-01-29 23:01 ` Fabio Estevam
@ 2019-01-30 5:47 ` Peng Fan
2019-01-30 6:50 ` Lukasz Majewski
1 sibling, 1 reply; 39+ messages in thread
From: Peng Fan @ 2019-01-30 5:47 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: Lukasz Majewski [mailto:lukma at denx.de]
> Sent: 2019年1月30日 6:58
> To: Peng Fan <peng.fan@nxp.com>
> Cc: sbabic at denx.de; Fabio Estevam <fabio.estevam@nxp.com>;
> dl-uboot-imx <uboot-imx@nxp.com>; u-boot at lists.denx.de
> Subject: Re: [U-Boot] [PATCH 16/20] imx8m: fix sd to mmc1 and emmc to
> mmc2 for i.MX8MM
>
> Hi Peng,
>
> > Since the SD is usdhc2 and eMMC is usdhc3,
>
> Is this true on all IMX8M boards? Or is it only on the development kit you do
> have?
This is a hack for board, needs to be fixed in next version.
>
> My point is that this shall be setup by DTS aliases or maybe by Kconfig option.
Could you share more information?
Thanks,
Peng.
>
> > this cause mapping problem
> > for spl_boot_device. So far hard coded them to correct MMC index, so
> > that SD and eMMC boot can work.
> >
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > ---
> > arch/arm/mach-imx/spl.c | 9 +++++++++
> > 1 file changed, 9 insertions(+)
> >
> > diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index
> > ebd8ff9290..0048832be8 100644
> > --- a/arch/arm/mach-imx/spl.c
> > +++ b/arch/arm/mach-imx/spl.c
> > @@ -147,9 +147,18 @@ u32 spl_boot_device(void)
> > case SD1_BOOT:
> > case MMC1_BOOT:
> > return BOOT_DEVICE_MMC1;
> > +#if defined(CONFIG_IMX8MM)
> > + case SD2_BOOT:
> > + case MMC2_BOOT:
> > + return BOOT_DEVICE_MMC1;
> > + case SD3_BOOT:
> > + case MMC3_BOOT:
> > + return BOOT_DEVICE_MMC2;
> > +#else
> > case SD2_BOOT:
> > case MMC2_BOOT:
> > return BOOT_DEVICE_MMC2;
> > +#endif
> > #endif
> > case NAND_BOOT:
> > return BOOT_DEVICE_NAND;
>
>
>
>
> Best regards,
>
> Lukasz Majewski
>
> --
>
> DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> lukma at denx.de
^ permalink raw reply [flat|nested] 39+ messages in thread
* [U-Boot] [PATCH 16/20] imx8m: fix sd to mmc1 and emmc to mmc2 for i.MX8MM
2019-01-30 5:47 ` Peng Fan
@ 2019-01-30 6:50 ` Lukasz Majewski
2019-01-30 6:51 ` Peng Fan
0 siblings, 1 reply; 39+ messages in thread
From: Lukasz Majewski @ 2019-01-30 6:50 UTC (permalink / raw)
To: u-boot
Hi Peng,
> > -----Original Message-----
> > From: Lukasz Majewski [mailto:lukma at denx.de]
> > Sent: 2019年1月30日 6:58
> > To: Peng Fan <peng.fan@nxp.com>
> > Cc: sbabic at denx.de; Fabio Estevam <fabio.estevam@nxp.com>;
> > dl-uboot-imx <uboot-imx@nxp.com>; u-boot at lists.denx.de
> > Subject: Re: [U-Boot] [PATCH 16/20] imx8m: fix sd to mmc1 and emmc
> > to mmc2 for i.MX8MM
> >
> > Hi Peng,
> >
> > > Since the SD is usdhc2 and eMMC is usdhc3,
> >
> > Is this true on all IMX8M boards? Or is it only on the development
> > kit you do have?
>
> This is a hack for board, needs to be fixed in next version.
>
> >
> > My point is that this shall be setup by DTS aliases or maybe by
> > Kconfig option.
>
> Could you share more information?
For example:
/ {
model = "K+P iMX6Q";
compatible = "kp,imx6-kp", "fsl,imx6";
aliases {
mmc0 = &usdhc2;
mmc1 = &usdhc4;
usb1 = &usbh1;
};
chosen {
stdout-path = &uart1;
};
And the "aliases" set the order in which you get the devices (like
mmc0, mmc1 above).
>
> Thanks,
> Peng.
>
> >
> > > this cause mapping problem
> > > for spl_boot_device. So far hard coded them to correct MMC index,
> > > so that SD and eMMC boot can work.
> > >
> > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > ---
> > > arch/arm/mach-imx/spl.c | 9 +++++++++
> > > 1 file changed, 9 insertions(+)
> > >
> > > diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c
> > > index ebd8ff9290..0048832be8 100644
> > > --- a/arch/arm/mach-imx/spl.c
> > > +++ b/arch/arm/mach-imx/spl.c
> > > @@ -147,9 +147,18 @@ u32 spl_boot_device(void)
> > > case SD1_BOOT:
> > > case MMC1_BOOT:
> > > return BOOT_DEVICE_MMC1;
> > > +#if defined(CONFIG_IMX8MM)
> > > + case SD2_BOOT:
> > > + case MMC2_BOOT:
> > > + return BOOT_DEVICE_MMC1;
> > > + case SD3_BOOT:
> > > + case MMC3_BOOT:
> > > + return BOOT_DEVICE_MMC2;
> > > +#else
> > > case SD2_BOOT:
> > > case MMC2_BOOT:
> > > return BOOT_DEVICE_MMC2;
> > > +#endif
> > > #endif
> > > case NAND_BOOT:
> > > return BOOT_DEVICE_NAND;
> >
> >
> >
> >
> > Best regards,
> >
> > Lukasz Majewski
> >
> > --
> >
> > DENX Software Engineering GmbH, Managing Director: Wolfgang
> > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell,
> > Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> > lukma at denx.de
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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^ permalink raw reply [flat|nested] 39+ messages in thread* [U-Boot] [PATCH 16/20] imx8m: fix sd to mmc1 and emmc to mmc2 for i.MX8MM
2019-01-30 6:50 ` Lukasz Majewski
@ 2019-01-30 6:51 ` Peng Fan
2019-01-30 8:19 ` Lukasz Majewski
0 siblings, 1 reply; 39+ messages in thread
From: Peng Fan @ 2019-01-30 6:51 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: Lukasz Majewski [mailto:lukma at denx.de]
> Sent: 2019年1月30日 14:50
> To: Peng Fan <peng.fan@nxp.com>
> Cc: sbabic at denx.de; Fabio Estevam <fabio.estevam@nxp.com>;
> dl-uboot-imx <uboot-imx@nxp.com>; u-boot at lists.denx.de
> Subject: Re: [U-Boot] [PATCH 16/20] imx8m: fix sd to mmc1 and emmc to
> mmc2 for i.MX8MM
>
> Hi Peng,
>
> > > -----Original Message-----
> > > From: Lukasz Majewski [mailto:lukma at denx.de]
> > > Sent: 2019年1月30日 6:58
> > > To: Peng Fan <peng.fan@nxp.com>
> > > Cc: sbabic at denx.de; Fabio Estevam <fabio.estevam@nxp.com>;
> > > dl-uboot-imx <uboot-imx@nxp.com>; u-boot at lists.denx.de
> > > Subject: Re: [U-Boot] [PATCH 16/20] imx8m: fix sd to mmc1 and emmc
> > > to mmc2 for i.MX8MM
> > >
> > > Hi Peng,
> > >
> > > > Since the SD is usdhc2 and eMMC is usdhc3,
> > >
> > > Is this true on all IMX8M boards? Or is it only on the development
> > > kit you do have?
> >
> > This is a hack for board, needs to be fixed in next version.
> >
> > >
> > > My point is that this shall be setup by DTS aliases or maybe by
> > > Kconfig option.
> >
> > Could you share more information?
>
> For example:
>
> / {
> model = "K+P iMX6Q";
> compatible = "kp,imx6-kp", "fsl,imx6";
>
> aliases {
> mmc0 = &usdhc2;
> mmc1 = &usdhc4;
> usb1 = &usbh1;
> };
>
> chosen {
> stdout-path = &uart1;
> };
>
>
> And the "aliases" set the order in which you get the devices (like mmc0,
> mmc1 above).
Then we need SPL to have Device tree support, right?
Thanks,
Peng.
>
> >
> > Thanks,
> > Peng.
> >
> > >
> > > > this cause mapping problem
> > > > for spl_boot_device. So far hard coded them to correct MMC index,
> > > > so that SD and eMMC boot can work.
> > > >
> > > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > > ---
> > > > arch/arm/mach-imx/spl.c | 9 +++++++++
> > > > 1 file changed, 9 insertions(+)
> > > >
> > > > diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c
> > > > index ebd8ff9290..0048832be8 100644
> > > > --- a/arch/arm/mach-imx/spl.c
> > > > +++ b/arch/arm/mach-imx/spl.c
> > > > @@ -147,9 +147,18 @@ u32 spl_boot_device(void)
> > > > case SD1_BOOT:
> > > > case MMC1_BOOT:
> > > > return BOOT_DEVICE_MMC1;
> > > > +#if defined(CONFIG_IMX8MM)
> > > > + case SD2_BOOT:
> > > > + case MMC2_BOOT:
> > > > + return BOOT_DEVICE_MMC1;
> > > > + case SD3_BOOT:
> > > > + case MMC3_BOOT:
> > > > + return BOOT_DEVICE_MMC2;
> > > > +#else
> > > > case SD2_BOOT:
> > > > case MMC2_BOOT:
> > > > return BOOT_DEVICE_MMC2;
> > > > +#endif
> > > > #endif
> > > > case NAND_BOOT:
> > > > return BOOT_DEVICE_NAND;
> > >
> > >
> > >
> > >
> > > Best regards,
> > >
> > > Lukasz Majewski
> > >
> > > --
> > >
> > > DENX Software Engineering GmbH, Managing Director: Wolfgang
> > > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell,
> > > Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> > > lukma at denx.de
>
>
>
>
> Best regards,
>
> Lukasz Majewski
>
> --
>
> DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> lukma at denx.de
^ permalink raw reply [flat|nested] 39+ messages in thread* [U-Boot] [PATCH 16/20] imx8m: fix sd to mmc1 and emmc to mmc2 for i.MX8MM
2019-01-30 6:51 ` Peng Fan
@ 2019-01-30 8:19 ` Lukasz Majewski
0 siblings, 0 replies; 39+ messages in thread
From: Lukasz Majewski @ 2019-01-30 8:19 UTC (permalink / raw)
To: u-boot
Hi Peng,
> > -----Original Message-----
> > From: Lukasz Majewski [mailto:lukma at denx.de]
> > Sent: 2019年1月30日 14:50
> > To: Peng Fan <peng.fan@nxp.com>
> > Cc: sbabic at denx.de; Fabio Estevam <fabio.estevam@nxp.com>;
> > dl-uboot-imx <uboot-imx@nxp.com>; u-boot at lists.denx.de
> > Subject: Re: [U-Boot] [PATCH 16/20] imx8m: fix sd to mmc1 and emmc
> > to mmc2 for i.MX8MM
> >
> > Hi Peng,
> >
> > > > -----Original Message-----
> > > > From: Lukasz Majewski [mailto:lukma at denx.de]
> > > > Sent: 2019年1月30日 6:58
> > > > To: Peng Fan <peng.fan@nxp.com>
> > > > Cc: sbabic at denx.de; Fabio Estevam <fabio.estevam@nxp.com>;
> > > > dl-uboot-imx <uboot-imx@nxp.com>; u-boot at lists.denx.de
> > > > Subject: Re: [U-Boot] [PATCH 16/20] imx8m: fix sd to mmc1 and
> > > > emmc to mmc2 for i.MX8MM
> > > >
> > > > Hi Peng,
> > > >
> > > > > Since the SD is usdhc2 and eMMC is usdhc3,
> > > >
> > > > Is this true on all IMX8M boards? Or is it only on the
> > > > development kit you do have?
> > >
> > > This is a hack for board, needs to be fixed in next version.
> > >
> > > >
> > > > My point is that this shall be setup by DTS aliases or maybe by
> > > > Kconfig option.
> > >
> > > Could you share more information?
> >
> > For example:
> >
> > / {
> > model = "K+P iMX6Q";
> > compatible = "kp,imx6-kp", "fsl,imx6";
> >
> > aliases {
> > mmc0 = &usdhc2;
> > mmc1 = &usdhc4;
> > usb1 = &usbh1;
> > };
> >
> > chosen {
> > stdout-path = &uart1;
> > };
> >
> >
> > And the "aliases" set the order in which you get the devices (like
> > mmc0, mmc1 above).
>
> Then we need SPL to have Device tree support, right?
Yes, this would be the easiest way to support this feature.
If your board doesn't have any footprint constraints (and boottime)
then IMHO it would be worth to switch to full (including SPL)
conversion to DM/DTS.
Other option would be to provide such configuration via Kconfig or
define spl_boot_device(void) in board's file.
>
> Thanks,
> Peng.
>
> >
> > >
> > > Thanks,
> > > Peng.
> > >
> > > >
> > > > > this cause mapping problem
> > > > > for spl_boot_device. So far hard coded them to correct MMC
> > > > > index, so that SD and eMMC boot can work.
> > > > >
> > > > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > > > ---
> > > > > arch/arm/mach-imx/spl.c | 9 +++++++++
> > > > > 1 file changed, 9 insertions(+)
> > > > >
> > > > > diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c
> > > > > index ebd8ff9290..0048832be8 100644
> > > > > --- a/arch/arm/mach-imx/spl.c
> > > > > +++ b/arch/arm/mach-imx/spl.c
> > > > > @@ -147,9 +147,18 @@ u32 spl_boot_device(void)
> > > > > case SD1_BOOT:
> > > > > case MMC1_BOOT:
> > > > > return BOOT_DEVICE_MMC1;
> > > > > +#if defined(CONFIG_IMX8MM)
> > > > > + case SD2_BOOT:
> > > > > + case MMC2_BOOT:
> > > > > + return BOOT_DEVICE_MMC1;
> > > > > + case SD3_BOOT:
> > > > > + case MMC3_BOOT:
> > > > > + return BOOT_DEVICE_MMC2;
> > > > > +#else
> > > > > case SD2_BOOT:
> > > > > case MMC2_BOOT:
> > > > > return BOOT_DEVICE_MMC2;
> > > > > +#endif
> > > > > #endif
> > > > > case NAND_BOOT:
> > > > > return BOOT_DEVICE_NAND;
> > > >
> > > >
> > > >
> > > >
> > > > Best regards,
> > > >
> > > > Lukasz Majewski
> > > >
> > > > --
> > > >
> > > > DENX Software Engineering GmbH, Managing Director: Wolfgang
> > > > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194
> > > > Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax:
> > > > (+49)-8142-66989-80 Email: lukma at denx.de
> >
> >
> >
> >
> > Best regards,
> >
> > Lukasz Majewski
> >
> > --
> >
> > DENX Software Engineering GmbH, Managing Director: Wolfgang
> > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell,
> > Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> > lukma at denx.de
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
-------------- next part --------------
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^ permalink raw reply [flat|nested] 39+ messages in thread
* [U-Boot] [PATCH 17/20] imx8m: soc: enable SCTR clock before timer init
2019-01-28 9:39 [U-Boot] [PATCH 00/20] imx: add i.MX8MM support Peng Fan
` (15 preceding siblings ...)
2019-01-28 9:40 ` [U-Boot] [PATCH 16/20] imx8m: fix sd to mmc1 and emmc to mmc2 for i.MX8MM Peng Fan
@ 2019-01-28 9:40 ` Peng Fan
2019-01-28 9:40 ` [U-Boot] [PATCH 18/20] serial: Kconfig: make MXC_UART usable for MX7 and IMX8M Peng Fan
` (2 subsequent siblings)
19 siblings, 0 replies; 39+ messages in thread
From: Peng Fan @ 2019-01-28 9:40 UTC (permalink / raw)
To: u-boot
To i.MX8MM SCTR clock is disabled by ROM, so before timer init
need to enable it.
To i.MX8MQ, it does not hurt the clock is enabled again.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/mach-imx/imx8m/soc.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 98388003bc..f1480c9d26 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -230,6 +230,12 @@ static void imx_set_wdog_powerdown(bool enable)
int arch_cpu_init(void)
{
+ /*
+ * ROM might disable clock for SCTR,
+ * enable the clock before timer_init.
+ */
+ if (IS_ENABLED(CONFIG_SPL_BUILD))
+ clock_enable(CCGR_SCTR, 1);
/*
* Init timer at very early state, because sscg pll setting
* will use it
--
2.14.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* [U-Boot] [PATCH 18/20] serial: Kconfig: make MXC_UART usable for MX7 and IMX8M
2019-01-28 9:39 [U-Boot] [PATCH 00/20] imx: add i.MX8MM support Peng Fan
` (16 preceding siblings ...)
2019-01-28 9:40 ` [U-Boot] [PATCH 17/20] imx8m: soc: enable SCTR clock before timer init Peng Fan
@ 2019-01-28 9:40 ` Peng Fan
2019-01-28 9:43 ` [U-Boot] [PATCH 19/20] pinctrl: add imx8m driver Peng Fan
2019-01-28 9:43 ` [U-Boot] [PATCH 20/20] imx: add i.MX8MM EVK board support Peng Fan
19 siblings, 0 replies; 39+ messages in thread
From: Peng Fan @ 2019-01-28 9:40 UTC (permalink / raw)
To: u-boot
i.MX7 and i.MX8M use mxc uart driver, so let's make the SoC could
use MXC_UART kconfig.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
drivers/serial/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 887cd687c0..e53f880cd9 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -552,7 +552,7 @@ config MVEBU_A3700_UART
config MXC_UART
bool "IMX serial port support"
- depends on MX5 || MX6
+ depends on MX5 || MX6 || MX7 || IMX8M
help
If you have a machine based on a Motorola IMX CPU you
can enable its onboard serial port by enabling this option.
--
2.14.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* [U-Boot] [PATCH 19/20] pinctrl: add imx8m driver
2019-01-28 9:39 [U-Boot] [PATCH 00/20] imx: add i.MX8MM support Peng Fan
` (17 preceding siblings ...)
2019-01-28 9:40 ` [U-Boot] [PATCH 18/20] serial: Kconfig: make MXC_UART usable for MX7 and IMX8M Peng Fan
@ 2019-01-28 9:43 ` Peng Fan
2019-01-28 9:43 ` [U-Boot] [PATCH 20/20] imx: add i.MX8MM EVK board support Peng Fan
19 siblings, 0 replies; 39+ messages in thread
From: Peng Fan @ 2019-01-28 9:43 UTC (permalink / raw)
To: u-boot
Add i.mx8m pinctrl driver.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
drivers/pinctrl/nxp/Kconfig | 14 ++++++++++++++
drivers/pinctrl/nxp/Makefile | 1 +
drivers/pinctrl/nxp/pinctrl-imx8m.c | 36 ++++++++++++++++++++++++++++++++++++
3 files changed, 51 insertions(+)
create mode 100644 drivers/pinctrl/nxp/pinctrl-imx8m.c
diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig
index f1d5a5c50d..61f93be42d 100644
--- a/drivers/pinctrl/nxp/Kconfig
+++ b/drivers/pinctrl/nxp/Kconfig
@@ -75,6 +75,20 @@ config PINCTRL_IMX8
only parses the 'fsl,pins' property and configures related
registers.
+config PINCTRL_IMX8M
+ bool "IMX8M pinctrl driver"
+ depends on ARCH_IMX8M && PINCTRL_FULL
+ select DEVRES
+ select PINCTRL_IMX
+ help
+ Say Y here to enable the imx8m pinctrl driver
+
+ This provides a simple pinctrl driver for i.MX8M SoC familiy.
+ This feature depends on device tree configuration. This driver
+ is different from the linux one, this is a simple implementation,
+ only parses the 'fsl,pins' property and configure related
+ registers.
+
config PINCTRL_VYBRID
bool "Vybrid (vf610) pinctrl driver"
depends on ARCH_VF610 && PINCTRL_FULL
diff --git a/drivers/pinctrl/nxp/Makefile b/drivers/pinctrl/nxp/Makefile
index 891ee6e477..b340d9448a 100644
--- a/drivers/pinctrl/nxp/Makefile
+++ b/drivers/pinctrl/nxp/Makefile
@@ -5,4 +5,5 @@ obj-$(CONFIG_PINCTRL_IMX7) += pinctrl-imx7.o
obj-$(CONFIG_PINCTRL_IMX7ULP) += pinctrl-imx7ulp.o
obj-$(CONFIG_PINCTRL_IMX_SCU) += pinctrl-scu.o
obj-$(CONFIG_PINCTRL_IMX8) += pinctrl-imx8.o
+obj-$(CONFIG_PINCTRL_IMX8M) += pinctrl-imx8m.o
obj-$(CONFIG_PINCTRL_VYBRID) += pinctrl-vf610.o
diff --git a/drivers/pinctrl/nxp/pinctrl-imx8m.c b/drivers/pinctrl/nxp/pinctrl-imx8m.c
new file mode 100644
index 0000000000..8bb03b7a62
--- /dev/null
+++ b/drivers/pinctrl/nxp/pinctrl-imx8m.c
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <dm/device.h>
+#include <dm/pinctrl.h>
+
+#include "pinctrl-imx.h"
+
+static struct imx_pinctrl_soc_info imx8mq_pinctrl_soc_info;
+
+static int imx8mq_pinctrl_probe(struct udevice *dev)
+{
+ struct imx_pinctrl_soc_info *info =
+ (struct imx_pinctrl_soc_info *)dev_get_driver_data(dev);
+
+ return imx_pinctrl_probe(dev, info);
+}
+
+static const struct udevice_id imx8m_pinctrl_match[] = {
+ { .compatible = "fsl,imx8mq-iomuxc", .data = (ulong)&imx8mq_pinctrl_soc_info },
+ { .compatible = "fsl,imx8mm-iomuxc", .data = (ulong)&imx8mq_pinctrl_soc_info },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(imx8mq_pinctrl) = {
+ .name = "imx8mq-pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = of_match_ptr(imx8m_pinctrl_match),
+ .probe = imx8mq_pinctrl_probe,
+ .remove = imx_pinctrl_remove,
+ .priv_auto_alloc_size = sizeof(struct imx_pinctrl_priv),
+ .ops = &imx_pinctrl_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
--
2.14.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* [U-Boot] [PATCH 20/20] imx: add i.MX8MM EVK board support
2019-01-28 9:39 [U-Boot] [PATCH 00/20] imx: add i.MX8MM support Peng Fan
` (18 preceding siblings ...)
2019-01-28 9:43 ` [U-Boot] [PATCH 19/20] pinctrl: add imx8m driver Peng Fan
@ 2019-01-28 9:43 ` Peng Fan
2019-01-29 23:18 ` Lukasz Majewski
19 siblings, 1 reply; 39+ messages in thread
From: Peng Fan @ 2019-01-28 9:43 UTC (permalink / raw)
To: u-boot
Add i.MX8MM EVK board support.
Add board and SoC dts
Add ddr training code
support SD/MMC/GPIO/PINCTRL/UART
U-Boot SPL 2019.01-00148-g1179cffe66 (Jan 28 2019 - 17:37:34 +0800)
Normal Boot
Trying to boot from MMC1
U-Boot 2019.01-00148-g1179cffe66 (Jan 28 2019 - 17:37:34 +0800)
CPU: Freescale i.MX8MMQ rev1.0 at 1200 MHz
Reset cause: POR
Model: NXP i.MX8MM EVK board
DRAM: 2 GiB
MMC: FSL_SDHC: 1, FSL_SDHC: 2
In: serial
Out: serial
Err: serial
Net: No ethernet found.
Hit any key to stop autoboot: 2
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/dts/fsl-imx8mm-evk.dts | 203 +++
arch/arm/dts/fsl-imx8mm.dtsi | 586 ++++++++
arch/arm/mach-imx/imx8m/Kconfig | 7 +
board/freescale/imx8mm_evk/Kconfig | 12 +
board/freescale/imx8mm_evk/MAINTAINERS | 6 +
board/freescale/imx8mm_evk/Makefile | 12 +
board/freescale/imx8mm_evk/imx8mm_evk.c | 144 ++
board/freescale/imx8mm_evk/lpddr4_timing.c | 1980 ++++++++++++++++++++++++++++
board/freescale/imx8mm_evk/spl.c | 187 +++
configs/imx8mm_evk_defconfig | 41 +
include/configs/imx8mm_evk.h | 221 ++++
11 files changed, 3399 insertions(+)
create mode 100644 arch/arm/dts/fsl-imx8mm-evk.dts
create mode 100644 arch/arm/dts/fsl-imx8mm.dtsi
create mode 100644 board/freescale/imx8mm_evk/Kconfig
create mode 100644 board/freescale/imx8mm_evk/MAINTAINERS
create mode 100644 board/freescale/imx8mm_evk/Makefile
create mode 100644 board/freescale/imx8mm_evk/imx8mm_evk.c
create mode 100644 board/freescale/imx8mm_evk/lpddr4_timing.c
create mode 100644 board/freescale/imx8mm_evk/spl.c
create mode 100644 configs/imx8mm_evk_defconfig
create mode 100644 include/configs/imx8mm_evk.h
diff --git a/arch/arm/dts/fsl-imx8mm-evk.dts b/arch/arm/dts/fsl-imx8mm-evk.dts
new file mode 100644
index 0000000000..df409eca47
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8mm-evk.dts
@@ -0,0 +1,203 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+#include "fsl-imx8mm.dtsi"
+
+/ {
+ model = "NXP i.MX8MM EVK board";
+ compatible = "fsl,imx8mm-evk", "fsl,imx8mm";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg_usdhc2_vmmc: regulator-usdhc2 {
+ compatible = "regulator-fixed";
+ regulator-name = "VSD_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ off-on-delay = <20000>;
+ enable-active-high;
+ };
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+
+ imx8mm-evk {
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
+ MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
+ MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
+ MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
+ MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
+ MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
+ MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
+ MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
+ MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
+ MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
+ MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
+ MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
+ MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
+ MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
+ MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
+ >;
+ };
+
+ pinctrl_gpio_led: gpioledgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
+ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2grpgpio {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
+ MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
+ >;
+ };
+ };
+};
+
+&uart2 { /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ status = "okay";
+};
+
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
diff --git a/arch/arm/dts/fsl-imx8mm.dtsi b/arch/arm/dts/fsl-imx8mm.dtsi
new file mode 100644
index 0000000000..8a808f856d
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8mm.dtsi
@@ -0,0 +1,586 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2017-2019 NXP
+ */
+
+#include <dt-bindings/clock/imx8mm-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/pins-imx8mm.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+ compatible = "fsl,imx8mm";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ i2c0 = &i2c1;
+ i2c1 = &i2c2;
+ i2c2 = &i2c3;
+ i2c3 = &i2c4;
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ serial3 = &uart4;
+ spi0 = &ecspi1;
+ spi1 = &ecspi2;
+ spi2 = &ecspi3;
+ mmc0 = &usdhc1;
+ mmc1 = &usdhc2;
+ mmc2 = &usdhc3;
+ gpio0 = &gpio1;
+ gpio1 = &gpio2;
+ gpio2 = &gpio3;
+ gpio3 = &gpio4;
+ gpio4 = &gpio5;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ A53_0: cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0>;
+ enable-method = "psci";
+ next-level-cache = <&A53_L2>;
+ };
+
+ A53_1: cpu at 1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1>;
+ enable-method = "psci";
+ next-level-cache = <&A53_L2>;
+ };
+
+ A53_2: cpu at 2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x2>;
+ enable-method = "psci";
+ next-level-cache = <&A53_L2>;
+ };
+
+ A53_3: cpu at 3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x3>;
+ enable-method = "psci";
+ next-level-cache = <&A53_L2>;
+ };
+
+ A53_L2: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ memory at 40000000 {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0 0x80000000>;
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ osc_32k: clock at 0 {
+ compatible = "fixed-clock";
+ reg = <0>;
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "osc_32k";
+ };
+
+ osc_24m: clock at 1 {
+ compatible = "fixed-clock";
+ reg = <1>;
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "osc_24m";
+ };
+
+ clk_ext1: clock at 2 {
+ compatible = "fixed-clock";
+ reg = <3>;
+ #clock-cells = <0>;
+ clock-frequency = <133000000>;
+ clock-output-names = "clk_ext1";
+ };
+
+ clk_ext2: clock at 3 {
+ compatible = "fixed-clock";
+ reg = <4>;
+ #clock-cells = <0>;
+ clock-frequency = <133000000>;
+ clock-output-names = "clk_ext2";
+ };
+
+ clk_ext3: clock at 4 {
+ compatible = "fixed-clock";
+ reg = <5>;
+ #clock-cells = <0>;
+ clock-frequency = <133000000>;
+ clock-output-names = "clk_ext3";
+ };
+
+ clk_ext4: clock at 5 {
+ compatible = "fixed-clock";
+ reg = <6>;
+ #clock-cells = <0>;
+ clock-frequency= <133000000>;
+ clock-output-names = "clk_ext4";
+ };
+ };
+
+ gic: interrupt-controller at 38800000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */
+ <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 7
+ (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
+ clock-frequency = <8000000>;
+ arm,no-tick-in-suspend;
+ };
+
+ soc at 0 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ aips1: bus at 30000000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x30000000 0x0 0x400000>;
+ ranges;
+
+ gpio1: gpio at 30200000 {
+ compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
+ reg = <0x0 0x30200000 0x0 0x10000>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio at 30210000 {
+ compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
+ reg = <0x0 0x30210000 0x0 0x10000>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio at 30220000 {
+ compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
+ reg = <0x0 0x30220000 0x0 0x10000>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio at 30230000 {
+ compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
+ reg = <0x0 0x30230000 0x0 0x10000>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio5: gpio at 30240000 {
+ compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
+ reg = <0x0 0x30240000 0x0 0x10000>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ wdog1: wdog at 30280000 {
+ compatible = "fsl,imx21-wdt";
+ reg = <0 0x30280000 0 0x10000>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_WDOG1_ROOT>;
+ status = "disabled";
+ };
+
+ wdog2: wdog at 30290000 {
+ compatible = "fsl,imx21-wdt";
+ reg = <0 0x30290000 0 0x10000>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_WDOG2_ROOT>;
+ status = "disabled";
+ };
+
+ wdog3: wdog at 302a0000 {
+ compatible = "fsl,imx21-wdt";
+ reg = <0 0x302a0000 0 0x10000>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_WDOG3_ROOT>;
+ status = "disabled";
+ };
+
+ sdma2: dma-controller at 302c0000 {
+ compatible = "fsl,imx8mq-sdma", "fsl,imx7d-sdma";
+ reg = <0x0 0x302c0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>,
+ <&clk IMX8MM_CLK_SDMA2_ROOT>;
+ clock-names = "ipg", "ahb";
+ #dma-cells = <3>;
+ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
+ fsl,ratio-1-1;
+ status = "okay";
+ };
+
+ sdma3: dma-controller at 302b0000 {
+ compatible = "fsl,imx8mq-sdma", "fsl,imx7d-sdma";
+ reg = <0x0 0x302b0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>,
+ <&clk IMX8MM_CLK_SDMA3_ROOT>;
+ clock-names = "ipg", "ahb";
+ #dma-cells = <3>;
+ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
+ fsl,ratio-1-1;
+ status = "okay";
+ };
+
+ iomuxc: pinctrl at 30330000 {
+ compatible = "fsl,imx8mm-iomuxc";
+ reg = <0x0 0x30330000 0x0 0x10000>;
+ };
+
+ gpr: iomuxc-gpr at 30340000 {
+ compatible = "fsl,imx8mm-iomuxc-gpr", "syscon";
+ reg = <0x0 0x30340000 0x0 0x10000>;
+ };
+
+ ocotp: ocotp-ctrl at 30350000 {
+ compatible = "fsl,imx8mq-ocotp", "fsl,imx7d-ocotp", "syscon";
+ reg = <0 0x30350000 0 0x10000>;
+ clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>;
+ /* For nvmem subnodes */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ anatop: anatop at 30360000 {
+ compatible = "fsl,imx8mm-anatop", "syscon", "simple-bus";
+ reg = <0x0 0x30360000 0x0 0x10000>;
+ };
+
+ snvs: snvs at 30370000 {
+ compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
+ reg = <0x0 0x30370000 0x0 0x10000>;
+
+ snvs_rtc: snvs-rtc-lp{
+ compatible = "fsl,sec-v4.0-mon-rtc-lp";
+ regmap =<&snvs>;
+ offset = <0x34>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ snvs_pwrkey: snvs-powerkey {
+ compatible = "fsl,sec-v4.0-pwrkey";
+ regmap = <&snvs>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ linux,keycode = <KEY_POWER>;
+ wakeup-source;
+ };
+ };
+
+ clk: clock-controller at 30380000 {
+ compatible = "fsl,imx8mm-ccm";
+ reg = <0x0 0x30380000 0x0 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
+ <&clk_ext3>, <&clk_ext4>;
+ clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
+ "clk_ext3", "clk_ext4";
+ };
+
+ src: src at 30390000 {
+ compatible = "fsl,imx8mm-src", "syscon";
+ reg = <0x0 0x30390000 0x0 0x10000>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ #reset-cells = <1>;
+ };
+
+ gpc: gpc at 303a0000 {
+ compatible = "fsl,imx8mm-gpc", "syscon";
+ reg = <0x0 0x303a0000 0x0 0x10000>;
+ interrupt-controller;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <3>;
+ };
+ };
+
+ aips2: bus at 30400000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x30400000 0x0 0x400000>;
+ ranges;
+
+ pwm1: pwm at 30660000 {
+ compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
+ reg = <0x0 0x30660000 0x0 0x10000>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_PWM1_ROOT>,
+ <&clk IMX8MM_CLK_PWM1_ROOT>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm2: pwm at 30670000 {
+ compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
+ reg = <0x0 0x30670000 0x0 0x10000>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_PWM2_ROOT>,
+ <&clk IMX8MM_CLK_PWM2_ROOT>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm3: pwm at 30680000 {
+ compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
+ reg = <0x0 0x30680000 0x0 0x10000>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_PWM3_ROOT>,
+ <&clk IMX8MM_CLK_PWM3_ROOT>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm4: pwm at 30690000 {
+ compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
+ reg = <0x0 0x30690000 0x0 0x10000>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_PWM4_ROOT>,
+ <&clk IMX8MM_CLK_PWM4_ROOT>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+ };
+
+ aips3: bus at 30800000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x30800000 0x0 0x400000>;
+ ranges;
+
+ ecspi1: ecspi at 30820000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
+ reg = <0x0 0x30820000 0x0 0x10000>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>,
+ <&clk IMX8MM_CLK_ECSPI1_ROOT>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ ecspi2: ecspi at 30830000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
+ reg = <0x0 0x30830000 0x0 0x10000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>,
+ <&clk IMX8MM_CLK_ECSPI2_ROOT>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ ecspi3: ecspi at 30840000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
+ reg = <0x0 0x30840000 0x0 0x10000>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>,
+ <&clk IMX8MM_CLK_ECSPI3_ROOT>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ uart1: serial at 30860000 {
+ compatible = "fsl,imx8mm-uart",
+ "fsl,imx6q-uart", "fsl,imx21-uart";
+ reg = <0x0 0x30860000 0x0 0x10000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_UART1_ROOT>,
+ <&clk IMX8MM_CLK_UART1_ROOT>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ uart3: serial at 30880000 {
+ compatible = "fsl,imx8mm-uart",
+ "fsl,imx6q-uart", "fsl,imx21-uart";
+ reg = <0x0 0x30880000 0x0 0x10000>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_UART3_ROOT>,
+ <&clk IMX8MM_CLK_UART3_ROOT>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ uart2: serial at 30890000 {
+ compatible = "fsl,imx8mm-uart",
+ "fsl,imx6q-uart", "fsl,imx21-uart";
+ reg = <0x0 0x30890000 0x0 0x10000>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_UART2_ROOT>,
+ <&clk IMX8MM_CLK_UART2_ROOT>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ i2c1: i2c at 30a20000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
+ reg = <0x0 0x30a20000 0x0 0x10000>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_I2C1_ROOT>;
+ status = "disabled";
+ };
+
+ i2c2: i2c at 30a30000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
+ reg = <0x0 0x30a30000 0x0 0x10000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_I2C2_ROOT>;
+ status = "disabled";
+ };
+
+ i2c3: i2c at 30a40000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
+ reg = <0x0 0x30a40000 0x0 0x10000>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_I2C3_ROOT>;
+ status = "disabled";
+ };
+
+ i2c4: i2c at 30a50000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
+ reg = <0x0 0x30a50000 0x0 0x10000>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_I2C4_ROOT>;
+ status = "disabled";
+ };
+
+ uart4: serial at 30a60000 {
+ compatible = "fsl,imx8mq-uart",
+ "fsl,imx6q-uart", "fsl,imx21-uart";
+ reg = <0x0 0x30a60000 0x0 0x10000>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_UART4_ROOT>,
+ <&clk IMX8MM_CLK_UART4_ROOT>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ usdhc1: mmc at 30b40000 {
+ compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc";
+ reg = <0x0 0x30b40000 0x0 0x10000>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_DUMMY>,
+ <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
+ <&clk IMX8MM_CLK_USDHC1_ROOT>;
+ clock-names = "ipg", "ahb", "per";
+ assigned-clocks = <&clk IMX8MM_CLK_USDHC1>;
+ assigned-clock-rates = <400000000>;
+ fsl,tuning-start-tap = <20>;
+ fsl,tuning-step= <2>;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ usdhc2: mmc at 30b50000 {
+ compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc";
+ reg = <0x0 0x30b50000 0x0 0x10000>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_DUMMY>,
+ <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
+ <&clk IMX8MM_CLK_USDHC2_ROOT>;
+ clock-names = "ipg", "ahb", "per";
+ fsl,tuning-start-tap = <20>;
+ fsl,tuning-step= <2>;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ usdhc3: mmc at 30b60000 {
+ compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc";
+ reg = <0x0 0x30b60000 0x0 0x10000>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_DUMMY>,
+ <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
+ <&clk IMX8MM_CLK_USDHC3_ROOT>;
+ clock-names = "ipg", "ahb", "per";
+ assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
+ assigned-clock-rates = <400000000>;
+ fsl,tuning-start-tap = <20>;
+ fsl,tuning-step= <2>;
+ bus-width = <4>;
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 35c978e863..f520075875 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -24,8 +24,15 @@ config TARGET_IMX8MQ_EVK
select IMX8MQ
select IMX8M_LPDDR4
+config TARGET_IMX8MM_EVK
+ bool "imx8mm LPDDR4 EVK board"
+ select IMX8MM
+ select SUPPORT_SPL
+ select IMX8M_LPDDR4
+
endchoice
source "board/freescale/imx8mq_evk/Kconfig"
+source "board/freescale/imx8mm_evk/Kconfig"
endif
diff --git a/board/freescale/imx8mm_evk/Kconfig b/board/freescale/imx8mm_evk/Kconfig
new file mode 100644
index 0000000000..299691a619
--- /dev/null
+++ b/board/freescale/imx8mm_evk/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_IMX8MM_EVK
+
+config SYS_BOARD
+ default "imx8mm_evk"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "imx8mm_evk"
+
+endif
diff --git a/board/freescale/imx8mm_evk/MAINTAINERS b/board/freescale/imx8mm_evk/MAINTAINERS
new file mode 100644
index 0000000000..b031bb0674
--- /dev/null
+++ b/board/freescale/imx8mm_evk/MAINTAINERS
@@ -0,0 +1,6 @@
+i.MX8MM EVK BOARD
+M: Peng Fan <peng.fan@nxp.com>
+S: Maintained
+F: board/freescale/imx8mm_evk/
+F: include/configs/imx8mm_evk.h
+F: configs/imx8mm_evk_defconfig
diff --git a/board/freescale/imx8mm_evk/Makefile b/board/freescale/imx8mm_evk/Makefile
new file mode 100644
index 0000000000..1db7b62caf
--- /dev/null
+++ b/board/freescale/imx8mm_evk/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright 2018 NXP
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += imx8mm_evk.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
+endif
diff --git a/board/freescale/imx8mm_evk/imx8mm_evk.c b/board/freescale/imx8mm_evk/imx8mm_evk.c
new file mode 100644
index 0000000000..a681aca04d
--- /dev/null
+++ b/board/freescale/imx8mm_evk/imx8mm_evk.c
@@ -0,0 +1,144 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm-generic/gpio.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include <asm/arch/imx8mm_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/arch/clock.h>
+#include <spl.h>
+#include <asm/mach-imx/dma.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+
+static iomux_v3_cfg_t const uart_pads[] = {
+ IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+ IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+int board_early_init_f(void)
+{
+ struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+ imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+ set_wdog_reset(wdog);
+
+ imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_POSTCLK_INIT
+int board_postclk_init(void)
+{
+ /* TODO */
+ return 0;
+}
+#endif
+
+int dram_init(void)
+{
+ /* rom_pointer[1] contains the size of TEE occupies */
+ if (rom_pointer[1])
+ gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
+ else
+ gd->ram_size = PHYS_SDRAM_SIZE;
+
+ return 0;
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_FEC_MXC
+#define FEC_RST_PAD IMX_GPIO_NR(4, 22)
+static iomux_v3_cfg_t const fec1_rst_pads[] = {
+ IMX8MM_PAD_SAI2_RXC_GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_fec(void)
+{
+ imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
+ ARRAY_SIZE(fec1_rst_pads));
+
+ gpio_request(FEC_RST_PAD, "fec1_rst");
+ gpio_direction_output(FEC_RST_PAD, 0);
+ udelay(500);
+ gpio_direction_output(FEC_RST_PAD, 1);
+}
+
+static int setup_fec(void)
+{
+ struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
+ = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+ setup_iomux_fec();
+
+ /* Use 125M anatop REF_CLK1 for ENET1, not from external */
+ clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
+ IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT, 0);
+ return set_clk_enet(ENET_125MHZ);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ /* enable rgmii rxc skew and phy mode select to RGMII copper */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+ return 0;
+}
+#endif
+
+int board_init(void)
+{
+#ifdef CONFIG_FEC_MXC
+ setup_fec();
+#endif
+ return 0;
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+ return devno - 1;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ env_set("board_name", "EVK");
+ env_set("board_rev", "iMX8MM");
+#endif
+ return 0;
+}
diff --git a/board/freescale/imx8mm_evk/lpddr4_timing.c b/board/freescale/imx8mm_evk/lpddr4_timing.c
new file mode 100644
index 0000000000..4bade5bf74
--- /dev/null
+++ b/board/freescale/imx8mm_evk/lpddr4_timing.c
@@ -0,0 +1,1980 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <linux/kernel.h>
+#include <common.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/lpddr4_define.h>
+
+struct dram_cfg_param lpddr4_ddrc_cfg[] = {
+ /* Start to config, default 3200mbps */
+ { DDRC_DBG1(0), 0x00000001 },
+ { DDRC_PWRCTL(0), 0x00000001 },
+ { DDRC_MSTR(0), 0xa1080020 },
+ { DDRC_RFSHTMG(0), 0x005b00d2 },
+ { DDRC_INIT0(0), 0xC003061B },
+ { DDRC_INIT1(0), 0x009D0000 },
+ { DDRC_INIT3(0), 0x00D4002D },
+ { DDRC_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 },
+ { DDRC_INIT6(0), 0x0066004a },
+ { DDRC_INIT7(0), 0x0006004a },
+
+ { DDRC_DRAMTMG0(0), 0x1A201B22 },
+ { DDRC_DRAMTMG1(0), 0x00060633 },
+ { DDRC_DRAMTMG3(0), 0x00C0C000 },
+ { DDRC_DRAMTMG4(0), 0x0F04080F },
+ { DDRC_DRAMTMG5(0), 0x02040C0C },
+ { DDRC_DRAMTMG6(0), 0x01010007 },
+ { DDRC_DRAMTMG7(0), 0x00000401 },
+ { DDRC_DRAMTMG12(0), 0x00020600 },
+ { DDRC_DRAMTMG13(0), 0x0C100002 },
+ { DDRC_DRAMTMG14(0), 0x000000E6 },
+ { DDRC_DRAMTMG17(0), 0x00A00050 },
+
+ { DDRC_ZQCTL0(0), 0x03200018 },
+ { DDRC_ZQCTL1(0), 0x028061A8 },
+ { DDRC_ZQCTL2(0), 0x00000000 },
+
+ { DDRC_DFITMG0(0), 0x0497820A },
+ { DDRC_DFITMG2(0), 0x0000170A },
+ { DDRC_DRAMTMG2(0), 0x070E171a },
+ { DDRC_DBICTL(0), 0x00000001 },
+
+ { DDRC_DFITMG1(0), 0x00080303 },
+ { DDRC_DFIUPD0(0), 0xE0400018 },
+ { DDRC_DFIUPD1(0), 0x00DF00E4 },
+ { DDRC_DFIUPD2(0), 0x80000000 },
+ { DDRC_DFIMISC(0), 0x00000011 },
+
+ { DDRC_DFIPHYMSTR(0), 0x00000000 },
+ { DDRC_RANKCTL(0), 0x00000c99 },
+
+ /* address mapping */
+ { DDRC_ADDRMAP0(0), 0x0000001f },
+ { DDRC_ADDRMAP1(0), 0x00080808 },
+ { DDRC_ADDRMAP2(0), 0x00000000 },
+ { DDRC_ADDRMAP3(0), 0x00000000 },
+ { DDRC_ADDRMAP4(0), 0x00001f1f },
+ { DDRC_ADDRMAP5(0), 0x07070707 },
+ { DDRC_ADDRMAP6(0), 0x07070707 },
+ { DDRC_ADDRMAP7(0), 0x00000f0f },
+
+ /* performance setting */
+ { DDRC_SCHED(0), 0x29001701 },
+ { DDRC_SCHED1(0), 0x0000002c },
+ { DDRC_PERFHPR1(0), 0x04000030 },
+ { DDRC_PERFLPR1(0), 0x900093e7 },
+ { DDRC_PERFWR1(0), 0x20005574 },
+ { DDRC_PCCFG(0), 0x00000111 },
+ { DDRC_PCFGW_0(0), 0x000072ff },
+ { DDRC_PCFGQOS0_0(0), 0x02100e07 },
+ { DDRC_PCFGQOS1_0(0), 0x00620096 },
+ { DDRC_PCFGWQOS0_0(0), 0x01100e07 },
+ { DDRC_PCFGWQOS1_0(0), 0x00c8012c },
+
+ /* frequency P1&P2 */
+ /* Frequency 1: 400mbps */
+ { DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c },
+ { DDRC_FREQ1_DRAMTMG1(0), 0x00030410 },
+ { DDRC_FREQ1_DRAMTMG2(0), 0x0203090c },
+ { DDRC_FREQ1_DRAMTMG3(0), 0x00505006 },
+ { DDRC_FREQ1_DRAMTMG4(0), 0x05040305 },
+ { DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504 },
+ { DDRC_FREQ1_DRAMTMG6(0), 0x0a060004 },
+ { DDRC_FREQ1_DRAMTMG7(0), 0x0000090e },
+ { DDRC_FREQ1_DRAMTMG14(0), 0x00000032 },
+ { DDRC_FREQ1_DRAMTMG15(0), 0x00000000 },
+ { DDRC_FREQ1_DRAMTMG17(0), 0x0036001b },
+ { DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1 },
+ { DDRC_FREQ1_DFITMG0(0), 0x03818200 },
+ { DDRC_FREQ1_DFITMG2(0), 0x00000000 },
+ { DDRC_FREQ1_RFSHTMG(0), 0x000C001c },
+ { DDRC_FREQ1_INIT3(0), 0x00840000 },
+ { DDRC_FREQ1_INIT4(0), 0x00310000 },
+ { DDRC_FREQ1_INIT6(0), 0x0066004a },
+ { DDRC_FREQ1_INIT7(0), 0x0006004a },
+
+ /* Frequency 2: 100mbps */
+ { DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c },
+ { DDRC_FREQ2_DRAMTMG1(0), 0x00030410 },
+ { DDRC_FREQ2_DRAMTMG2(0), 0x0203090c },
+ { DDRC_FREQ2_DRAMTMG3(0), 0x00505006 },
+ { DDRC_FREQ2_DRAMTMG4(0), 0x05040305 },
+ { DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504 },
+ { DDRC_FREQ2_DRAMTMG6(0), 0x0a060004 },
+ { DDRC_FREQ2_DRAMTMG7(0), 0x0000090e },
+ { DDRC_FREQ2_DRAMTMG14(0), 0x00000032 },
+ { DDRC_FREQ2_DRAMTMG17(0), 0x0036001b },
+ { DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1 },
+ { DDRC_FREQ2_DFITMG0(0), 0x03818200 },
+ { DDRC_FREQ2_DFITMG2(0), 0x00000000 },
+ { DDRC_FREQ2_RFSHTMG(0), 0x0003800c },
+ { DDRC_FREQ2_RFSHTMG(0), 0x00030007 },
+ { DDRC_FREQ2_INIT3(0), 0x00840000 },
+ { DDRC_FREQ2_INIT4(0), 0x00310008 },
+ { DDRC_FREQ2_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 },
+ { DDRC_FREQ2_INIT6(0), 0x0066004a },
+ { DDRC_FREQ2_INIT7(0), 0x0006004a },
+
+ /* boot start point */
+ { DDRC_MSTR2(0), 0x2 }, //DDRC_MSTR2
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
+ { 0x1005f, 0x1ff },
+ { 0x1015f, 0x1ff },
+ { 0x1105f, 0x1ff },
+ { 0x1115f, 0x1ff },
+ { 0x1205f, 0x1ff },
+ { 0x1215f, 0x1ff },
+ { 0x1305f, 0x1ff },
+ { 0x1315f, 0x1ff },
+
+ { 0x11005f, 0x1ff },
+ { 0x11015f, 0x1ff },
+ { 0x11105f, 0x1ff },
+ { 0x11115f, 0x1ff },
+ { 0x11205f, 0x1ff },
+ { 0x11215f, 0x1ff },
+ { 0x11305f, 0x1ff },
+ { 0x11315f, 0x1ff },
+
+ { 0x21005f, 0x1ff },
+ { 0x21015f, 0x1ff },
+ { 0x21105f, 0x1ff },
+ { 0x21115f, 0x1ff },
+ { 0x21205f, 0x1ff },
+ { 0x21215f, 0x1ff },
+ { 0x21305f, 0x1ff },
+ { 0x21315f, 0x1ff },
+
+ { 0x55, 0x1ff },
+ { 0x1055, 0x1ff },
+ { 0x2055, 0x1ff },
+ { 0x3055, 0x1ff },
+ { 0x4055, 0x1ff },
+ { 0x5055, 0x1ff },
+ { 0x6055, 0x1ff },
+ { 0x7055, 0x1ff },
+ { 0x8055, 0x1ff },
+ { 0x9055, 0x1ff },
+
+ { 0x200c5, 0x19 },
+ { 0x1200c5, 0x7 },
+ { 0x2200c5, 0x7 },
+
+ { 0x2002e, 0x2 },
+ { 0x12002e, 0x2 },
+ { 0x22002e, 0x2 },
+
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+
+ { 0x20024, 0xab },
+ { 0x2003a, 0x0 },
+
+ { 0x120024, 0xab },
+ { 0x2003a, 0x0 },
+
+ { 0x220024, 0xab },
+ { 0x2003a, 0x0 },
+
+ { 0x20056, 0x3 },
+ { 0x120056, 0xa },
+ { 0x220056, 0xa },
+
+ { 0x1004d, 0xe00 },
+ { 0x1014d, 0xe00 },
+ { 0x1104d, 0xe00 },
+ { 0x1114d, 0xe00 },
+ { 0x1204d, 0xe00 },
+ { 0x1214d, 0xe00 },
+ { 0x1304d, 0xe00 },
+ { 0x1314d, 0xe00 },
+
+ { 0x11004d, 0xe00 },
+ { 0x11014d, 0xe00 },
+ { 0x11104d, 0xe00 },
+ { 0x11114d, 0xe00 },
+ { 0x11204d, 0xe00 },
+ { 0x11214d, 0xe00 },
+ { 0x11304d, 0xe00 },
+ { 0x11314d, 0xe00 },
+
+ { 0x21004d, 0xe00 },
+ { 0x21014d, 0xe00 },
+ { 0x21104d, 0xe00 },
+ { 0x21114d, 0xe00 },
+ { 0x21204d, 0xe00 },
+ { 0x21214d, 0xe00 },
+ { 0x21304d, 0xe00 },
+ { 0x21314d, 0xe00 },
+
+ { 0x10049, 0xfbe },
+ { 0x10149, 0xfbe },
+ { 0x11049, 0xfbe },
+ { 0x11149, 0xfbe },
+ { 0x12049, 0xfbe },
+ { 0x12149, 0xfbe },
+ { 0x13049, 0xfbe },
+ { 0x13149, 0xfbe },
+
+ { 0x110049, 0xfbe },
+ { 0x110149, 0xfbe },
+ { 0x111049, 0xfbe },
+ { 0x111149, 0xfbe },
+ { 0x112049, 0xfbe },
+ { 0x112149, 0xfbe },
+ { 0x113049, 0xfbe },
+ { 0x113149, 0xfbe },
+
+ { 0x210049, 0xfbe },
+ { 0x210149, 0xfbe },
+ { 0x211049, 0xfbe },
+ { 0x211149, 0xfbe },
+ { 0x212049, 0xfbe },
+ { 0x212149, 0xfbe },
+ { 0x213049, 0xfbe },
+ { 0x213149, 0xfbe },
+
+ { 0x43, 0x63 },
+ { 0x1043, 0x63 },
+ { 0x2043, 0x63 },
+ { 0x3043, 0x63 },
+ { 0x4043, 0x63 },
+ { 0x5043, 0x63 },
+ { 0x6043, 0x63 },
+ { 0x7043, 0x63 },
+ { 0x8043, 0x63 },
+ { 0x9043, 0x63 },
+
+ { 0x20018, 0x3 },
+ { 0x20075, 0x4 },
+ { 0x20050, 0x0 },
+ { 0x20008, 0x2ee },
+ { 0x120008, 0x64 },
+ { 0x220008, 0x19 },
+ { 0x20088, 0x9 },
+
+ { 0x200b2, 0x1d4 },
+ { 0x10043, 0x5a1 },
+ { 0x10143, 0x5a1 },
+ { 0x11043, 0x5a1 },
+ { 0x11143, 0x5a1 },
+ { 0x12043, 0x5a1 },
+ { 0x12143, 0x5a1 },
+ { 0x13043, 0x5a1 },
+ { 0x13143, 0x5a1 },
+
+ { 0x1200b2, 0xdc },
+ { 0x110043, 0x5a1 },
+ { 0x110143, 0x5a1 },
+ { 0x111043, 0x5a1 },
+ { 0x111143, 0x5a1 },
+ { 0x112043, 0x5a1 },
+ { 0x112143, 0x5a1 },
+ { 0x113043, 0x5a1 },
+ { 0x113143, 0x5a1 },
+
+ { 0x2200b2, 0xdc },
+ { 0x210043, 0x5a1 },
+ { 0x210143, 0x5a1 },
+ { 0x211043, 0x5a1 },
+ { 0x211143, 0x5a1 },
+ { 0x212043, 0x5a1 },
+ { 0x212143, 0x5a1 },
+ { 0x213043, 0x5a1 },
+ { 0x213143, 0x5a1 },
+
+ { 0x200fa, 0x1 },
+ { 0x1200fa, 0x1 },
+ { 0x2200fa, 0x1 },
+
+ { 0x20019, 0x1 },
+ { 0x120019, 0x1 },
+ { 0x220019, 0x1 },
+
+ { 0x200f0, 0x660 },
+ { 0x200f1, 0x0 },
+ { 0x200f2, 0x4444 },
+ { 0x200f3, 0x8888 },
+ { 0x200f4, 0x5665 },
+ { 0x200f5, 0x0 },
+ { 0x200f6, 0x0 },
+ { 0x200f7, 0xf000 },
+
+ { 0x20025, 0x0 },
+ { 0x2002d, LPDDR4_PHY_DMIPinPresent },
+ { 0x12002d, LPDDR4_PHY_DMIPinPresent },
+ { 0x22002d, LPDDR4_PHY_DMIPinPresent },
+ { 0x200c7, 0x21 },
+ { 0x200ca, 0x24 },
+ { 0x1200c7, 0x21 },
+ { 0x1200ca, 0x24 },
+ { 0x2200c7, 0x21 },
+ { 0x2200ca, 0x24 },
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param lpddr4_ddrphy_trained_csr[] = {
+ { 0x200b2, 0x0 },
+ { 0x1200b2, 0x0 },
+ { 0x2200b2, 0x0 },
+ { 0x200cb, 0x0 },
+ { 0x10043, 0x0 },
+ { 0x110043, 0x0 },
+ { 0x210043, 0x0 },
+ { 0x10143, 0x0 },
+ { 0x110143, 0x0 },
+ { 0x210143, 0x0 },
+ { 0x11043, 0x0 },
+ { 0x111043, 0x0 },
+ { 0x211043, 0x0 },
+ { 0x11143, 0x0 },
+ { 0x111143, 0x0 },
+ { 0x211143, 0x0 },
+ { 0x12043, 0x0 },
+ { 0x112043, 0x0 },
+ { 0x212043, 0x0 },
+ { 0x12143, 0x0 },
+ { 0x112143, 0x0 },
+ { 0x212143, 0x0 },
+ { 0x13043, 0x0 },
+ { 0x113043, 0x0 },
+ { 0x213043, 0x0 },
+ { 0x13143, 0x0 },
+ { 0x113143, 0x0 },
+ { 0x213143, 0x0 },
+ { 0x80, 0x0 },
+ { 0x100080, 0x0 },
+ { 0x200080, 0x0 },
+ { 0x1080, 0x0 },
+ { 0x101080, 0x0 },
+ { 0x201080, 0x0 },
+ { 0x2080, 0x0 },
+ { 0x102080, 0x0 },
+ { 0x202080, 0x0 },
+ { 0x3080, 0x0 },
+ { 0x103080, 0x0 },
+ { 0x203080, 0x0 },
+ { 0x4080, 0x0 },
+ { 0x104080, 0x0 },
+ { 0x204080, 0x0 },
+ { 0x5080, 0x0 },
+ { 0x105080, 0x0 },
+ { 0x205080, 0x0 },
+ { 0x6080, 0x0 },
+ { 0x106080, 0x0 },
+ { 0x206080, 0x0 },
+ { 0x7080, 0x0 },
+ { 0x107080, 0x0 },
+ { 0x207080, 0x0 },
+ { 0x8080, 0x0 },
+ { 0x108080, 0x0 },
+ { 0x208080, 0x0 },
+ { 0x9080, 0x0 },
+ { 0x109080, 0x0 },
+ { 0x209080, 0x0 },
+ { 0x10080, 0x0 },
+ { 0x110080, 0x0 },
+ { 0x210080, 0x0 },
+ { 0x10180, 0x0 },
+ { 0x110180, 0x0 },
+ { 0x210180, 0x0 },
+ { 0x11080, 0x0 },
+ { 0x111080, 0x0 },
+ { 0x211080, 0x0 },
+ { 0x11180, 0x0 },
+ { 0x111180, 0x0 },
+ { 0x211180, 0x0 },
+ { 0x12080, 0x0 },
+ { 0x112080, 0x0 },
+ { 0x212080, 0x0 },
+ { 0x12180, 0x0 },
+ { 0x112180, 0x0 },
+ { 0x212180, 0x0 },
+ { 0x13080, 0x0 },
+ { 0x113080, 0x0 },
+ { 0x213080, 0x0 },
+ { 0x13180, 0x0 },
+ { 0x113180, 0x0 },
+ { 0x213180, 0x0 },
+ { 0x10081, 0x0 },
+ { 0x110081, 0x0 },
+ { 0x210081, 0x0 },
+ { 0x10181, 0x0 },
+ { 0x110181, 0x0 },
+ { 0x210181, 0x0 },
+ { 0x11081, 0x0 },
+ { 0x111081, 0x0 },
+ { 0x211081, 0x0 },
+ { 0x11181, 0x0 },
+ { 0x111181, 0x0 },
+ { 0x211181, 0x0 },
+ { 0x12081, 0x0 },
+ { 0x112081, 0x0 },
+ { 0x212081, 0x0 },
+ { 0x12181, 0x0 },
+ { 0x112181, 0x0 },
+ { 0x212181, 0x0 },
+ { 0x13081, 0x0 },
+ { 0x113081, 0x0 },
+ { 0x213081, 0x0 },
+ { 0x13181, 0x0 },
+ { 0x113181, 0x0 },
+ { 0x213181, 0x0 },
+ { 0x100d0, 0x0 },
+ { 0x1100d0, 0x0 },
+ { 0x2100d0, 0x0 },
+ { 0x101d0, 0x0 },
+ { 0x1101d0, 0x0 },
+ { 0x2101d0, 0x0 },
+ { 0x110d0, 0x0 },
+ { 0x1110d0, 0x0 },
+ { 0x2110d0, 0x0 },
+ { 0x111d0, 0x0 },
+ { 0x1111d0, 0x0 },
+ { 0x2111d0, 0x0 },
+ { 0x120d0, 0x0 },
+ { 0x1120d0, 0x0 },
+ { 0x2120d0, 0x0 },
+ { 0x121d0, 0x0 },
+ { 0x1121d0, 0x0 },
+ { 0x2121d0, 0x0 },
+ { 0x130d0, 0x0 },
+ { 0x1130d0, 0x0 },
+ { 0x2130d0, 0x0 },
+ { 0x131d0, 0x0 },
+ { 0x1131d0, 0x0 },
+ { 0x2131d0, 0x0 },
+ { 0x100d1, 0x0 },
+ { 0x1100d1, 0x0 },
+ { 0x2100d1, 0x0 },
+ { 0x101d1, 0x0 },
+ { 0x1101d1, 0x0 },
+ { 0x2101d1, 0x0 },
+ { 0x110d1, 0x0 },
+ { 0x1110d1, 0x0 },
+ { 0x2110d1, 0x0 },
+ { 0x111d1, 0x0 },
+ { 0x1111d1, 0x0 },
+ { 0x2111d1, 0x0 },
+ { 0x120d1, 0x0 },
+ { 0x1120d1, 0x0 },
+ { 0x2120d1, 0x0 },
+ { 0x121d1, 0x0 },
+ { 0x1121d1, 0x0 },
+ { 0x2121d1, 0x0 },
+ { 0x130d1, 0x0 },
+ { 0x1130d1, 0x0 },
+ { 0x2130d1, 0x0 },
+ { 0x131d1, 0x0 },
+ { 0x1131d1, 0x0 },
+ { 0x2131d1, 0x0 },
+ { 0x10068, 0x0 },
+ { 0x10168, 0x0 },
+ { 0x10268, 0x0 },
+ { 0x10368, 0x0 },
+ { 0x10468, 0x0 },
+ { 0x10568, 0x0 },
+ { 0x10668, 0x0 },
+ { 0x10768, 0x0 },
+ { 0x10868, 0x0 },
+ { 0x11068, 0x0 },
+ { 0x11168, 0x0 },
+ { 0x11268, 0x0 },
+ { 0x11368, 0x0 },
+ { 0x11468, 0x0 },
+ { 0x11568, 0x0 },
+ { 0x11668, 0x0 },
+ { 0x11768, 0x0 },
+ { 0x11868, 0x0 },
+ { 0x12068, 0x0 },
+ { 0x12168, 0x0 },
+ { 0x12268, 0x0 },
+ { 0x12368, 0x0 },
+ { 0x12468, 0x0 },
+ { 0x12568, 0x0 },
+ { 0x12668, 0x0 },
+ { 0x12768, 0x0 },
+ { 0x12868, 0x0 },
+ { 0x13068, 0x0 },
+ { 0x13168, 0x0 },
+ { 0x13268, 0x0 },
+ { 0x13368, 0x0 },
+ { 0x13468, 0x0 },
+ { 0x13568, 0x0 },
+ { 0x13668, 0x0 },
+ { 0x13768, 0x0 },
+ { 0x13868, 0x0 },
+ { 0x10069, 0x0 },
+ { 0x10169, 0x0 },
+ { 0x10269, 0x0 },
+ { 0x10369, 0x0 },
+ { 0x10469, 0x0 },
+ { 0x10569, 0x0 },
+ { 0x10669, 0x0 },
+ { 0x10769, 0x0 },
+ { 0x10869, 0x0 },
+ { 0x11069, 0x0 },
+ { 0x11169, 0x0 },
+ { 0x11269, 0x0 },
+ { 0x11369, 0x0 },
+ { 0x11469, 0x0 },
+ { 0x11569, 0x0 },
+ { 0x11669, 0x0 },
+ { 0x11769, 0x0 },
+ { 0x11869, 0x0 },
+ { 0x12069, 0x0 },
+ { 0x12169, 0x0 },
+ { 0x12269, 0x0 },
+ { 0x12369, 0x0 },
+ { 0x12469, 0x0 },
+ { 0x12569, 0x0 },
+ { 0x12669, 0x0 },
+ { 0x12769, 0x0 },
+ { 0x12869, 0x0 },
+ { 0x13069, 0x0 },
+ { 0x13169, 0x0 },
+ { 0x13269, 0x0 },
+ { 0x13369, 0x0 },
+ { 0x13469, 0x0 },
+ { 0x13569, 0x0 },
+ { 0x13669, 0x0 },
+ { 0x13769, 0x0 },
+ { 0x13869, 0x0 },
+ { 0x1008c, 0x0 },
+ { 0x11008c, 0x0 },
+ { 0x21008c, 0x0 },
+ { 0x1018c, 0x0 },
+ { 0x11018c, 0x0 },
+ { 0x21018c, 0x0 },
+ { 0x1108c, 0x0 },
+ { 0x11108c, 0x0 },
+ { 0x21108c, 0x0 },
+ { 0x1118c, 0x0 },
+ { 0x11118c, 0x0 },
+ { 0x21118c, 0x0 },
+ { 0x1208c, 0x0 },
+ { 0x11208c, 0x0 },
+ { 0x21208c, 0x0 },
+ { 0x1218c, 0x0 },
+ { 0x11218c, 0x0 },
+ { 0x21218c, 0x0 },
+ { 0x1308c, 0x0 },
+ { 0x11308c, 0x0 },
+ { 0x21308c, 0x0 },
+ { 0x1318c, 0x0 },
+ { 0x11318c, 0x0 },
+ { 0x21318c, 0x0 },
+ { 0x1008d, 0x0 },
+ { 0x11008d, 0x0 },
+ { 0x21008d, 0x0 },
+ { 0x1018d, 0x0 },
+ { 0x11018d, 0x0 },
+ { 0x21018d, 0x0 },
+ { 0x1108d, 0x0 },
+ { 0x11108d, 0x0 },
+ { 0x21108d, 0x0 },
+ { 0x1118d, 0x0 },
+ { 0x11118d, 0x0 },
+ { 0x21118d, 0x0 },
+ { 0x1208d, 0x0 },
+ { 0x11208d, 0x0 },
+ { 0x21208d, 0x0 },
+ { 0x1218d, 0x0 },
+ { 0x11218d, 0x0 },
+ { 0x21218d, 0x0 },
+ { 0x1308d, 0x0 },
+ { 0x11308d, 0x0 },
+ { 0x21308d, 0x0 },
+ { 0x1318d, 0x0 },
+ { 0x11318d, 0x0 },
+ { 0x21318d, 0x0 },
+ { 0x100c0, 0x0 },
+ { 0x1100c0, 0x0 },
+ { 0x2100c0, 0x0 },
+ { 0x101c0, 0x0 },
+ { 0x1101c0, 0x0 },
+ { 0x2101c0, 0x0 },
+ { 0x102c0, 0x0 },
+ { 0x1102c0, 0x0 },
+ { 0x2102c0, 0x0 },
+ { 0x103c0, 0x0 },
+ { 0x1103c0, 0x0 },
+ { 0x2103c0, 0x0 },
+ { 0x104c0, 0x0 },
+ { 0x1104c0, 0x0 },
+ { 0x2104c0, 0x0 },
+ { 0x105c0, 0x0 },
+ { 0x1105c0, 0x0 },
+ { 0x2105c0, 0x0 },
+ { 0x106c0, 0x0 },
+ { 0x1106c0, 0x0 },
+ { 0x2106c0, 0x0 },
+ { 0x107c0, 0x0 },
+ { 0x1107c0, 0x0 },
+ { 0x2107c0, 0x0 },
+ { 0x108c0, 0x0 },
+ { 0x1108c0, 0x0 },
+ { 0x2108c0, 0x0 },
+ { 0x110c0, 0x0 },
+ { 0x1110c0, 0x0 },
+ { 0x2110c0, 0x0 },
+ { 0x111c0, 0x0 },
+ { 0x1111c0, 0x0 },
+ { 0x2111c0, 0x0 },
+ { 0x112c0, 0x0 },
+ { 0x1112c0, 0x0 },
+ { 0x2112c0, 0x0 },
+ { 0x113c0, 0x0 },
+ { 0x1113c0, 0x0 },
+ { 0x2113c0, 0x0 },
+ { 0x114c0, 0x0 },
+ { 0x1114c0, 0x0 },
+ { 0x2114c0, 0x0 },
+ { 0x115c0, 0x0 },
+ { 0x1115c0, 0x0 },
+ { 0x2115c0, 0x0 },
+ { 0x116c0, 0x0 },
+ { 0x1116c0, 0x0 },
+ { 0x2116c0, 0x0 },
+ { 0x117c0, 0x0 },
+ { 0x1117c0, 0x0 },
+ { 0x2117c0, 0x0 },
+ { 0x118c0, 0x0 },
+ { 0x1118c0, 0x0 },
+ { 0x2118c0, 0x0 },
+ { 0x120c0, 0x0 },
+ { 0x1120c0, 0x0 },
+ { 0x2120c0, 0x0 },
+ { 0x121c0, 0x0 },
+ { 0x1121c0, 0x0 },
+ { 0x2121c0, 0x0 },
+ { 0x122c0, 0x0 },
+ { 0x1122c0, 0x0 },
+ { 0x2122c0, 0x0 },
+ { 0x123c0, 0x0 },
+ { 0x1123c0, 0x0 },
+ { 0x2123c0, 0x0 },
+ { 0x124c0, 0x0 },
+ { 0x1124c0, 0x0 },
+ { 0x2124c0, 0x0 },
+ { 0x125c0, 0x0 },
+ { 0x1125c0, 0x0 },
+ { 0x2125c0, 0x0 },
+ { 0x126c0, 0x0 },
+ { 0x1126c0, 0x0 },
+ { 0x2126c0, 0x0 },
+ { 0x127c0, 0x0 },
+ { 0x1127c0, 0x0 },
+ { 0x2127c0, 0x0 },
+ { 0x128c0, 0x0 },
+ { 0x1128c0, 0x0 },
+ { 0x2128c0, 0x0 },
+ { 0x130c0, 0x0 },
+ { 0x1130c0, 0x0 },
+ { 0x2130c0, 0x0 },
+ { 0x131c0, 0x0 },
+ { 0x1131c0, 0x0 },
+ { 0x2131c0, 0x0 },
+ { 0x132c0, 0x0 },
+ { 0x1132c0, 0x0 },
+ { 0x2132c0, 0x0 },
+ { 0x133c0, 0x0 },
+ { 0x1133c0, 0x0 },
+ { 0x2133c0, 0x0 },
+ { 0x134c0, 0x0 },
+ { 0x1134c0, 0x0 },
+ { 0x2134c0, 0x0 },
+ { 0x135c0, 0x0 },
+ { 0x1135c0, 0x0 },
+ { 0x2135c0, 0x0 },
+ { 0x136c0, 0x0 },
+ { 0x1136c0, 0x0 },
+ { 0x2136c0, 0x0 },
+ { 0x137c0, 0x0 },
+ { 0x1137c0, 0x0 },
+ { 0x2137c0, 0x0 },
+ { 0x138c0, 0x0 },
+ { 0x1138c0, 0x0 },
+ { 0x2138c0, 0x0 },
+ { 0x100c1, 0x0 },
+ { 0x1100c1, 0x0 },
+ { 0x2100c1, 0x0 },
+ { 0x101c1, 0x0 },
+ { 0x1101c1, 0x0 },
+ { 0x2101c1, 0x0 },
+ { 0x102c1, 0x0 },
+ { 0x1102c1, 0x0 },
+ { 0x2102c1, 0x0 },
+ { 0x103c1, 0x0 },
+ { 0x1103c1, 0x0 },
+ { 0x2103c1, 0x0 },
+ { 0x104c1, 0x0 },
+ { 0x1104c1, 0x0 },
+ { 0x2104c1, 0x0 },
+ { 0x105c1, 0x0 },
+ { 0x1105c1, 0x0 },
+ { 0x2105c1, 0x0 },
+ { 0x106c1, 0x0 },
+ { 0x1106c1, 0x0 },
+ { 0x2106c1, 0x0 },
+ { 0x107c1, 0x0 },
+ { 0x1107c1, 0x0 },
+ { 0x2107c1, 0x0 },
+ { 0x108c1, 0x0 },
+ { 0x1108c1, 0x0 },
+ { 0x2108c1, 0x0 },
+ { 0x110c1, 0x0 },
+ { 0x1110c1, 0x0 },
+ { 0x2110c1, 0x0 },
+ { 0x111c1, 0x0 },
+ { 0x1111c1, 0x0 },
+ { 0x2111c1, 0x0 },
+ { 0x112c1, 0x0 },
+ { 0x1112c1, 0x0 },
+ { 0x2112c1, 0x0 },
+ { 0x113c1, 0x0 },
+ { 0x1113c1, 0x0 },
+ { 0x2113c1, 0x0 },
+ { 0x114c1, 0x0 },
+ { 0x1114c1, 0x0 },
+ { 0x2114c1, 0x0 },
+ { 0x115c1, 0x0 },
+ { 0x1115c1, 0x0 },
+ { 0x2115c1, 0x0 },
+ { 0x116c1, 0x0 },
+ { 0x1116c1, 0x0 },
+ { 0x2116c1, 0x0 },
+ { 0x117c1, 0x0 },
+ { 0x1117c1, 0x0 },
+ { 0x2117c1, 0x0 },
+ { 0x118c1, 0x0 },
+ { 0x1118c1, 0x0 },
+ { 0x2118c1, 0x0 },
+ { 0x120c1, 0x0 },
+ { 0x1120c1, 0x0 },
+ { 0x2120c1, 0x0 },
+ { 0x121c1, 0x0 },
+ { 0x1121c1, 0x0 },
+ { 0x2121c1, 0x0 },
+ { 0x122c1, 0x0 },
+ { 0x1122c1, 0x0 },
+ { 0x2122c1, 0x0 },
+ { 0x123c1, 0x0 },
+ { 0x1123c1, 0x0 },
+ { 0x2123c1, 0x0 },
+ { 0x124c1, 0x0 },
+ { 0x1124c1, 0x0 },
+ { 0x2124c1, 0x0 },
+ { 0x125c1, 0x0 },
+ { 0x1125c1, 0x0 },
+ { 0x2125c1, 0x0 },
+ { 0x126c1, 0x0 },
+ { 0x1126c1, 0x0 },
+ { 0x2126c1, 0x0 },
+ { 0x127c1, 0x0 },
+ { 0x1127c1, 0x0 },
+ { 0x2127c1, 0x0 },
+ { 0x128c1, 0x0 },
+ { 0x1128c1, 0x0 },
+ { 0x2128c1, 0x0 },
+ { 0x130c1, 0x0 },
+ { 0x1130c1, 0x0 },
+ { 0x2130c1, 0x0 },
+ { 0x131c1, 0x0 },
+ { 0x1131c1, 0x0 },
+ { 0x2131c1, 0x0 },
+ { 0x132c1, 0x0 },
+ { 0x1132c1, 0x0 },
+ { 0x2132c1, 0x0 },
+ { 0x133c1, 0x0 },
+ { 0x1133c1, 0x0 },
+ { 0x2133c1, 0x0 },
+ { 0x134c1, 0x0 },
+ { 0x1134c1, 0x0 },
+ { 0x2134c1, 0x0 },
+ { 0x135c1, 0x0 },
+ { 0x1135c1, 0x0 },
+ { 0x2135c1, 0x0 },
+ { 0x136c1, 0x0 },
+ { 0x1136c1, 0x0 },
+ { 0x2136c1, 0x0 },
+ { 0x137c1, 0x0 },
+ { 0x1137c1, 0x0 },
+ { 0x2137c1, 0x0 },
+ { 0x138c1, 0x0 },
+ { 0x1138c1, 0x0 },
+ { 0x2138c1, 0x0 },
+ { 0x10020, 0x0 },
+ { 0x110020, 0x0 },
+ { 0x210020, 0x0 },
+ { 0x11020, 0x0 },
+ { 0x111020, 0x0 },
+ { 0x211020, 0x0 },
+ { 0x12020, 0x0 },
+ { 0x112020, 0x0 },
+ { 0x212020, 0x0 },
+ { 0x13020, 0x0 },
+ { 0x113020, 0x0 },
+ { 0x213020, 0x0 },
+ { 0x20072, 0x0 },
+ { 0x20073, 0x0 },
+ { 0x20074, 0x0 },
+ { 0x100aa, 0x0 },
+ { 0x110aa, 0x0 },
+ { 0x120aa, 0x0 },
+ { 0x130aa, 0x0 },
+ { 0x20010, 0x0 },
+ { 0x120010, 0x0 },
+ { 0x220010, 0x0 },
+ { 0x20011, 0x0 },
+ { 0x120011, 0x0 },
+ { 0x220011, 0x0 },
+ { 0x100ae, 0x0 },
+ { 0x1100ae, 0x0 },
+ { 0x2100ae, 0x0 },
+ { 0x100af, 0x0 },
+ { 0x1100af, 0x0 },
+ { 0x2100af, 0x0 },
+ { 0x110ae, 0x0 },
+ { 0x1110ae, 0x0 },
+ { 0x2110ae, 0x0 },
+ { 0x110af, 0x0 },
+ { 0x1110af, 0x0 },
+ { 0x2110af, 0x0 },
+ { 0x120ae, 0x0 },
+ { 0x1120ae, 0x0 },
+ { 0x2120ae, 0x0 },
+ { 0x120af, 0x0 },
+ { 0x1120af, 0x0 },
+ { 0x2120af, 0x0 },
+ { 0x130ae, 0x0 },
+ { 0x1130ae, 0x0 },
+ { 0x2130ae, 0x0 },
+ { 0x130af, 0x0 },
+ { 0x1130af, 0x0 },
+ { 0x2130af, 0x0 },
+ { 0x20020, 0x0 },
+ { 0x120020, 0x0 },
+ { 0x220020, 0x0 },
+ { 0x100a0, 0x0 },
+ { 0x100a1, 0x0 },
+ { 0x100a2, 0x0 },
+ { 0x100a3, 0x0 },
+ { 0x100a4, 0x0 },
+ { 0x100a5, 0x0 },
+ { 0x100a6, 0x0 },
+ { 0x100a7, 0x0 },
+ { 0x110a0, 0x0 },
+ { 0x110a1, 0x0 },
+ { 0x110a2, 0x0 },
+ { 0x110a3, 0x0 },
+ { 0x110a4, 0x0 },
+ { 0x110a5, 0x0 },
+ { 0x110a6, 0x0 },
+ { 0x110a7, 0x0 },
+ { 0x120a0, 0x0 },
+ { 0x120a1, 0x0 },
+ { 0x120a2, 0x0 },
+ { 0x120a3, 0x0 },
+ { 0x120a4, 0x0 },
+ { 0x120a5, 0x0 },
+ { 0x120a6, 0x0 },
+ { 0x120a7, 0x0 },
+ { 0x130a0, 0x0 },
+ { 0x130a1, 0x0 },
+ { 0x130a2, 0x0 },
+ { 0x130a3, 0x0 },
+ { 0x130a4, 0x0 },
+ { 0x130a5, 0x0 },
+ { 0x130a6, 0x0 },
+ { 0x130a7, 0x0 },
+ { 0x2007c, 0x0 },
+ { 0x12007c, 0x0 },
+ { 0x22007c, 0x0 },
+ { 0x2007d, 0x0 },
+ { 0x12007d, 0x0 },
+ { 0x22007d, 0x0 },
+ { 0x400fd, 0x0 },
+ { 0x400c0, 0x0 },
+ { 0x90201, 0x0 },
+ { 0x190201, 0x0 },
+ { 0x290201, 0x0 },
+ { 0x90202, 0x0 },
+ { 0x190202, 0x0 },
+ { 0x290202, 0x0 },
+ { 0x90203, 0x0 },
+ { 0x190203, 0x0 },
+ { 0x290203, 0x0 },
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+ { 0x90205, 0x0 },
+ { 0x190205, 0x0 },
+ { 0x290205, 0x0 },
+ { 0x90206, 0x0 },
+ { 0x190206, 0x0 },
+ { 0x290206, 0x0 },
+ { 0x90207, 0x0 },
+ { 0x190207, 0x0 },
+ { 0x290207, 0x0 },
+ { 0x90208, 0x0 },
+ { 0x190208, 0x0 },
+ { 0x290208, 0x0 },
+ { 0x10062, 0x0 },
+ { 0x10162, 0x0 },
+ { 0x10262, 0x0 },
+ { 0x10362, 0x0 },
+ { 0x10462, 0x0 },
+ { 0x10562, 0x0 },
+ { 0x10662, 0x0 },
+ { 0x10762, 0x0 },
+ { 0x10862, 0x0 },
+ { 0x11062, 0x0 },
+ { 0x11162, 0x0 },
+ { 0x11262, 0x0 },
+ { 0x11362, 0x0 },
+ { 0x11462, 0x0 },
+ { 0x11562, 0x0 },
+ { 0x11662, 0x0 },
+ { 0x11762, 0x0 },
+ { 0x11862, 0x0 },
+ { 0x12062, 0x0 },
+ { 0x12162, 0x0 },
+ { 0x12262, 0x0 },
+ { 0x12362, 0x0 },
+ { 0x12462, 0x0 },
+ { 0x12562, 0x0 },
+ { 0x12662, 0x0 },
+ { 0x12762, 0x0 },
+ { 0x12862, 0x0 },
+ { 0x13062, 0x0 },
+ { 0x13162, 0x0 },
+ { 0x13262, 0x0 },
+ { 0x13362, 0x0 },
+ { 0x13462, 0x0 },
+ { 0x13562, 0x0 },
+ { 0x13662, 0x0 },
+ { 0x13762, 0x0 },
+ { 0x13862, 0x0 },
+ { 0x20077, 0x0 },
+ { 0x10001, 0x0 },
+ { 0x11001, 0x0 },
+ { 0x12001, 0x0 },
+ { 0x13001, 0x0 },
+ { 0x10040, 0x0 },
+ { 0x10140, 0x0 },
+ { 0x10240, 0x0 },
+ { 0x10340, 0x0 },
+ { 0x10440, 0x0 },
+ { 0x10540, 0x0 },
+ { 0x10640, 0x0 },
+ { 0x10740, 0x0 },
+ { 0x10840, 0x0 },
+ { 0x10030, 0x0 },
+ { 0x10130, 0x0 },
+ { 0x10230, 0x0 },
+ { 0x10330, 0x0 },
+ { 0x10430, 0x0 },
+ { 0x10530, 0x0 },
+ { 0x10630, 0x0 },
+ { 0x10730, 0x0 },
+ { 0x10830, 0x0 },
+ { 0x11040, 0x0 },
+ { 0x11140, 0x0 },
+ { 0x11240, 0x0 },
+ { 0x11340, 0x0 },
+ { 0x11440, 0x0 },
+ { 0x11540, 0x0 },
+ { 0x11640, 0x0 },
+ { 0x11740, 0x0 },
+ { 0x11840, 0x0 },
+ { 0x11030, 0x0 },
+ { 0x11130, 0x0 },
+ { 0x11230, 0x0 },
+ { 0x11330, 0x0 },
+ { 0x11430, 0x0 },
+ { 0x11530, 0x0 },
+ { 0x11630, 0x0 },
+ { 0x11730, 0x0 },
+ { 0x11830, 0x0 },
+ { 0x12040, 0x0 },
+ { 0x12140, 0x0 },
+ { 0x12240, 0x0 },
+ { 0x12340, 0x0 },
+ { 0x12440, 0x0 },
+ { 0x12540, 0x0 },
+ { 0x12640, 0x0 },
+ { 0x12740, 0x0 },
+ { 0x12840, 0x0 },
+ { 0x12030, 0x0 },
+ { 0x12130, 0x0 },
+ { 0x12230, 0x0 },
+ { 0x12330, 0x0 },
+ { 0x12430, 0x0 },
+ { 0x12530, 0x0 },
+ { 0x12630, 0x0 },
+ { 0x12730, 0x0 },
+ { 0x12830, 0x0 },
+ { 0x13040, 0x0 },
+ { 0x13140, 0x0 },
+ { 0x13240, 0x0 },
+ { 0x13340, 0x0 },
+ { 0x13440, 0x0 },
+ { 0x13540, 0x0 },
+ { 0x13640, 0x0 },
+ { 0x13740, 0x0 },
+ { 0x13840, 0x0 },
+ { 0x13030, 0x0 },
+ { 0x13130, 0x0 },
+ { 0x13230, 0x0 },
+ { 0x13330, 0x0 },
+ { 0x13430, 0x0 },
+ { 0x13530, 0x0 },
+ { 0x13630, 0x0 },
+ { 0x13730, 0x0 },
+ { 0x13830, 0x0 },
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param lpddr4_fsp0_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54000, 0x0 },
+ { 0x54001, 0x0 },
+ { 0x54002, 0x0 },
+ { 0x54003, 0xbb8 },
+ { 0x54004, 0x2 },
+ { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt
+ { 0x54006, LPDDR4_PHY_VREF_VALUE },
+ { 0x54007, 0x0 },
+ { 0x54008, 0x131f },
+ { 0x54009, 0xc8 },
+ { 0x5400a, 0x0 },
+ { 0x5400b, 0x2 },
+ { 0x5400c, 0x0 },
+ { 0x5400d, 0x0 },
+ { 0x5400e, 0x0 },
+ { 0x5400f, 0x0 },
+ { 0x54010, 0x0 },
+ { 0x54011, 0x0 },
+ { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
+ { 0x54013, 0x0 },
+ { 0x54014, 0x0 },
+ { 0x54015, 0x0 },
+ { 0x54016, 0x0 },
+ { 0x54017, 0x0 },
+ { 0x54018, 0x0 },
+ { 0x54019, 0x2dd4 },
+ { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d08 },
+ { 0x5401d, 0x0 },
+ { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
+ { 0x5401f, 0x2dd4 },
+ { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d08 },
+ { 0x54023, 0x0 },
+ { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
+ { 0x54025, 0x0 },
+ { 0x54026, 0x0 },
+ { 0x54027, 0x0 },
+ { 0x54028, 0x0 },
+ { 0x54029, 0x0 },
+ { 0x5402a, 0x0 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, LPDDR4_CS },
+ { 0x5402d, 0x0 },
+ { 0x5402e, 0x0 },
+ { 0x5402f, 0x0 },
+ { 0x54030, 0x0 },
+ { 0x54031, 0x0 },
+ { 0x54032, 0xd400 },
+ { 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x84d },
+ { 0x54036, 0x4d },
+ { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
+ { 0x54038, 0xd400 },
+ { 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x84d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
+ { 0x5403e, 0x0 },
+ { 0x5403f, 0x0 },
+ { 0x54040, 0x0 },
+ { 0x54041, 0x0 },
+ { 0x54042, 0x0 },
+ { 0x54043, 0x0 },
+ { 0x54044, 0x0 },
+ { 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param lpddr4_fsp1_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54000, 0x0 },
+ { 0x54001, 0x0 },
+ { 0x54002, 0x101 },
+ { 0x54003, 0x190 },
+ { 0x54004, 0x2 },
+ { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt
+ { 0x54006, LPDDR4_PHY_VREF_VALUE },
+ { 0x54007, 0x0 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400a, 0x0 },
+ { 0x5400b, 0x2 },
+ { 0x5400c, 0x0 },
+ { 0x5400d, 0x0 },
+ { 0x5400e, 0x0 },
+ { 0x5400f, 0x0 },
+ { 0x54010, 0x0 },
+ { 0x54011, 0x0 },
+ { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
+ { 0x54013, 0x0 },
+ { 0x54014, 0x0 },
+ { 0x54015, 0x0 },
+ { 0x54016, 0x0 },
+ { 0x54017, 0x0 },
+ { 0x54018, 0x0 },
+ { 0x54019, 0x84 },
+ { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d08 },
+ { 0x5401d, 0x0 },
+ { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
+ { 0x5401f, 0x84 },
+ { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d08 },
+ { 0x54023, 0x0 },
+ { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
+ { 0x54025, 0x0 },
+ { 0x54026, 0x0 },
+ { 0x54027, 0x0 },
+ { 0x54028, 0x0 },
+ { 0x54029, 0x0 },
+ { 0x5402a, 0x0 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, LPDDR4_CS },
+ { 0x5402d, 0x0 },
+ { 0x5402e, 0x0 },
+ { 0x5402f, 0x0 },
+ { 0x54030, 0x0 },
+ { 0x54031, 0x0 },
+ { 0x54032, 0x8400 },
+ { 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x84d },
+ { 0x54036, 0x4d },
+ { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
+ { 0x54038, 0x8400 },
+ { 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x84d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
+ { 0x5403e, 0x0 },
+ { 0x5403f, 0x0 },
+ { 0x54040, 0x0 },
+ { 0x54041, 0x0 },
+ { 0x54042, 0x0 },
+ { 0x54043, 0x0 },
+ { 0x54044, 0x0 },
+ { 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param lpddr4_fsp2_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54000, 0x0 },
+ { 0x54001, 0x0 },
+ { 0x54002, 0x102 },
+ { 0x54003, 0x64 },
+ { 0x54004, 0x2 },
+ { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt
+ { 0x54006, LPDDR4_PHY_VREF_VALUE },
+ { 0x54007, 0x0 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400a, 0x0 },
+ { 0x5400b, 0x2 },
+ { 0x5400c, 0x0 },
+ { 0x5400d, 0x0 },
+ { 0x5400e, 0x0 },
+ { 0x5400f, 0x0 },
+ { 0x54010, 0x0 },
+ { 0x54011, 0x0 },
+ { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
+ { 0x54013, 0x0 },
+ { 0x54014, 0x0 },
+ { 0x54015, 0x0 },
+ { 0x54016, 0x0 },
+ { 0x54017, 0x0 },
+ { 0x54018, 0x0 },
+ { 0x54019, 0x84 },
+ { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d08 },
+ { 0x5401d, 0x0 },
+ { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
+ { 0x5401f, 0x84 },
+ { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d08 },
+ { 0x54023, 0x0 },
+ { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
+ { 0x54025, 0x0 },
+ { 0x54026, 0x0 },
+ { 0x54027, 0x0 },
+ { 0x54028, 0x0 },
+ { 0x54029, 0x0 },
+ { 0x5402a, 0x0 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, LPDDR4_CS },
+ { 0x5402d, 0x0 },
+ { 0x5402e, 0x0 },
+ { 0x5402f, 0x0 },
+ { 0x54030, 0x0 },
+ { 0x54031, 0x0 },
+ { 0x54032, 0x8400 },
+ { 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x84d },
+ { 0x54036, 0x4d },
+ { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
+ { 0x54038, 0x8400 },
+ { 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x84d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
+ { 0x5403e, 0x0 },
+ { 0x5403f, 0x0 },
+ { 0x54040, 0x0 },
+ { 0x54041, 0x0 },
+ { 0x54042, 0x0 },
+ { 0x54043, 0x0 },
+ { 0x54044, 0x0 },
+ { 0xd0000, 0x1 },
+};
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54000, 0x0 },
+ { 0x54001, 0x0 },
+ { 0x54002, 0x0 },
+ { 0x54003, 0xbb8 },
+ { 0x54004, 0x2 },
+ { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt
+ { 0x54006, LPDDR4_PHY_VREF_VALUE },
+ { 0x54007, 0x0 },
+ { 0x54008, 0x61 },
+ { 0x54009, 0xc8 },
+ { 0x5400a, 0x0 },
+ { 0x5400b, 0x2 },
+ { 0x5400c, 0x0 },
+ { 0x5400d, 0x0 },
+ { 0x5400e, 0x0 },
+ { 0x5400f, 0x100 },
+ { 0x54010, 0x1f7f },
+ { 0x54011, 0x0 },
+ { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
+ { 0x54013, 0x0 },
+ { 0x54014, 0x0 },
+ { 0x54015, 0x0 },
+ { 0x54016, 0x0 },
+ { 0x54017, 0x0 },
+ { 0x54018, 0x0 },
+ { 0x54019, 0x2dd4 },
+ { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d08 },
+ { 0x5401d, 0x0 },
+ { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
+ { 0x5401f, 0x2dd4 },
+ { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d08 },
+ { 0x54023, 0x0 },
+ { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
+ { 0x54025, 0x0 },
+ { 0x54026, 0x0 },
+ { 0x54027, 0x0 },
+ { 0x54028, 0x0 },
+ { 0x54029, 0x0 },
+ { 0x5402a, 0x0 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, LPDDR4_CS },
+ { 0x5402d, 0x0 },
+ { 0x5402e, 0x0 },
+ { 0x5402f, 0x0 },
+ { 0x54030, 0x0 },
+ { 0x54031, 0x0 },
+ { 0x54032, 0xd400 },
+ { 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x84d },
+ { 0x54036, 0x4d },
+ { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
+ { 0x54038, 0xd400 },
+ { 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x84d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
+ { 0x5403e, 0x0 },
+ { 0x5403f, 0x0 },
+ { 0x54040, 0x0 },
+ { 0x54041, 0x0 },
+ { 0x54042, 0x0 },
+ { 0x54043, 0x0 },
+ { 0x54044, 0x0 },
+ { 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param lpddr4_phy_pie[] = {
+ { 0xd0000, 0x0 },
+ { 0x90000, 0x10 },
+ { 0x90001, 0x400 },
+ { 0x90002, 0x10e },
+ { 0x90003, 0x0 },
+ { 0x90004, 0x0 },
+ { 0x90005, 0x8 },
+ { 0x90029, 0xb },
+ { 0x9002a, 0x480 },
+ { 0x9002b, 0x109 },
+ { 0x9002c, 0x8 },
+ { 0x9002d, 0x448 },
+ { 0x9002e, 0x139 },
+ { 0x9002f, 0x8 },
+ { 0x90030, 0x478 },
+ { 0x90031, 0x109 },
+ { 0x90032, 0x0 },
+ { 0x90033, 0xe8 },
+ { 0x90034, 0x109 },
+ { 0x90035, 0x2 },
+ { 0x90036, 0x10 },
+ { 0x90037, 0x139 },
+ { 0x90038, 0xf },
+ { 0x90039, 0x7c0 },
+ { 0x9003a, 0x139 },
+ { 0x9003b, 0x44 },
+ { 0x9003c, 0x630 },
+ { 0x9003d, 0x159 },
+ { 0x9003e, 0x14f },
+ { 0x9003f, 0x630 },
+ { 0x90040, 0x159 },
+ { 0x90041, 0x47 },
+ { 0x90042, 0x630 },
+ { 0x90043, 0x149 },
+ { 0x90044, 0x4f },
+ { 0x90045, 0x630 },
+ { 0x90046, 0x179 },
+ { 0x90047, 0x8 },
+ { 0x90048, 0xe0 },
+ { 0x90049, 0x109 },
+ { 0x9004a, 0x0 },
+ { 0x9004b, 0x7c8 },
+ { 0x9004c, 0x109 },
+ { 0x9004d, 0x0 },
+ { 0x9004e, 0x1 },
+ { 0x9004f, 0x8 },
+ { 0x90050, 0x0 },
+ { 0x90051, 0x45a },
+ { 0x90052, 0x9 },
+ { 0x90053, 0x0 },
+ { 0x90054, 0x448 },
+ { 0x90055, 0x109 },
+ { 0x90056, 0x40 },
+ { 0x90057, 0x630 },
+ { 0x90058, 0x179 },
+ { 0x90059, 0x1 },
+ { 0x9005a, 0x618 },
+ { 0x9005b, 0x109 },
+ { 0x9005c, 0x40c0 },
+ { 0x9005d, 0x630 },
+ { 0x9005e, 0x149 },
+ { 0x9005f, 0x8 },
+ { 0x90060, 0x4 },
+ { 0x90061, 0x48 },
+ { 0x90062, 0x4040 },
+ { 0x90063, 0x630 },
+ { 0x90064, 0x149 },
+ { 0x90065, 0x0 },
+ { 0x90066, 0x4 },
+ { 0x90067, 0x48 },
+ { 0x90068, 0x40 },
+ { 0x90069, 0x630 },
+ { 0x9006a, 0x149 },
+ { 0x9006b, 0x10 },
+ { 0x9006c, 0x4 },
+ { 0x9006d, 0x18 },
+ { 0x9006e, 0x0 },
+ { 0x9006f, 0x4 },
+ { 0x90070, 0x78 },
+ { 0x90071, 0x549 },
+ { 0x90072, 0x630 },
+ { 0x90073, 0x159 },
+ { 0x90074, 0xd49 },
+ { 0x90075, 0x630 },
+ { 0x90076, 0x159 },
+ { 0x90077, 0x94a },
+ { 0x90078, 0x630 },
+ { 0x90079, 0x159 },
+ { 0x9007a, 0x441 },
+ { 0x9007b, 0x630 },
+ { 0x9007c, 0x149 },
+ { 0x9007d, 0x42 },
+ { 0x9007e, 0x630 },
+ { 0x9007f, 0x149 },
+ { 0x90080, 0x1 },
+ { 0x90081, 0x630 },
+ { 0x90082, 0x149 },
+ { 0x90083, 0x0 },
+ { 0x90084, 0xe0 },
+ { 0x90085, 0x109 },
+ { 0x90086, 0xa },
+ { 0x90087, 0x10 },
+ { 0x90088, 0x109 },
+ { 0x90089, 0x9 },
+ { 0x9008a, 0x3c0 },
+ { 0x9008b, 0x149 },
+ { 0x9008c, 0x9 },
+ { 0x9008d, 0x3c0 },
+ { 0x9008e, 0x159 },
+ { 0x9008f, 0x18 },
+ { 0x90090, 0x10 },
+ { 0x90091, 0x109 },
+ { 0x90092, 0x0 },
+ { 0x90093, 0x3c0 },
+ { 0x90094, 0x109 },
+ { 0x90095, 0x18 },
+ { 0x90096, 0x4 },
+ { 0x90097, 0x48 },
+ { 0x90098, 0x18 },
+ { 0x90099, 0x4 },
+ { 0x9009a, 0x58 },
+ { 0x9009b, 0xa },
+ { 0x9009c, 0x10 },
+ { 0x9009d, 0x109 },
+ { 0x9009e, 0x2 },
+ { 0x9009f, 0x10 },
+ { 0x900a0, 0x109 },
+ { 0x900a1, 0x5 },
+ { 0x900a2, 0x7c0 },
+ { 0x900a3, 0x109 },
+ { 0x900a4, 0x10 },
+ { 0x900a5, 0x10 },
+ { 0x900a6, 0x109 },
+ { 0x40000, 0x811 },
+ { 0x40020, 0x880 },
+ { 0x40040, 0x0 },
+ { 0x40060, 0x0 },
+ { 0x40001, 0x4008 },
+ { 0x40021, 0x83 },
+ { 0x40041, 0x4f },
+ { 0x40061, 0x0 },
+ { 0x40002, 0x4040 },
+ { 0x40022, 0x83 },
+ { 0x40042, 0x51 },
+ { 0x40062, 0x0 },
+ { 0x40003, 0x811 },
+ { 0x40023, 0x880 },
+ { 0x40043, 0x0 },
+ { 0x40063, 0x0 },
+ { 0x40004, 0x720 },
+ { 0x40024, 0xf },
+ { 0x40044, 0x1740 },
+ { 0x40064, 0x0 },
+ { 0x40005, 0x16 },
+ { 0x40025, 0x83 },
+ { 0x40045, 0x4b },
+ { 0x40065, 0x0 },
+ { 0x40006, 0x716 },
+ { 0x40026, 0xf },
+ { 0x40046, 0x2001 },
+ { 0x40066, 0x0 },
+ { 0x40007, 0x716 },
+ { 0x40027, 0xf },
+ { 0x40047, 0x2800 },
+ { 0x40067, 0x0 },
+ { 0x40008, 0x716 },
+ { 0x40028, 0xf },
+ { 0x40048, 0xf00 },
+ { 0x40068, 0x0 },
+ { 0x40009, 0x720 },
+ { 0x40029, 0xf },
+ { 0x40049, 0x1400 },
+ { 0x40069, 0x0 },
+ { 0x4000a, 0xe08 },
+ { 0x4002a, 0xc15 },
+ { 0x4004a, 0x0 },
+ { 0x4006a, 0x0 },
+ { 0x4000b, 0x623 },
+ { 0x4002b, 0x15 },
+ { 0x4004b, 0x0 },
+ { 0x4006b, 0x0 },
+ { 0x4000c, 0x4028 },
+ { 0x4002c, 0x80 },
+ { 0x4004c, 0x0 },
+ { 0x4006c, 0x0 },
+ { 0x4000d, 0xe08 },
+ { 0x4002d, 0xc1a },
+ { 0x4004d, 0x0 },
+ { 0x4006d, 0x0 },
+ { 0x4000e, 0x623 },
+ { 0x4002e, 0x1a },
+ { 0x4004e, 0x0 },
+ { 0x4006e, 0x0 },
+ { 0x4000f, 0x4040 },
+ { 0x4002f, 0x80 },
+ { 0x4004f, 0x0 },
+ { 0x4006f, 0x0 },
+ { 0x40010, 0x2604 },
+ { 0x40030, 0x15 },
+ { 0x40050, 0x0 },
+ { 0x40070, 0x0 },
+ { 0x40011, 0x708 },
+ { 0x40031, 0x5 },
+ { 0x40051, 0x0 },
+ { 0x40071, 0x2002 },
+ { 0x40012, 0x8 },
+ { 0x40032, 0x80 },
+ { 0x40052, 0x0 },
+ { 0x40072, 0x0 },
+ { 0x40013, 0x2604 },
+ { 0x40033, 0x1a },
+ { 0x40053, 0x0 },
+ { 0x40073, 0x0 },
+ { 0x40014, 0x708 },
+ { 0x40034, 0xa },
+ { 0x40054, 0x0 },
+ { 0x40074, 0x2002 },
+ { 0x40015, 0x4040 },
+ { 0x40035, 0x80 },
+ { 0x40055, 0x0 },
+ { 0x40075, 0x0 },
+ { 0x40016, 0x60a },
+ { 0x40036, 0x15 },
+ { 0x40056, 0x1200 },
+ { 0x40076, 0x0 },
+ { 0x40017, 0x61a },
+ { 0x40037, 0x15 },
+ { 0x40057, 0x1300 },
+ { 0x40077, 0x0 },
+ { 0x40018, 0x60a },
+ { 0x40038, 0x1a },
+ { 0x40058, 0x1200 },
+ { 0x40078, 0x0 },
+ { 0x40019, 0x642 },
+ { 0x40039, 0x1a },
+ { 0x40059, 0x1300 },
+ { 0x40079, 0x0 },
+ { 0x4001a, 0x4808 },
+ { 0x4003a, 0x880 },
+ { 0x4005a, 0x0 },
+ { 0x4007a, 0x0 },
+ { 0x900a7, 0x0 },
+ { 0x900a8, 0x790 },
+ { 0x900a9, 0x11a },
+ { 0x900aa, 0x8 },
+ { 0x900ab, 0x7aa },
+ { 0x900ac, 0x2a },
+ { 0x900ad, 0x10 },
+ { 0x900ae, 0x7b2 },
+ { 0x900af, 0x2a },
+ { 0x900b0, 0x0 },
+ { 0x900b1, 0x7c8 },
+ { 0x900b2, 0x109 },
+ { 0x900b3, 0x10 },
+ { 0x900b4, 0x2a8 },
+ { 0x900b5, 0x129 },
+ { 0x900b6, 0x8 },
+ { 0x900b7, 0x370 },
+ { 0x900b8, 0x129 },
+ { 0x900b9, 0xa },
+ { 0x900ba, 0x3c8 },
+ { 0x900bb, 0x1a9 },
+ { 0x900bc, 0xc },
+ { 0x900bd, 0x408 },
+ { 0x900be, 0x199 },
+ { 0x900bf, 0x14 },
+ { 0x900c0, 0x790 },
+ { 0x900c1, 0x11a },
+ { 0x900c2, 0x8 },
+ { 0x900c3, 0x4 },
+ { 0x900c4, 0x18 },
+ { 0x900c5, 0xe },
+ { 0x900c6, 0x408 },
+ { 0x900c7, 0x199 },
+ { 0x900c8, 0x8 },
+ { 0x900c9, 0x8568 },
+ { 0x900ca, 0x108 },
+ { 0x900cb, 0x18 },
+ { 0x900cc, 0x790 },
+ { 0x900cd, 0x16a },
+ { 0x900ce, 0x8 },
+ { 0x900cf, 0x1d8 },
+ { 0x900d0, 0x169 },
+ { 0x900d1, 0x10 },
+ { 0x900d2, 0x8558 },
+ { 0x900d3, 0x168 },
+ { 0x900d4, 0x70 },
+ { 0x900d5, 0x788 },
+ { 0x900d6, 0x16a },
+ { 0x900d7, 0x1ff8 },
+ { 0x900d8, 0x85a8 },
+ { 0x900d9, 0x1e8 },
+ { 0x900da, 0x50 },
+ { 0x900db, 0x798 },
+ { 0x900dc, 0x16a },
+ { 0x900dd, 0x60 },
+ { 0x900de, 0x7a0 },
+ { 0x900df, 0x16a },
+ { 0x900e0, 0x8 },
+ { 0x900e1, 0x8310 },
+ { 0x900e2, 0x168 },
+ { 0x900e3, 0x8 },
+ { 0x900e4, 0xa310 },
+ { 0x900e5, 0x168 },
+ { 0x900e6, 0xa },
+ { 0x900e7, 0x408 },
+ { 0x900e8, 0x169 },
+ { 0x900e9, 0x6e },
+ { 0x900ea, 0x0 },
+ { 0x900eb, 0x68 },
+ { 0x900ec, 0x0 },
+ { 0x900ed, 0x408 },
+ { 0x900ee, 0x169 },
+ { 0x900ef, 0x0 },
+ { 0x900f0, 0x8310 },
+ { 0x900f1, 0x168 },
+ { 0x900f2, 0x0 },
+ { 0x900f3, 0xa310 },
+ { 0x900f4, 0x168 },
+ { 0x900f5, 0x1ff8 },
+ { 0x900f6, 0x85a8 },
+ { 0x900f7, 0x1e8 },
+ { 0x900f8, 0x68 },
+ { 0x900f9, 0x798 },
+ { 0x900fa, 0x16a },
+ { 0x900fb, 0x78 },
+ { 0x900fc, 0x7a0 },
+ { 0x900fd, 0x16a },
+ { 0x900fe, 0x68 },
+ { 0x900ff, 0x790 },
+ { 0x90100, 0x16a },
+ { 0x90101, 0x8 },
+ { 0x90102, 0x8b10 },
+ { 0x90103, 0x168 },
+ { 0x90104, 0x8 },
+ { 0x90105, 0xab10 },
+ { 0x90106, 0x168 },
+ { 0x90107, 0xa },
+ { 0x90108, 0x408 },
+ { 0x90109, 0x169 },
+ { 0x9010a, 0x58 },
+ { 0x9010b, 0x0 },
+ { 0x9010c, 0x68 },
+ { 0x9010d, 0x0 },
+ { 0x9010e, 0x408 },
+ { 0x9010f, 0x169 },
+ { 0x90110, 0x0 },
+ { 0x90111, 0x8b10 },
+ { 0x90112, 0x168 },
+ { 0x90113, 0x0 },
+ { 0x90114, 0xab10 },
+ { 0x90115, 0x168 },
+ { 0x90116, 0x0 },
+ { 0x90117, 0x1d8 },
+ { 0x90118, 0x169 },
+ { 0x90119, 0x80 },
+ { 0x9011a, 0x790 },
+ { 0x9011b, 0x16a },
+ { 0x9011c, 0x18 },
+ { 0x9011d, 0x7aa },
+ { 0x9011e, 0x6a },
+ { 0x9011f, 0xa },
+ { 0x90120, 0x0 },
+ { 0x90121, 0x1e9 },
+ { 0x90122, 0x8 },
+ { 0x90123, 0x8080 },
+ { 0x90124, 0x108 },
+ { 0x90125, 0xf },
+ { 0x90126, 0x408 },
+ { 0x90127, 0x169 },
+ { 0x90128, 0xc },
+ { 0x90129, 0x0 },
+ { 0x9012a, 0x68 },
+ { 0x9012b, 0x9 },
+ { 0x9012c, 0x0 },
+ { 0x9012d, 0x1a9 },
+ { 0x9012e, 0x0 },
+ { 0x9012f, 0x408 },
+ { 0x90130, 0x169 },
+ { 0x90131, 0x0 },
+ { 0x90132, 0x8080 },
+ { 0x90133, 0x108 },
+ { 0x90134, 0x8 },
+ { 0x90135, 0x7aa },
+ { 0x90136, 0x6a },
+ { 0x90137, 0x0 },
+ { 0x90138, 0x8568 },
+ { 0x90139, 0x108 },
+ { 0x9013a, 0xb7 },
+ { 0x9013b, 0x790 },
+ { 0x9013c, 0x16a },
+ { 0x9013d, 0x1f },
+ { 0x9013e, 0x0 },
+ { 0x9013f, 0x68 },
+ { 0x90140, 0x8 },
+ { 0x90141, 0x8558 },
+ { 0x90142, 0x168 },
+ { 0x90143, 0xf },
+ { 0x90144, 0x408 },
+ { 0x90145, 0x169 },
+ { 0x90146, 0xc },
+ { 0x90147, 0x0 },
+ { 0x90148, 0x68 },
+ { 0x90149, 0x0 },
+ { 0x9014a, 0x408 },
+ { 0x9014b, 0x169 },
+ { 0x9014c, 0x0 },
+ { 0x9014d, 0x8558 },
+ { 0x9014e, 0x168 },
+ { 0x9014f, 0x8 },
+ { 0x90150, 0x3c8 },
+ { 0x90151, 0x1a9 },
+ { 0x90152, 0x3 },
+ { 0x90153, 0x370 },
+ { 0x90154, 0x129 },
+ { 0x90155, 0x20 },
+ { 0x90156, 0x2aa },
+ { 0x90157, 0x9 },
+ { 0x90158, 0x0 },
+ { 0x90159, 0x400 },
+ { 0x9015a, 0x10e },
+ { 0x9015b, 0x8 },
+ { 0x9015c, 0xe8 },
+ { 0x9015d, 0x109 },
+ { 0x9015e, 0x0 },
+ { 0x9015f, 0x8140 },
+ { 0x90160, 0x10c },
+ { 0x90161, 0x10 },
+ { 0x90162, 0x8138 },
+ { 0x90163, 0x10c },
+ { 0x90164, 0x8 },
+ { 0x90165, 0x7c8 },
+ { 0x90166, 0x101 },
+ { 0x90167, 0x8 },
+ { 0x90168, 0x0 },
+ { 0x90169, 0x8 },
+ { 0x9016a, 0x8 },
+ { 0x9016b, 0x448 },
+ { 0x9016c, 0x109 },
+ { 0x9016d, 0xf },
+ { 0x9016e, 0x7c0 },
+ { 0x9016f, 0x109 },
+ { 0x90170, 0x0 },
+ { 0x90171, 0xe8 },
+ { 0x90172, 0x109 },
+ { 0x90173, 0x47 },
+ { 0x90174, 0x630 },
+ { 0x90175, 0x109 },
+ { 0x90176, 0x8 },
+ { 0x90177, 0x618 },
+ { 0x90178, 0x109 },
+ { 0x90179, 0x8 },
+ { 0x9017a, 0xe0 },
+ { 0x9017b, 0x109 },
+ { 0x9017c, 0x0 },
+ { 0x9017d, 0x7c8 },
+ { 0x9017e, 0x109 },
+ { 0x9017f, 0x8 },
+ { 0x90180, 0x8140 },
+ { 0x90181, 0x10c },
+ { 0x90182, 0x0 },
+ { 0x90183, 0x1 },
+ { 0x90184, 0x8 },
+ { 0x90185, 0x8 },
+ { 0x90186, 0x4 },
+ { 0x90187, 0x8 },
+ { 0x90188, 0x8 },
+ { 0x90189, 0x7c8 },
+ { 0x9018a, 0x101 },
+ { 0x90006, 0x0 },
+ { 0x90007, 0x0 },
+ { 0x90008, 0x8 },
+ { 0x90009, 0x0 },
+ { 0x9000a, 0x0 },
+ { 0x9000b, 0x0 },
+ { 0xd00e7, 0x400 },
+ { 0x90017, 0x0 },
+ { 0x9001f, 0x2a },
+ { 0x90026, 0x6a },
+ { 0x400d0, 0x0 },
+ { 0x400d1, 0x101 },
+ { 0x400d2, 0x105 },
+ { 0x400d3, 0x107 },
+ { 0x400d4, 0x10f },
+ { 0x400d5, 0x202 },
+ { 0x400d6, 0x20a },
+ { 0x400d7, 0x20b },
+ { 0x2003a, 0x2 },
+ { 0x2000b, 0x5d },
+ { 0x2000c, 0xbb },
+ { 0x2000d, 0x753 },
+ { 0x2000e, 0x2c },
+ { 0x12000b, 0xc },
+ { 0x12000c, 0x19 },
+ { 0x12000d, 0xfa },
+ { 0x12000e, 0x10 },
+ { 0x22000b, 0x3 },
+ { 0x22000c, 0x6 },
+ { 0x22000d, 0x3e },
+ { 0x22000e, 0x10 },
+ { 0x9000c, 0x0 },
+ { 0x9000d, 0x173 },
+ { 0x9000e, 0x60 },
+ { 0x9000f, 0x6110 },
+ { 0x90010, 0x2152 },
+ { 0x90011, 0xdfbd },
+ { 0x90012, 0x60 },
+ { 0x90013, 0x6152 },
+ { 0x20010, 0x5a },
+ { 0x20011, 0x3 },
+ { 0x40080, 0xe0 },
+ { 0x40081, 0x12 },
+ { 0x40082, 0xe0 },
+ { 0x40083, 0x12 },
+ { 0x40084, 0xe0 },
+ { 0x40085, 0x12 },
+ { 0x140080, 0xe0 },
+ { 0x140081, 0x12 },
+ { 0x140082, 0xe0 },
+ { 0x140083, 0x12 },
+ { 0x140084, 0xe0 },
+ { 0x140085, 0x12 },
+ { 0x240080, 0xe0 },
+ { 0x240081, 0x12 },
+ { 0x240082, 0xe0 },
+ { 0x240083, 0x12 },
+ { 0x240084, 0xe0 },
+ { 0x240085, 0x12 },
+ { 0x400fd, 0xf },
+ { 0x10011, 0x1 },
+ { 0x10012, 0x1 },
+ { 0x10013, 0x180 },
+ { 0x10018, 0x1 },
+ { 0x10002, 0x6209 },
+ { 0x100b2, 0x1 },
+ { 0x101b4, 0x1 },
+ { 0x102b4, 0x1 },
+ { 0x103b4, 0x1 },
+ { 0x104b4, 0x1 },
+ { 0x105b4, 0x1 },
+ { 0x106b4, 0x1 },
+ { 0x107b4, 0x1 },
+ { 0x108b4, 0x1 },
+ { 0x11011, 0x1 },
+ { 0x11012, 0x1 },
+ { 0x11013, 0x180 },
+ { 0x11018, 0x1 },
+ { 0x11002, 0x6209 },
+ { 0x110b2, 0x1 },
+ { 0x111b4, 0x1 },
+ { 0x112b4, 0x1 },
+ { 0x113b4, 0x1 },
+ { 0x114b4, 0x1 },
+ { 0x115b4, 0x1 },
+ { 0x116b4, 0x1 },
+ { 0x117b4, 0x1 },
+ { 0x118b4, 0x1 },
+ { 0x12011, 0x1 },
+ { 0x12012, 0x1 },
+ { 0x12013, 0x180 },
+ { 0x12018, 0x1 },
+ { 0x12002, 0x6209 },
+ { 0x120b2, 0x1 },
+ { 0x121b4, 0x1 },
+ { 0x122b4, 0x1 },
+ { 0x123b4, 0x1 },
+ { 0x124b4, 0x1 },
+ { 0x125b4, 0x1 },
+ { 0x126b4, 0x1 },
+ { 0x127b4, 0x1 },
+ { 0x128b4, 0x1 },
+ { 0x13011, 0x1 },
+ { 0x13012, 0x1 },
+ { 0x13013, 0x180 },
+ { 0x13018, 0x1 },
+ { 0x13002, 0x6209 },
+ { 0x130b2, 0x1 },
+ { 0x131b4, 0x1 },
+ { 0x132b4, 0x1 },
+ { 0x133b4, 0x1 },
+ { 0x134b4, 0x1 },
+ { 0x135b4, 0x1 },
+ { 0x136b4, 0x1 },
+ { 0x137b4, 0x1 },
+ { 0x138b4, 0x1 },
+ { 0x2003a, 0x2 },
+ { 0xc0080, 0x2 },
+ { 0xd0000, 0x1 },
+};
+
+struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
+ {
+ /* P0 3000mts 1D */
+ .drate = 3000,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = lpddr4_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg),
+ },
+ {
+ /* P0 3000mts 2D */
+ .drate = 3000,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = lpddr4_fsp0_2d_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg),
+ },
+ {
+ /* P1 400mts 1D */
+ .drate = 400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = lpddr4_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg),
+ },
+ {
+ /* P1 100mts 1D */
+ .drate = 100,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = lpddr4_fsp2_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg),
+ },
+};
+
+/* lpddr4 timing config params on EVK board */
+struct dram_timing_info dram_timing = {
+ .ddrc_cfg = lpddr4_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
+ .ddrphy_cfg = lpddr4_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg),
+ .fsp_msg = lpddr4_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg),
+ .ddrphy_trained_csr = lpddr4_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(lpddr4_ddrphy_trained_csr),
+ .ddrphy_pie = lpddr4_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
+};
diff --git a/board/freescale/imx8mm_evk/spl.c b/board/freescale/imx8mm_evk/spl.c
new file mode 100644
index 0000000000..cf1dfc2c2a
--- /dev/null
+++ b/board/freescale/imx8mm_evk/spl.c
@@ -0,0 +1,187 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/arch/imx8mm_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <power/pmic.h>
+#include <asm/arch/clock.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include <asm/arch/ddr.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void spl_dram_init(void)
+{
+ ddr_init(&dram_timing);
+}
+
+#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 18)
+#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
+
+#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
+ PAD_CTL_PE | PAD_CTL_FSEL2)
+#define USDHC_GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE1)
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+ IMX8MM_PAD_NAND_WE_B_USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MM_PAD_NAND_WP_B_USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MM_PAD_NAND_DATA04_USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MM_PAD_NAND_DATA05_USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MM_PAD_NAND_DATA06_USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MM_PAD_NAND_DATA07_USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MM_PAD_NAND_RE_B_USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MM_PAD_NAND_CE2_B_USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MM_PAD_NAND_CE3_B_USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MM_PAD_NAND_CLE_USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+ IMX8MM_PAD_SD2_CLK_USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MM_PAD_SD2_CMD_USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MM_PAD_SD2_DATA0_USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MM_PAD_SD2_DATA1_USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MM_PAD_SD2_DATA2_USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MM_PAD_SD2_RESET_B_GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
+};
+
+/*
+ * The evk board uses DAT3 to detect CD card plugin,
+ * in u-boot we mux the pin to GPIO when doing board_mmc_getcd.
+ */
+static iomux_v3_cfg_t const usdhc2_cd_pad =
+ IMX8MM_PAD_SD2_DATA3_GPIO2_IO18 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL);
+
+static iomux_v3_cfg_t const usdhc2_dat3_pad =
+ IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 |
+ MUX_PAD_CTRL(USDHC_PAD_CTRL);
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+ {USDHC2_BASE_ADDR, 0, 1},
+ {USDHC3_BASE_ADDR, 0, 1},
+};
+
+int board_mmc_init(bd_t *bis)
+{
+ int i, ret;
+ /*
+ * According to the board_mmc_init() the following map is done:
+ * (U-Boot device node) (Physical Port)
+ * mmc0 USDHC1
+ * mmc1 USDHC2
+ */
+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ switch (i) {
+ case 0:
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
+ ARRAY_SIZE(usdhc2_pads));
+ gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
+ gpio_direction_output(USDHC2_PWR_GPIO, 0);
+ udelay(500);
+ gpio_direction_output(USDHC2_PWR_GPIO, 1);
+ break;
+ case 1:
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ imx_iomux_v3_setup_multiple_pads(usdhc3_pads,
+ ARRAY_SIZE(usdhc3_pads));
+ break;
+ default:
+ printf("USDHC controllers %d not supported \n", i + 1);
+ return -EINVAL;
+ }
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ case USDHC3_BASE_ADDR:
+ ret = 1;
+ break;
+ case USDHC2_BASE_ADDR:
+ imx_iomux_v3_setup_pad(usdhc2_cd_pad);
+ gpio_request(USDHC2_CD_GPIO, "usdhc2 cd");
+ gpio_direction_input(USDHC2_CD_GPIO);
+
+ /*
+ * Since it is the DAT3 pin, this pin is pulled to
+ * low voltage if no card
+ */
+ ret = gpio_get_value(USDHC2_CD_GPIO);
+
+ imx_iomux_v3_setup_pad(usdhc2_dat3_pad);
+ return ret;
+ }
+
+ return 1;
+}
+
+void spl_board_init(void)
+{
+ puts("Normal Boot\n");
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ /* Just empty function now - can't decide what to choose */
+ debug("%s: %s\n", __func__, name);
+
+ return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+ int ret;
+
+ /* Clear global data */
+ memset((void *)gd, 0, sizeof(gd_t));
+
+ arch_cpu_init();
+
+ init_uart_clk(1);
+
+ board_early_init_f();
+
+ timer_init();
+
+ preloader_console_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ ret = spl_init();
+ if (ret) {
+ debug("spl_init() failed: %d\n", ret);
+ hang();
+ }
+
+ enable_tzc380();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ board_init_r(NULL, 0);
+}
diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig
new file mode 100644
index 0000000000..6110f23e38
--- /dev/null
+++ b/configs/imx8mm_evk_defconfig
@@ -0,0 +1,41 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_IMX8MM_EVK=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage.cfg,SPL_TEXT_BASE=0x7E1000"
+CONFIG_DEFAULT_FDT_FILE="fsl-imx8mm-evk.dtb"
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mm-evk"
+CONFIG_DM_GPIO=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
+CONFIG_DM_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_DM_THERMAL=y
diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h
new file mode 100644
index 0000000000..f944308757
--- /dev/null
+++ b/include/configs/imx8mm_evk.h
@@ -0,0 +1,221 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef __IMX8MM_EVK_H
+#define __IMX8MM_EVK_H
+
+#include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>
+
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CSF_SIZE 0x2000 /* 8K region */
+#endif
+
+#define CONFIG_SPL_MAX_SIZE (148 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_UBOOT_BASE \
+ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+
+#ifdef CONFIG_SPL_BUILD
+/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
+#define CONFIG_SPL_STACK 0x91fff0
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_BSS_START_ADDR 0x00910000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
+#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */
+#define CONFIG_SYS_ICACHE_OFF
+#define CONFIG_SYS_DCACHE_OFF
+
+#define CONFIG_MALLOC_F_ADDR 0x912000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
+
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */
+
+#undef CONFIG_DM_MMC
+#undef CONFIG_DM_PMIC
+#undef CONFIG_DM_PMIC_PFUZE100
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+#endif
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_POSTCLK_INIT
+#define CONFIG_BOARD_LATE_INIT
+
+/* Flat Device Tree Definitions */
+#define CONFIG_OF_BOARD_SETUP
+
+#undef CONFIG_CMD_EXPORTENV
+#undef CONFIG_CMD_IMPORTENV
+#undef CONFIG_CMD_IMLS
+
+#undef CONFIG_CMD_CRC32
+#undef CONFIG_BOOTM_NETBSD
+
+/* ENET Config */
+/* ENET1 */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_MII
+#define CONFIG_ETHPRIME "FEC"
+
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_FEC_MXC_PHYADDR 0
+#define FEC_QUIRK_ENET_MAC
+
+#define CONFIG_PHY_GIGE
+#define IMX_FEC_BASE 0x30BE0000
+
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ATHEROS
+#endif
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "script=boot.scr\0" \
+ "image=Image\0" \
+ "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \
+ "fdt_addr=0x43000000\0" \
+ "fdt_high=0xffffffffffffffff\0" \
+ "boot_fdt=try\0" \
+ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ "initrd_addr=0x43800000\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+ "mmcautodetect=yes\0" \
+ "mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \
+ "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source\0" \
+ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if run loadfdt; then " \
+ "booti ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "else " \
+ "echo wait for boot; " \
+ "fi;\0" \
+ "netargs=setenv bootargs ${jh_clk} console=${console} " \
+ "root=/dev/nfs " \
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+ "netboot=echo Booting from net ...; " \
+ "run netargs; " \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "${get_cmd} ${loadaddr} ${image}; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+ "booti ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "else " \
+ "booti; " \
+ "fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev}; if mmc rescan; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loadimage; then " \
+ "run mmcboot; " \
+ "else run netboot; " \
+ "fi; " \
+ "fi; " \
+ "else booti ${loadaddr} - ${fdt_addr}; fi"
+
+/* Link Definitions */
+#define CONFIG_LOADADDR 0x40480000
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_ENV_OVERWRITE
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_ENV_OFFSET (64 * SZ_64K)
+#endif
+#define CONFIG_ENV_SIZE 0x1000
+#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC2 */
+#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN SZ_32M
+
+#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define PHYS_SDRAM 0x40000000
+#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
+
+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1))
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
+
+/* Monitor Command Prompt */
+#undef CONFIG_SYS_PROMPT
+#define CONFIG_SYS_PROMPT "u-boot=> "
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_CBSIZE 2048
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+
+#define CONFIG_IMX_BOOTAUX
+
+/* USDHC */
+#define CONFIG_CMD_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+
+#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
+#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
+
+#define CONFIG_MXC_OCOTP
+#define CONFIG_CMD_FUSE
+
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_SPEED 100000
+
+#define CONFIG_OF_SYSTEM_SETUP
+
+#endif
--
2.14.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* [U-Boot] [PATCH 20/20] imx: add i.MX8MM EVK board support
2019-01-28 9:43 ` [U-Boot] [PATCH 20/20] imx: add i.MX8MM EVK board support Peng Fan
@ 2019-01-29 23:18 ` Lukasz Majewski
2019-01-30 5:49 ` Peng Fan
0 siblings, 1 reply; 39+ messages in thread
From: Lukasz Majewski @ 2019-01-29 23:18 UTC (permalink / raw)
To: u-boot
Hi Peng,
> Add i.MX8MM EVK board support.
>
> Add board and SoC dts
> Add ddr training code
> support SD/MMC/GPIO/PINCTRL/UART
>
> U-Boot SPL 2019.01-00148-g1179cffe66 (Jan 28 2019 - 17:37:34 +0800)
> Normal Boot
> Trying to boot from MMC1
>
> U-Boot 2019.01-00148-g1179cffe66 (Jan 28 2019 - 17:37:34 +0800)
>
> CPU: Freescale i.MX8MMQ rev1.0 at 1200 MHz
> Reset cause: POR
> Model: NXP i.MX8MM EVK board
> DRAM: 2 GiB
> MMC: FSL_SDHC: 1, FSL_SDHC: 2
> In: serial
> Out: serial
> Err: serial
> DM
You set/adjust latter in the code the fec network driver. Why it is not
found?
Could you also share the output of "dm tree" command?
I suppose/guess that this board shall support as much as possible of
the DT/DM conversions?
> Hit any key to stop autoboot: 2
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> arch/arm/dts/fsl-imx8mm-evk.dts | 203 +++
> arch/arm/dts/fsl-imx8mm.dtsi | 586 ++++++++
> arch/arm/mach-imx/imx8m/Kconfig | 7 +
> board/freescale/imx8mm_evk/Kconfig | 12 +
> board/freescale/imx8mm_evk/MAINTAINERS | 6 +
> board/freescale/imx8mm_evk/Makefile | 12 +
> board/freescale/imx8mm_evk/imx8mm_evk.c | 144 ++
> board/freescale/imx8mm_evk/lpddr4_timing.c | 1980
> ++++++++++++++++++++++++++++
> board/freescale/imx8mm_evk/spl.c | 187 +++
> configs/imx8mm_evk_defconfig | 41 +
> include/configs/imx8mm_evk.h | 221 ++++ 11 files
> changed, 3399 insertions(+) create mode 100644
> arch/arm/dts/fsl-imx8mm-evk.dts create mode 100644
> arch/arm/dts/fsl-imx8mm.dtsi create mode 100644
> board/freescale/imx8mm_evk/Kconfig create mode 100644
> board/freescale/imx8mm_evk/MAINTAINERS create mode 100644
> board/freescale/imx8mm_evk/Makefile create mode 100644
> board/freescale/imx8mm_evk/imx8mm_evk.c create mode 100644
> board/freescale/imx8mm_evk/lpddr4_timing.c create mode 100644
> board/freescale/imx8mm_evk/spl.c create mode 100644
> configs/imx8mm_evk_defconfig create mode 100644
> include/configs/imx8mm_evk.h
>
> diff --git a/arch/arm/dts/fsl-imx8mm-evk.dts
> b/arch/arm/dts/fsl-imx8mm-evk.dts new file mode 100644
> index 0000000000..df409eca47
> --- /dev/null
> +++ b/arch/arm/dts/fsl-imx8mm-evk.dts
> @@ -0,0 +1,203 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019 NXP
> + */
> +
> +/dts-v1/;
> +
> +#include "fsl-imx8mm.dtsi"
> +
> +/ {
> + model = "NXP i.MX8MM EVK board";
> + compatible = "fsl,imx8mm-evk", "fsl,imx8mm";
> +
> + chosen {
> + stdout-path = &uart2;
> + };
> +
> + regulators {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + reg_usdhc2_vmmc: regulator-usdhc2 {
> + compatible = "regulator-fixed";
> + regulator-name = "VSD_3V3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
> + off-on-delay = <20000>;
> + enable-active-high;
> + };
> + };
> +};
> +
> +&iomuxc {
> + pinctrl-names = "default";
> +
> + imx8mm-evk {
> + pinctrl_fec1: fec1grp {
> + fsl,pins = <
> +
> MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
> +
> MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
> +
> MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
> +
> MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
> +
> MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
> +
> MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
> +
> MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
> +
> MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
> +
> MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
> +
> MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
> +
> MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
> +
> MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
> +
> MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
> +
> MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
> +
> MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
> + >;
> + };
> +
> + pinctrl_gpio_led: gpioledgrp {
> + fsl,pins = <
> +
> MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
> + >;
> + };
> +
> + pinctrl_uart2: uart2grp {
> + fsl,pins = <
> +
> MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
> +
> MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
> + >;
> + };
> +
> + pinctrl_usdhc2_gpio: usdhc2grpgpio {
> + fsl,pins = <
> +
> MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
> +
> MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
> + >;
> + };
> +
> + pinctrl_usdhc2: usdhc2grp {
> + fsl,pins = <
> +
> MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
> +
> MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
> +
> MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
> +
> MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
> +
> MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
> +
> MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
> +
> MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
> + >;
> + };
> +
> + pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
> + fsl,pins = <
> +
> MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
> +
> MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
> +
> MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
> +
> MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
> +
> MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
> +
> MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
> +
> MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
> + >;
> + };
> +
> + pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
> + fsl,pins = <
> +
> MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
> +
> MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
> +
> MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
> +
> MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
> +
> MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
> +
> MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
> +
> MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
> + >;
> + };
> +
> + pinctrl_usdhc3: usdhc3grp {
> + fsl,pins = <
> +
> MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
> +
> MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
> +
> MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
> +
> MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
> +
> MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
> +
> MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
> +
> MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
> +
> MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
> +
> MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
> +
> MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
> +
> MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
> + >;
> + };
> +
> + pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
> + fsl,pins = <
> +
> MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
> +
> MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
> +
> MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
> +
> MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
> +
> MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
> +
> MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
> +
> MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
> +
> MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
> +
> MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
> +
> MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
> +
> MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
> + >;
> + };
> +
> + pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
> + fsl,pins = <
> +
> MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
> +
> MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
> +
> MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
> +
> MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
> +
> MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
> +
> MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
> +
> MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
> +
> MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
> +
> MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
> +
> MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
> +
> MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
> + >;
> + };
> +
> + pinctrl_wdog: wdoggrp {
> + fsl,pins = <
> +
> MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
> + >;
> + };
> + };
> +};
> +
> +&uart2 { /* console */
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart2>;
> + status = "okay";
> +};
> +
> +&usdhc2 {
> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
> + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
> + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
> + cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
> + bus-width = <4>;
> + vmmc-supply = <®_usdhc2_vmmc>;
> + status = "okay";
> +};
> +
> +&usdhc3 {
> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> + pinctrl-0 = <&pinctrl_usdhc3>;
> + pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
> + pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
> + bus-width = <8>;
> + non-removable;
> + status = "okay";
> +};
> +
> +&wdog1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_wdog>;
> + fsl,ext-reset-output;
> + status = "okay";
> +};
> diff --git a/arch/arm/dts/fsl-imx8mm.dtsi
> b/arch/arm/dts/fsl-imx8mm.dtsi new file mode 100644
> index 0000000000..8a808f856d
> --- /dev/null
> +++ b/arch/arm/dts/fsl-imx8mm.dtsi
> @@ -0,0 +1,586 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2017-2019 NXP
> + */
> +
> +#include <dt-bindings/clock/imx8mm-clock.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/pinctrl/pins-imx8mm.h>
> +#include <dt-bindings/thermal/thermal.h>
> +
> +/ {
> + compatible = "fsl,imx8mm";
> + interrupt-parent = <&gic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + aliases {
> + i2c0 = &i2c1;
> + i2c1 = &i2c2;
> + i2c2 = &i2c3;
> + i2c3 = &i2c4;
> + serial0 = &uart1;
> + serial1 = &uart2;
> + serial2 = &uart3;
> + serial3 = &uart4;
> + spi0 = &ecspi1;
> + spi1 = &ecspi2;
> + spi2 = &ecspi3;
> + mmc0 = &usdhc1;
> + mmc1 = &usdhc2;
> + mmc2 = &usdhc3;
> + gpio0 = &gpio1;
> + gpio1 = &gpio2;
> + gpio2 = &gpio3;
> + gpio3 = &gpio4;
> + gpio4 = &gpio5;
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + A53_0: cpu at 0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x0>;
> + enable-method = "psci";
> + next-level-cache = <&A53_L2>;
> + };
> +
> + A53_1: cpu at 1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1>;
> + enable-method = "psci";
> + next-level-cache = <&A53_L2>;
> + };
> +
> + A53_2: cpu at 2 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x2>;
> + enable-method = "psci";
> + next-level-cache = <&A53_L2>;
> + };
> +
> + A53_3: cpu at 3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x3>;
> + enable-method = "psci";
> + next-level-cache = <&A53_L2>;
> + };
> +
> + A53_L2: l2-cache0 {
> + compatible = "cache";
> + };
> + };
> +
> + memory at 40000000 {
> + device_type = "memory";
> + reg = <0x0 0x40000000 0 0x80000000>;
> + };
> +
> + clocks {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + osc_32k: clock at 0 {
> + compatible = "fixed-clock";
> + reg = <0>;
> + #clock-cells = <0>;
> + clock-frequency = <32768>;
> + clock-output-names = "osc_32k";
> + };
> +
> + osc_24m: clock at 1 {
> + compatible = "fixed-clock";
> + reg = <1>;
> + #clock-cells = <0>;
> + clock-frequency = <24000000>;
> + clock-output-names = "osc_24m";
> + };
> +
> + clk_ext1: clock at 2 {
> + compatible = "fixed-clock";
> + reg = <3>;
> + #clock-cells = <0>;
> + clock-frequency = <133000000>;
> + clock-output-names = "clk_ext1";
> + };
> +
> + clk_ext2: clock at 3 {
> + compatible = "fixed-clock";
> + reg = <4>;
> + #clock-cells = <0>;
> + clock-frequency = <133000000>;
> + clock-output-names = "clk_ext2";
> + };
> +
> + clk_ext3: clock at 4 {
> + compatible = "fixed-clock";
> + reg = <5>;
> + #clock-cells = <0>;
> + clock-frequency = <133000000>;
> + clock-output-names = "clk_ext3";
> + };
> +
> + clk_ext4: clock at 5 {
> + compatible = "fixed-clock";
> + reg = <6>;
> + #clock-cells = <0>;
> + clock-frequency= <133000000>;
> + clock-output-names = "clk_ext4";
> + };
> + };
> +
> + gic: interrupt-controller at 38800000 {
> + compatible = "arm,gic-v3";
> + reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */
> + <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base +
> SGI_base) */
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> +
> + pmu {
> + compatible = "arm,armv8-pmuv3";
> + interrupts = <GIC_PPI 7
> + (GIC_CPU_MASK_SIMPLE(6) |
> IRQ_TYPE_LEVEL_HIGH)>;
> + interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>,
> <&A53_3>;
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) |
> IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) |
> IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) |
> IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) |
> IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
> + clock-frequency = <8000000>;
> + arm,no-tick-in-suspend;
> + };
> +
> + soc at 0 {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + aips1: bus at 30000000 {
> + compatible = "fsl,aips-bus", "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x30000000 0x0 0x400000>;
> + ranges;
> +
> + gpio1: gpio at 30200000 {
> + compatible = "fsl,imx8mm-gpio",
> "fsl,imx35-gpio";
> + reg = <0x0 0x30200000 0x0 0x10000>;
> + interrupts = <GIC_SPI 64
> IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 65
> IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpio2: gpio at 30210000 {
> + compatible = "fsl,imx8mm-gpio",
> "fsl,imx35-gpio";
> + reg = <0x0 0x30210000 0x0 0x10000>;
> + interrupts = <GIC_SPI 66
> IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 67
> IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpio3: gpio at 30220000 {
> + compatible = "fsl,imx8mm-gpio",
> "fsl,imx35-gpio";
> + reg = <0x0 0x30220000 0x0 0x10000>;
> + interrupts = <GIC_SPI 68
> IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 69
> IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpio4: gpio at 30230000 {
> + compatible = "fsl,imx8mm-gpio",
> "fsl,imx35-gpio";
> + reg = <0x0 0x30230000 0x0 0x10000>;
> + interrupts = <GIC_SPI 70
> IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 71
> IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpio5: gpio at 30240000 {
> + compatible = "fsl,imx8mm-gpio",
> "fsl,imx35-gpio";
> + reg = <0x0 0x30240000 0x0 0x10000>;
> + interrupts = <GIC_SPI 72
> IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 73
> IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + wdog1: wdog at 30280000 {
> + compatible = "fsl,imx21-wdt";
> + reg = <0 0x30280000 0 0x10000>;
> + interrupts = <GIC_SPI 78
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk
> IMX8MM_CLK_WDOG1_ROOT>;
> + status = "disabled";
> + };
> +
> + wdog2: wdog at 30290000 {
> + compatible = "fsl,imx21-wdt";
> + reg = <0 0x30290000 0 0x10000>;
> + interrupts = <GIC_SPI 79
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk
> IMX8MM_CLK_WDOG2_ROOT>;
> + status = "disabled";
> + };
> +
> + wdog3: wdog at 302a0000 {
> + compatible = "fsl,imx21-wdt";
> + reg = <0 0x302a0000 0 0x10000>;
> + interrupts = <GIC_SPI 10
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk
> IMX8MM_CLK_WDOG3_ROOT>;
> + status = "disabled";
> + };
> +
> + sdma2: dma-controller at 302c0000 {
> + compatible = "fsl,imx8mq-sdma",
> "fsl,imx7d-sdma";
> + reg = <0x0 0x302c0000 0x0 0x10000>;
> + interrupts = <GIC_SPI 103
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk
> IMX8MM_CLK_SDMA2_ROOT>,
> + <&clk
> IMX8MM_CLK_SDMA2_ROOT>;
> + clock-names = "ipg", "ahb";
> + #dma-cells = <3>;
> + fsl,sdma-ram-script-name =
> "imx/sdma/sdma-imx7d.bin";
> + fsl,ratio-1-1;
> + status = "okay";
> + };
> +
> + sdma3: dma-controller at 302b0000 {
> + compatible = "fsl,imx8mq-sdma",
> "fsl,imx7d-sdma";
> + reg = <0x0 0x302b0000 0x0 0x10000>;
> + interrupts = <GIC_SPI 34
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk
> IMX8MM_CLK_SDMA3_ROOT>,
> + <&clk IMX8MM_CLK_SDMA3_ROOT>;
> + clock-names = "ipg", "ahb";
> + #dma-cells = <3>;
> + fsl,sdma-ram-script-name =
> "imx/sdma/sdma-imx7d.bin";
> + fsl,ratio-1-1;
> + status = "okay";
> + };
> +
> + iomuxc: pinctrl at 30330000 {
> + compatible = "fsl,imx8mm-iomuxc";
> + reg = <0x0 0x30330000 0x0 0x10000>;
> + };
> +
> + gpr: iomuxc-gpr at 30340000 {
> + compatible =
> "fsl,imx8mm-iomuxc-gpr", "syscon";
> + reg = <0x0 0x30340000 0x0 0x10000>;
> + };
> +
> + ocotp: ocotp-ctrl at 30350000 {
> + compatible = "fsl,imx8mq-ocotp",
> "fsl,imx7d-ocotp", "syscon";
> + reg = <0 0x30350000 0 0x10000>;
> + clocks = <&clk
> IMX8MM_CLK_OCOTP_ROOT>;
> + /* For nvmem subnodes */
> + #address-cells = <1>;
> + #size-cells = <1>;
> + };
> +
> + anatop: anatop at 30360000 {
> + compatible = "fsl,imx8mm-anatop",
> "syscon", "simple-bus";
> + reg = <0x0 0x30360000 0x0 0x10000>;
> + };
> +
> + snvs: snvs at 30370000 {
> + compatible =
> "fsl,sec-v4.0-mon","syscon", "simple-mfd";
> + reg = <0x0 0x30370000 0x0 0x10000>;
> +
> + snvs_rtc: snvs-rtc-lp{
> + compatible =
> "fsl,sec-v4.0-mon-rtc-lp";
> + regmap =<&snvs>;
> + offset = <0x34>;
> + interrupts = <GIC_SPI 19
> IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 20
> IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + snvs_pwrkey: snvs-powerkey {
> + compatible =
> "fsl,sec-v4.0-pwrkey";
> + regmap = <&snvs>;
> + interrupts = <GIC_SPI 4
> IRQ_TYPE_LEVEL_HIGH>;
> + linux,keycode = <KEY_POWER>;
> + wakeup-source;
> + };
> + };
> +
> + clk: clock-controller at 30380000 {
> + compatible = "fsl,imx8mm-ccm";
> + reg = <0x0 0x30380000 0x0 0x10000>;
> + #clock-cells = <1>;
> + clocks = <&osc_32k>, <&osc_24m>,
> <&clk_ext1>, <&clk_ext2>,
> + <&clk_ext3>, <&clk_ext4>;
> + clock-names = "osc_32k", "osc_24m",
> "clk_ext1", "clk_ext2",
> + "clk_ext3", "clk_ext4";
> + };
> +
> + src: src at 30390000 {
> + compatible = "fsl,imx8mm-src",
> "syscon";
> + reg = <0x0 0x30390000 0x0 0x10000>;
> + interrupts = <GIC_SPI 89
> IRQ_TYPE_LEVEL_HIGH>;
> + #reset-cells = <1>;
> + };
> +
> + gpc: gpc at 303a0000 {
> + compatible = "fsl,imx8mm-gpc",
> "syscon";
> + reg = <0x0 0x303a0000 0x0 0x10000>;
> + interrupt-controller;
> + interrupts = <GIC_SPI 87
> IRQ_TYPE_LEVEL_HIGH>;
> + #interrupt-cells = <3>;
> + };
> + };
> +
> + aips2: bus at 30400000 {
> + compatible = "fsl,aips-bus", "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x30400000 0x0 0x400000>;
> + ranges;
> +
> + pwm1: pwm at 30660000 {
> + compatible = "fsl,imx8mm-pwm",
> "fsl,imx27-pwm";
> + reg = <0x0 0x30660000 0x0 0x10000>;
> + interrupts = <GIC_SPI 81
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MM_CLK_PWM1_ROOT>,
> + <&clk IMX8MM_CLK_PWM1_ROOT>;
> + clock-names = "ipg", "per";
> + #pwm-cells = <2>;
> + status = "disabled";
> + };
> +
> + pwm2: pwm at 30670000 {
> + compatible = "fsl,imx8mm-pwm",
> "fsl,imx27-pwm";
> + reg = <0x0 0x30670000 0x0 0x10000>;
> + interrupts = <GIC_SPI 82
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MM_CLK_PWM2_ROOT>,
> + <&clk IMX8MM_CLK_PWM2_ROOT>;
> + clock-names = "ipg", "per";
> + #pwm-cells = <2>;
> + status = "disabled";
> + };
> +
> + pwm3: pwm at 30680000 {
> + compatible = "fsl,imx8mm-pwm",
> "fsl,imx27-pwm";
> + reg = <0x0 0x30680000 0x0 0x10000>;
> + interrupts = <GIC_SPI 83
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MM_CLK_PWM3_ROOT>,
> + <&clk IMX8MM_CLK_PWM3_ROOT>;
> + clock-names = "ipg", "per";
> + #pwm-cells = <2>;
> + status = "disabled";
> + };
> +
> + pwm4: pwm at 30690000 {
> + compatible = "fsl,imx8mm-pwm",
> "fsl,imx27-pwm";
> + reg = <0x0 0x30690000 0x0 0x10000>;
> + interrupts = <GIC_SPI 84
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MM_CLK_PWM4_ROOT>,
> + <&clk IMX8MM_CLK_PWM4_ROOT>;
> + clock-names = "ipg", "per";
> + #pwm-cells = <2>;
> + status = "disabled";
> + };
> + };
> +
> + aips3: bus at 30800000 {
> + compatible = "fsl,aips-bus", "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x30800000 0x0 0x400000>;
> + ranges;
> +
> + ecspi1: ecspi at 30820000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,imx8mm-ecspi",
> "fsl,imx51-ecspi";
> + reg = <0x0 0x30820000 0x0 0x10000>;
> + interrupts = <GIC_SPI 31
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk
> IMX8MM_CLK_ECSPI1_ROOT>,
> + <&clk
> IMX8MM_CLK_ECSPI1_ROOT>;
> + clock-names = "ipg", "per";
> + status = "disabled";
> + };
> +
> + ecspi2: ecspi at 30830000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,imx8mm-ecspi",
> "fsl,imx51-ecspi";
> + reg = <0x0 0x30830000 0x0 0x10000>;
> + interrupts = <GIC_SPI 32
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk
> IMX8MM_CLK_ECSPI2_ROOT>,
> + <&clk
> IMX8MM_CLK_ECSPI2_ROOT>;
> + clock-names = "ipg", "per";
> + status = "disabled";
> + };
> +
> + ecspi3: ecspi at 30840000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,imx8mm-ecspi",
> "fsl,imx51-ecspi";
> + reg = <0x0 0x30840000 0x0 0x10000>;
> + interrupts = <GIC_SPI 33
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk
> IMX8MM_CLK_ECSPI3_ROOT>,
> + <&clk
> IMX8MM_CLK_ECSPI3_ROOT>;
> + clock-names = "ipg", "per";
> + status = "disabled";
> + };
> +
> + uart1: serial at 30860000 {
> + compatible = "fsl,imx8mm-uart",
> + "fsl,imx6q-uart",
> "fsl,imx21-uart";
> + reg = <0x0 0x30860000 0x0 0x10000>;
> + interrupts = <GIC_SPI 26
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk
> IMX8MM_CLK_UART1_ROOT>,
> + <&clk
> IMX8MM_CLK_UART1_ROOT>;
> + clock-names = "ipg", "per";
> + status = "disabled";
> + };
> +
> + uart3: serial at 30880000 {
> + compatible = "fsl,imx8mm-uart",
> + "fsl,imx6q-uart",
> "fsl,imx21-uart";
> + reg = <0x0 0x30880000 0x0 0x10000>;
> + interrupts = <GIC_SPI 28
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk
> IMX8MM_CLK_UART3_ROOT>,
> + <&clk
> IMX8MM_CLK_UART3_ROOT>;
> + clock-names = "ipg", "per";
> + status = "disabled";
> + };
> +
> + uart2: serial at 30890000 {
> + compatible = "fsl,imx8mm-uart",
> + "fsl,imx6q-uart",
> "fsl,imx21-uart";
> + reg = <0x0 0x30890000 0x0 0x10000>;
> + interrupts = <GIC_SPI 27
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk
> IMX8MM_CLK_UART2_ROOT>,
> + <&clk
> IMX8MM_CLK_UART2_ROOT>;
> + clock-names = "ipg", "per";
> + status = "disabled";
> + };
> +
> + i2c1: i2c at 30a20000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,imx8mm-i2c",
> "fsl,imx21-i2c";
> + reg = <0x0 0x30a20000 0x0 0x10000>;
> + interrupts = <GIC_SPI 35
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MM_CLK_I2C1_ROOT>;
> + status = "disabled";
> + };
> +
> + i2c2: i2c at 30a30000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,imx8mm-i2c",
> "fsl,imx21-i2c";
> + reg = <0x0 0x30a30000 0x0 0x10000>;
> + interrupts = <GIC_SPI 36
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MM_CLK_I2C2_ROOT>;
> + status = "disabled";
> + };
> +
> + i2c3: i2c at 30a40000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,imx8mm-i2c",
> "fsl,imx21-i2c";
> + reg = <0x0 0x30a40000 0x0 0x10000>;
> + interrupts = <GIC_SPI 37
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MM_CLK_I2C3_ROOT>;
> + status = "disabled";
> + };
> +
> + i2c4: i2c at 30a50000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,imx8mm-i2c",
> "fsl,imx21-i2c";
> + reg = <0x0 0x30a50000 0x0 0x10000>;
> + interrupts = <GIC_SPI 38
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MM_CLK_I2C4_ROOT>;
> + status = "disabled";
> + };
> +
> + uart4: serial at 30a60000 {
> + compatible = "fsl,imx8mq-uart",
> + "fsl,imx6q-uart",
> "fsl,imx21-uart";
> + reg = <0x0 0x30a60000 0x0 0x10000>;
> + interrupts = <GIC_SPI 29
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk
> IMX8MM_CLK_UART4_ROOT>,
> + <&clk
> IMX8MM_CLK_UART4_ROOT>;
> + clock-names = "ipg", "per";
> + status = "disabled";
> + };
> +
> + usdhc1: mmc at 30b40000 {
> + compatible = "fsl,imx8mq-usdhc",
> "fsl,imx7d-usdhc";
> + reg = <0x0 0x30b40000 0x0 0x10000>;
> + interrupts = <GIC_SPI 22
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MM_CLK_DUMMY>,
> + <&clk
> IMX8MM_CLK_NAND_USDHC_BUS>,
> + <&clk
> IMX8MM_CLK_USDHC1_ROOT>;
> + clock-names = "ipg", "ahb", "per";
> + assigned-clocks = <&clk
> IMX8MM_CLK_USDHC1>;
> + assigned-clock-rates = <400000000>;
> + fsl,tuning-start-tap = <20>;
> + fsl,tuning-step= <2>;
> + bus-width = <4>;
> + status = "disabled";
> + };
> +
> + usdhc2: mmc at 30b50000 {
> + compatible = "fsl,imx8mq-usdhc",
> "fsl,imx7d-usdhc";
> + reg = <0x0 0x30b50000 0x0 0x10000>;
> + interrupts = <GIC_SPI 23
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MM_CLK_DUMMY>,
> + <&clk
> IMX8MM_CLK_NAND_USDHC_BUS>,
> + <&clk
> IMX8MM_CLK_USDHC2_ROOT>;
> + clock-names = "ipg", "ahb", "per";
> + fsl,tuning-start-tap = <20>;
> + fsl,tuning-step= <2>;
> + bus-width = <4>;
> + status = "disabled";
> + };
> +
> + usdhc3: mmc at 30b60000 {
> + compatible = "fsl,imx8mq-usdhc",
> "fsl,imx7d-usdhc";
> + reg = <0x0 0x30b60000 0x0 0x10000>;
> + interrupts = <GIC_SPI 24
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MM_CLK_DUMMY>,
> + <&clk
> IMX8MM_CLK_NAND_USDHC_BUS>,
> + <&clk
> IMX8MM_CLK_USDHC3_ROOT>;
> + clock-names = "ipg", "ahb", "per";
> + assigned-clocks = <&clk
> IMX8MM_CLK_USDHC3_ROOT>;
> + assigned-clock-rates = <400000000>;
> + fsl,tuning-start-tap = <20>;
> + fsl,tuning-step= <2>;
> + bus-width = <4>;
> + status = "disabled";
> + };
> + };
> + };
> +};
> diff --git a/arch/arm/mach-imx/imx8m/Kconfig
> b/arch/arm/mach-imx/imx8m/Kconfig index 35c978e863..f520075875 100644
> --- a/arch/arm/mach-imx/imx8m/Kconfig
> +++ b/arch/arm/mach-imx/imx8m/Kconfig
> @@ -24,8 +24,15 @@ config TARGET_IMX8MQ_EVK
> select IMX8MQ
> select IMX8M_LPDDR4
>
> +config TARGET_IMX8MM_EVK
> + bool "imx8mm LPDDR4 EVK board"
> + select IMX8MM
> + select SUPPORT_SPL
> + select IMX8M_LPDDR4
Here you shall put the select DM_{UART,USDHC, etc}
> +
> endchoice
>
> source "board/freescale/imx8mq_evk/Kconfig"
> +source "board/freescale/imx8mm_evk/Kconfig"
>
> endif
> diff --git a/board/freescale/imx8mm_evk/Kconfig
> b/board/freescale/imx8mm_evk/Kconfig new file mode 100644
> index 0000000000..299691a619
> --- /dev/null
> +++ b/board/freescale/imx8mm_evk/Kconfig
> @@ -0,0 +1,12 @@
> +if TARGET_IMX8MM_EVK
> +
> +config SYS_BOARD
> + default "imx8mm_evk"
> +
> +config SYS_VENDOR
> + default "freescale"
> +
> +config SYS_CONFIG_NAME
> + default "imx8mm_evk"
> +
> +endif
> diff --git a/board/freescale/imx8mm_evk/MAINTAINERS
> b/board/freescale/imx8mm_evk/MAINTAINERS new file mode 100644
> index 0000000000..b031bb0674
> --- /dev/null
> +++ b/board/freescale/imx8mm_evk/MAINTAINERS
> @@ -0,0 +1,6 @@
> +i.MX8MM EVK BOARD
> +M: Peng Fan <peng.fan@nxp.com>
> +S: Maintained
> +F: board/freescale/imx8mm_evk/
> +F: include/configs/imx8mm_evk.h
> +F: configs/imx8mm_evk_defconfig
> diff --git a/board/freescale/imx8mm_evk/Makefile
> b/board/freescale/imx8mm_evk/Makefile new file mode 100644
> index 0000000000..1db7b62caf
> --- /dev/null
> +++ b/board/freescale/imx8mm_evk/Makefile
> @@ -0,0 +1,12 @@
> +#
> +# Copyright 2018 NXP
> +#
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +
> +obj-y += imx8mm_evk.o
> +
> +ifdef CONFIG_SPL_BUILD
> +obj-y += spl.o
> +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
> +endif
> diff --git a/board/freescale/imx8mm_evk/imx8mm_evk.c
> b/board/freescale/imx8mm_evk/imx8mm_evk.c new file mode 100644
> index 0000000000..a681aca04d
> --- /dev/null
> +++ b/board/freescale/imx8mm_evk/imx8mm_evk.c
> @@ -0,0 +1,144 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2018 NXP
> + */
> +
> +#include <common.h>
> +#include <malloc.h>
> +#include <errno.h>
> +#include <asm/io.h>
> +#include <miiphy.h>
> +#include <netdev.h>
> +#include <asm/mach-imx/iomux-v3.h>
> +#include <asm-generic/gpio.h>
> +#include <fsl_esdhc.h>
> +#include <mmc.h>
> +#include <asm/arch/imx8mm_pins.h>
> +#include <asm/arch/sys_proto.h>
> +#include <asm/mach-imx/gpio.h>
> +#include <asm/mach-imx/mxc_i2c.h>
> +#include <asm/arch/clock.h>
> +#include <spl.h>
> +#include <asm/mach-imx/dma.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
> +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE |
> PAD_CTL_PUE | PAD_CTL_PE) +
> +static iomux_v3_cfg_t const uart_pads[] = {
> + IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
> + IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
> +};
> +
> +static iomux_v3_cfg_t const wdog_pads[] = {
> + IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B |
> MUX_PAD_CTRL(WDOG_PAD_CTRL), +};
> +
> +int board_early_init_f(void)
> +{
> + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
> +
> + imx_iomux_v3_setup_multiple_pads(wdog_pads,
> ARRAY_SIZE(wdog_pads)); +
> + set_wdog_reset(wdog);
> +
> + imx_iomux_v3_setup_multiple_pads(uart_pads,
> ARRAY_SIZE(uart_pads)); +
> + return 0;
> +}
> +
> +#ifdef CONFIG_BOARD_POSTCLK_INIT
> +int board_postclk_init(void)
> +{
> + /* TODO */
> + return 0;
> +}
> +#endif
> +
> +int dram_init(void)
> +{
> + /* rom_pointer[1] contains the size of TEE occupies */
> + if (rom_pointer[1])
> + gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
> + else
> + gd->ram_size = PHYS_SDRAM_SIZE;
> +
> + return 0;
> +}
> +
> +#ifdef CONFIG_OF_BOARD_SETUP
> +int ft_board_setup(void *blob, bd_t *bd)
^^^ - fdt_board_setup ?
> +{
> + return 0;
> +}
> +#endif
> +
> +#ifdef CONFIG_FEC_MXC
> +#define FEC_RST_PAD IMX_GPIO_NR(4, 22)
> +static iomux_v3_cfg_t const fec1_rst_pads[] = {
> + IMX8MM_PAD_SAI2_RXC_GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
This shall be done with fsl_fec.c DM driver - there is support for
adding reset pin (to dts).
> +};
> +
> +static void setup_iomux_fec(void)
> +{
> + imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
> + ARRAY_SIZE(fec1_rst_pads));
> +
> + gpio_request(FEC_RST_PAD, "fec1_rst");
> + gpio_direction_output(FEC_RST_PAD, 0);
> + udelay(500);
> + gpio_direction_output(FEC_RST_PAD, 1);
> +}
This shall be replaced with DM/DTS of the fsl_fec.c driver. Please also
note that there are (at least on imx6q) some timing issues when we move
the code to DM/DTS (some delay is needed).
> +
> +static int setup_fec(void)
> +{
> + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
> + = (struct iomuxc_gpr_base_regs
> *)IOMUXC_GPR_BASE_ADDR; +
> + setup_iomux_fec();
> +
> + /* Use 125M anatop REF_CLK1 for ENET1, not from external */
> + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
> + IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT,
> 0);
> + return set_clk_enet(ENET_125MHZ);
> +}
> +
> +int board_phy_config(struct phy_device *phydev)
> +{
> + /* enable rgmii rxc skew and phy mode select to RGMII copper
> */
> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
> +
> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
> +
> + if (phydev->drv->config)
> + phydev->drv->config(phydev);
> + return 0;
Which PHY do you use? E.g. KSZ... support passing those values via DTS.
> +}
> +#endif
> +
> +int board_init(void)
> +{
> +#ifdef CONFIG_FEC_MXC
> + setup_fec();
> +#endif
> + return 0;
> +}
> +
> +int board_mmc_get_env_dev(int devno)
> +{
> + return devno - 1;
> +}
> +
> +int board_late_init(void)
> +{
> +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> + env_set("board_name", "EVK");
> + env_set("board_rev", "iMX8MM");
> +#endif
> + return 0;
> +}
> diff --git a/board/freescale/imx8mm_evk/lpddr4_timing.c
> b/board/freescale/imx8mm_evk/lpddr4_timing.c new file mode 100644
> index 0000000000..4bade5bf74
> --- /dev/null
> +++ b/board/freescale/imx8mm_evk/lpddr4_timing.c
> @@ -0,0 +1,1980 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2018 NXP
Author is missing.
> + */
> +
> +#include <linux/kernel.h>
> +#include <common.h>
> +#include <asm/arch/ddr.h>
> +#include <asm/arch/lpddr4_define.h>
> +
> +struct dram_cfg_param lpddr4_ddrc_cfg[] = {
> + /* Start to config, default 3200mbps */
> + { DDRC_DBG1(0), 0x00000001 },
> + { DDRC_PWRCTL(0), 0x00000001 },
> + { DDRC_MSTR(0), 0xa1080020 },
> + { DDRC_RFSHTMG(0), 0x005b00d2 },
> + { DDRC_INIT0(0), 0xC003061B },
> + { DDRC_INIT1(0), 0x009D0000 },
> + { DDRC_INIT3(0), 0x00D4002D },
> + { DDRC_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 },
> + { DDRC_INIT6(0), 0x0066004a },
> + { DDRC_INIT7(0), 0x0006004a },
> +
> + { DDRC_DRAMTMG0(0), 0x1A201B22 },
> + { DDRC_DRAMTMG1(0), 0x00060633 },
> + { DDRC_DRAMTMG3(0), 0x00C0C000 },
> + { DDRC_DRAMTMG4(0), 0x0F04080F },
> + { DDRC_DRAMTMG5(0), 0x02040C0C },
> + { DDRC_DRAMTMG6(0), 0x01010007 },
> + { DDRC_DRAMTMG7(0), 0x00000401 },
> + { DDRC_DRAMTMG12(0), 0x00020600 },
> + { DDRC_DRAMTMG13(0), 0x0C100002 },
> + { DDRC_DRAMTMG14(0), 0x000000E6 },
> + { DDRC_DRAMTMG17(0), 0x00A00050 },
> +
> + { DDRC_ZQCTL0(0), 0x03200018 },
> + { DDRC_ZQCTL1(0), 0x028061A8 },
> + { DDRC_ZQCTL2(0), 0x00000000 },
> +
> + { DDRC_DFITMG0(0), 0x0497820A },
> + { DDRC_DFITMG2(0), 0x0000170A },
> + { DDRC_DRAMTMG2(0), 0x070E171a },
> + { DDRC_DBICTL(0), 0x00000001 },
> +
> + { DDRC_DFITMG1(0), 0x00080303 },
> + { DDRC_DFIUPD0(0), 0xE0400018 },
> + { DDRC_DFIUPD1(0), 0x00DF00E4 },
> + { DDRC_DFIUPD2(0), 0x80000000 },
> + { DDRC_DFIMISC(0), 0x00000011 },
> +
> + { DDRC_DFIPHYMSTR(0), 0x00000000 },
> + { DDRC_RANKCTL(0), 0x00000c99 },
> +
> + /* address mapping */
> + { DDRC_ADDRMAP0(0), 0x0000001f },
> + { DDRC_ADDRMAP1(0), 0x00080808 },
> + { DDRC_ADDRMAP2(0), 0x00000000 },
> + { DDRC_ADDRMAP3(0), 0x00000000 },
> + { DDRC_ADDRMAP4(0), 0x00001f1f },
> + { DDRC_ADDRMAP5(0), 0x07070707 },
> + { DDRC_ADDRMAP6(0), 0x07070707 },
> + { DDRC_ADDRMAP7(0), 0x00000f0f },
> +
> + /* performance setting */
> + { DDRC_SCHED(0), 0x29001701 },
> + { DDRC_SCHED1(0), 0x0000002c },
> + { DDRC_PERFHPR1(0), 0x04000030 },
> + { DDRC_PERFLPR1(0), 0x900093e7 },
> + { DDRC_PERFWR1(0), 0x20005574 },
> + { DDRC_PCCFG(0), 0x00000111 },
> + { DDRC_PCFGW_0(0), 0x000072ff },
> + { DDRC_PCFGQOS0_0(0), 0x02100e07 },
> + { DDRC_PCFGQOS1_0(0), 0x00620096 },
> + { DDRC_PCFGWQOS0_0(0), 0x01100e07 },
> + { DDRC_PCFGWQOS1_0(0), 0x00c8012c },
> +
> + /* frequency P1&P2 */
> + /* Frequency 1: 400mbps */
> + { DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c },
> + { DDRC_FREQ1_DRAMTMG1(0), 0x00030410 },
> + { DDRC_FREQ1_DRAMTMG2(0), 0x0203090c },
> + { DDRC_FREQ1_DRAMTMG3(0), 0x00505006 },
> + { DDRC_FREQ1_DRAMTMG4(0), 0x05040305 },
> + { DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504 },
> + { DDRC_FREQ1_DRAMTMG6(0), 0x0a060004 },
> + { DDRC_FREQ1_DRAMTMG7(0), 0x0000090e },
> + { DDRC_FREQ1_DRAMTMG14(0), 0x00000032 },
> + { DDRC_FREQ1_DRAMTMG15(0), 0x00000000 },
> + { DDRC_FREQ1_DRAMTMG17(0), 0x0036001b },
> + { DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1 },
> + { DDRC_FREQ1_DFITMG0(0), 0x03818200 },
> + { DDRC_FREQ1_DFITMG2(0), 0x00000000 },
> + { DDRC_FREQ1_RFSHTMG(0), 0x000C001c },
> + { DDRC_FREQ1_INIT3(0), 0x00840000 },
> + { DDRC_FREQ1_INIT4(0), 0x00310000 },
> + { DDRC_FREQ1_INIT6(0), 0x0066004a },
> + { DDRC_FREQ1_INIT7(0), 0x0006004a },
> +
> + /* Frequency 2: 100mbps */
> + { DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c },
> + { DDRC_FREQ2_DRAMTMG1(0), 0x00030410 },
> + { DDRC_FREQ2_DRAMTMG2(0), 0x0203090c },
> + { DDRC_FREQ2_DRAMTMG3(0), 0x00505006 },
> + { DDRC_FREQ2_DRAMTMG4(0), 0x05040305 },
> + { DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504 },
> + { DDRC_FREQ2_DRAMTMG6(0), 0x0a060004 },
> + { DDRC_FREQ2_DRAMTMG7(0), 0x0000090e },
> + { DDRC_FREQ2_DRAMTMG14(0), 0x00000032 },
> + { DDRC_FREQ2_DRAMTMG17(0), 0x0036001b },
> + { DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1 },
> + { DDRC_FREQ2_DFITMG0(0), 0x03818200 },
> + { DDRC_FREQ2_DFITMG2(0), 0x00000000 },
> + { DDRC_FREQ2_RFSHTMG(0), 0x0003800c },
> + { DDRC_FREQ2_RFSHTMG(0), 0x00030007 },
> + { DDRC_FREQ2_INIT3(0), 0x00840000 },
> + { DDRC_FREQ2_INIT4(0), 0x00310008 },
> + { DDRC_FREQ2_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 },
> + { DDRC_FREQ2_INIT6(0), 0x0066004a },
> + { DDRC_FREQ2_INIT7(0), 0x0006004a },
> +
> + /* boot start point */
> + { DDRC_MSTR2(0), 0x2 }, //DDRC_MSTR2
> +};
> +
> +/* PHY Initialize Configuration */
> +struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
> + { 0x1005f, 0x1ff },
> + { 0x1015f, 0x1ff },
> + { 0x1105f, 0x1ff },
> + { 0x1115f, 0x1ff },
> + { 0x1205f, 0x1ff },
> + { 0x1215f, 0x1ff },
> + { 0x1305f, 0x1ff },
> + { 0x1315f, 0x1ff },
> +
> + { 0x11005f, 0x1ff },
> + { 0x11015f, 0x1ff },
> + { 0x11105f, 0x1ff },
> + { 0x11115f, 0x1ff },
> + { 0x11205f, 0x1ff },
> + { 0x11215f, 0x1ff },
> + { 0x11305f, 0x1ff },
> + { 0x11315f, 0x1ff },
> +
> + { 0x21005f, 0x1ff },
> + { 0x21015f, 0x1ff },
> + { 0x21105f, 0x1ff },
> + { 0x21115f, 0x1ff },
> + { 0x21205f, 0x1ff },
> + { 0x21215f, 0x1ff },
> + { 0x21305f, 0x1ff },
> + { 0x21315f, 0x1ff },
> +
> + { 0x55, 0x1ff },
> + { 0x1055, 0x1ff },
> + { 0x2055, 0x1ff },
> + { 0x3055, 0x1ff },
> + { 0x4055, 0x1ff },
> + { 0x5055, 0x1ff },
> + { 0x6055, 0x1ff },
> + { 0x7055, 0x1ff },
> + { 0x8055, 0x1ff },
> + { 0x9055, 0x1ff },
> +
> + { 0x200c5, 0x19 },
> + { 0x1200c5, 0x7 },
> + { 0x2200c5, 0x7 },
> +
> + { 0x2002e, 0x2 },
> + { 0x12002e, 0x2 },
> + { 0x22002e, 0x2 },
> +
> + { 0x90204, 0x0 },
> + { 0x190204, 0x0 },
> + { 0x290204, 0x0 },
> +
> + { 0x20024, 0xab },
> + { 0x2003a, 0x0 },
> +
> + { 0x120024, 0xab },
> + { 0x2003a, 0x0 },
> +
> + { 0x220024, 0xab },
> + { 0x2003a, 0x0 },
> +
> + { 0x20056, 0x3 },
> + { 0x120056, 0xa },
> + { 0x220056, 0xa },
> +
> + { 0x1004d, 0xe00 },
> + { 0x1014d, 0xe00 },
> + { 0x1104d, 0xe00 },
> + { 0x1114d, 0xe00 },
> + { 0x1204d, 0xe00 },
> + { 0x1214d, 0xe00 },
> + { 0x1304d, 0xe00 },
> + { 0x1314d, 0xe00 },
> +
> + { 0x11004d, 0xe00 },
> + { 0x11014d, 0xe00 },
> + { 0x11104d, 0xe00 },
> + { 0x11114d, 0xe00 },
> + { 0x11204d, 0xe00 },
> + { 0x11214d, 0xe00 },
> + { 0x11304d, 0xe00 },
> + { 0x11314d, 0xe00 },
> +
> + { 0x21004d, 0xe00 },
> + { 0x21014d, 0xe00 },
> + { 0x21104d, 0xe00 },
> + { 0x21114d, 0xe00 },
> + { 0x21204d, 0xe00 },
> + { 0x21214d, 0xe00 },
> + { 0x21304d, 0xe00 },
> + { 0x21314d, 0xe00 },
> +
> + { 0x10049, 0xfbe },
> + { 0x10149, 0xfbe },
> + { 0x11049, 0xfbe },
> + { 0x11149, 0xfbe },
> + { 0x12049, 0xfbe },
> + { 0x12149, 0xfbe },
> + { 0x13049, 0xfbe },
> + { 0x13149, 0xfbe },
> +
> + { 0x110049, 0xfbe },
> + { 0x110149, 0xfbe },
> + { 0x111049, 0xfbe },
> + { 0x111149, 0xfbe },
> + { 0x112049, 0xfbe },
> + { 0x112149, 0xfbe },
> + { 0x113049, 0xfbe },
> + { 0x113149, 0xfbe },
> +
> + { 0x210049, 0xfbe },
> + { 0x210149, 0xfbe },
> + { 0x211049, 0xfbe },
> + { 0x211149, 0xfbe },
> + { 0x212049, 0xfbe },
> + { 0x212149, 0xfbe },
> + { 0x213049, 0xfbe },
> + { 0x213149, 0xfbe },
> +
> + { 0x43, 0x63 },
> + { 0x1043, 0x63 },
> + { 0x2043, 0x63 },
> + { 0x3043, 0x63 },
> + { 0x4043, 0x63 },
> + { 0x5043, 0x63 },
> + { 0x6043, 0x63 },
> + { 0x7043, 0x63 },
> + { 0x8043, 0x63 },
> + { 0x9043, 0x63 },
> +
> + { 0x20018, 0x3 },
> + { 0x20075, 0x4 },
> + { 0x20050, 0x0 },
> + { 0x20008, 0x2ee },
> + { 0x120008, 0x64 },
> + { 0x220008, 0x19 },
> + { 0x20088, 0x9 },
> +
> + { 0x200b2, 0x1d4 },
> + { 0x10043, 0x5a1 },
> + { 0x10143, 0x5a1 },
> + { 0x11043, 0x5a1 },
> + { 0x11143, 0x5a1 },
> + { 0x12043, 0x5a1 },
> + { 0x12143, 0x5a1 },
> + { 0x13043, 0x5a1 },
> + { 0x13143, 0x5a1 },
> +
> + { 0x1200b2, 0xdc },
> + { 0x110043, 0x5a1 },
> + { 0x110143, 0x5a1 },
> + { 0x111043, 0x5a1 },
> + { 0x111143, 0x5a1 },
> + { 0x112043, 0x5a1 },
> + { 0x112143, 0x5a1 },
> + { 0x113043, 0x5a1 },
> + { 0x113143, 0x5a1 },
> +
> + { 0x2200b2, 0xdc },
> + { 0x210043, 0x5a1 },
> + { 0x210143, 0x5a1 },
> + { 0x211043, 0x5a1 },
> + { 0x211143, 0x5a1 },
> + { 0x212043, 0x5a1 },
> + { 0x212143, 0x5a1 },
> + { 0x213043, 0x5a1 },
> + { 0x213143, 0x5a1 },
> +
> + { 0x200fa, 0x1 },
> + { 0x1200fa, 0x1 },
> + { 0x2200fa, 0x1 },
> +
> + { 0x20019, 0x1 },
> + { 0x120019, 0x1 },
> + { 0x220019, 0x1 },
> +
> + { 0x200f0, 0x660 },
> + { 0x200f1, 0x0 },
> + { 0x200f2, 0x4444 },
> + { 0x200f3, 0x8888 },
> + { 0x200f4, 0x5665 },
> + { 0x200f5, 0x0 },
> + { 0x200f6, 0x0 },
> + { 0x200f7, 0xf000 },
> +
> + { 0x20025, 0x0 },
> + { 0x2002d, LPDDR4_PHY_DMIPinPresent },
> + { 0x12002d, LPDDR4_PHY_DMIPinPresent },
> + { 0x22002d, LPDDR4_PHY_DMIPinPresent },
> + { 0x200c7, 0x21 },
> + { 0x200ca, 0x24 },
> + { 0x1200c7, 0x21 },
> + { 0x1200ca, 0x24 },
> + { 0x2200c7, 0x21 },
> + { 0x2200ca, 0x24 },
Why do you add tuple - offset and value? Shouldn't we have the
DDR training functions here?
It is possible to train IMX6Q and Vybrid's DDR3 (as fair as I know).
Would it be also possible to add the DDR4 training code for IMX8?
> +};
> +
> +/* ddr phy trained csr */
> +struct dram_cfg_param lpddr4_ddrphy_trained_csr[] = {
> + { 0x200b2, 0x0 },
> + { 0x1200b2, 0x0 },
> + { 0x2200b2, 0x0 },
> + { 0x200cb, 0x0 },
> + { 0x10043, 0x0 },
> + { 0x110043, 0x0 },
> + { 0x210043, 0x0 },
> + { 0x10143, 0x0 },
> + { 0x110143, 0x0 },
> + { 0x210143, 0x0 },
> + { 0x11043, 0x0 },
> + { 0x111043, 0x0 },
> + { 0x211043, 0x0 },
> + { 0x11143, 0x0 },
> + { 0x111143, 0x0 },
> + { 0x211143, 0x0 },
> + { 0x12043, 0x0 },
> + { 0x112043, 0x0 },
> + { 0x212043, 0x0 },
> + { 0x12143, 0x0 },
> + { 0x112143, 0x0 },
> + { 0x212143, 0x0 },
> + { 0x13043, 0x0 },
> + { 0x113043, 0x0 },
> + { 0x213043, 0x0 },
> + { 0x13143, 0x0 },
> + { 0x113143, 0x0 },
> + { 0x213143, 0x0 },
> + { 0x80, 0x0 },
> + { 0x100080, 0x0 },
> + { 0x200080, 0x0 },
> + { 0x1080, 0x0 },
> + { 0x101080, 0x0 },
> + { 0x201080, 0x0 },
> + { 0x2080, 0x0 },
> + { 0x102080, 0x0 },
> + { 0x202080, 0x0 },
> + { 0x3080, 0x0 },
> + { 0x103080, 0x0 },
> + { 0x203080, 0x0 },
> + { 0x4080, 0x0 },
> + { 0x104080, 0x0 },
> + { 0x204080, 0x0 },
> + { 0x5080, 0x0 },
> + { 0x105080, 0x0 },
> + { 0x205080, 0x0 },
> + { 0x6080, 0x0 },
> + { 0x106080, 0x0 },
> + { 0x206080, 0x0 },
> + { 0x7080, 0x0 },
> + { 0x107080, 0x0 },
> + { 0x207080, 0x0 },
> + { 0x8080, 0x0 },
> + { 0x108080, 0x0 },
> + { 0x208080, 0x0 },
> + { 0x9080, 0x0 },
> + { 0x109080, 0x0 },
> + { 0x209080, 0x0 },
> + { 0x10080, 0x0 },
> + { 0x110080, 0x0 },
> + { 0x210080, 0x0 },
> + { 0x10180, 0x0 },
> + { 0x110180, 0x0 },
> + { 0x210180, 0x0 },
> + { 0x11080, 0x0 },
> + { 0x111080, 0x0 },
> + { 0x211080, 0x0 },
> + { 0x11180, 0x0 },
> + { 0x111180, 0x0 },
> + { 0x211180, 0x0 },
> + { 0x12080, 0x0 },
> + { 0x112080, 0x0 },
> + { 0x212080, 0x0 },
> + { 0x12180, 0x0 },
> + { 0x112180, 0x0 },
> + { 0x212180, 0x0 },
> + { 0x13080, 0x0 },
> + { 0x113080, 0x0 },
> + { 0x213080, 0x0 },
> + { 0x13180, 0x0 },
> + { 0x113180, 0x0 },
> + { 0x213180, 0x0 },
> + { 0x10081, 0x0 },
> + { 0x110081, 0x0 },
> + { 0x210081, 0x0 },
> + { 0x10181, 0x0 },
> + { 0x110181, 0x0 },
> + { 0x210181, 0x0 },
> + { 0x11081, 0x0 },
> + { 0x111081, 0x0 },
> + { 0x211081, 0x0 },
> + { 0x11181, 0x0 },
> + { 0x111181, 0x0 },
> + { 0x211181, 0x0 },
> + { 0x12081, 0x0 },
> + { 0x112081, 0x0 },
> + { 0x212081, 0x0 },
> + { 0x12181, 0x0 },
> + { 0x112181, 0x0 },
> + { 0x212181, 0x0 },
> + { 0x13081, 0x0 },
> + { 0x113081, 0x0 },
> + { 0x213081, 0x0 },
> + { 0x13181, 0x0 },
> + { 0x113181, 0x0 },
> + { 0x213181, 0x0 },
> + { 0x100d0, 0x0 },
> + { 0x1100d0, 0x0 },
> + { 0x2100d0, 0x0 },
> + { 0x101d0, 0x0 },
> + { 0x1101d0, 0x0 },
> + { 0x2101d0, 0x0 },
> + { 0x110d0, 0x0 },
> + { 0x1110d0, 0x0 },
> + { 0x2110d0, 0x0 },
> + { 0x111d0, 0x0 },
> + { 0x1111d0, 0x0 },
> + { 0x2111d0, 0x0 },
> + { 0x120d0, 0x0 },
> + { 0x1120d0, 0x0 },
> + { 0x2120d0, 0x0 },
> + { 0x121d0, 0x0 },
> + { 0x1121d0, 0x0 },
> + { 0x2121d0, 0x0 },
> + { 0x130d0, 0x0 },
> + { 0x1130d0, 0x0 },
> + { 0x2130d0, 0x0 },
> + { 0x131d0, 0x0 },
> + { 0x1131d0, 0x0 },
> + { 0x2131d0, 0x0 },
> + { 0x100d1, 0x0 },
> + { 0x1100d1, 0x0 },
> + { 0x2100d1, 0x0 },
> + { 0x101d1, 0x0 },
> + { 0x1101d1, 0x0 },
> + { 0x2101d1, 0x0 },
> + { 0x110d1, 0x0 },
> + { 0x1110d1, 0x0 },
> + { 0x2110d1, 0x0 },
> + { 0x111d1, 0x0 },
> + { 0x1111d1, 0x0 },
> + { 0x2111d1, 0x0 },
> + { 0x120d1, 0x0 },
> + { 0x1120d1, 0x0 },
> + { 0x2120d1, 0x0 },
> + { 0x121d1, 0x0 },
> + { 0x1121d1, 0x0 },
> + { 0x2121d1, 0x0 },
> + { 0x130d1, 0x0 },
> + { 0x1130d1, 0x0 },
> + { 0x2130d1, 0x0 },
> + { 0x131d1, 0x0 },
> + { 0x1131d1, 0x0 },
> + { 0x2131d1, 0x0 },
> + { 0x10068, 0x0 },
> + { 0x10168, 0x0 },
> + { 0x10268, 0x0 },
> + { 0x10368, 0x0 },
> + { 0x10468, 0x0 },
> + { 0x10568, 0x0 },
> + { 0x10668, 0x0 },
> + { 0x10768, 0x0 },
> + { 0x10868, 0x0 },
> + { 0x11068, 0x0 },
> + { 0x11168, 0x0 },
> + { 0x11268, 0x0 },
> + { 0x11368, 0x0 },
> + { 0x11468, 0x0 },
> + { 0x11568, 0x0 },
> + { 0x11668, 0x0 },
> + { 0x11768, 0x0 },
> + { 0x11868, 0x0 },
> + { 0x12068, 0x0 },
> + { 0x12168, 0x0 },
> + { 0x12268, 0x0 },
> + { 0x12368, 0x0 },
> + { 0x12468, 0x0 },
> + { 0x12568, 0x0 },
> + { 0x12668, 0x0 },
> + { 0x12768, 0x0 },
> + { 0x12868, 0x0 },
> + { 0x13068, 0x0 },
> + { 0x13168, 0x0 },
> + { 0x13268, 0x0 },
> + { 0x13368, 0x0 },
> + { 0x13468, 0x0 },
> + { 0x13568, 0x0 },
> + { 0x13668, 0x0 },
> + { 0x13768, 0x0 },
> + { 0x13868, 0x0 },
> + { 0x10069, 0x0 },
> + { 0x10169, 0x0 },
> + { 0x10269, 0x0 },
> + { 0x10369, 0x0 },
> + { 0x10469, 0x0 },
> + { 0x10569, 0x0 },
> + { 0x10669, 0x0 },
> + { 0x10769, 0x0 },
> + { 0x10869, 0x0 },
> + { 0x11069, 0x0 },
> + { 0x11169, 0x0 },
> + { 0x11269, 0x0 },
> + { 0x11369, 0x0 },
> + { 0x11469, 0x0 },
> + { 0x11569, 0x0 },
> + { 0x11669, 0x0 },
> + { 0x11769, 0x0 },
> + { 0x11869, 0x0 },
> + { 0x12069, 0x0 },
> + { 0x12169, 0x0 },
> + { 0x12269, 0x0 },
> + { 0x12369, 0x0 },
> + { 0x12469, 0x0 },
> + { 0x12569, 0x0 },
> + { 0x12669, 0x0 },
> + { 0x12769, 0x0 },
> + { 0x12869, 0x0 },
> + { 0x13069, 0x0 },
> + { 0x13169, 0x0 },
> + { 0x13269, 0x0 },
> + { 0x13369, 0x0 },
> + { 0x13469, 0x0 },
> + { 0x13569, 0x0 },
> + { 0x13669, 0x0 },
> + { 0x13769, 0x0 },
> + { 0x13869, 0x0 },
> + { 0x1008c, 0x0 },
> + { 0x11008c, 0x0 },
> + { 0x21008c, 0x0 },
> + { 0x1018c, 0x0 },
> + { 0x11018c, 0x0 },
> + { 0x21018c, 0x0 },
> + { 0x1108c, 0x0 },
> + { 0x11108c, 0x0 },
> + { 0x21108c, 0x0 },
> + { 0x1118c, 0x0 },
> + { 0x11118c, 0x0 },
> + { 0x21118c, 0x0 },
> + { 0x1208c, 0x0 },
> + { 0x11208c, 0x0 },
> + { 0x21208c, 0x0 },
> + { 0x1218c, 0x0 },
> + { 0x11218c, 0x0 },
> + { 0x21218c, 0x0 },
> + { 0x1308c, 0x0 },
> + { 0x11308c, 0x0 },
> + { 0x21308c, 0x0 },
> + { 0x1318c, 0x0 },
> + { 0x11318c, 0x0 },
> + { 0x21318c, 0x0 },
> + { 0x1008d, 0x0 },
> + { 0x11008d, 0x0 },
> + { 0x21008d, 0x0 },
> + { 0x1018d, 0x0 },
> + { 0x11018d, 0x0 },
> + { 0x21018d, 0x0 },
> + { 0x1108d, 0x0 },
> + { 0x11108d, 0x0 },
> + { 0x21108d, 0x0 },
> + { 0x1118d, 0x0 },
> + { 0x11118d, 0x0 },
> + { 0x21118d, 0x0 },
> + { 0x1208d, 0x0 },
> + { 0x11208d, 0x0 },
> + { 0x21208d, 0x0 },
> + { 0x1218d, 0x0 },
> + { 0x11218d, 0x0 },
> + { 0x21218d, 0x0 },
> + { 0x1308d, 0x0 },
> + { 0x11308d, 0x0 },
> + { 0x21308d, 0x0 },
> + { 0x1318d, 0x0 },
> + { 0x11318d, 0x0 },
> + { 0x21318d, 0x0 },
> + { 0x100c0, 0x0 },
> + { 0x1100c0, 0x0 },
> + { 0x2100c0, 0x0 },
> + { 0x101c0, 0x0 },
> + { 0x1101c0, 0x0 },
> + { 0x2101c0, 0x0 },
> + { 0x102c0, 0x0 },
> + { 0x1102c0, 0x0 },
> + { 0x2102c0, 0x0 },
> + { 0x103c0, 0x0 },
> + { 0x1103c0, 0x0 },
> + { 0x2103c0, 0x0 },
> + { 0x104c0, 0x0 },
> + { 0x1104c0, 0x0 },
> + { 0x2104c0, 0x0 },
> + { 0x105c0, 0x0 },
> + { 0x1105c0, 0x0 },
> + { 0x2105c0, 0x0 },
> + { 0x106c0, 0x0 },
> + { 0x1106c0, 0x0 },
> + { 0x2106c0, 0x0 },
> + { 0x107c0, 0x0 },
> + { 0x1107c0, 0x0 },
> + { 0x2107c0, 0x0 },
> + { 0x108c0, 0x0 },
> + { 0x1108c0, 0x0 },
> + { 0x2108c0, 0x0 },
> + { 0x110c0, 0x0 },
> + { 0x1110c0, 0x0 },
> + { 0x2110c0, 0x0 },
> + { 0x111c0, 0x0 },
> + { 0x1111c0, 0x0 },
> + { 0x2111c0, 0x0 },
> + { 0x112c0, 0x0 },
> + { 0x1112c0, 0x0 },
> + { 0x2112c0, 0x0 },
> + { 0x113c0, 0x0 },
> + { 0x1113c0, 0x0 },
> + { 0x2113c0, 0x0 },
> + { 0x114c0, 0x0 },
> + { 0x1114c0, 0x0 },
> + { 0x2114c0, 0x0 },
> + { 0x115c0, 0x0 },
> + { 0x1115c0, 0x0 },
> + { 0x2115c0, 0x0 },
> + { 0x116c0, 0x0 },
> + { 0x1116c0, 0x0 },
> + { 0x2116c0, 0x0 },
> + { 0x117c0, 0x0 },
> + { 0x1117c0, 0x0 },
> + { 0x2117c0, 0x0 },
> + { 0x118c0, 0x0 },
> + { 0x1118c0, 0x0 },
> + { 0x2118c0, 0x0 },
> + { 0x120c0, 0x0 },
> + { 0x1120c0, 0x0 },
> + { 0x2120c0, 0x0 },
> + { 0x121c0, 0x0 },
> + { 0x1121c0, 0x0 },
> + { 0x2121c0, 0x0 },
> + { 0x122c0, 0x0 },
> + { 0x1122c0, 0x0 },
> + { 0x2122c0, 0x0 },
> + { 0x123c0, 0x0 },
> + { 0x1123c0, 0x0 },
> + { 0x2123c0, 0x0 },
> + { 0x124c0, 0x0 },
> + { 0x1124c0, 0x0 },
> + { 0x2124c0, 0x0 },
> + { 0x125c0, 0x0 },
> + { 0x1125c0, 0x0 },
> + { 0x2125c0, 0x0 },
> + { 0x126c0, 0x0 },
> + { 0x1126c0, 0x0 },
> + { 0x2126c0, 0x0 },
> + { 0x127c0, 0x0 },
> + { 0x1127c0, 0x0 },
> + { 0x2127c0, 0x0 },
> + { 0x128c0, 0x0 },
> + { 0x1128c0, 0x0 },
> + { 0x2128c0, 0x0 },
> + { 0x130c0, 0x0 },
> + { 0x1130c0, 0x0 },
> + { 0x2130c0, 0x0 },
> + { 0x131c0, 0x0 },
> + { 0x1131c0, 0x0 },
> + { 0x2131c0, 0x0 },
> + { 0x132c0, 0x0 },
> + { 0x1132c0, 0x0 },
> + { 0x2132c0, 0x0 },
> + { 0x133c0, 0x0 },
> + { 0x1133c0, 0x0 },
> + { 0x2133c0, 0x0 },
> + { 0x134c0, 0x0 },
> + { 0x1134c0, 0x0 },
> + { 0x2134c0, 0x0 },
> + { 0x135c0, 0x0 },
> + { 0x1135c0, 0x0 },
> + { 0x2135c0, 0x0 },
> + { 0x136c0, 0x0 },
> + { 0x1136c0, 0x0 },
> + { 0x2136c0, 0x0 },
> + { 0x137c0, 0x0 },
> + { 0x1137c0, 0x0 },
> + { 0x2137c0, 0x0 },
> + { 0x138c0, 0x0 },
> + { 0x1138c0, 0x0 },
> + { 0x2138c0, 0x0 },
> + { 0x100c1, 0x0 },
> + { 0x1100c1, 0x0 },
> + { 0x2100c1, 0x0 },
> + { 0x101c1, 0x0 },
> + { 0x1101c1, 0x0 },
> + { 0x2101c1, 0x0 },
> + { 0x102c1, 0x0 },
> + { 0x1102c1, 0x0 },
> + { 0x2102c1, 0x0 },
> + { 0x103c1, 0x0 },
> + { 0x1103c1, 0x0 },
> + { 0x2103c1, 0x0 },
> + { 0x104c1, 0x0 },
> + { 0x1104c1, 0x0 },
> + { 0x2104c1, 0x0 },
> + { 0x105c1, 0x0 },
> + { 0x1105c1, 0x0 },
> + { 0x2105c1, 0x0 },
> + { 0x106c1, 0x0 },
> + { 0x1106c1, 0x0 },
> + { 0x2106c1, 0x0 },
> + { 0x107c1, 0x0 },
> + { 0x1107c1, 0x0 },
> + { 0x2107c1, 0x0 },
> + { 0x108c1, 0x0 },
> + { 0x1108c1, 0x0 },
> + { 0x2108c1, 0x0 },
> + { 0x110c1, 0x0 },
> + { 0x1110c1, 0x0 },
> + { 0x2110c1, 0x0 },
> + { 0x111c1, 0x0 },
> + { 0x1111c1, 0x0 },
> + { 0x2111c1, 0x0 },
> + { 0x112c1, 0x0 },
> + { 0x1112c1, 0x0 },
> + { 0x2112c1, 0x0 },
> + { 0x113c1, 0x0 },
> + { 0x1113c1, 0x0 },
> + { 0x2113c1, 0x0 },
> + { 0x114c1, 0x0 },
> + { 0x1114c1, 0x0 },
> + { 0x2114c1, 0x0 },
> + { 0x115c1, 0x0 },
> + { 0x1115c1, 0x0 },
> + { 0x2115c1, 0x0 },
> + { 0x116c1, 0x0 },
> + { 0x1116c1, 0x0 },
> + { 0x2116c1, 0x0 },
> + { 0x117c1, 0x0 },
> + { 0x1117c1, 0x0 },
> + { 0x2117c1, 0x0 },
> + { 0x118c1, 0x0 },
> + { 0x1118c1, 0x0 },
> + { 0x2118c1, 0x0 },
> + { 0x120c1, 0x0 },
> + { 0x1120c1, 0x0 },
> + { 0x2120c1, 0x0 },
> + { 0x121c1, 0x0 },
> + { 0x1121c1, 0x0 },
> + { 0x2121c1, 0x0 },
> + { 0x122c1, 0x0 },
> + { 0x1122c1, 0x0 },
> + { 0x2122c1, 0x0 },
> + { 0x123c1, 0x0 },
> + { 0x1123c1, 0x0 },
> + { 0x2123c1, 0x0 },
> + { 0x124c1, 0x0 },
> + { 0x1124c1, 0x0 },
> + { 0x2124c1, 0x0 },
> + { 0x125c1, 0x0 },
> + { 0x1125c1, 0x0 },
> + { 0x2125c1, 0x0 },
> + { 0x126c1, 0x0 },
> + { 0x1126c1, 0x0 },
> + { 0x2126c1, 0x0 },
> + { 0x127c1, 0x0 },
> + { 0x1127c1, 0x0 },
> + { 0x2127c1, 0x0 },
> + { 0x128c1, 0x0 },
> + { 0x1128c1, 0x0 },
> + { 0x2128c1, 0x0 },
> + { 0x130c1, 0x0 },
> + { 0x1130c1, 0x0 },
> + { 0x2130c1, 0x0 },
> + { 0x131c1, 0x0 },
> + { 0x1131c1, 0x0 },
> + { 0x2131c1, 0x0 },
> + { 0x132c1, 0x0 },
> + { 0x1132c1, 0x0 },
> + { 0x2132c1, 0x0 },
> + { 0x133c1, 0x0 },
> + { 0x1133c1, 0x0 },
> + { 0x2133c1, 0x0 },
> + { 0x134c1, 0x0 },
> + { 0x1134c1, 0x0 },
> + { 0x2134c1, 0x0 },
> + { 0x135c1, 0x0 },
> + { 0x1135c1, 0x0 },
> + { 0x2135c1, 0x0 },
> + { 0x136c1, 0x0 },
> + { 0x1136c1, 0x0 },
> + { 0x2136c1, 0x0 },
> + { 0x137c1, 0x0 },
> + { 0x1137c1, 0x0 },
> + { 0x2137c1, 0x0 },
> + { 0x138c1, 0x0 },
> + { 0x1138c1, 0x0 },
> + { 0x2138c1, 0x0 },
> + { 0x10020, 0x0 },
> + { 0x110020, 0x0 },
> + { 0x210020, 0x0 },
> + { 0x11020, 0x0 },
> + { 0x111020, 0x0 },
> + { 0x211020, 0x0 },
> + { 0x12020, 0x0 },
> + { 0x112020, 0x0 },
> + { 0x212020, 0x0 },
> + { 0x13020, 0x0 },
> + { 0x113020, 0x0 },
> + { 0x213020, 0x0 },
> + { 0x20072, 0x0 },
> + { 0x20073, 0x0 },
> + { 0x20074, 0x0 },
> + { 0x100aa, 0x0 },
> + { 0x110aa, 0x0 },
> + { 0x120aa, 0x0 },
> + { 0x130aa, 0x0 },
> + { 0x20010, 0x0 },
> + { 0x120010, 0x0 },
> + { 0x220010, 0x0 },
> + { 0x20011, 0x0 },
> + { 0x120011, 0x0 },
> + { 0x220011, 0x0 },
> + { 0x100ae, 0x0 },
> + { 0x1100ae, 0x0 },
> + { 0x2100ae, 0x0 },
> + { 0x100af, 0x0 },
> + { 0x1100af, 0x0 },
> + { 0x2100af, 0x0 },
> + { 0x110ae, 0x0 },
> + { 0x1110ae, 0x0 },
> + { 0x2110ae, 0x0 },
> + { 0x110af, 0x0 },
> + { 0x1110af, 0x0 },
> + { 0x2110af, 0x0 },
> + { 0x120ae, 0x0 },
> + { 0x1120ae, 0x0 },
> + { 0x2120ae, 0x0 },
> + { 0x120af, 0x0 },
> + { 0x1120af, 0x0 },
> + { 0x2120af, 0x0 },
> + { 0x130ae, 0x0 },
> + { 0x1130ae, 0x0 },
> + { 0x2130ae, 0x0 },
> + { 0x130af, 0x0 },
> + { 0x1130af, 0x0 },
> + { 0x2130af, 0x0 },
> + { 0x20020, 0x0 },
> + { 0x120020, 0x0 },
> + { 0x220020, 0x0 },
> + { 0x100a0, 0x0 },
> + { 0x100a1, 0x0 },
> + { 0x100a2, 0x0 },
> + { 0x100a3, 0x0 },
> + { 0x100a4, 0x0 },
> + { 0x100a5, 0x0 },
> + { 0x100a6, 0x0 },
> + { 0x100a7, 0x0 },
> + { 0x110a0, 0x0 },
> + { 0x110a1, 0x0 },
> + { 0x110a2, 0x0 },
> + { 0x110a3, 0x0 },
> + { 0x110a4, 0x0 },
> + { 0x110a5, 0x0 },
> + { 0x110a6, 0x0 },
> + { 0x110a7, 0x0 },
> + { 0x120a0, 0x0 },
> + { 0x120a1, 0x0 },
> + { 0x120a2, 0x0 },
> + { 0x120a3, 0x0 },
> + { 0x120a4, 0x0 },
> + { 0x120a5, 0x0 },
> + { 0x120a6, 0x0 },
> + { 0x120a7, 0x0 },
> + { 0x130a0, 0x0 },
> + { 0x130a1, 0x0 },
> + { 0x130a2, 0x0 },
> + { 0x130a3, 0x0 },
> + { 0x130a4, 0x0 },
> + { 0x130a5, 0x0 },
> + { 0x130a6, 0x0 },
> + { 0x130a7, 0x0 },
> + { 0x2007c, 0x0 },
> + { 0x12007c, 0x0 },
> + { 0x22007c, 0x0 },
> + { 0x2007d, 0x0 },
> + { 0x12007d, 0x0 },
> + { 0x22007d, 0x0 },
> + { 0x400fd, 0x0 },
> + { 0x400c0, 0x0 },
> + { 0x90201, 0x0 },
> + { 0x190201, 0x0 },
> + { 0x290201, 0x0 },
> + { 0x90202, 0x0 },
> + { 0x190202, 0x0 },
> + { 0x290202, 0x0 },
> + { 0x90203, 0x0 },
> + { 0x190203, 0x0 },
> + { 0x290203, 0x0 },
> + { 0x90204, 0x0 },
> + { 0x190204, 0x0 },
> + { 0x290204, 0x0 },
> + { 0x90205, 0x0 },
> + { 0x190205, 0x0 },
> + { 0x290205, 0x0 },
> + { 0x90206, 0x0 },
> + { 0x190206, 0x0 },
> + { 0x290206, 0x0 },
> + { 0x90207, 0x0 },
> + { 0x190207, 0x0 },
> + { 0x290207, 0x0 },
> + { 0x90208, 0x0 },
> + { 0x190208, 0x0 },
> + { 0x290208, 0x0 },
> + { 0x10062, 0x0 },
> + { 0x10162, 0x0 },
> + { 0x10262, 0x0 },
> + { 0x10362, 0x0 },
> + { 0x10462, 0x0 },
> + { 0x10562, 0x0 },
> + { 0x10662, 0x0 },
> + { 0x10762, 0x0 },
> + { 0x10862, 0x0 },
> + { 0x11062, 0x0 },
> + { 0x11162, 0x0 },
> + { 0x11262, 0x0 },
> + { 0x11362, 0x0 },
> + { 0x11462, 0x0 },
> + { 0x11562, 0x0 },
> + { 0x11662, 0x0 },
> + { 0x11762, 0x0 },
> + { 0x11862, 0x0 },
> + { 0x12062, 0x0 },
> + { 0x12162, 0x0 },
> + { 0x12262, 0x0 },
> + { 0x12362, 0x0 },
> + { 0x12462, 0x0 },
> + { 0x12562, 0x0 },
> + { 0x12662, 0x0 },
> + { 0x12762, 0x0 },
> + { 0x12862, 0x0 },
> + { 0x13062, 0x0 },
> + { 0x13162, 0x0 },
> + { 0x13262, 0x0 },
> + { 0x13362, 0x0 },
> + { 0x13462, 0x0 },
> + { 0x13562, 0x0 },
> + { 0x13662, 0x0 },
> + { 0x13762, 0x0 },
> + { 0x13862, 0x0 },
> + { 0x20077, 0x0 },
> + { 0x10001, 0x0 },
> + { 0x11001, 0x0 },
> + { 0x12001, 0x0 },
> + { 0x13001, 0x0 },
> + { 0x10040, 0x0 },
> + { 0x10140, 0x0 },
> + { 0x10240, 0x0 },
> + { 0x10340, 0x0 },
> + { 0x10440, 0x0 },
> + { 0x10540, 0x0 },
> + { 0x10640, 0x0 },
> + { 0x10740, 0x0 },
> + { 0x10840, 0x0 },
> + { 0x10030, 0x0 },
> + { 0x10130, 0x0 },
> + { 0x10230, 0x0 },
> + { 0x10330, 0x0 },
> + { 0x10430, 0x0 },
> + { 0x10530, 0x0 },
> + { 0x10630, 0x0 },
> + { 0x10730, 0x0 },
> + { 0x10830, 0x0 },
> + { 0x11040, 0x0 },
> + { 0x11140, 0x0 },
> + { 0x11240, 0x0 },
> + { 0x11340, 0x0 },
> + { 0x11440, 0x0 },
> + { 0x11540, 0x0 },
> + { 0x11640, 0x0 },
> + { 0x11740, 0x0 },
> + { 0x11840, 0x0 },
> + { 0x11030, 0x0 },
> + { 0x11130, 0x0 },
> + { 0x11230, 0x0 },
> + { 0x11330, 0x0 },
> + { 0x11430, 0x0 },
> + { 0x11530, 0x0 },
> + { 0x11630, 0x0 },
> + { 0x11730, 0x0 },
> + { 0x11830, 0x0 },
> + { 0x12040, 0x0 },
> + { 0x12140, 0x0 },
> + { 0x12240, 0x0 },
> + { 0x12340, 0x0 },
> + { 0x12440, 0x0 },
> + { 0x12540, 0x0 },
> + { 0x12640, 0x0 },
> + { 0x12740, 0x0 },
> + { 0x12840, 0x0 },
> + { 0x12030, 0x0 },
> + { 0x12130, 0x0 },
> + { 0x12230, 0x0 },
> + { 0x12330, 0x0 },
> + { 0x12430, 0x0 },
> + { 0x12530, 0x0 },
> + { 0x12630, 0x0 },
> + { 0x12730, 0x0 },
> + { 0x12830, 0x0 },
> + { 0x13040, 0x0 },
> + { 0x13140, 0x0 },
> + { 0x13240, 0x0 },
> + { 0x13340, 0x0 },
> + { 0x13440, 0x0 },
> + { 0x13540, 0x0 },
> + { 0x13640, 0x0 },
> + { 0x13740, 0x0 },
> + { 0x13840, 0x0 },
> + { 0x13030, 0x0 },
> + { 0x13130, 0x0 },
> + { 0x13230, 0x0 },
> + { 0x13330, 0x0 },
> + { 0x13430, 0x0 },
> + { 0x13530, 0x0 },
> + { 0x13630, 0x0 },
> + { 0x13730, 0x0 },
> + { 0x13830, 0x0 },
> +};
The same as above. Please look into imx6q DDR3 training code.
> +
> +/* P0 message block paremeter for training firmware */
> +struct dram_cfg_param lpddr4_fsp0_cfg[] = {
> + { 0xd0000, 0x0 },
> + { 0x54000, 0x0 },
> + { 0x54001, 0x0 },
> + { 0x54002, 0x0 },
> + { 0x54003, 0xbb8 },
> + { 0x54004, 0x2 },
> + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY
> Ron/Rtt
> + { 0x54006, LPDDR4_PHY_VREF_VALUE },
> + { 0x54007, 0x0 },
> + { 0x54008, 0x131f },
> + { 0x54009, 0xc8 },
> + { 0x5400a, 0x0 },
> + { 0x5400b, 0x2 },
> + { 0x5400c, 0x0 },
> + { 0x5400d, 0x0 },
> + { 0x5400e, 0x0 },
> + { 0x5400f, 0x0 },
> + { 0x54010, 0x0 },
> + { 0x54011, 0x0 },
> + { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
> + { 0x54013, 0x0 },
> + { 0x54014, 0x0 },
> + { 0x54015, 0x0 },
> + { 0x54016, 0x0 },
> + { 0x54017, 0x0 },
> + { 0x54018, 0x0 },
> + { 0x54019, 0x2dd4 },
> + { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
> + { 0x5401b, 0x4d66 },
> + { 0x5401c, 0x4d08 },
> + { 0x5401d, 0x0 },
> + { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
> + { 0x5401f, 0x2dd4 },
> + { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
> + { 0x54021, 0x4d66 },
> + { 0x54022, 0x4d08 },
> + { 0x54023, 0x0 },
> + { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
> + { 0x54025, 0x0 },
> + { 0x54026, 0x0 },
> + { 0x54027, 0x0 },
> + { 0x54028, 0x0 },
> + { 0x54029, 0x0 },
> + { 0x5402a, 0x0 },
> + { 0x5402b, 0x1000 },
> + { 0x5402c, LPDDR4_CS },
> + { 0x5402d, 0x0 },
> + { 0x5402e, 0x0 },
> + { 0x5402f, 0x0 },
> + { 0x54030, 0x0 },
> + { 0x54031, 0x0 },
> + { 0x54032, 0xd400 },
> + { 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
> + { 0x54034, 0x6600 },
> + { 0x54035, 0x84d },
> + { 0x54036, 0x4d },
> + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
> + { 0x54038, 0xd400 },
> + { 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
> + { 0x5403a, 0x6600 },
> + { 0x5403b, 0x84d },
> + { 0x5403c, 0x4d },
> + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
> + { 0x5403e, 0x0 },
> + { 0x5403f, 0x0 },
> + { 0x54040, 0x0 },
> + { 0x54041, 0x0 },
> + { 0x54042, 0x0 },
> + { 0x54043, 0x0 },
> + { 0x54044, 0x0 },
> + { 0xd0000, 0x1 },
> +};
> +
> +/* P1 message block paremeter for training firmware */
> +struct dram_cfg_param lpddr4_fsp1_cfg[] = {
> + { 0xd0000, 0x0 },
> + { 0x54000, 0x0 },
> + { 0x54001, 0x0 },
> + { 0x54002, 0x101 },
> + { 0x54003, 0x190 },
> + { 0x54004, 0x2 },
> + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY
> Ron/Rtt
> + { 0x54006, LPDDR4_PHY_VREF_VALUE },
> + { 0x54007, 0x0 },
> + { 0x54008, 0x121f },
> + { 0x54009, 0xc8 },
> + { 0x5400a, 0x0 },
> + { 0x5400b, 0x2 },
> + { 0x5400c, 0x0 },
> + { 0x5400d, 0x0 },
> + { 0x5400e, 0x0 },
> + { 0x5400f, 0x0 },
> + { 0x54010, 0x0 },
> + { 0x54011, 0x0 },
> + { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
> + { 0x54013, 0x0 },
> + { 0x54014, 0x0 },
> + { 0x54015, 0x0 },
> + { 0x54016, 0x0 },
> + { 0x54017, 0x0 },
> + { 0x54018, 0x0 },
> + { 0x54019, 0x84 },
> + { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
> + { 0x5401b, 0x4d66 },
> + { 0x5401c, 0x4d08 },
> + { 0x5401d, 0x0 },
> + { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
> + { 0x5401f, 0x84 },
> + { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
> + { 0x54021, 0x4d66 },
> + { 0x54022, 0x4d08 },
> + { 0x54023, 0x0 },
> + { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
> + { 0x54025, 0x0 },
> + { 0x54026, 0x0 },
> + { 0x54027, 0x0 },
> + { 0x54028, 0x0 },
> + { 0x54029, 0x0 },
> + { 0x5402a, 0x0 },
> + { 0x5402b, 0x1000 },
> + { 0x5402c, LPDDR4_CS },
> + { 0x5402d, 0x0 },
> + { 0x5402e, 0x0 },
> + { 0x5402f, 0x0 },
> + { 0x54030, 0x0 },
> + { 0x54031, 0x0 },
> + { 0x54032, 0x8400 },
> + { 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
> + { 0x54034, 0x6600 },
> + { 0x54035, 0x84d },
> + { 0x54036, 0x4d },
> + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
> + { 0x54038, 0x8400 },
> + { 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
> + { 0x5403a, 0x6600 },
> + { 0x5403b, 0x84d },
> + { 0x5403c, 0x4d },
> + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
> + { 0x5403e, 0x0 },
> + { 0x5403f, 0x0 },
> + { 0x54040, 0x0 },
> + { 0x54041, 0x0 },
> + { 0x54042, 0x0 },
> + { 0x54043, 0x0 },
> + { 0x54044, 0x0 },
> + { 0xd0000, 0x1 },
> +};
> +
> +/* P1 message block paremeter for training firmware */
> +struct dram_cfg_param lpddr4_fsp2_cfg[] = {
> + { 0xd0000, 0x0 },
> + { 0x54000, 0x0 },
> + { 0x54001, 0x0 },
> + { 0x54002, 0x102 },
> + { 0x54003, 0x64 },
> + { 0x54004, 0x2 },
> + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY
> Ron/Rtt
> + { 0x54006, LPDDR4_PHY_VREF_VALUE },
> + { 0x54007, 0x0 },
> + { 0x54008, 0x121f },
> + { 0x54009, 0xc8 },
> + { 0x5400a, 0x0 },
> + { 0x5400b, 0x2 },
> + { 0x5400c, 0x0 },
> + { 0x5400d, 0x0 },
> + { 0x5400e, 0x0 },
> + { 0x5400f, 0x0 },
> + { 0x54010, 0x0 },
> + { 0x54011, 0x0 },
> + { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
> + { 0x54013, 0x0 },
> + { 0x54014, 0x0 },
> + { 0x54015, 0x0 },
> + { 0x54016, 0x0 },
> + { 0x54017, 0x0 },
> + { 0x54018, 0x0 },
> + { 0x54019, 0x84 },
> + { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
> + { 0x5401b, 0x4d66 },
> + { 0x5401c, 0x4d08 },
> + { 0x5401d, 0x0 },
> + { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
> + { 0x5401f, 0x84 },
> + { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
> + { 0x54021, 0x4d66 },
> + { 0x54022, 0x4d08 },
> + { 0x54023, 0x0 },
> + { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
> + { 0x54025, 0x0 },
> + { 0x54026, 0x0 },
> + { 0x54027, 0x0 },
> + { 0x54028, 0x0 },
> + { 0x54029, 0x0 },
> + { 0x5402a, 0x0 },
> + { 0x5402b, 0x1000 },
> + { 0x5402c, LPDDR4_CS },
> + { 0x5402d, 0x0 },
> + { 0x5402e, 0x0 },
> + { 0x5402f, 0x0 },
> + { 0x54030, 0x0 },
> + { 0x54031, 0x0 },
> + { 0x54032, 0x8400 },
> + { 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
> + { 0x54034, 0x6600 },
> + { 0x54035, 0x84d },
> + { 0x54036, 0x4d },
> + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
> + { 0x54038, 0x8400 },
> + { 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
> + { 0x5403a, 0x6600 },
> + { 0x5403b, 0x84d },
> + { 0x5403c, 0x4d },
> + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
> + { 0x5403e, 0x0 },
> + { 0x5403f, 0x0 },
> + { 0x54040, 0x0 },
> + { 0x54041, 0x0 },
> + { 0x54042, 0x0 },
> + { 0x54043, 0x0 },
> + { 0x54044, 0x0 },
> + { 0xd0000, 0x1 },
> +};
> +
> +/* P0 2D message block paremeter for training firmware */
> +struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
> + { 0xd0000, 0x0 },
> + { 0x54000, 0x0 },
> + { 0x54001, 0x0 },
> + { 0x54002, 0x0 },
> + { 0x54003, 0xbb8 },
> + { 0x54004, 0x2 },
> + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY
> Ron/Rtt
> + { 0x54006, LPDDR4_PHY_VREF_VALUE },
> + { 0x54007, 0x0 },
> + { 0x54008, 0x61 },
> + { 0x54009, 0xc8 },
> + { 0x5400a, 0x0 },
> + { 0x5400b, 0x2 },
> + { 0x5400c, 0x0 },
> + { 0x5400d, 0x0 },
> + { 0x5400e, 0x0 },
> + { 0x5400f, 0x100 },
> + { 0x54010, 0x1f7f },
> + { 0x54011, 0x0 },
> + { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
> + { 0x54013, 0x0 },
> + { 0x54014, 0x0 },
> + { 0x54015, 0x0 },
> + { 0x54016, 0x0 },
> + { 0x54017, 0x0 },
> + { 0x54018, 0x0 },
> + { 0x54019, 0x2dd4 },
> + { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
> + { 0x5401b, 0x4d66 },
> + { 0x5401c, 0x4d08 },
> + { 0x5401d, 0x0 },
> + { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
> + { 0x5401f, 0x2dd4 },
> + { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
> + { 0x54021, 0x4d66 },
> + { 0x54022, 0x4d08 },
> + { 0x54023, 0x0 },
> + { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
> + { 0x54025, 0x0 },
> + { 0x54026, 0x0 },
> + { 0x54027, 0x0 },
> + { 0x54028, 0x0 },
> + { 0x54029, 0x0 },
> + { 0x5402a, 0x0 },
> + { 0x5402b, 0x1000 },
> + { 0x5402c, LPDDR4_CS },
> + { 0x5402d, 0x0 },
> + { 0x5402e, 0x0 },
> + { 0x5402f, 0x0 },
> + { 0x54030, 0x0 },
> + { 0x54031, 0x0 },
> + { 0x54032, 0xd400 },
> + { 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
> + { 0x54034, 0x6600 },
> + { 0x54035, 0x84d },
> + { 0x54036, 0x4d },
> + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
> + { 0x54038, 0xd400 },
> + { 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
> + { 0x5403a, 0x6600 },
> + { 0x5403b, 0x84d },
> + { 0x5403c, 0x4d },
> + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
> + { 0x5403e, 0x0 },
> + { 0x5403f, 0x0 },
> + { 0x54040, 0x0 },
> + { 0x54041, 0x0 },
> + { 0x54042, 0x0 },
> + { 0x54043, 0x0 },
> + { 0x54044, 0x0 },
> + { 0xd0000, 0x1 },
> +};
> +
> +/* DRAM PHY init engine image */
> +struct dram_cfg_param lpddr4_phy_pie[] = {
> + { 0xd0000, 0x0 },
> + { 0x90000, 0x10 },
> + { 0x90001, 0x400 },
> + { 0x90002, 0x10e },
> + { 0x90003, 0x0 },
> + { 0x90004, 0x0 },
> + { 0x90005, 0x8 },
> + { 0x90029, 0xb },
> + { 0x9002a, 0x480 },
> + { 0x9002b, 0x109 },
> + { 0x9002c, 0x8 },
> + { 0x9002d, 0x448 },
> + { 0x9002e, 0x139 },
> + { 0x9002f, 0x8 },
> + { 0x90030, 0x478 },
> + { 0x90031, 0x109 },
> + { 0x90032, 0x0 },
> + { 0x90033, 0xe8 },
> + { 0x90034, 0x109 },
> + { 0x90035, 0x2 },
> + { 0x90036, 0x10 },
> + { 0x90037, 0x139 },
> + { 0x90038, 0xf },
> + { 0x90039, 0x7c0 },
> + { 0x9003a, 0x139 },
> + { 0x9003b, 0x44 },
> + { 0x9003c, 0x630 },
> + { 0x9003d, 0x159 },
> + { 0x9003e, 0x14f },
> + { 0x9003f, 0x630 },
> + { 0x90040, 0x159 },
> + { 0x90041, 0x47 },
> + { 0x90042, 0x630 },
> + { 0x90043, 0x149 },
> + { 0x90044, 0x4f },
> + { 0x90045, 0x630 },
> + { 0x90046, 0x179 },
> + { 0x90047, 0x8 },
> + { 0x90048, 0xe0 },
> + { 0x90049, 0x109 },
> + { 0x9004a, 0x0 },
> + { 0x9004b, 0x7c8 },
> + { 0x9004c, 0x109 },
> + { 0x9004d, 0x0 },
> + { 0x9004e, 0x1 },
> + { 0x9004f, 0x8 },
> + { 0x90050, 0x0 },
> + { 0x90051, 0x45a },
> + { 0x90052, 0x9 },
> + { 0x90053, 0x0 },
> + { 0x90054, 0x448 },
> + { 0x90055, 0x109 },
> + { 0x90056, 0x40 },
> + { 0x90057, 0x630 },
> + { 0x90058, 0x179 },
> + { 0x90059, 0x1 },
> + { 0x9005a, 0x618 },
> + { 0x9005b, 0x109 },
> + { 0x9005c, 0x40c0 },
> + { 0x9005d, 0x630 },
> + { 0x9005e, 0x149 },
> + { 0x9005f, 0x8 },
> + { 0x90060, 0x4 },
> + { 0x90061, 0x48 },
> + { 0x90062, 0x4040 },
> + { 0x90063, 0x630 },
> + { 0x90064, 0x149 },
> + { 0x90065, 0x0 },
> + { 0x90066, 0x4 },
> + { 0x90067, 0x48 },
> + { 0x90068, 0x40 },
> + { 0x90069, 0x630 },
> + { 0x9006a, 0x149 },
> + { 0x9006b, 0x10 },
> + { 0x9006c, 0x4 },
> + { 0x9006d, 0x18 },
> + { 0x9006e, 0x0 },
> + { 0x9006f, 0x4 },
> + { 0x90070, 0x78 },
> + { 0x90071, 0x549 },
> + { 0x90072, 0x630 },
> + { 0x90073, 0x159 },
> + { 0x90074, 0xd49 },
> + { 0x90075, 0x630 },
> + { 0x90076, 0x159 },
> + { 0x90077, 0x94a },
> + { 0x90078, 0x630 },
> + { 0x90079, 0x159 },
> + { 0x9007a, 0x441 },
> + { 0x9007b, 0x630 },
> + { 0x9007c, 0x149 },
> + { 0x9007d, 0x42 },
> + { 0x9007e, 0x630 },
> + { 0x9007f, 0x149 },
> + { 0x90080, 0x1 },
> + { 0x90081, 0x630 },
> + { 0x90082, 0x149 },
> + { 0x90083, 0x0 },
> + { 0x90084, 0xe0 },
> + { 0x90085, 0x109 },
> + { 0x90086, 0xa },
> + { 0x90087, 0x10 },
> + { 0x90088, 0x109 },
> + { 0x90089, 0x9 },
> + { 0x9008a, 0x3c0 },
> + { 0x9008b, 0x149 },
> + { 0x9008c, 0x9 },
> + { 0x9008d, 0x3c0 },
> + { 0x9008e, 0x159 },
> + { 0x9008f, 0x18 },
> + { 0x90090, 0x10 },
> + { 0x90091, 0x109 },
> + { 0x90092, 0x0 },
> + { 0x90093, 0x3c0 },
> + { 0x90094, 0x109 },
> + { 0x90095, 0x18 },
> + { 0x90096, 0x4 },
> + { 0x90097, 0x48 },
> + { 0x90098, 0x18 },
> + { 0x90099, 0x4 },
> + { 0x9009a, 0x58 },
> + { 0x9009b, 0xa },
> + { 0x9009c, 0x10 },
> + { 0x9009d, 0x109 },
> + { 0x9009e, 0x2 },
> + { 0x9009f, 0x10 },
> + { 0x900a0, 0x109 },
> + { 0x900a1, 0x5 },
> + { 0x900a2, 0x7c0 },
> + { 0x900a3, 0x109 },
> + { 0x900a4, 0x10 },
> + { 0x900a5, 0x10 },
> + { 0x900a6, 0x109 },
> + { 0x40000, 0x811 },
> + { 0x40020, 0x880 },
> + { 0x40040, 0x0 },
> + { 0x40060, 0x0 },
> + { 0x40001, 0x4008 },
> + { 0x40021, 0x83 },
> + { 0x40041, 0x4f },
> + { 0x40061, 0x0 },
> + { 0x40002, 0x4040 },
> + { 0x40022, 0x83 },
> + { 0x40042, 0x51 },
> + { 0x40062, 0x0 },
> + { 0x40003, 0x811 },
> + { 0x40023, 0x880 },
> + { 0x40043, 0x0 },
> + { 0x40063, 0x0 },
> + { 0x40004, 0x720 },
> + { 0x40024, 0xf },
> + { 0x40044, 0x1740 },
> + { 0x40064, 0x0 },
> + { 0x40005, 0x16 },
> + { 0x40025, 0x83 },
> + { 0x40045, 0x4b },
> + { 0x40065, 0x0 },
> + { 0x40006, 0x716 },
> + { 0x40026, 0xf },
> + { 0x40046, 0x2001 },
> + { 0x40066, 0x0 },
> + { 0x40007, 0x716 },
> + { 0x40027, 0xf },
> + { 0x40047, 0x2800 },
> + { 0x40067, 0x0 },
> + { 0x40008, 0x716 },
> + { 0x40028, 0xf },
> + { 0x40048, 0xf00 },
> + { 0x40068, 0x0 },
> + { 0x40009, 0x720 },
> + { 0x40029, 0xf },
> + { 0x40049, 0x1400 },
> + { 0x40069, 0x0 },
> + { 0x4000a, 0xe08 },
> + { 0x4002a, 0xc15 },
> + { 0x4004a, 0x0 },
> + { 0x4006a, 0x0 },
> + { 0x4000b, 0x623 },
> + { 0x4002b, 0x15 },
> + { 0x4004b, 0x0 },
> + { 0x4006b, 0x0 },
> + { 0x4000c, 0x4028 },
> + { 0x4002c, 0x80 },
> + { 0x4004c, 0x0 },
> + { 0x4006c, 0x0 },
> + { 0x4000d, 0xe08 },
> + { 0x4002d, 0xc1a },
> + { 0x4004d, 0x0 },
> + { 0x4006d, 0x0 },
> + { 0x4000e, 0x623 },
> + { 0x4002e, 0x1a },
> + { 0x4004e, 0x0 },
> + { 0x4006e, 0x0 },
> + { 0x4000f, 0x4040 },
> + { 0x4002f, 0x80 },
> + { 0x4004f, 0x0 },
> + { 0x4006f, 0x0 },
> + { 0x40010, 0x2604 },
> + { 0x40030, 0x15 },
> + { 0x40050, 0x0 },
> + { 0x40070, 0x0 },
> + { 0x40011, 0x708 },
> + { 0x40031, 0x5 },
> + { 0x40051, 0x0 },
> + { 0x40071, 0x2002 },
> + { 0x40012, 0x8 },
> + { 0x40032, 0x80 },
> + { 0x40052, 0x0 },
> + { 0x40072, 0x0 },
> + { 0x40013, 0x2604 },
> + { 0x40033, 0x1a },
> + { 0x40053, 0x0 },
> + { 0x40073, 0x0 },
> + { 0x40014, 0x708 },
> + { 0x40034, 0xa },
> + { 0x40054, 0x0 },
> + { 0x40074, 0x2002 },
> + { 0x40015, 0x4040 },
> + { 0x40035, 0x80 },
> + { 0x40055, 0x0 },
> + { 0x40075, 0x0 },
> + { 0x40016, 0x60a },
> + { 0x40036, 0x15 },
> + { 0x40056, 0x1200 },
> + { 0x40076, 0x0 },
> + { 0x40017, 0x61a },
> + { 0x40037, 0x15 },
> + { 0x40057, 0x1300 },
> + { 0x40077, 0x0 },
> + { 0x40018, 0x60a },
> + { 0x40038, 0x1a },
> + { 0x40058, 0x1200 },
> + { 0x40078, 0x0 },
> + { 0x40019, 0x642 },
> + { 0x40039, 0x1a },
> + { 0x40059, 0x1300 },
> + { 0x40079, 0x0 },
> + { 0x4001a, 0x4808 },
> + { 0x4003a, 0x880 },
> + { 0x4005a, 0x0 },
> + { 0x4007a, 0x0 },
> + { 0x900a7, 0x0 },
> + { 0x900a8, 0x790 },
> + { 0x900a9, 0x11a },
> + { 0x900aa, 0x8 },
> + { 0x900ab, 0x7aa },
> + { 0x900ac, 0x2a },
> + { 0x900ad, 0x10 },
> + { 0x900ae, 0x7b2 },
> + { 0x900af, 0x2a },
> + { 0x900b0, 0x0 },
> + { 0x900b1, 0x7c8 },
> + { 0x900b2, 0x109 },
> + { 0x900b3, 0x10 },
> + { 0x900b4, 0x2a8 },
> + { 0x900b5, 0x129 },
> + { 0x900b6, 0x8 },
> + { 0x900b7, 0x370 },
> + { 0x900b8, 0x129 },
> + { 0x900b9, 0xa },
> + { 0x900ba, 0x3c8 },
> + { 0x900bb, 0x1a9 },
> + { 0x900bc, 0xc },
> + { 0x900bd, 0x408 },
> + { 0x900be, 0x199 },
> + { 0x900bf, 0x14 },
> + { 0x900c0, 0x790 },
> + { 0x900c1, 0x11a },
> + { 0x900c2, 0x8 },
> + { 0x900c3, 0x4 },
> + { 0x900c4, 0x18 },
> + { 0x900c5, 0xe },
> + { 0x900c6, 0x408 },
> + { 0x900c7, 0x199 },
> + { 0x900c8, 0x8 },
> + { 0x900c9, 0x8568 },
> + { 0x900ca, 0x108 },
> + { 0x900cb, 0x18 },
> + { 0x900cc, 0x790 },
> + { 0x900cd, 0x16a },
> + { 0x900ce, 0x8 },
> + { 0x900cf, 0x1d8 },
> + { 0x900d0, 0x169 },
> + { 0x900d1, 0x10 },
> + { 0x900d2, 0x8558 },
> + { 0x900d3, 0x168 },
> + { 0x900d4, 0x70 },
> + { 0x900d5, 0x788 },
> + { 0x900d6, 0x16a },
> + { 0x900d7, 0x1ff8 },
> + { 0x900d8, 0x85a8 },
> + { 0x900d9, 0x1e8 },
> + { 0x900da, 0x50 },
> + { 0x900db, 0x798 },
> + { 0x900dc, 0x16a },
> + { 0x900dd, 0x60 },
> + { 0x900de, 0x7a0 },
> + { 0x900df, 0x16a },
> + { 0x900e0, 0x8 },
> + { 0x900e1, 0x8310 },
> + { 0x900e2, 0x168 },
> + { 0x900e3, 0x8 },
> + { 0x900e4, 0xa310 },
> + { 0x900e5, 0x168 },
> + { 0x900e6, 0xa },
> + { 0x900e7, 0x408 },
> + { 0x900e8, 0x169 },
> + { 0x900e9, 0x6e },
> + { 0x900ea, 0x0 },
> + { 0x900eb, 0x68 },
> + { 0x900ec, 0x0 },
> + { 0x900ed, 0x408 },
> + { 0x900ee, 0x169 },
> + { 0x900ef, 0x0 },
> + { 0x900f0, 0x8310 },
> + { 0x900f1, 0x168 },
> + { 0x900f2, 0x0 },
> + { 0x900f3, 0xa310 },
> + { 0x900f4, 0x168 },
> + { 0x900f5, 0x1ff8 },
> + { 0x900f6, 0x85a8 },
> + { 0x900f7, 0x1e8 },
> + { 0x900f8, 0x68 },
> + { 0x900f9, 0x798 },
> + { 0x900fa, 0x16a },
> + { 0x900fb, 0x78 },
> + { 0x900fc, 0x7a0 },
> + { 0x900fd, 0x16a },
> + { 0x900fe, 0x68 },
> + { 0x900ff, 0x790 },
> + { 0x90100, 0x16a },
> + { 0x90101, 0x8 },
> + { 0x90102, 0x8b10 },
> + { 0x90103, 0x168 },
> + { 0x90104, 0x8 },
> + { 0x90105, 0xab10 },
> + { 0x90106, 0x168 },
> + { 0x90107, 0xa },
> + { 0x90108, 0x408 },
> + { 0x90109, 0x169 },
> + { 0x9010a, 0x58 },
> + { 0x9010b, 0x0 },
> + { 0x9010c, 0x68 },
> + { 0x9010d, 0x0 },
> + { 0x9010e, 0x408 },
> + { 0x9010f, 0x169 },
> + { 0x90110, 0x0 },
> + { 0x90111, 0x8b10 },
> + { 0x90112, 0x168 },
> + { 0x90113, 0x0 },
> + { 0x90114, 0xab10 },
> + { 0x90115, 0x168 },
> + { 0x90116, 0x0 },
> + { 0x90117, 0x1d8 },
> + { 0x90118, 0x169 },
> + { 0x90119, 0x80 },
> + { 0x9011a, 0x790 },
> + { 0x9011b, 0x16a },
> + { 0x9011c, 0x18 },
> + { 0x9011d, 0x7aa },
> + { 0x9011e, 0x6a },
> + { 0x9011f, 0xa },
> + { 0x90120, 0x0 },
> + { 0x90121, 0x1e9 },
> + { 0x90122, 0x8 },
> + { 0x90123, 0x8080 },
> + { 0x90124, 0x108 },
> + { 0x90125, 0xf },
> + { 0x90126, 0x408 },
> + { 0x90127, 0x169 },
> + { 0x90128, 0xc },
> + { 0x90129, 0x0 },
> + { 0x9012a, 0x68 },
> + { 0x9012b, 0x9 },
> + { 0x9012c, 0x0 },
> + { 0x9012d, 0x1a9 },
> + { 0x9012e, 0x0 },
> + { 0x9012f, 0x408 },
> + { 0x90130, 0x169 },
> + { 0x90131, 0x0 },
> + { 0x90132, 0x8080 },
> + { 0x90133, 0x108 },
> + { 0x90134, 0x8 },
> + { 0x90135, 0x7aa },
> + { 0x90136, 0x6a },
> + { 0x90137, 0x0 },
> + { 0x90138, 0x8568 },
> + { 0x90139, 0x108 },
> + { 0x9013a, 0xb7 },
> + { 0x9013b, 0x790 },
> + { 0x9013c, 0x16a },
> + { 0x9013d, 0x1f },
> + { 0x9013e, 0x0 },
> + { 0x9013f, 0x68 },
> + { 0x90140, 0x8 },
> + { 0x90141, 0x8558 },
> + { 0x90142, 0x168 },
> + { 0x90143, 0xf },
> + { 0x90144, 0x408 },
> + { 0x90145, 0x169 },
> + { 0x90146, 0xc },
> + { 0x90147, 0x0 },
> + { 0x90148, 0x68 },
> + { 0x90149, 0x0 },
> + { 0x9014a, 0x408 },
> + { 0x9014b, 0x169 },
> + { 0x9014c, 0x0 },
> + { 0x9014d, 0x8558 },
> + { 0x9014e, 0x168 },
> + { 0x9014f, 0x8 },
> + { 0x90150, 0x3c8 },
> + { 0x90151, 0x1a9 },
> + { 0x90152, 0x3 },
> + { 0x90153, 0x370 },
> + { 0x90154, 0x129 },
> + { 0x90155, 0x20 },
> + { 0x90156, 0x2aa },
> + { 0x90157, 0x9 },
> + { 0x90158, 0x0 },
> + { 0x90159, 0x400 },
> + { 0x9015a, 0x10e },
> + { 0x9015b, 0x8 },
> + { 0x9015c, 0xe8 },
> + { 0x9015d, 0x109 },
> + { 0x9015e, 0x0 },
> + { 0x9015f, 0x8140 },
> + { 0x90160, 0x10c },
> + { 0x90161, 0x10 },
> + { 0x90162, 0x8138 },
> + { 0x90163, 0x10c },
> + { 0x90164, 0x8 },
> + { 0x90165, 0x7c8 },
> + { 0x90166, 0x101 },
> + { 0x90167, 0x8 },
> + { 0x90168, 0x0 },
> + { 0x90169, 0x8 },
> + { 0x9016a, 0x8 },
> + { 0x9016b, 0x448 },
> + { 0x9016c, 0x109 },
> + { 0x9016d, 0xf },
> + { 0x9016e, 0x7c0 },
> + { 0x9016f, 0x109 },
> + { 0x90170, 0x0 },
> + { 0x90171, 0xe8 },
> + { 0x90172, 0x109 },
> + { 0x90173, 0x47 },
> + { 0x90174, 0x630 },
> + { 0x90175, 0x109 },
> + { 0x90176, 0x8 },
> + { 0x90177, 0x618 },
> + { 0x90178, 0x109 },
> + { 0x90179, 0x8 },
> + { 0x9017a, 0xe0 },
> + { 0x9017b, 0x109 },
> + { 0x9017c, 0x0 },
> + { 0x9017d, 0x7c8 },
> + { 0x9017e, 0x109 },
> + { 0x9017f, 0x8 },
> + { 0x90180, 0x8140 },
> + { 0x90181, 0x10c },
> + { 0x90182, 0x0 },
> + { 0x90183, 0x1 },
> + { 0x90184, 0x8 },
> + { 0x90185, 0x8 },
> + { 0x90186, 0x4 },
> + { 0x90187, 0x8 },
> + { 0x90188, 0x8 },
> + { 0x90189, 0x7c8 },
> + { 0x9018a, 0x101 },
> + { 0x90006, 0x0 },
> + { 0x90007, 0x0 },
> + { 0x90008, 0x8 },
> + { 0x90009, 0x0 },
> + { 0x9000a, 0x0 },
> + { 0x9000b, 0x0 },
> + { 0xd00e7, 0x400 },
> + { 0x90017, 0x0 },
> + { 0x9001f, 0x2a },
> + { 0x90026, 0x6a },
> + { 0x400d0, 0x0 },
> + { 0x400d1, 0x101 },
> + { 0x400d2, 0x105 },
> + { 0x400d3, 0x107 },
> + { 0x400d4, 0x10f },
> + { 0x400d5, 0x202 },
> + { 0x400d6, 0x20a },
> + { 0x400d7, 0x20b },
> + { 0x2003a, 0x2 },
> + { 0x2000b, 0x5d },
> + { 0x2000c, 0xbb },
> + { 0x2000d, 0x753 },
> + { 0x2000e, 0x2c },
> + { 0x12000b, 0xc },
> + { 0x12000c, 0x19 },
> + { 0x12000d, 0xfa },
> + { 0x12000e, 0x10 },
> + { 0x22000b, 0x3 },
> + { 0x22000c, 0x6 },
> + { 0x22000d, 0x3e },
> + { 0x22000e, 0x10 },
> + { 0x9000c, 0x0 },
> + { 0x9000d, 0x173 },
> + { 0x9000e, 0x60 },
> + { 0x9000f, 0x6110 },
> + { 0x90010, 0x2152 },
> + { 0x90011, 0xdfbd },
> + { 0x90012, 0x60 },
> + { 0x90013, 0x6152 },
> + { 0x20010, 0x5a },
> + { 0x20011, 0x3 },
> + { 0x40080, 0xe0 },
> + { 0x40081, 0x12 },
> + { 0x40082, 0xe0 },
> + { 0x40083, 0x12 },
> + { 0x40084, 0xe0 },
> + { 0x40085, 0x12 },
> + { 0x140080, 0xe0 },
> + { 0x140081, 0x12 },
> + { 0x140082, 0xe0 },
> + { 0x140083, 0x12 },
> + { 0x140084, 0xe0 },
> + { 0x140085, 0x12 },
> + { 0x240080, 0xe0 },
> + { 0x240081, 0x12 },
> + { 0x240082, 0xe0 },
> + { 0x240083, 0x12 },
> + { 0x240084, 0xe0 },
> + { 0x240085, 0x12 },
> + { 0x400fd, 0xf },
> + { 0x10011, 0x1 },
> + { 0x10012, 0x1 },
> + { 0x10013, 0x180 },
> + { 0x10018, 0x1 },
> + { 0x10002, 0x6209 },
> + { 0x100b2, 0x1 },
> + { 0x101b4, 0x1 },
> + { 0x102b4, 0x1 },
> + { 0x103b4, 0x1 },
> + { 0x104b4, 0x1 },
> + { 0x105b4, 0x1 },
> + { 0x106b4, 0x1 },
> + { 0x107b4, 0x1 },
> + { 0x108b4, 0x1 },
> + { 0x11011, 0x1 },
> + { 0x11012, 0x1 },
> + { 0x11013, 0x180 },
> + { 0x11018, 0x1 },
> + { 0x11002, 0x6209 },
> + { 0x110b2, 0x1 },
> + { 0x111b4, 0x1 },
> + { 0x112b4, 0x1 },
> + { 0x113b4, 0x1 },
> + { 0x114b4, 0x1 },
> + { 0x115b4, 0x1 },
> + { 0x116b4, 0x1 },
> + { 0x117b4, 0x1 },
> + { 0x118b4, 0x1 },
> + { 0x12011, 0x1 },
> + { 0x12012, 0x1 },
> + { 0x12013, 0x180 },
> + { 0x12018, 0x1 },
> + { 0x12002, 0x6209 },
> + { 0x120b2, 0x1 },
> + { 0x121b4, 0x1 },
> + { 0x122b4, 0x1 },
> + { 0x123b4, 0x1 },
> + { 0x124b4, 0x1 },
> + { 0x125b4, 0x1 },
> + { 0x126b4, 0x1 },
> + { 0x127b4, 0x1 },
> + { 0x128b4, 0x1 },
> + { 0x13011, 0x1 },
> + { 0x13012, 0x1 },
> + { 0x13013, 0x180 },
> + { 0x13018, 0x1 },
> + { 0x13002, 0x6209 },
> + { 0x130b2, 0x1 },
> + { 0x131b4, 0x1 },
> + { 0x132b4, 0x1 },
> + { 0x133b4, 0x1 },
> + { 0x134b4, 0x1 },
> + { 0x135b4, 0x1 },
> + { 0x136b4, 0x1 },
> + { 0x137b4, 0x1 },
> + { 0x138b4, 0x1 },
> + { 0x2003a, 0x2 },
> + { 0xc0080, 0x2 },
> + { 0xd0000, 0x1 },
> +};
The same as above.
> +
> +struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
> + {
> + /* P0 3000mts 1D */
> + .drate = 3000,
> + .fw_type = FW_1D_IMAGE,
> + .fsp_cfg = lpddr4_fsp0_cfg,
> + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg),
> + },
> + {
> + /* P0 3000mts 2D */
> + .drate = 3000,
> + .fw_type = FW_2D_IMAGE,
> + .fsp_cfg = lpddr4_fsp0_2d_cfg,
> + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg),
> + },
> + {
> + /* P1 400mts 1D */
> + .drate = 400,
> + .fw_type = FW_1D_IMAGE,
> + .fsp_cfg = lpddr4_fsp1_cfg,
> + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg),
> + },
> + {
> + /* P1 100mts 1D */
> + .drate = 100,
> + .fw_type = FW_1D_IMAGE,
> + .fsp_cfg = lpddr4_fsp2_cfg,
> + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg),
> + },
> +};
> +
> +/* lpddr4 timing config params on EVK board */
> +struct dram_timing_info dram_timing = {
> + .ddrc_cfg = lpddr4_ddrc_cfg,
> + .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
> + .ddrphy_cfg = lpddr4_ddrphy_cfg,
> + .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg),
> + .fsp_msg = lpddr4_dram_fsp_msg,
> + .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg),
> + .ddrphy_trained_csr = lpddr4_ddrphy_trained_csr,
> + .ddrphy_trained_csr_num =
> ARRAY_SIZE(lpddr4_ddrphy_trained_csr),
> + .ddrphy_pie = lpddr4_phy_pie,
> + .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
It would be best to get the above values calculated dynamically for
this SoC.
> +};
> diff --git a/board/freescale/imx8mm_evk/spl.c
> b/board/freescale/imx8mm_evk/spl.c new file mode 100644
> index 0000000000..cf1dfc2c2a
> --- /dev/null
> +++ b/board/freescale/imx8mm_evk/spl.c
> @@ -0,0 +1,187 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019 NXP
> + */
> +
> +#include <common.h>
> +#include <spl.h>
> +#include <asm/io.h>
> +#include <errno.h>
> +#include <asm/io.h>
> +#include <asm/mach-imx/iomux-v3.h>
> +#include <asm/arch/imx8mm_pins.h>
> +#include <asm/arch/sys_proto.h>
> +#include <power/pmic.h>
> +#include <asm/arch/clock.h>
> +#include <asm/mach-imx/gpio.h>
> +#include <asm/mach-imx/mxc_i2c.h>
> +#include <fsl_esdhc.h>
> +#include <mmc.h>
> +#include <asm/arch/ddr.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +void spl_dram_init(void)
> +{
> + ddr_init(&dram_timing);
> +}
> +
> +#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 18)
> +#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
> +
> +#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
> + PAD_CTL_PE | PAD_CTL_FSEL2)
> +#define USDHC_GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE1)
> +
> +static iomux_v3_cfg_t const usdhc3_pads[] = {
> + IMX8MM_PAD_NAND_WE_B_USDHC3_CLK |
> MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + IMX8MM_PAD_NAND_WP_B_USDHC3_CMD |
> MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + IMX8MM_PAD_NAND_DATA04_USDHC3_DATA0 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + IMX8MM_PAD_NAND_DATA05_USDHC3_DATA1 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + IMX8MM_PAD_NAND_DATA06_USDHC3_DATA2 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + IMX8MM_PAD_NAND_DATA07_USDHC3_DATA3 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + IMX8MM_PAD_NAND_RE_B_USDHC3_DATA4 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + IMX8MM_PAD_NAND_CE2_B_USDHC3_DATA5 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + IMX8MM_PAD_NAND_CE3_B_USDHC3_DATA6 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + IMX8MM_PAD_NAND_CLE_USDHC3_DATA7 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL), +};
> +
> +static iomux_v3_cfg_t const usdhc2_pads[] = {
> + IMX8MM_PAD_SD2_CLK_USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + IMX8MM_PAD_SD2_CMD_USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + IMX8MM_PAD_SD2_DATA0_USDHC2_DATA0 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + IMX8MM_PAD_SD2_DATA1_USDHC2_DATA1 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + IMX8MM_PAD_SD2_DATA2_USDHC2_DATA2 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + IMX8MM_PAD_SD2_RESET_B_GPIO2_IO19 |
> MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), +};
> +
> +/*
> + * The evk board uses DAT3 to detect CD card plugin,
> + * in u-boot we mux the pin to GPIO when doing board_mmc_getcd.
> + */
> +static iomux_v3_cfg_t const usdhc2_cd_pad =
> + IMX8MM_PAD_SD2_DATA3_GPIO2_IO18 |
> MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL); +
> +static iomux_v3_cfg_t const usdhc2_dat3_pad =
> + IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 |
> + MUX_PAD_CTRL(USDHC_PAD_CTRL);
> +
> +static struct fsl_esdhc_cfg usdhc_cfg[2] = {
> + {USDHC2_BASE_ADDR, 0, 1},
> + {USDHC3_BASE_ADDR, 0, 1},
> +};
> +
> +int board_mmc_init(bd_t *bis)
> +{
> + int i, ret;
> + /*
> + * According to the board_mmc_init() the following map is
> done:
> + * (U-Boot device node) (Physical Port)
> + * mmc0 USDHC1
> + * mmc1 USDHC2
> + */
> + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
> + switch (i) {
> + case 0:
> + usdhc_cfg[0].sdhc_clk =
> mxc_get_clock(MXC_ESDHC2_CLK);
> + imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
> +
> ARRAY_SIZE(usdhc2_pads));
> + gpio_request(USDHC2_PWR_GPIO,
> "usdhc2_reset");
> + gpio_direction_output(USDHC2_PWR_GPIO, 0);
> + udelay(500);
> + gpio_direction_output(USDHC2_PWR_GPIO, 1);
> + break;
> + case 1:
> + usdhc_cfg[1].sdhc_clk =
> mxc_get_clock(MXC_ESDHC3_CLK);
> + imx_iomux_v3_setup_multiple_pads(usdhc3_pads,
> +
> ARRAY_SIZE(usdhc3_pads));
> + break;
It would be best if you could enable DM/DTS in SPL too from the outset
(and share the SPL size).
Do you have any timeline for converting SPL to DM/DTS?
> + default:
> + printf("USDHC controllers %d not supported
> \n", i + 1);
> + return -EINVAL;
> + }
> +
> + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +int board_mmc_getcd(struct mmc *mmc)
> +{
> + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg
> *)mmc->priv;
> + int ret = 0;
> +
> + switch (cfg->esdhc_base) {
> + case USDHC3_BASE_ADDR:
> + ret = 1;
> + break;
> + case USDHC2_BASE_ADDR:
> + imx_iomux_v3_setup_pad(usdhc2_cd_pad);
> + gpio_request(USDHC2_CD_GPIO, "usdhc2 cd");
> + gpio_direction_input(USDHC2_CD_GPIO);
> +
> + /*
> + * Since it is the DAT3 pin, this pin is pulled to
> + * low voltage if no card
> + */
> + ret = gpio_get_value(USDHC2_CD_GPIO);
> +
> + imx_iomux_v3_setup_pad(usdhc2_dat3_pad);
> + return ret;
> + }
> +
> + return 1;
> +}
> +
> +void spl_board_init(void)
> +{
> + puts("Normal Boot\n");
> +}
> +
> +#ifdef CONFIG_SPL_LOAD_FIT
> +int board_fit_config_name_match(const char *name)
> +{
> + /* Just empty function now - can't decide what to choose */
> + debug("%s: %s\n", __func__, name);
> +
> + return 0;
> +}
> +#endif
> +
> +void board_init_f(ulong dummy)
> +{
> + int ret;
> +
> + /* Clear global data */
> + memset((void *)gd, 0, sizeof(gd_t));
> +
> + arch_cpu_init();
> +
> + init_uart_clk(1);
> +
> + board_early_init_f();
> +
> + timer_init();
> +
> + preloader_console_init();
> +
> + /* Clear the BSS. */
> + memset(__bss_start, 0, __bss_end - __bss_start);
> +
> + ret = spl_init();
> + if (ret) {
> + debug("spl_init() failed: %d\n", ret);
> + hang();
> + }
> +
> + enable_tzc380();
> +
> + /* DDR initialization */
> + spl_dram_init();
> +
> + board_init_r(NULL, 0);
> +}
> diff --git a/configs/imx8mm_evk_defconfig
> b/configs/imx8mm_evk_defconfig new file mode 100644
> index 0000000000..6110f23e38
> --- /dev/null
> +++ b/configs/imx8mm_evk_defconfig
> @@ -0,0 +1,41 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_IMX8M=y
> +CONFIG_SYS_TEXT_BASE=0x40200000
> +CONFIG_SPL_GPIO_SUPPORT=y
> +CONFIG_SYS_MALLOC_F_LEN=0x2000
> +CONFIG_TARGET_IMX8MM_EVK=y
> +CONFIG_SPL_MMC_SUPPORT=y
> +CONFIG_SPL_SERIAL_SUPPORT=y
> +CONFIG_SPL=y
> +CONFIG_FIT=y
> +CONFIG_FIT_EXTERNAL_OFFSET=0x3000
> +CONFIG_SPL_LOAD_FIT=y
> +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
> +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage.cfg,SPL_TEXT_BASE=0x7E1000"
> +CONFIG_DEFAULT_FDT_FILE="fsl-imx8mm-evk.dtb"
> +CONFIG_SPL_BOARD_INIT=y
> +CONFIG_SPL_I2C_SUPPORT=y
> +CONFIG_HUSH_PARSER=y
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_I2C=y
> +CONFIG_CMD_CACHE=y
> +CONFIG_CMD_REGULATOR=y
> +CONFIG_CMD_EXT2=y
> +CONFIG_CMD_EXT4=y
> +CONFIG_CMD_EXT4_WRITE=y
> +CONFIG_CMD_FAT=y
> +CONFIG_OF_CONTROL=y
> +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mm-evk"
> +CONFIG_DM_GPIO=y
> +CONFIG_MXC_GPIO=y
> +CONFIG_DM_I2C=y
> +CONFIG_SYS_I2C_MXC=y
> +CONFIG_DM_MMC=y
> +CONFIG_DM_ETH=y
Here you enable the DM_ETH, but the welcome u-boot info says:
"Net: No ethernet found."
> +CONFIG_PINCTRL=y
> +CONFIG_PINCTRL_IMX8M=y
> +CONFIG_DM_REGULATOR=y
> +CONFIG_DM_REGULATOR_FIXED=y
> +CONFIG_DM_REGULATOR_GPIO=y
> +CONFIG_MXC_UART=y
> +CONFIG_DM_THERMAL=y
> diff --git a/include/configs/imx8mm_evk.h
> b/include/configs/imx8mm_evk.h new file mode 100644
> index 0000000000..f944308757
> --- /dev/null
> +++ b/include/configs/imx8mm_evk.h
> @@ -0,0 +1,221 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2018 NXP
> + */
> +
> +#ifndef __IMX8MM_EVK_H
> +#define __IMX8MM_EVK_H
> +
> +#include <linux/sizes.h>
> +#include <asm/arch/imx-regs.h>
> +
> +#ifdef CONFIG_SECURE_BOOT
> +#define CONFIG_CSF_SIZE 0x2000 /* 8K region */
> +#endif
> +
> +#define CONFIG_SPL_MAX_SIZE (148 * 1024)
> +#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
> +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
> +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
> +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
> +#define CONFIG_SYS_UBOOT_BASE \
> + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR *
> 512) +
> +#ifdef CONFIG_SPL_BUILD
> +/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
> +#define CONFIG_SPL_WATCHDOG_SUPPORT
> +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
> +#define CONFIG_SPL_POWER_SUPPORT
> +#define
> CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
> +#define CONFIG_SPL_STACK 0x91fff0 +#define
> CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT
> +#define CONFIG_SPL_BSS_START_ADDR 0x00910000
> +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
> +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
> +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */
> +#define CONFIG_SYS_ICACHE_OFF
> +#define CONFIG_SYS_DCACHE_OFF
> +
> +#define CONFIG_MALLOC_F_ADDR 0x912000 /* malloc f
> used before GD_FLG_FULL_MALLOC_INIT set */ +
> +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error
> info not panic */ +
> +#undef CONFIG_DM_MMC
> +#undef CONFIG_DM_PMIC
> +#undef CONFIG_DM_PMIC_PFUZE100
Why do you need to undef those config options?
> +
> +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> +
> +#endif
> +
> +#define CONFIG_REMAKE_ELF
> +
> +#define CONFIG_BOARD_EARLY_INIT_F
> +#define CONFIG_BOARD_POSTCLK_INIT
> +#define CONFIG_BOARD_LATE_INIT
> +
> +/* Flat Device Tree Definitions */
> +#define CONFIG_OF_BOARD_SETUP
> +
> +#undef CONFIG_CMD_EXPORTENV
> +#undef CONFIG_CMD_IMPORTENV
> +#undef CONFIG_CMD_IMLS
> +
> +#undef CONFIG_CMD_CRC32
> +#undef CONFIG_BOOTM_NETBSD
There seems to be some issue with inheritance, as you need to undef
those values manually.
Why is it needed?
> +
> +/* ENET Config */
> +/* ENET1 */
> +#if defined(CONFIG_CMD_NET)
> +#define CONFIG_CMD_PING
> +#define CONFIG_CMD_DHCP
> +#define CONFIG_CMD_MII
> +#define CONFIG_MII
> +#define CONFIG_ETHPRIME "FEC"
> +
> +#define CONFIG_FEC_MXC
> +#define CONFIG_FEC_XCV_TYPE RGMII
> +#define CONFIG_FEC_MXC_PHYADDR 0
> +#define FEC_QUIRK_ENET_MAC
> +
> +#define CONFIG_PHY_GIGE
> +#define IMX_FEC_BASE 0x30BE0000
> +
> +#define CONFIG_PHYLIB
> +#define CONFIG_PHY_ATHEROS
> +#endif
> +
> +/* Initial environment variables */
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + "script=boot.scr\0" \
> + "image=Image\0" \
> + "console=ttymxc1,115200
> earlycon=ec_imx6q,0x30890000,115200\0" \
> + "fdt_addr=0x43000000\0" \
> + "fdt_high=0xffffffffffffffff\0" \
> + "boot_fdt=try\0" \
> + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
> + "initrd_addr=0x43800000\0" \
> + "initrd_high=0xffffffffffffffff\0" \
> + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
> + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
> + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
> + "mmcautodetect=yes\0" \
> + "mmcargs=setenv bootargs ${jh_clk} console=${console}
> root=${mmcroot}\0 " \
> + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}
> ${script};\0" \
> + "bootscript=echo Running bootscript from mmc ...; " \
> + "source\0" \
> + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}
> ${image}\0" \
> + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr}
> ${fdt_file}\0" \
> + "mmcboot=echo Booting from mmc ...; " \
> + "run mmcargs; " \
> + "if test ${boot_fdt} = yes || test ${boot_fdt} =
> try; then " \
> + "if run loadfdt; then " \
> + "booti ${loadaddr} - ${fdt_addr}; " \
> + "else " \
> + "echo WARN: Cannot load the DT; " \
> + "fi; " \
> + "else " \
> + "echo wait for boot; " \
> + "fi;\0" \
> + "netargs=setenv bootargs ${jh_clk} console=${console} " \
> + "root=/dev/nfs " \
> + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
> + "netboot=echo Booting from net ...; " \
> + "run netargs; " \
> + "if test ${ip_dyn} = yes; then " \
> + "setenv get_cmd dhcp; " \
> + "else " \
> + "setenv get_cmd tftp; " \
> + "fi; " \
> + "${get_cmd} ${loadaddr} ${image}; " \
> + "if test ${boot_fdt} = yes || test ${boot_fdt} =
> try; then " \
> + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then
> " \
> + "booti ${loadaddr} - ${fdt_addr}; " \
> + "else " \
> + "echo WARN: Cannot load the DT; " \
> + "fi; " \
> + "else " \
> + "booti; " \
> + "fi;\0"
> +
> +#define CONFIG_BOOTCOMMAND \
> + "mmc dev ${mmcdev}; if mmc rescan; then " \
> + "if run loadbootscript; then " \
> + "run bootscript; " \
> + "else " \
> + "if run loadimage; then " \
> + "run mmcboot; " \
> + "else run netboot; " \
> + "fi; " \
> + "fi; " \
> + "else booti ${loadaddr} - ${fdt_addr}; fi"
> +
> +/* Link Definitions */
> +#define CONFIG_LOADADDR 0x40480000
> +
> +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
> +
> +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
> +#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
> +#define CONFIG_SYS_INIT_SP_OFFSET \
> + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> +#define CONFIG_SYS_INIT_SP_ADDR \
> + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
> +
> +#define CONFIG_ENV_OVERWRITE
> +#if defined(CONFIG_ENV_IS_IN_MMC)
> +#define CONFIG_ENV_OFFSET (64 * SZ_64K)
> +#endif
> +#define CONFIG_ENV_SIZE 0x1000
> +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC2 */
> +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /*
> USDHC2 */ +
> +/* Size of malloc() pool */
> +#define CONFIG_SYS_MALLOC_LEN SZ_32M
> +
> +#define CONFIG_SYS_SDRAM_BASE 0x40000000
> +#define PHYS_SDRAM 0x40000000
> +#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR
> */ +
> +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
> +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START +
> (PHYS_SDRAM_SIZE >> 1)) +
> +#define CONFIG_BAUDRATE 115200
> +
> +#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
> +
> +/* Monitor Command Prompt */
> +#undef CONFIG_SYS_PROMPT
> +#define CONFIG_SYS_PROMPT "u-boot=> "
> +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
> +#define CONFIG_SYS_CBSIZE 2048
> +#define CONFIG_SYS_MAXARGS 64
> +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
> +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
> + sizeof(CONFIG_SYS_PROMPT) +
> 16) +
> +#define CONFIG_IMX_BOOTAUX
> +
> +/* USDHC */
> +#define CONFIG_CMD_MMC
> +#define CONFIG_FSL_ESDHC
> +#define CONFIG_FSL_USDHC
> +
> +#define CONFIG_SYS_FSL_USDHC_NUM 2
> +#define CONFIG_SYS_FSL_ESDHC_ADDR 0
> +
> +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
> +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
> +
> +#define CONFIG_MXC_OCOTP
> +#define CONFIG_CMD_FUSE
> +
> +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
> +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
> +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
> +#define CONFIG_SYS_I2C_SPEED 100000
Some of those values are (SYS_I2C_*, MXC_OCOTP, FSL_*) are already
supported by Kconfig. Please use Kconfig instead.
> +
> +#define CONFIG_OF_SYSTEM_SETUP
> +
> +#endif
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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^ permalink raw reply [flat|nested] 39+ messages in thread* [U-Boot] [PATCH 20/20] imx: add i.MX8MM EVK board support
2019-01-29 23:18 ` Lukasz Majewski
@ 2019-01-30 5:49 ` Peng Fan
2019-01-30 6:53 ` Lukasz Majewski
0 siblings, 1 reply; 39+ messages in thread
From: Peng Fan @ 2019-01-30 5:49 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: Lukasz Majewski [mailto:lukma at denx.de]
> Sent: 2019年1月30日 7:19
> To: Peng Fan <peng.fan@nxp.com>
> Cc: sbabic at denx.de; Fabio Estevam <fabio.estevam@nxp.com>;
> dl-uboot-imx <uboot-imx@nxp.com>; u-boot at lists.denx.de
> Subject: Re: [U-Boot] [PATCH 20/20] imx: add i.MX8MM EVK board support
>
> Hi Peng,
>
> > Add i.MX8MM EVK board support.
> >
> > Add board and SoC dts
> > Add ddr training code
> > support SD/MMC/GPIO/PINCTRL/UART
> >
> > U-Boot SPL 2019.01-00148-g1179cffe66 (Jan 28 2019 - 17:37:34 +0800)
> > Normal Boot
> > Trying to boot from MMC1
> >
> > U-Boot 2019.01-00148-g1179cffe66 (Jan 28 2019 - 17:37:34 +0800)
> >
> > CPU: Freescale i.MX8MMQ rev1.0 at 1200 MHz
> > Reset cause: POR
> > Model: NXP i.MX8MM EVK board
> > DRAM: 2 GiB
> > MMC: FSL_SDHC: 1, FSL_SDHC: 2
> > In: serial
> > Out: serial
> > Err: serial
> > DM
>
> You set/adjust latter in the code the fec network driver. Why it is not
> found?
I dropped network support, could add it in V2.
>
> Could you also share the output of "dm tree" command?
Sure.
>
> I suppose/guess that this board shall support as much as possible of
> the DT/DM conversions?
Ok.
Regards,
Peng.
>
> > Hit any key to stop autoboot: 2
> >
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > ---
> > arch/arm/dts/fsl-imx8mm-evk.dts | 203 +++
> > arch/arm/dts/fsl-imx8mm.dtsi | 586 ++++++++
> > arch/arm/mach-imx/imx8m/Kconfig | 7 +
> > board/freescale/imx8mm_evk/Kconfig | 12 +
> > board/freescale/imx8mm_evk/MAINTAINERS | 6 +
> > board/freescale/imx8mm_evk/Makefile | 12 +
> > board/freescale/imx8mm_evk/imx8mm_evk.c | 144 ++
> > board/freescale/imx8mm_evk/lpddr4_timing.c | 1980
> > ++++++++++++++++++++++++++++
> > board/freescale/imx8mm_evk/spl.c | 187 +++
> > configs/imx8mm_evk_defconfig | 41 +
> > include/configs/imx8mm_evk.h | 221 ++++ 11 files
> > changed, 3399 insertions(+) create mode 100644
> > arch/arm/dts/fsl-imx8mm-evk.dts create mode 100644
> > arch/arm/dts/fsl-imx8mm.dtsi create mode 100644
> > board/freescale/imx8mm_evk/Kconfig create mode 100644
> > board/freescale/imx8mm_evk/MAINTAINERS create mode 100644
> > board/freescale/imx8mm_evk/Makefile create mode 100644
> > board/freescale/imx8mm_evk/imx8mm_evk.c create mode 100644
> > board/freescale/imx8mm_evk/lpddr4_timing.c create mode 100644
> > board/freescale/imx8mm_evk/spl.c create mode 100644
> > configs/imx8mm_evk_defconfig create mode 100644
> > include/configs/imx8mm_evk.h
> >
> > diff --git a/arch/arm/dts/fsl-imx8mm-evk.dts
> > b/arch/arm/dts/fsl-imx8mm-evk.dts new file mode 100644
> > index 0000000000..df409eca47
> > --- /dev/null
> > +++ b/arch/arm/dts/fsl-imx8mm-evk.dts
> > @@ -0,0 +1,203 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright 2019 NXP
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include "fsl-imx8mm.dtsi"
> > +
> > +/ {
> > + model = "NXP i.MX8MM EVK board";
> > + compatible = "fsl,imx8mm-evk", "fsl,imx8mm";
> > +
> > + chosen {
> > + stdout-path = &uart2;
> > + };
> > +
> > + regulators {
> > + compatible = "simple-bus";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + reg_usdhc2_vmmc: regulator-usdhc2 {
> > + compatible = "regulator-fixed";
> > + regulator-name = "VSD_3V3";
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
> > + off-on-delay = <20000>;
> > + enable-active-high;
> > + };
> > + };
> > +};
> > +
> > +&iomuxc {
> > + pinctrl-names = "default";
> > +
> > + imx8mm-evk {
> > + pinctrl_fec1: fec1grp {
> > + fsl,pins = <
> > +
> > MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
> > +
> > MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
> > +
> > MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
> > +
> > MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
> > +
> > MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
> > +
> > MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
> > +
> > MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
> > +
> > MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
> > +
> > MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
> > +
> > MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
> > +
> > MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
> > +
> > MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
> > +
> > MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
> > +
> > MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
> > +
> > MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
> > + >;
> > + };
> > +
> > + pinctrl_gpio_led: gpioledgrp {
> > + fsl,pins = <
> > +
> > MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
> > + >;
> > + };
> > +
> > + pinctrl_uart2: uart2grp {
> > + fsl,pins = <
> > +
> > MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
> > +
> > MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
> > + >;
> > + };
> > +
> > + pinctrl_usdhc2_gpio: usdhc2grpgpio {
> > + fsl,pins = <
> > +
> > MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
> > +
> > MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
> > + >;
> > + };
> > +
> > + pinctrl_usdhc2: usdhc2grp {
> > + fsl,pins = <
> > +
> > MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
> > +
> > MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
> > +
> > MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
> > +
> > MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
> > +
> > MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
> > +
> > MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
> > +
> > MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
> > + >;
> > + };
> > +
> > + pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
> > + fsl,pins = <
> > +
> > MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
> > +
> > MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
> > +
> > MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
> > +
> > MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
> > +
> > MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
> > +
> > MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
> > +
> > MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
> > + >;
> > + };
> > +
> > + pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
> > + fsl,pins = <
> > +
> > MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
> > +
> > MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
> > +
> > MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
> > +
> > MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
> > +
> > MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
> > +
> > MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
> > +
> > MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
> > + >;
> > + };
> > +
> > + pinctrl_usdhc3: usdhc3grp {
> > + fsl,pins = <
> > +
> > MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
> > +
> > MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
> > +
> > MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
> > +
> > MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
> > +
> > MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
> > +
> > MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
> > +
> > MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
> > +
> > MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
> > +
> > MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
> > +
> > MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
> > +
> > MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
> > + >;
> > + };
> > +
> > + pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
> > + fsl,pins = <
> > +
> > MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
> > +
> > MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
> > +
> > MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
> > +
> > MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
> > +
> > MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
> > +
> > MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
> > +
> > MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
> > +
> > MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
> > +
> > MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
> > +
> > MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
> > +
> > MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
> > + >;
> > + };
> > +
> > + pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
> > + fsl,pins = <
> > +
> > MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
> > +
> > MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
> > +
> > MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
> > +
> > MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
> > +
> > MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
> > +
> > MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
> > +
> > MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
> > +
> > MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
> > +
> > MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
> > +
> > MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
> > +
> > MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
> > + >;
> > + };
> > +
> > + pinctrl_wdog: wdoggrp {
> > + fsl,pins = <
> > +
> > MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
> > + >;
> > + };
> > + };
> > +};
> > +
> > +&uart2 { /* console */
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_uart2>;
> > + status = "okay";
> > +};
> > +
> > +&usdhc2 {
> > + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> > + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
> > + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
> > + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
> > + cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
> > + bus-width = <4>;
> > + vmmc-supply = <®_usdhc2_vmmc>;
> > + status = "okay";
> > +};
> > +
> > +&usdhc3 {
> > + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> > + pinctrl-0 = <&pinctrl_usdhc3>;
> > + pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
> > + pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
> > + bus-width = <8>;
> > + non-removable;
> > + status = "okay";
> > +};
> > +
> > +&wdog1 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_wdog>;
> > + fsl,ext-reset-output;
> > + status = "okay";
> > +};
> > diff --git a/arch/arm/dts/fsl-imx8mm.dtsi
> > b/arch/arm/dts/fsl-imx8mm.dtsi new file mode 100644
> > index 0000000000..8a808f856d
> > --- /dev/null
> > +++ b/arch/arm/dts/fsl-imx8mm.dtsi
> > @@ -0,0 +1,586 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +/*
> > + * Copyright 2017-2019 NXP
> > + */
> > +
> > +#include <dt-bindings/clock/imx8mm-clock.h>
> > +#include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/input/input.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +#include <dt-bindings/pinctrl/pins-imx8mm.h>
> > +#include <dt-bindings/thermal/thermal.h>
> > +
> > +/ {
> > + compatible = "fsl,imx8mm";
> > + interrupt-parent = <&gic>;
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + aliases {
> > + i2c0 = &i2c1;
> > + i2c1 = &i2c2;
> > + i2c2 = &i2c3;
> > + i2c3 = &i2c4;
> > + serial0 = &uart1;
> > + serial1 = &uart2;
> > + serial2 = &uart3;
> > + serial3 = &uart4;
> > + spi0 = &ecspi1;
> > + spi1 = &ecspi2;
> > + spi2 = &ecspi3;
> > + mmc0 = &usdhc1;
> > + mmc1 = &usdhc2;
> > + mmc2 = &usdhc3;
> > + gpio0 = &gpio1;
> > + gpio1 = &gpio2;
> > + gpio2 = &gpio3;
> > + gpio3 = &gpio4;
> > + gpio4 = &gpio5;
> > + };
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + A53_0: cpu at 0 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a53";
> > + reg = <0x0>;
> > + enable-method = "psci";
> > + next-level-cache = <&A53_L2>;
> > + };
> > +
> > + A53_1: cpu at 1 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a53";
> > + reg = <0x1>;
> > + enable-method = "psci";
> > + next-level-cache = <&A53_L2>;
> > + };
> > +
> > + A53_2: cpu at 2 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a53";
> > + reg = <0x2>;
> > + enable-method = "psci";
> > + next-level-cache = <&A53_L2>;
> > + };
> > +
> > + A53_3: cpu at 3 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a53";
> > + reg = <0x3>;
> > + enable-method = "psci";
> > + next-level-cache = <&A53_L2>;
> > + };
> > +
> > + A53_L2: l2-cache0 {
> > + compatible = "cache";
> > + };
> > + };
> > +
> > + memory at 40000000 {
> > + device_type = "memory";
> > + reg = <0x0 0x40000000 0 0x80000000>;
> > + };
> > +
> > + clocks {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + osc_32k: clock at 0 {
> > + compatible = "fixed-clock";
> > + reg = <0>;
> > + #clock-cells = <0>;
> > + clock-frequency = <32768>;
> > + clock-output-names = "osc_32k";
> > + };
> > +
> > + osc_24m: clock at 1 {
> > + compatible = "fixed-clock";
> > + reg = <1>;
> > + #clock-cells = <0>;
> > + clock-frequency = <24000000>;
> > + clock-output-names = "osc_24m";
> > + };
> > +
> > + clk_ext1: clock at 2 {
> > + compatible = "fixed-clock";
> > + reg = <3>;
> > + #clock-cells = <0>;
> > + clock-frequency = <133000000>;
> > + clock-output-names = "clk_ext1";
> > + };
> > +
> > + clk_ext2: clock at 3 {
> > + compatible = "fixed-clock";
> > + reg = <4>;
> > + #clock-cells = <0>;
> > + clock-frequency = <133000000>;
> > + clock-output-names = "clk_ext2";
> > + };
> > +
> > + clk_ext3: clock at 4 {
> > + compatible = "fixed-clock";
> > + reg = <5>;
> > + #clock-cells = <0>;
> > + clock-frequency = <133000000>;
> > + clock-output-names = "clk_ext3";
> > + };
> > +
> > + clk_ext4: clock at 5 {
> > + compatible = "fixed-clock";
> > + reg = <6>;
> > + #clock-cells = <0>;
> > + clock-frequency= <133000000>;
> > + clock-output-names = "clk_ext4";
> > + };
> > + };
> > +
> > + gic: interrupt-controller at 38800000 {
> > + compatible = "arm,gic-v3";
> > + reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */
> > + <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base +
> > SGI_base) */
> > + #interrupt-cells = <3>;
> > + interrupt-controller;
> > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> > + };
> > +
> > + psci {
> > + compatible = "arm,psci-1.0";
> > + method = "smc";
> > + };
> > +
> > + pmu {
> > + compatible = "arm,armv8-pmuv3";
> > + interrupts = <GIC_PPI 7
> > + (GIC_CPU_MASK_SIMPLE(6) |
> > IRQ_TYPE_LEVEL_HIGH)>;
> > + interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>,
> > <&A53_3>;
> > + };
> > +
> > + timer {
> > + compatible = "arm,armv8-timer";
> > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) |
> > IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
> > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) |
> > IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
> > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) |
> > IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
> > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) |
> > IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
> > + clock-frequency = <8000000>;
> > + arm,no-tick-in-suspend;
> > + };
> > +
> > + soc at 0 {
> > + compatible = "simple-bus";
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> > +
> > + aips1: bus at 30000000 {
> > + compatible = "fsl,aips-bus", "simple-bus";
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + reg = <0x0 0x30000000 0x0 0x400000>;
> > + ranges;
> > +
> > + gpio1: gpio at 30200000 {
> > + compatible = "fsl,imx8mm-gpio",
> > "fsl,imx35-gpio";
> > + reg = <0x0 0x30200000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 64
> > IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 65
> > IRQ_TYPE_LEVEL_HIGH>;
> > + gpio-controller;
> > + #gpio-cells = <2>;
> > + interrupt-controller;
> > + #interrupt-cells = <2>;
> > + };
> > +
> > + gpio2: gpio at 30210000 {
> > + compatible = "fsl,imx8mm-gpio",
> > "fsl,imx35-gpio";
> > + reg = <0x0 0x30210000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 66
> > IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 67
> > IRQ_TYPE_LEVEL_HIGH>;
> > + gpio-controller;
> > + #gpio-cells = <2>;
> > + interrupt-controller;
> > + #interrupt-cells = <2>;
> > + };
> > +
> > + gpio3: gpio at 30220000 {
> > + compatible = "fsl,imx8mm-gpio",
> > "fsl,imx35-gpio";
> > + reg = <0x0 0x30220000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 68
> > IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 69
> > IRQ_TYPE_LEVEL_HIGH>;
> > + gpio-controller;
> > + #gpio-cells = <2>;
> > + interrupt-controller;
> > + #interrupt-cells = <2>;
> > + };
> > +
> > + gpio4: gpio at 30230000 {
> > + compatible = "fsl,imx8mm-gpio",
> > "fsl,imx35-gpio";
> > + reg = <0x0 0x30230000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 70
> > IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 71
> > IRQ_TYPE_LEVEL_HIGH>;
> > + gpio-controller;
> > + #gpio-cells = <2>;
> > + interrupt-controller;
> > + #interrupt-cells = <2>;
> > + };
> > +
> > + gpio5: gpio at 30240000 {
> > + compatible = "fsl,imx8mm-gpio",
> > "fsl,imx35-gpio";
> > + reg = <0x0 0x30240000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 72
> > IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 73
> > IRQ_TYPE_LEVEL_HIGH>;
> > + gpio-controller;
> > + #gpio-cells = <2>;
> > + interrupt-controller;
> > + #interrupt-cells = <2>;
> > + };
> > +
> > + wdog1: wdog at 30280000 {
> > + compatible = "fsl,imx21-wdt";
> > + reg = <0 0x30280000 0 0x10000>;
> > + interrupts = <GIC_SPI 78
> > IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk
> > IMX8MM_CLK_WDOG1_ROOT>;
> > + status = "disabled";
> > + };
> > +
> > + wdog2: wdog at 30290000 {
> > + compatible = "fsl,imx21-wdt";
> > + reg = <0 0x30290000 0 0x10000>;
> > + interrupts = <GIC_SPI 79
> > IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk
> > IMX8MM_CLK_WDOG2_ROOT>;
> > + status = "disabled";
> > + };
> > +
> > + wdog3: wdog at 302a0000 {
> > + compatible = "fsl,imx21-wdt";
> > + reg = <0 0x302a0000 0 0x10000>;
> > + interrupts = <GIC_SPI 10
> > IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk
> > IMX8MM_CLK_WDOG3_ROOT>;
> > + status = "disabled";
> > + };
> > +
> > + sdma2: dma-controller at 302c0000 {
> > + compatible = "fsl,imx8mq-sdma",
> > "fsl,imx7d-sdma";
> > + reg = <0x0 0x302c0000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 103
> > IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk
> > IMX8MM_CLK_SDMA2_ROOT>,
> > + <&clk
> > IMX8MM_CLK_SDMA2_ROOT>;
> > + clock-names = "ipg", "ahb";
> > + #dma-cells = <3>;
> > + fsl,sdma-ram-script-name =
> > "imx/sdma/sdma-imx7d.bin";
> > + fsl,ratio-1-1;
> > + status = "okay";
> > + };
> > +
> > + sdma3: dma-controller at 302b0000 {
> > + compatible = "fsl,imx8mq-sdma",
> > "fsl,imx7d-sdma";
> > + reg = <0x0 0x302b0000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 34
> > IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk
> > IMX8MM_CLK_SDMA3_ROOT>,
> > + <&clk IMX8MM_CLK_SDMA3_ROOT>;
> > + clock-names = "ipg", "ahb";
> > + #dma-cells = <3>;
> > + fsl,sdma-ram-script-name =
> > "imx/sdma/sdma-imx7d.bin";
> > + fsl,ratio-1-1;
> > + status = "okay";
> > + };
> > +
> > + iomuxc: pinctrl at 30330000 {
> > + compatible = "fsl,imx8mm-iomuxc";
> > + reg = <0x0 0x30330000 0x0 0x10000>;
> > + };
> > +
> > + gpr: iomuxc-gpr at 30340000 {
> > + compatible =
> > "fsl,imx8mm-iomuxc-gpr", "syscon";
> > + reg = <0x0 0x30340000 0x0 0x10000>;
> > + };
> > +
> > + ocotp: ocotp-ctrl at 30350000 {
> > + compatible = "fsl,imx8mq-ocotp",
> > "fsl,imx7d-ocotp", "syscon";
> > + reg = <0 0x30350000 0 0x10000>;
> > + clocks = <&clk
> > IMX8MM_CLK_OCOTP_ROOT>;
> > + /* For nvmem subnodes */
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + };
> > +
> > + anatop: anatop at 30360000 {
> > + compatible = "fsl,imx8mm-anatop",
> > "syscon", "simple-bus";
> > + reg = <0x0 0x30360000 0x0 0x10000>;
> > + };
> > +
> > + snvs: snvs at 30370000 {
> > + compatible =
> > "fsl,sec-v4.0-mon","syscon", "simple-mfd";
> > + reg = <0x0 0x30370000 0x0 0x10000>;
> > +
> > + snvs_rtc: snvs-rtc-lp{
> > + compatible =
> > "fsl,sec-v4.0-mon-rtc-lp";
> > + regmap =<&snvs>;
> > + offset = <0x34>;
> > + interrupts = <GIC_SPI 19
> > IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 20
> > IRQ_TYPE_LEVEL_HIGH>;
> > + };
> > +
> > + snvs_pwrkey: snvs-powerkey {
> > + compatible =
> > "fsl,sec-v4.0-pwrkey";
> > + regmap = <&snvs>;
> > + interrupts = <GIC_SPI 4
> > IRQ_TYPE_LEVEL_HIGH>;
> > + linux,keycode = <KEY_POWER>;
> > + wakeup-source;
> > + };
> > + };
> > +
> > + clk: clock-controller at 30380000 {
> > + compatible = "fsl,imx8mm-ccm";
> > + reg = <0x0 0x30380000 0x0 0x10000>;
> > + #clock-cells = <1>;
> > + clocks = <&osc_32k>, <&osc_24m>,
> > <&clk_ext1>, <&clk_ext2>,
> > + <&clk_ext3>, <&clk_ext4>;
> > + clock-names = "osc_32k", "osc_24m",
> > "clk_ext1", "clk_ext2",
> > + "clk_ext3", "clk_ext4";
> > + };
> > +
> > + src: src at 30390000 {
> > + compatible = "fsl,imx8mm-src",
> > "syscon";
> > + reg = <0x0 0x30390000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 89
> > IRQ_TYPE_LEVEL_HIGH>;
> > + #reset-cells = <1>;
> > + };
> > +
> > + gpc: gpc at 303a0000 {
> > + compatible = "fsl,imx8mm-gpc",
> > "syscon";
> > + reg = <0x0 0x303a0000 0x0 0x10000>;
> > + interrupt-controller;
> > + interrupts = <GIC_SPI 87
> > IRQ_TYPE_LEVEL_HIGH>;
> > + #interrupt-cells = <3>;
> > + };
> > + };
> > +
> > + aips2: bus at 30400000 {
> > + compatible = "fsl,aips-bus", "simple-bus";
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + reg = <0x0 0x30400000 0x0 0x400000>;
> > + ranges;
> > +
> > + pwm1: pwm at 30660000 {
> > + compatible = "fsl,imx8mm-pwm",
> > "fsl,imx27-pwm";
> > + reg = <0x0 0x30660000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 81
> > IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk IMX8MM_CLK_PWM1_ROOT>,
> > + <&clk IMX8MM_CLK_PWM1_ROOT>;
> > + clock-names = "ipg", "per";
> > + #pwm-cells = <2>;
> > + status = "disabled";
> > + };
> > +
> > + pwm2: pwm at 30670000 {
> > + compatible = "fsl,imx8mm-pwm",
> > "fsl,imx27-pwm";
> > + reg = <0x0 0x30670000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 82
> > IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk IMX8MM_CLK_PWM2_ROOT>,
> > + <&clk IMX8MM_CLK_PWM2_ROOT>;
> > + clock-names = "ipg", "per";
> > + #pwm-cells = <2>;
> > + status = "disabled";
> > + };
> > +
> > + pwm3: pwm at 30680000 {
> > + compatible = "fsl,imx8mm-pwm",
> > "fsl,imx27-pwm";
> > + reg = <0x0 0x30680000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 83
> > IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk IMX8MM_CLK_PWM3_ROOT>,
> > + <&clk IMX8MM_CLK_PWM3_ROOT>;
> > + clock-names = "ipg", "per";
> > + #pwm-cells = <2>;
> > + status = "disabled";
> > + };
> > +
> > + pwm4: pwm at 30690000 {
> > + compatible = "fsl,imx8mm-pwm",
> > "fsl,imx27-pwm";
> > + reg = <0x0 0x30690000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 84
> > IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk IMX8MM_CLK_PWM4_ROOT>,
> > + <&clk IMX8MM_CLK_PWM4_ROOT>;
> > + clock-names = "ipg", "per";
> > + #pwm-cells = <2>;
> > + status = "disabled";
> > + };
> > + };
> > +
> > + aips3: bus at 30800000 {
> > + compatible = "fsl,aips-bus", "simple-bus";
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + reg = <0x0 0x30800000 0x0 0x400000>;
> > + ranges;
> > +
> > + ecspi1: ecspi at 30820000 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + compatible = "fsl,imx8mm-ecspi",
> > "fsl,imx51-ecspi";
> > + reg = <0x0 0x30820000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 31
> > IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk
> > IMX8MM_CLK_ECSPI1_ROOT>,
> > + <&clk
> > IMX8MM_CLK_ECSPI1_ROOT>;
> > + clock-names = "ipg", "per";
> > + status = "disabled";
> > + };
> > +
> > + ecspi2: ecspi at 30830000 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + compatible = "fsl,imx8mm-ecspi",
> > "fsl,imx51-ecspi";
> > + reg = <0x0 0x30830000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 32
> > IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk
> > IMX8MM_CLK_ECSPI2_ROOT>,
> > + <&clk
> > IMX8MM_CLK_ECSPI2_ROOT>;
> > + clock-names = "ipg", "per";
> > + status = "disabled";
> > + };
> > +
> > + ecspi3: ecspi at 30840000 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + compatible = "fsl,imx8mm-ecspi",
> > "fsl,imx51-ecspi";
> > + reg = <0x0 0x30840000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 33
> > IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk
> > IMX8MM_CLK_ECSPI3_ROOT>,
> > + <&clk
> > IMX8MM_CLK_ECSPI3_ROOT>;
> > + clock-names = "ipg", "per";
> > + status = "disabled";
> > + };
> > +
> > + uart1: serial at 30860000 {
> > + compatible = "fsl,imx8mm-uart",
> > + "fsl,imx6q-uart",
> > "fsl,imx21-uart";
> > + reg = <0x0 0x30860000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 26
> > IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk
> > IMX8MM_CLK_UART1_ROOT>,
> > + <&clk
> > IMX8MM_CLK_UART1_ROOT>;
> > + clock-names = "ipg", "per";
> > + status = "disabled";
> > + };
> > +
> > + uart3: serial at 30880000 {
> > + compatible = "fsl,imx8mm-uart",
> > + "fsl,imx6q-uart",
> > "fsl,imx21-uart";
> > + reg = <0x0 0x30880000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 28
> > IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk
> > IMX8MM_CLK_UART3_ROOT>,
> > + <&clk
> > IMX8MM_CLK_UART3_ROOT>;
> > + clock-names = "ipg", "per";
> > + status = "disabled";
> > + };
> > +
> > + uart2: serial at 30890000 {
> > + compatible = "fsl,imx8mm-uart",
> > + "fsl,imx6q-uart",
> > "fsl,imx21-uart";
> > + reg = <0x0 0x30890000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 27
> > IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk
> > IMX8MM_CLK_UART2_ROOT>,
> > + <&clk
> > IMX8MM_CLK_UART2_ROOT>;
> > + clock-names = "ipg", "per";
> > + status = "disabled";
> > + };
> > +
> > + i2c1: i2c at 30a20000 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + compatible = "fsl,imx8mm-i2c",
> > "fsl,imx21-i2c";
> > + reg = <0x0 0x30a20000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 35
> > IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk IMX8MM_CLK_I2C1_ROOT>;
> > + status = "disabled";
> > + };
> > +
> > + i2c2: i2c at 30a30000 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + compatible = "fsl,imx8mm-i2c",
> > "fsl,imx21-i2c";
> > + reg = <0x0 0x30a30000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 36
> > IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk IMX8MM_CLK_I2C2_ROOT>;
> > + status = "disabled";
> > + };
> > +
> > + i2c3: i2c at 30a40000 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + compatible = "fsl,imx8mm-i2c",
> > "fsl,imx21-i2c";
> > + reg = <0x0 0x30a40000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 37
> > IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk IMX8MM_CLK_I2C3_ROOT>;
> > + status = "disabled";
> > + };
> > +
> > + i2c4: i2c at 30a50000 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + compatible = "fsl,imx8mm-i2c",
> > "fsl,imx21-i2c";
> > + reg = <0x0 0x30a50000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 38
> > IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk IMX8MM_CLK_I2C4_ROOT>;
> > + status = "disabled";
> > + };
> > +
> > + uart4: serial at 30a60000 {
> > + compatible = "fsl,imx8mq-uart",
> > + "fsl,imx6q-uart",
> > "fsl,imx21-uart";
> > + reg = <0x0 0x30a60000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 29
> > IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk
> > IMX8MM_CLK_UART4_ROOT>,
> > + <&clk
> > IMX8MM_CLK_UART4_ROOT>;
> > + clock-names = "ipg", "per";
> > + status = "disabled";
> > + };
> > +
> > + usdhc1: mmc at 30b40000 {
> > + compatible = "fsl,imx8mq-usdhc",
> > "fsl,imx7d-usdhc";
> > + reg = <0x0 0x30b40000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 22
> > IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk IMX8MM_CLK_DUMMY>,
> > + <&clk
> > IMX8MM_CLK_NAND_USDHC_BUS>,
> > + <&clk
> > IMX8MM_CLK_USDHC1_ROOT>;
> > + clock-names = "ipg", "ahb", "per";
> > + assigned-clocks = <&clk
> > IMX8MM_CLK_USDHC1>;
> > + assigned-clock-rates = <400000000>;
> > + fsl,tuning-start-tap = <20>;
> > + fsl,tuning-step= <2>;
> > + bus-width = <4>;
> > + status = "disabled";
> > + };
> > +
> > + usdhc2: mmc at 30b50000 {
> > + compatible = "fsl,imx8mq-usdhc",
> > "fsl,imx7d-usdhc";
> > + reg = <0x0 0x30b50000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 23
> > IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk IMX8MM_CLK_DUMMY>,
> > + <&clk
> > IMX8MM_CLK_NAND_USDHC_BUS>,
> > + <&clk
> > IMX8MM_CLK_USDHC2_ROOT>;
> > + clock-names = "ipg", "ahb", "per";
> > + fsl,tuning-start-tap = <20>;
> > + fsl,tuning-step= <2>;
> > + bus-width = <4>;
> > + status = "disabled";
> > + };
> > +
> > + usdhc3: mmc at 30b60000 {
> > + compatible = "fsl,imx8mq-usdhc",
> > "fsl,imx7d-usdhc";
> > + reg = <0x0 0x30b60000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 24
> > IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk IMX8MM_CLK_DUMMY>,
> > + <&clk
> > IMX8MM_CLK_NAND_USDHC_BUS>,
> > + <&clk
> > IMX8MM_CLK_USDHC3_ROOT>;
> > + clock-names = "ipg", "ahb", "per";
> > + assigned-clocks = <&clk
> > IMX8MM_CLK_USDHC3_ROOT>;
> > + assigned-clock-rates = <400000000>;
> > + fsl,tuning-start-tap = <20>;
> > + fsl,tuning-step= <2>;
> > + bus-width = <4>;
> > + status = "disabled";
> > + };
> > + };
> > + };
> > +};
> > diff --git a/arch/arm/mach-imx/imx8m/Kconfig
> > b/arch/arm/mach-imx/imx8m/Kconfig index 35c978e863..f520075875
> 100644
> > --- a/arch/arm/mach-imx/imx8m/Kconfig
> > +++ b/arch/arm/mach-imx/imx8m/Kconfig
> > @@ -24,8 +24,15 @@ config TARGET_IMX8MQ_EVK
> > select IMX8MQ
> > select IMX8M_LPDDR4
> >
> > +config TARGET_IMX8MM_EVK
> > + bool "imx8mm LPDDR4 EVK board"
> > + select IMX8MM
> > + select SUPPORT_SPL
> > + select IMX8M_LPDDR4
>
> Here you shall put the select DM_{UART,USDHC, etc}
>
> > +
> > endchoice
> >
> > source "board/freescale/imx8mq_evk/Kconfig"
> > +source "board/freescale/imx8mm_evk/Kconfig"
> >
> > endif
> > diff --git a/board/freescale/imx8mm_evk/Kconfig
> > b/board/freescale/imx8mm_evk/Kconfig new file mode 100644
> > index 0000000000..299691a619
> > --- /dev/null
> > +++ b/board/freescale/imx8mm_evk/Kconfig
> > @@ -0,0 +1,12 @@
> > +if TARGET_IMX8MM_EVK
> > +
> > +config SYS_BOARD
> > + default "imx8mm_evk"
> > +
> > +config SYS_VENDOR
> > + default "freescale"
> > +
> > +config SYS_CONFIG_NAME
> > + default "imx8mm_evk"
> > +
> > +endif
> > diff --git a/board/freescale/imx8mm_evk/MAINTAINERS
> > b/board/freescale/imx8mm_evk/MAINTAINERS new file mode 100644
> > index 0000000000..b031bb0674
> > --- /dev/null
> > +++ b/board/freescale/imx8mm_evk/MAINTAINERS
> > @@ -0,0 +1,6 @@
> > +i.MX8MM EVK BOARD
> > +M: Peng Fan <peng.fan@nxp.com>
> > +S: Maintained
> > +F: board/freescale/imx8mm_evk/
> > +F: include/configs/imx8mm_evk.h
> > +F: configs/imx8mm_evk_defconfig
> > diff --git a/board/freescale/imx8mm_evk/Makefile
> > b/board/freescale/imx8mm_evk/Makefile new file mode 100644
> > index 0000000000..1db7b62caf
> > --- /dev/null
> > +++ b/board/freescale/imx8mm_evk/Makefile
> > @@ -0,0 +1,12 @@
> > +#
> > +# Copyright 2018 NXP
> > +#
> > +# SPDX-License-Identifier: GPL-2.0+
> > +#
> > +
> > +obj-y += imx8mm_evk.o
> > +
> > +ifdef CONFIG_SPL_BUILD
> > +obj-y += spl.o
> > +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
> > +endif
> > diff --git a/board/freescale/imx8mm_evk/imx8mm_evk.c
> > b/board/freescale/imx8mm_evk/imx8mm_evk.c new file mode 100644
> > index 0000000000..a681aca04d
> > --- /dev/null
> > +++ b/board/freescale/imx8mm_evk/imx8mm_evk.c
> > @@ -0,0 +1,144 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright 2018 NXP
> > + */
> > +
> > +#include <common.h>
> > +#include <malloc.h>
> > +#include <errno.h>
> > +#include <asm/io.h>
> > +#include <miiphy.h>
> > +#include <netdev.h>
> > +#include <asm/mach-imx/iomux-v3.h>
> > +#include <asm-generic/gpio.h>
> > +#include <fsl_esdhc.h>
> > +#include <mmc.h>
> > +#include <asm/arch/imx8mm_pins.h>
> > +#include <asm/arch/sys_proto.h>
> > +#include <asm/mach-imx/gpio.h>
> > +#include <asm/mach-imx/mxc_i2c.h>
> > +#include <asm/arch/clock.h>
> > +#include <spl.h>
> > +#include <asm/mach-imx/dma.h>
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
> > +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE |
> > PAD_CTL_PUE | PAD_CTL_PE) +
> > +static iomux_v3_cfg_t const uart_pads[] = {
> > + IMX8MM_PAD_UART2_RXD_UART2_RX |
> MUX_PAD_CTRL(UART_PAD_CTRL),
> > + IMX8MM_PAD_UART2_TXD_UART2_TX |
> MUX_PAD_CTRL(UART_PAD_CTRL),
> > +};
> > +
> > +static iomux_v3_cfg_t const wdog_pads[] = {
> > + IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B |
> > MUX_PAD_CTRL(WDOG_PAD_CTRL), +};
> > +
> > +int board_early_init_f(void)
> > +{
> > + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
> > +
> > + imx_iomux_v3_setup_multiple_pads(wdog_pads,
> > ARRAY_SIZE(wdog_pads)); +
> > + set_wdog_reset(wdog);
> > +
> > + imx_iomux_v3_setup_multiple_pads(uart_pads,
> > ARRAY_SIZE(uart_pads)); +
> > + return 0;
> > +}
> > +
> > +#ifdef CONFIG_BOARD_POSTCLK_INIT
> > +int board_postclk_init(void)
> > +{
> > + /* TODO */
> > + return 0;
> > +}
> > +#endif
> > +
> > +int dram_init(void)
> > +{
> > + /* rom_pointer[1] contains the size of TEE occupies */
> > + if (rom_pointer[1])
> > + gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
> > + else
> > + gd->ram_size = PHYS_SDRAM_SIZE;
> > +
> > + return 0;
> > +}
> > +
> > +#ifdef CONFIG_OF_BOARD_SETUP
> > +int ft_board_setup(void *blob, bd_t *bd)
> ^^^ - fdt_board_setup ?
> > +{
> > + return 0;
> > +}
> > +#endif
> > +
> > +#ifdef CONFIG_FEC_MXC
> > +#define FEC_RST_PAD IMX_GPIO_NR(4, 22)
> > +static iomux_v3_cfg_t const fec1_rst_pads[] = {
> > + IMX8MM_PAD_SAI2_RXC_GPIO4_IO22 |
> MUX_PAD_CTRL(NO_PAD_CTRL),
>
> This shall be done with fsl_fec.c DM driver - there is support for
> adding reset pin (to dts).
>
> > +};
> > +
> > +static void setup_iomux_fec(void)
> > +{
> > + imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
> > + ARRAY_SIZE(fec1_rst_pads));
> > +
> > + gpio_request(FEC_RST_PAD, "fec1_rst");
> > + gpio_direction_output(FEC_RST_PAD, 0);
> > + udelay(500);
> > + gpio_direction_output(FEC_RST_PAD, 1);
> > +}
>
> This shall be replaced with DM/DTS of the fsl_fec.c driver. Please also
> note that there are (at least on imx6q) some timing issues when we move
> the code to DM/DTS (some delay is needed).
>
> > +
> > +static int setup_fec(void)
> > +{
> > + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
> > + = (struct iomuxc_gpr_base_regs
> > *)IOMUXC_GPR_BASE_ADDR; +
> > + setup_iomux_fec();
> > +
> > + /* Use 125M anatop REF_CLK1 for ENET1, not from external */
> > + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
> > + IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT,
> > 0);
> > + return set_clk_enet(ENET_125MHZ);
> > +}
> > +
> > +int board_phy_config(struct phy_device *phydev)
> > +{
> > + /* enable rgmii rxc skew and phy mode select to RGMII copper
> > */
> > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
> > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
> > +
> > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
> > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
> > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
> > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
> > +
> > + if (phydev->drv->config)
> > + phydev->drv->config(phydev);
> > + return 0;
>
> Which PHY do you use? E.g. KSZ... support passing those values via DTS.
>
> > +}
> > +#endif
> > +
> > +int board_init(void)
> > +{
> > +#ifdef CONFIG_FEC_MXC
> > + setup_fec();
> > +#endif
> > + return 0;
> > +}
> > +
> > +int board_mmc_get_env_dev(int devno)
> > +{
> > + return devno - 1;
> > +}
> > +
> > +int board_late_init(void)
> > +{
> > +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> > + env_set("board_name", "EVK");
> > + env_set("board_rev", "iMX8MM");
> > +#endif
> > + return 0;
> > +}
> > diff --git a/board/freescale/imx8mm_evk/lpddr4_timing.c
> > b/board/freescale/imx8mm_evk/lpddr4_timing.c new file mode 100644
> > index 0000000000..4bade5bf74
> > --- /dev/null
> > +++ b/board/freescale/imx8mm_evk/lpddr4_timing.c
> > @@ -0,0 +1,1980 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright 2018 NXP
>
> Author is missing.
>
> > + */
> > +
> > +#include <linux/kernel.h>
> > +#include <common.h>
> > +#include <asm/arch/ddr.h>
> > +#include <asm/arch/lpddr4_define.h>
> > +
> > +struct dram_cfg_param lpddr4_ddrc_cfg[] = {
> > + /* Start to config, default 3200mbps */
> > + { DDRC_DBG1(0), 0x00000001 },
> > + { DDRC_PWRCTL(0), 0x00000001 },
> > + { DDRC_MSTR(0), 0xa1080020 },
> > + { DDRC_RFSHTMG(0), 0x005b00d2 },
> > + { DDRC_INIT0(0), 0xC003061B },
> > + { DDRC_INIT1(0), 0x009D0000 },
> > + { DDRC_INIT3(0), 0x00D4002D },
> > + { DDRC_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 },
> > + { DDRC_INIT6(0), 0x0066004a },
> > + { DDRC_INIT7(0), 0x0006004a },
> > +
> > + { DDRC_DRAMTMG0(0), 0x1A201B22 },
> > + { DDRC_DRAMTMG1(0), 0x00060633 },
> > + { DDRC_DRAMTMG3(0), 0x00C0C000 },
> > + { DDRC_DRAMTMG4(0), 0x0F04080F },
> > + { DDRC_DRAMTMG5(0), 0x02040C0C },
> > + { DDRC_DRAMTMG6(0), 0x01010007 },
> > + { DDRC_DRAMTMG7(0), 0x00000401 },
> > + { DDRC_DRAMTMG12(0), 0x00020600 },
> > + { DDRC_DRAMTMG13(0), 0x0C100002 },
> > + { DDRC_DRAMTMG14(0), 0x000000E6 },
> > + { DDRC_DRAMTMG17(0), 0x00A00050 },
> > +
> > + { DDRC_ZQCTL0(0), 0x03200018 },
> > + { DDRC_ZQCTL1(0), 0x028061A8 },
> > + { DDRC_ZQCTL2(0), 0x00000000 },
> > +
> > + { DDRC_DFITMG0(0), 0x0497820A },
> > + { DDRC_DFITMG2(0), 0x0000170A },
> > + { DDRC_DRAMTMG2(0), 0x070E171a },
> > + { DDRC_DBICTL(0), 0x00000001 },
> > +
> > + { DDRC_DFITMG1(0), 0x00080303 },
> > + { DDRC_DFIUPD0(0), 0xE0400018 },
> > + { DDRC_DFIUPD1(0), 0x00DF00E4 },
> > + { DDRC_DFIUPD2(0), 0x80000000 },
> > + { DDRC_DFIMISC(0), 0x00000011 },
> > +
> > + { DDRC_DFIPHYMSTR(0), 0x00000000 },
> > + { DDRC_RANKCTL(0), 0x00000c99 },
> > +
> > + /* address mapping */
> > + { DDRC_ADDRMAP0(0), 0x0000001f },
> > + { DDRC_ADDRMAP1(0), 0x00080808 },
> > + { DDRC_ADDRMAP2(0), 0x00000000 },
> > + { DDRC_ADDRMAP3(0), 0x00000000 },
> > + { DDRC_ADDRMAP4(0), 0x00001f1f },
> > + { DDRC_ADDRMAP5(0), 0x07070707 },
> > + { DDRC_ADDRMAP6(0), 0x07070707 },
> > + { DDRC_ADDRMAP7(0), 0x00000f0f },
> > +
> > + /* performance setting */
> > + { DDRC_SCHED(0), 0x29001701 },
> > + { DDRC_SCHED1(0), 0x0000002c },
> > + { DDRC_PERFHPR1(0), 0x04000030 },
> > + { DDRC_PERFLPR1(0), 0x900093e7 },
> > + { DDRC_PERFWR1(0), 0x20005574 },
> > + { DDRC_PCCFG(0), 0x00000111 },
> > + { DDRC_PCFGW_0(0), 0x000072ff },
> > + { DDRC_PCFGQOS0_0(0), 0x02100e07 },
> > + { DDRC_PCFGQOS1_0(0), 0x00620096 },
> > + { DDRC_PCFGWQOS0_0(0), 0x01100e07 },
> > + { DDRC_PCFGWQOS1_0(0), 0x00c8012c },
> > +
> > + /* frequency P1&P2 */
> > + /* Frequency 1: 400mbps */
> > + { DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c },
> > + { DDRC_FREQ1_DRAMTMG1(0), 0x00030410 },
> > + { DDRC_FREQ1_DRAMTMG2(0), 0x0203090c },
> > + { DDRC_FREQ1_DRAMTMG3(0), 0x00505006 },
> > + { DDRC_FREQ1_DRAMTMG4(0), 0x05040305 },
> > + { DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504 },
> > + { DDRC_FREQ1_DRAMTMG6(0), 0x0a060004 },
> > + { DDRC_FREQ1_DRAMTMG7(0), 0x0000090e },
> > + { DDRC_FREQ1_DRAMTMG14(0), 0x00000032 },
> > + { DDRC_FREQ1_DRAMTMG15(0), 0x00000000 },
> > + { DDRC_FREQ1_DRAMTMG17(0), 0x0036001b },
> > + { DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1 },
> > + { DDRC_FREQ1_DFITMG0(0), 0x03818200 },
> > + { DDRC_FREQ1_DFITMG2(0), 0x00000000 },
> > + { DDRC_FREQ1_RFSHTMG(0), 0x000C001c },
> > + { DDRC_FREQ1_INIT3(0), 0x00840000 },
> > + { DDRC_FREQ1_INIT4(0), 0x00310000 },
> > + { DDRC_FREQ1_INIT6(0), 0x0066004a },
> > + { DDRC_FREQ1_INIT7(0), 0x0006004a },
> > +
> > + /* Frequency 2: 100mbps */
> > + { DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c },
> > + { DDRC_FREQ2_DRAMTMG1(0), 0x00030410 },
> > + { DDRC_FREQ2_DRAMTMG2(0), 0x0203090c },
> > + { DDRC_FREQ2_DRAMTMG3(0), 0x00505006 },
> > + { DDRC_FREQ2_DRAMTMG4(0), 0x05040305 },
> > + { DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504 },
> > + { DDRC_FREQ2_DRAMTMG6(0), 0x0a060004 },
> > + { DDRC_FREQ2_DRAMTMG7(0), 0x0000090e },
> > + { DDRC_FREQ2_DRAMTMG14(0), 0x00000032 },
> > + { DDRC_FREQ2_DRAMTMG17(0), 0x0036001b },
> > + { DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1 },
> > + { DDRC_FREQ2_DFITMG0(0), 0x03818200 },
> > + { DDRC_FREQ2_DFITMG2(0), 0x00000000 },
> > + { DDRC_FREQ2_RFSHTMG(0), 0x0003800c },
> > + { DDRC_FREQ2_RFSHTMG(0), 0x00030007 },
> > + { DDRC_FREQ2_INIT3(0), 0x00840000 },
> > + { DDRC_FREQ2_INIT4(0), 0x00310008 },
> > + { DDRC_FREQ2_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 },
> > + { DDRC_FREQ2_INIT6(0), 0x0066004a },
> > + { DDRC_FREQ2_INIT7(0), 0x0006004a },
> > +
> > + /* boot start point */
> > + { DDRC_MSTR2(0), 0x2 }, //DDRC_MSTR2
> > +};
> > +
> > +/* PHY Initialize Configuration */
> > +struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
> > + { 0x1005f, 0x1ff },
> > + { 0x1015f, 0x1ff },
> > + { 0x1105f, 0x1ff },
> > + { 0x1115f, 0x1ff },
> > + { 0x1205f, 0x1ff },
> > + { 0x1215f, 0x1ff },
> > + { 0x1305f, 0x1ff },
> > + { 0x1315f, 0x1ff },
> > +
> > + { 0x11005f, 0x1ff },
> > + { 0x11015f, 0x1ff },
> > + { 0x11105f, 0x1ff },
> > + { 0x11115f, 0x1ff },
> > + { 0x11205f, 0x1ff },
> > + { 0x11215f, 0x1ff },
> > + { 0x11305f, 0x1ff },
> > + { 0x11315f, 0x1ff },
> > +
> > + { 0x21005f, 0x1ff },
> > + { 0x21015f, 0x1ff },
> > + { 0x21105f, 0x1ff },
> > + { 0x21115f, 0x1ff },
> > + { 0x21205f, 0x1ff },
> > + { 0x21215f, 0x1ff },
> > + { 0x21305f, 0x1ff },
> > + { 0x21315f, 0x1ff },
> > +
> > + { 0x55, 0x1ff },
> > + { 0x1055, 0x1ff },
> > + { 0x2055, 0x1ff },
> > + { 0x3055, 0x1ff },
> > + { 0x4055, 0x1ff },
> > + { 0x5055, 0x1ff },
> > + { 0x6055, 0x1ff },
> > + { 0x7055, 0x1ff },
> > + { 0x8055, 0x1ff },
> > + { 0x9055, 0x1ff },
> > +
> > + { 0x200c5, 0x19 },
> > + { 0x1200c5, 0x7 },
> > + { 0x2200c5, 0x7 },
> > +
> > + { 0x2002e, 0x2 },
> > + { 0x12002e, 0x2 },
> > + { 0x22002e, 0x2 },
> > +
> > + { 0x90204, 0x0 },
> > + { 0x190204, 0x0 },
> > + { 0x290204, 0x0 },
> > +
> > + { 0x20024, 0xab },
> > + { 0x2003a, 0x0 },
> > +
> > + { 0x120024, 0xab },
> > + { 0x2003a, 0x0 },
> > +
> > + { 0x220024, 0xab },
> > + { 0x2003a, 0x0 },
> > +
> > + { 0x20056, 0x3 },
> > + { 0x120056, 0xa },
> > + { 0x220056, 0xa },
> > +
> > + { 0x1004d, 0xe00 },
> > + { 0x1014d, 0xe00 },
> > + { 0x1104d, 0xe00 },
> > + { 0x1114d, 0xe00 },
> > + { 0x1204d, 0xe00 },
> > + { 0x1214d, 0xe00 },
> > + { 0x1304d, 0xe00 },
> > + { 0x1314d, 0xe00 },
> > +
> > + { 0x11004d, 0xe00 },
> > + { 0x11014d, 0xe00 },
> > + { 0x11104d, 0xe00 },
> > + { 0x11114d, 0xe00 },
> > + { 0x11204d, 0xe00 },
> > + { 0x11214d, 0xe00 },
> > + { 0x11304d, 0xe00 },
> > + { 0x11314d, 0xe00 },
> > +
> > + { 0x21004d, 0xe00 },
> > + { 0x21014d, 0xe00 },
> > + { 0x21104d, 0xe00 },
> > + { 0x21114d, 0xe00 },
> > + { 0x21204d, 0xe00 },
> > + { 0x21214d, 0xe00 },
> > + { 0x21304d, 0xe00 },
> > + { 0x21314d, 0xe00 },
> > +
> > + { 0x10049, 0xfbe },
> > + { 0x10149, 0xfbe },
> > + { 0x11049, 0xfbe },
> > + { 0x11149, 0xfbe },
> > + { 0x12049, 0xfbe },
> > + { 0x12149, 0xfbe },
> > + { 0x13049, 0xfbe },
> > + { 0x13149, 0xfbe },
> > +
> > + { 0x110049, 0xfbe },
> > + { 0x110149, 0xfbe },
> > + { 0x111049, 0xfbe },
> > + { 0x111149, 0xfbe },
> > + { 0x112049, 0xfbe },
> > + { 0x112149, 0xfbe },
> > + { 0x113049, 0xfbe },
> > + { 0x113149, 0xfbe },
> > +
> > + { 0x210049, 0xfbe },
> > + { 0x210149, 0xfbe },
> > + { 0x211049, 0xfbe },
> > + { 0x211149, 0xfbe },
> > + { 0x212049, 0xfbe },
> > + { 0x212149, 0xfbe },
> > + { 0x213049, 0xfbe },
> > + { 0x213149, 0xfbe },
> > +
> > + { 0x43, 0x63 },
> > + { 0x1043, 0x63 },
> > + { 0x2043, 0x63 },
> > + { 0x3043, 0x63 },
> > + { 0x4043, 0x63 },
> > + { 0x5043, 0x63 },
> > + { 0x6043, 0x63 },
> > + { 0x7043, 0x63 },
> > + { 0x8043, 0x63 },
> > + { 0x9043, 0x63 },
> > +
> > + { 0x20018, 0x3 },
> > + { 0x20075, 0x4 },
> > + { 0x20050, 0x0 },
> > + { 0x20008, 0x2ee },
> > + { 0x120008, 0x64 },
> > + { 0x220008, 0x19 },
> > + { 0x20088, 0x9 },
> > +
> > + { 0x200b2, 0x1d4 },
> > + { 0x10043, 0x5a1 },
> > + { 0x10143, 0x5a1 },
> > + { 0x11043, 0x5a1 },
> > + { 0x11143, 0x5a1 },
> > + { 0x12043, 0x5a1 },
> > + { 0x12143, 0x5a1 },
> > + { 0x13043, 0x5a1 },
> > + { 0x13143, 0x5a1 },
> > +
> > + { 0x1200b2, 0xdc },
> > + { 0x110043, 0x5a1 },
> > + { 0x110143, 0x5a1 },
> > + { 0x111043, 0x5a1 },
> > + { 0x111143, 0x5a1 },
> > + { 0x112043, 0x5a1 },
> > + { 0x112143, 0x5a1 },
> > + { 0x113043, 0x5a1 },
> > + { 0x113143, 0x5a1 },
> > +
> > + { 0x2200b2, 0xdc },
> > + { 0x210043, 0x5a1 },
> > + { 0x210143, 0x5a1 },
> > + { 0x211043, 0x5a1 },
> > + { 0x211143, 0x5a1 },
> > + { 0x212043, 0x5a1 },
> > + { 0x212143, 0x5a1 },
> > + { 0x213043, 0x5a1 },
> > + { 0x213143, 0x5a1 },
> > +
> > + { 0x200fa, 0x1 },
> > + { 0x1200fa, 0x1 },
> > + { 0x2200fa, 0x1 },
> > +
> > + { 0x20019, 0x1 },
> > + { 0x120019, 0x1 },
> > + { 0x220019, 0x1 },
> > +
> > + { 0x200f0, 0x660 },
> > + { 0x200f1, 0x0 },
> > + { 0x200f2, 0x4444 },
> > + { 0x200f3, 0x8888 },
> > + { 0x200f4, 0x5665 },
> > + { 0x200f5, 0x0 },
> > + { 0x200f6, 0x0 },
> > + { 0x200f7, 0xf000 },
> > +
> > + { 0x20025, 0x0 },
> > + { 0x2002d, LPDDR4_PHY_DMIPinPresent },
> > + { 0x12002d, LPDDR4_PHY_DMIPinPresent },
> > + { 0x22002d, LPDDR4_PHY_DMIPinPresent },
> > + { 0x200c7, 0x21 },
> > + { 0x200ca, 0x24 },
> > + { 0x1200c7, 0x21 },
> > + { 0x1200ca, 0x24 },
> > + { 0x2200c7, 0x21 },
> > + { 0x2200ca, 0x24 },
>
> Why do you add tuple - offset and value? Shouldn't we have the
> DDR training functions here?
>
> It is possible to train IMX6Q and Vybrid's DDR3 (as fair as I know).
> Would it be also possible to add the DDR4 training code for IMX8?
>
> > +};
> > +
> > +/* ddr phy trained csr */
> > +struct dram_cfg_param lpddr4_ddrphy_trained_csr[] = {
> > + { 0x200b2, 0x0 },
> > + { 0x1200b2, 0x0 },
> > + { 0x2200b2, 0x0 },
> > + { 0x200cb, 0x0 },
> > + { 0x10043, 0x0 },
> > + { 0x110043, 0x0 },
> > + { 0x210043, 0x0 },
> > + { 0x10143, 0x0 },
> > + { 0x110143, 0x0 },
> > + { 0x210143, 0x0 },
> > + { 0x11043, 0x0 },
> > + { 0x111043, 0x0 },
> > + { 0x211043, 0x0 },
> > + { 0x11143, 0x0 },
> > + { 0x111143, 0x0 },
> > + { 0x211143, 0x0 },
> > + { 0x12043, 0x0 },
> > + { 0x112043, 0x0 },
> > + { 0x212043, 0x0 },
> > + { 0x12143, 0x0 },
> > + { 0x112143, 0x0 },
> > + { 0x212143, 0x0 },
> > + { 0x13043, 0x0 },
> > + { 0x113043, 0x0 },
> > + { 0x213043, 0x0 },
> > + { 0x13143, 0x0 },
> > + { 0x113143, 0x0 },
> > + { 0x213143, 0x0 },
> > + { 0x80, 0x0 },
> > + { 0x100080, 0x0 },
> > + { 0x200080, 0x0 },
> > + { 0x1080, 0x0 },
> > + { 0x101080, 0x0 },
> > + { 0x201080, 0x0 },
> > + { 0x2080, 0x0 },
> > + { 0x102080, 0x0 },
> > + { 0x202080, 0x0 },
> > + { 0x3080, 0x0 },
> > + { 0x103080, 0x0 },
> > + { 0x203080, 0x0 },
> > + { 0x4080, 0x0 },
> > + { 0x104080, 0x0 },
> > + { 0x204080, 0x0 },
> > + { 0x5080, 0x0 },
> > + { 0x105080, 0x0 },
> > + { 0x205080, 0x0 },
> > + { 0x6080, 0x0 },
> > + { 0x106080, 0x0 },
> > + { 0x206080, 0x0 },
> > + { 0x7080, 0x0 },
> > + { 0x107080, 0x0 },
> > + { 0x207080, 0x0 },
> > + { 0x8080, 0x0 },
> > + { 0x108080, 0x0 },
> > + { 0x208080, 0x0 },
> > + { 0x9080, 0x0 },
> > + { 0x109080, 0x0 },
> > + { 0x209080, 0x0 },
> > + { 0x10080, 0x0 },
> > + { 0x110080, 0x0 },
> > + { 0x210080, 0x0 },
> > + { 0x10180, 0x0 },
> > + { 0x110180, 0x0 },
> > + { 0x210180, 0x0 },
> > + { 0x11080, 0x0 },
> > + { 0x111080, 0x0 },
> > + { 0x211080, 0x0 },
> > + { 0x11180, 0x0 },
> > + { 0x111180, 0x0 },
> > + { 0x211180, 0x0 },
> > + { 0x12080, 0x0 },
> > + { 0x112080, 0x0 },
> > + { 0x212080, 0x0 },
> > + { 0x12180, 0x0 },
> > + { 0x112180, 0x0 },
> > + { 0x212180, 0x0 },
> > + { 0x13080, 0x0 },
> > + { 0x113080, 0x0 },
> > + { 0x213080, 0x0 },
> > + { 0x13180, 0x0 },
> > + { 0x113180, 0x0 },
> > + { 0x213180, 0x0 },
> > + { 0x10081, 0x0 },
> > + { 0x110081, 0x0 },
> > + { 0x210081, 0x0 },
> > + { 0x10181, 0x0 },
> > + { 0x110181, 0x0 },
> > + { 0x210181, 0x0 },
> > + { 0x11081, 0x0 },
> > + { 0x111081, 0x0 },
> > + { 0x211081, 0x0 },
> > + { 0x11181, 0x0 },
> > + { 0x111181, 0x0 },
> > + { 0x211181, 0x0 },
> > + { 0x12081, 0x0 },
> > + { 0x112081, 0x0 },
> > + { 0x212081, 0x0 },
> > + { 0x12181, 0x0 },
> > + { 0x112181, 0x0 },
> > + { 0x212181, 0x0 },
> > + { 0x13081, 0x0 },
> > + { 0x113081, 0x0 },
> > + { 0x213081, 0x0 },
> > + { 0x13181, 0x0 },
> > + { 0x113181, 0x0 },
> > + { 0x213181, 0x0 },
> > + { 0x100d0, 0x0 },
> > + { 0x1100d0, 0x0 },
> > + { 0x2100d0, 0x0 },
> > + { 0x101d0, 0x0 },
> > + { 0x1101d0, 0x0 },
> > + { 0x2101d0, 0x0 },
> > + { 0x110d0, 0x0 },
> > + { 0x1110d0, 0x0 },
> > + { 0x2110d0, 0x0 },
> > + { 0x111d0, 0x0 },
> > + { 0x1111d0, 0x0 },
> > + { 0x2111d0, 0x0 },
> > + { 0x120d0, 0x0 },
> > + { 0x1120d0, 0x0 },
> > + { 0x2120d0, 0x0 },
> > + { 0x121d0, 0x0 },
> > + { 0x1121d0, 0x0 },
> > + { 0x2121d0, 0x0 },
> > + { 0x130d0, 0x0 },
> > + { 0x1130d0, 0x0 },
> > + { 0x2130d0, 0x0 },
> > + { 0x131d0, 0x0 },
> > + { 0x1131d0, 0x0 },
> > + { 0x2131d0, 0x0 },
> > + { 0x100d1, 0x0 },
> > + { 0x1100d1, 0x0 },
> > + { 0x2100d1, 0x0 },
> > + { 0x101d1, 0x0 },
> > + { 0x1101d1, 0x0 },
> > + { 0x2101d1, 0x0 },
> > + { 0x110d1, 0x0 },
> > + { 0x1110d1, 0x0 },
> > + { 0x2110d1, 0x0 },
> > + { 0x111d1, 0x0 },
> > + { 0x1111d1, 0x0 },
> > + { 0x2111d1, 0x0 },
> > + { 0x120d1, 0x0 },
> > + { 0x1120d1, 0x0 },
> > + { 0x2120d1, 0x0 },
> > + { 0x121d1, 0x0 },
> > + { 0x1121d1, 0x0 },
> > + { 0x2121d1, 0x0 },
> > + { 0x130d1, 0x0 },
> > + { 0x1130d1, 0x0 },
> > + { 0x2130d1, 0x0 },
> > + { 0x131d1, 0x0 },
> > + { 0x1131d1, 0x0 },
> > + { 0x2131d1, 0x0 },
> > + { 0x10068, 0x0 },
> > + { 0x10168, 0x0 },
> > + { 0x10268, 0x0 },
> > + { 0x10368, 0x0 },
> > + { 0x10468, 0x0 },
> > + { 0x10568, 0x0 },
> > + { 0x10668, 0x0 },
> > + { 0x10768, 0x0 },
> > + { 0x10868, 0x0 },
> > + { 0x11068, 0x0 },
> > + { 0x11168, 0x0 },
> > + { 0x11268, 0x0 },
> > + { 0x11368, 0x0 },
> > + { 0x11468, 0x0 },
> > + { 0x11568, 0x0 },
> > + { 0x11668, 0x0 },
> > + { 0x11768, 0x0 },
> > + { 0x11868, 0x0 },
> > + { 0x12068, 0x0 },
> > + { 0x12168, 0x0 },
> > + { 0x12268, 0x0 },
> > + { 0x12368, 0x0 },
> > + { 0x12468, 0x0 },
> > + { 0x12568, 0x0 },
> > + { 0x12668, 0x0 },
> > + { 0x12768, 0x0 },
> > + { 0x12868, 0x0 },
> > + { 0x13068, 0x0 },
> > + { 0x13168, 0x0 },
> > + { 0x13268, 0x0 },
> > + { 0x13368, 0x0 },
> > + { 0x13468, 0x0 },
> > + { 0x13568, 0x0 },
> > + { 0x13668, 0x0 },
> > + { 0x13768, 0x0 },
> > + { 0x13868, 0x0 },
> > + { 0x10069, 0x0 },
> > + { 0x10169, 0x0 },
> > + { 0x10269, 0x0 },
> > + { 0x10369, 0x0 },
> > + { 0x10469, 0x0 },
> > + { 0x10569, 0x0 },
> > + { 0x10669, 0x0 },
> > + { 0x10769, 0x0 },
> > + { 0x10869, 0x0 },
> > + { 0x11069, 0x0 },
> > + { 0x11169, 0x0 },
> > + { 0x11269, 0x0 },
> > + { 0x11369, 0x0 },
> > + { 0x11469, 0x0 },
> > + { 0x11569, 0x0 },
> > + { 0x11669, 0x0 },
> > + { 0x11769, 0x0 },
> > + { 0x11869, 0x0 },
> > + { 0x12069, 0x0 },
> > + { 0x12169, 0x0 },
> > + { 0x12269, 0x0 },
> > + { 0x12369, 0x0 },
> > + { 0x12469, 0x0 },
> > + { 0x12569, 0x0 },
> > + { 0x12669, 0x0 },
> > + { 0x12769, 0x0 },
> > + { 0x12869, 0x0 },
> > + { 0x13069, 0x0 },
> > + { 0x13169, 0x0 },
> > + { 0x13269, 0x0 },
> > + { 0x13369, 0x0 },
> > + { 0x13469, 0x0 },
> > + { 0x13569, 0x0 },
> > + { 0x13669, 0x0 },
> > + { 0x13769, 0x0 },
> > + { 0x13869, 0x0 },
> > + { 0x1008c, 0x0 },
> > + { 0x11008c, 0x0 },
> > + { 0x21008c, 0x0 },
> > + { 0x1018c, 0x0 },
> > + { 0x11018c, 0x0 },
> > + { 0x21018c, 0x0 },
> > + { 0x1108c, 0x0 },
> > + { 0x11108c, 0x0 },
> > + { 0x21108c, 0x0 },
> > + { 0x1118c, 0x0 },
> > + { 0x11118c, 0x0 },
> > + { 0x21118c, 0x0 },
> > + { 0x1208c, 0x0 },
> > + { 0x11208c, 0x0 },
> > + { 0x21208c, 0x0 },
> > + { 0x1218c, 0x0 },
> > + { 0x11218c, 0x0 },
> > + { 0x21218c, 0x0 },
> > + { 0x1308c, 0x0 },
> > + { 0x11308c, 0x0 },
> > + { 0x21308c, 0x0 },
> > + { 0x1318c, 0x0 },
> > + { 0x11318c, 0x0 },
> > + { 0x21318c, 0x0 },
> > + { 0x1008d, 0x0 },
> > + { 0x11008d, 0x0 },
> > + { 0x21008d, 0x0 },
> > + { 0x1018d, 0x0 },
> > + { 0x11018d, 0x0 },
> > + { 0x21018d, 0x0 },
> > + { 0x1108d, 0x0 },
> > + { 0x11108d, 0x0 },
> > + { 0x21108d, 0x0 },
> > + { 0x1118d, 0x0 },
> > + { 0x11118d, 0x0 },
> > + { 0x21118d, 0x0 },
> > + { 0x1208d, 0x0 },
> > + { 0x11208d, 0x0 },
> > + { 0x21208d, 0x0 },
> > + { 0x1218d, 0x0 },
> > + { 0x11218d, 0x0 },
> > + { 0x21218d, 0x0 },
> > + { 0x1308d, 0x0 },
> > + { 0x11308d, 0x0 },
> > + { 0x21308d, 0x0 },
> > + { 0x1318d, 0x0 },
> > + { 0x11318d, 0x0 },
> > + { 0x21318d, 0x0 },
> > + { 0x100c0, 0x0 },
> > + { 0x1100c0, 0x0 },
> > + { 0x2100c0, 0x0 },
> > + { 0x101c0, 0x0 },
> > + { 0x1101c0, 0x0 },
> > + { 0x2101c0, 0x0 },
> > + { 0x102c0, 0x0 },
> > + { 0x1102c0, 0x0 },
> > + { 0x2102c0, 0x0 },
> > + { 0x103c0, 0x0 },
> > + { 0x1103c0, 0x0 },
> > + { 0x2103c0, 0x0 },
> > + { 0x104c0, 0x0 },
> > + { 0x1104c0, 0x0 },
> > + { 0x2104c0, 0x0 },
> > + { 0x105c0, 0x0 },
> > + { 0x1105c0, 0x0 },
> > + { 0x2105c0, 0x0 },
> > + { 0x106c0, 0x0 },
> > + { 0x1106c0, 0x0 },
> > + { 0x2106c0, 0x0 },
> > + { 0x107c0, 0x0 },
> > + { 0x1107c0, 0x0 },
> > + { 0x2107c0, 0x0 },
> > + { 0x108c0, 0x0 },
> > + { 0x1108c0, 0x0 },
> > + { 0x2108c0, 0x0 },
> > + { 0x110c0, 0x0 },
> > + { 0x1110c0, 0x0 },
> > + { 0x2110c0, 0x0 },
> > + { 0x111c0, 0x0 },
> > + { 0x1111c0, 0x0 },
> > + { 0x2111c0, 0x0 },
> > + { 0x112c0, 0x0 },
> > + { 0x1112c0, 0x0 },
> > + { 0x2112c0, 0x0 },
> > + { 0x113c0, 0x0 },
> > + { 0x1113c0, 0x0 },
> > + { 0x2113c0, 0x0 },
> > + { 0x114c0, 0x0 },
> > + { 0x1114c0, 0x0 },
> > + { 0x2114c0, 0x0 },
> > + { 0x115c0, 0x0 },
> > + { 0x1115c0, 0x0 },
> > + { 0x2115c0, 0x0 },
> > + { 0x116c0, 0x0 },
> > + { 0x1116c0, 0x0 },
> > + { 0x2116c0, 0x0 },
> > + { 0x117c0, 0x0 },
> > + { 0x1117c0, 0x0 },
> > + { 0x2117c0, 0x0 },
> > + { 0x118c0, 0x0 },
> > + { 0x1118c0, 0x0 },
> > + { 0x2118c0, 0x0 },
> > + { 0x120c0, 0x0 },
> > + { 0x1120c0, 0x0 },
> > + { 0x2120c0, 0x0 },
> > + { 0x121c0, 0x0 },
> > + { 0x1121c0, 0x0 },
> > + { 0x2121c0, 0x0 },
> > + { 0x122c0, 0x0 },
> > + { 0x1122c0, 0x0 },
> > + { 0x2122c0, 0x0 },
> > + { 0x123c0, 0x0 },
> > + { 0x1123c0, 0x0 },
> > + { 0x2123c0, 0x0 },
> > + { 0x124c0, 0x0 },
> > + { 0x1124c0, 0x0 },
> > + { 0x2124c0, 0x0 },
> > + { 0x125c0, 0x0 },
> > + { 0x1125c0, 0x0 },
> > + { 0x2125c0, 0x0 },
> > + { 0x126c0, 0x0 },
> > + { 0x1126c0, 0x0 },
> > + { 0x2126c0, 0x0 },
> > + { 0x127c0, 0x0 },
> > + { 0x1127c0, 0x0 },
> > + { 0x2127c0, 0x0 },
> > + { 0x128c0, 0x0 },
> > + { 0x1128c0, 0x0 },
> > + { 0x2128c0, 0x0 },
> > + { 0x130c0, 0x0 },
> > + { 0x1130c0, 0x0 },
> > + { 0x2130c0, 0x0 },
> > + { 0x131c0, 0x0 },
> > + { 0x1131c0, 0x0 },
> > + { 0x2131c0, 0x0 },
> > + { 0x132c0, 0x0 },
> > + { 0x1132c0, 0x0 },
> > + { 0x2132c0, 0x0 },
> > + { 0x133c0, 0x0 },
> > + { 0x1133c0, 0x0 },
> > + { 0x2133c0, 0x0 },
> > + { 0x134c0, 0x0 },
> > + { 0x1134c0, 0x0 },
> > + { 0x2134c0, 0x0 },
> > + { 0x135c0, 0x0 },
> > + { 0x1135c0, 0x0 },
> > + { 0x2135c0, 0x0 },
> > + { 0x136c0, 0x0 },
> > + { 0x1136c0, 0x0 },
> > + { 0x2136c0, 0x0 },
> > + { 0x137c0, 0x0 },
> > + { 0x1137c0, 0x0 },
> > + { 0x2137c0, 0x0 },
> > + { 0x138c0, 0x0 },
> > + { 0x1138c0, 0x0 },
> > + { 0x2138c0, 0x0 },
> > + { 0x100c1, 0x0 },
> > + { 0x1100c1, 0x0 },
> > + { 0x2100c1, 0x0 },
> > + { 0x101c1, 0x0 },
> > + { 0x1101c1, 0x0 },
> > + { 0x2101c1, 0x0 },
> > + { 0x102c1, 0x0 },
> > + { 0x1102c1, 0x0 },
> > + { 0x2102c1, 0x0 },
> > + { 0x103c1, 0x0 },
> > + { 0x1103c1, 0x0 },
> > + { 0x2103c1, 0x0 },
> > + { 0x104c1, 0x0 },
> > + { 0x1104c1, 0x0 },
> > + { 0x2104c1, 0x0 },
> > + { 0x105c1, 0x0 },
> > + { 0x1105c1, 0x0 },
> > + { 0x2105c1, 0x0 },
> > + { 0x106c1, 0x0 },
> > + { 0x1106c1, 0x0 },
> > + { 0x2106c1, 0x0 },
> > + { 0x107c1, 0x0 },
> > + { 0x1107c1, 0x0 },
> > + { 0x2107c1, 0x0 },
> > + { 0x108c1, 0x0 },
> > + { 0x1108c1, 0x0 },
> > + { 0x2108c1, 0x0 },
> > + { 0x110c1, 0x0 },
> > + { 0x1110c1, 0x0 },
> > + { 0x2110c1, 0x0 },
> > + { 0x111c1, 0x0 },
> > + { 0x1111c1, 0x0 },
> > + { 0x2111c1, 0x0 },
> > + { 0x112c1, 0x0 },
> > + { 0x1112c1, 0x0 },
> > + { 0x2112c1, 0x0 },
> > + { 0x113c1, 0x0 },
> > + { 0x1113c1, 0x0 },
> > + { 0x2113c1, 0x0 },
> > + { 0x114c1, 0x0 },
> > + { 0x1114c1, 0x0 },
> > + { 0x2114c1, 0x0 },
> > + { 0x115c1, 0x0 },
> > + { 0x1115c1, 0x0 },
> > + { 0x2115c1, 0x0 },
> > + { 0x116c1, 0x0 },
> > + { 0x1116c1, 0x0 },
> > + { 0x2116c1, 0x0 },
> > + { 0x117c1, 0x0 },
> > + { 0x1117c1, 0x0 },
> > + { 0x2117c1, 0x0 },
> > + { 0x118c1, 0x0 },
> > + { 0x1118c1, 0x0 },
> > + { 0x2118c1, 0x0 },
> > + { 0x120c1, 0x0 },
> > + { 0x1120c1, 0x0 },
> > + { 0x2120c1, 0x0 },
> > + { 0x121c1, 0x0 },
> > + { 0x1121c1, 0x0 },
> > + { 0x2121c1, 0x0 },
> > + { 0x122c1, 0x0 },
> > + { 0x1122c1, 0x0 },
> > + { 0x2122c1, 0x0 },
> > + { 0x123c1, 0x0 },
> > + { 0x1123c1, 0x0 },
> > + { 0x2123c1, 0x0 },
> > + { 0x124c1, 0x0 },
> > + { 0x1124c1, 0x0 },
> > + { 0x2124c1, 0x0 },
> > + { 0x125c1, 0x0 },
> > + { 0x1125c1, 0x0 },
> > + { 0x2125c1, 0x0 },
> > + { 0x126c1, 0x0 },
> > + { 0x1126c1, 0x0 },
> > + { 0x2126c1, 0x0 },
> > + { 0x127c1, 0x0 },
> > + { 0x1127c1, 0x0 },
> > + { 0x2127c1, 0x0 },
> > + { 0x128c1, 0x0 },
> > + { 0x1128c1, 0x0 },
> > + { 0x2128c1, 0x0 },
> > + { 0x130c1, 0x0 },
> > + { 0x1130c1, 0x0 },
> > + { 0x2130c1, 0x0 },
> > + { 0x131c1, 0x0 },
> > + { 0x1131c1, 0x0 },
> > + { 0x2131c1, 0x0 },
> > + { 0x132c1, 0x0 },
> > + { 0x1132c1, 0x0 },
> > + { 0x2132c1, 0x0 },
> > + { 0x133c1, 0x0 },
> > + { 0x1133c1, 0x0 },
> > + { 0x2133c1, 0x0 },
> > + { 0x134c1, 0x0 },
> > + { 0x1134c1, 0x0 },
> > + { 0x2134c1, 0x0 },
> > + { 0x135c1, 0x0 },
> > + { 0x1135c1, 0x0 },
> > + { 0x2135c1, 0x0 },
> > + { 0x136c1, 0x0 },
> > + { 0x1136c1, 0x0 },
> > + { 0x2136c1, 0x0 },
> > + { 0x137c1, 0x0 },
> > + { 0x1137c1, 0x0 },
> > + { 0x2137c1, 0x0 },
> > + { 0x138c1, 0x0 },
> > + { 0x1138c1, 0x0 },
> > + { 0x2138c1, 0x0 },
> > + { 0x10020, 0x0 },
> > + { 0x110020, 0x0 },
> > + { 0x210020, 0x0 },
> > + { 0x11020, 0x0 },
> > + { 0x111020, 0x0 },
> > + { 0x211020, 0x0 },
> > + { 0x12020, 0x0 },
> > + { 0x112020, 0x0 },
> > + { 0x212020, 0x0 },
> > + { 0x13020, 0x0 },
> > + { 0x113020, 0x0 },
> > + { 0x213020, 0x0 },
> > + { 0x20072, 0x0 },
> > + { 0x20073, 0x0 },
> > + { 0x20074, 0x0 },
> > + { 0x100aa, 0x0 },
> > + { 0x110aa, 0x0 },
> > + { 0x120aa, 0x0 },
> > + { 0x130aa, 0x0 },
> > + { 0x20010, 0x0 },
> > + { 0x120010, 0x0 },
> > + { 0x220010, 0x0 },
> > + { 0x20011, 0x0 },
> > + { 0x120011, 0x0 },
> > + { 0x220011, 0x0 },
> > + { 0x100ae, 0x0 },
> > + { 0x1100ae, 0x0 },
> > + { 0x2100ae, 0x0 },
> > + { 0x100af, 0x0 },
> > + { 0x1100af, 0x0 },
> > + { 0x2100af, 0x0 },
> > + { 0x110ae, 0x0 },
> > + { 0x1110ae, 0x0 },
> > + { 0x2110ae, 0x0 },
> > + { 0x110af, 0x0 },
> > + { 0x1110af, 0x0 },
> > + { 0x2110af, 0x0 },
> > + { 0x120ae, 0x0 },
> > + { 0x1120ae, 0x0 },
> > + { 0x2120ae, 0x0 },
> > + { 0x120af, 0x0 },
> > + { 0x1120af, 0x0 },
> > + { 0x2120af, 0x0 },
> > + { 0x130ae, 0x0 },
> > + { 0x1130ae, 0x0 },
> > + { 0x2130ae, 0x0 },
> > + { 0x130af, 0x0 },
> > + { 0x1130af, 0x0 },
> > + { 0x2130af, 0x0 },
> > + { 0x20020, 0x0 },
> > + { 0x120020, 0x0 },
> > + { 0x220020, 0x0 },
> > + { 0x100a0, 0x0 },
> > + { 0x100a1, 0x0 },
> > + { 0x100a2, 0x0 },
> > + { 0x100a3, 0x0 },
> > + { 0x100a4, 0x0 },
> > + { 0x100a5, 0x0 },
> > + { 0x100a6, 0x0 },
> > + { 0x100a7, 0x0 },
> > + { 0x110a0, 0x0 },
> > + { 0x110a1, 0x0 },
> > + { 0x110a2, 0x0 },
> > + { 0x110a3, 0x0 },
> > + { 0x110a4, 0x0 },
> > + { 0x110a5, 0x0 },
> > + { 0x110a6, 0x0 },
> > + { 0x110a7, 0x0 },
> > + { 0x120a0, 0x0 },
> > + { 0x120a1, 0x0 },
> > + { 0x120a2, 0x0 },
> > + { 0x120a3, 0x0 },
> > + { 0x120a4, 0x0 },
> > + { 0x120a5, 0x0 },
> > + { 0x120a6, 0x0 },
> > + { 0x120a7, 0x0 },
> > + { 0x130a0, 0x0 },
> > + { 0x130a1, 0x0 },
> > + { 0x130a2, 0x0 },
> > + { 0x130a3, 0x0 },
> > + { 0x130a4, 0x0 },
> > + { 0x130a5, 0x0 },
> > + { 0x130a6, 0x0 },
> > + { 0x130a7, 0x0 },
> > + { 0x2007c, 0x0 },
> > + { 0x12007c, 0x0 },
> > + { 0x22007c, 0x0 },
> > + { 0x2007d, 0x0 },
> > + { 0x12007d, 0x0 },
> > + { 0x22007d, 0x0 },
> > + { 0x400fd, 0x0 },
> > + { 0x400c0, 0x0 },
> > + { 0x90201, 0x0 },
> > + { 0x190201, 0x0 },
> > + { 0x290201, 0x0 },
> > + { 0x90202, 0x0 },
> > + { 0x190202, 0x0 },
> > + { 0x290202, 0x0 },
> > + { 0x90203, 0x0 },
> > + { 0x190203, 0x0 },
> > + { 0x290203, 0x0 },
> > + { 0x90204, 0x0 },
> > + { 0x190204, 0x0 },
> > + { 0x290204, 0x0 },
> > + { 0x90205, 0x0 },
> > + { 0x190205, 0x0 },
> > + { 0x290205, 0x0 },
> > + { 0x90206, 0x0 },
> > + { 0x190206, 0x0 },
> > + { 0x290206, 0x0 },
> > + { 0x90207, 0x0 },
> > + { 0x190207, 0x0 },
> > + { 0x290207, 0x0 },
> > + { 0x90208, 0x0 },
> > + { 0x190208, 0x0 },
> > + { 0x290208, 0x0 },
> > + { 0x10062, 0x0 },
> > + { 0x10162, 0x0 },
> > + { 0x10262, 0x0 },
> > + { 0x10362, 0x0 },
> > + { 0x10462, 0x0 },
> > + { 0x10562, 0x0 },
> > + { 0x10662, 0x0 },
> > + { 0x10762, 0x0 },
> > + { 0x10862, 0x0 },
> > + { 0x11062, 0x0 },
> > + { 0x11162, 0x0 },
> > + { 0x11262, 0x0 },
> > + { 0x11362, 0x0 },
> > + { 0x11462, 0x0 },
> > + { 0x11562, 0x0 },
> > + { 0x11662, 0x0 },
> > + { 0x11762, 0x0 },
> > + { 0x11862, 0x0 },
> > + { 0x12062, 0x0 },
> > + { 0x12162, 0x0 },
> > + { 0x12262, 0x0 },
> > + { 0x12362, 0x0 },
> > + { 0x12462, 0x0 },
> > + { 0x12562, 0x0 },
> > + { 0x12662, 0x0 },
> > + { 0x12762, 0x0 },
> > + { 0x12862, 0x0 },
> > + { 0x13062, 0x0 },
> > + { 0x13162, 0x0 },
> > + { 0x13262, 0x0 },
> > + { 0x13362, 0x0 },
> > + { 0x13462, 0x0 },
> > + { 0x13562, 0x0 },
> > + { 0x13662, 0x0 },
> > + { 0x13762, 0x0 },
> > + { 0x13862, 0x0 },
> > + { 0x20077, 0x0 },
> > + { 0x10001, 0x0 },
> > + { 0x11001, 0x0 },
> > + { 0x12001, 0x0 },
> > + { 0x13001, 0x0 },
> > + { 0x10040, 0x0 },
> > + { 0x10140, 0x0 },
> > + { 0x10240, 0x0 },
> > + { 0x10340, 0x0 },
> > + { 0x10440, 0x0 },
> > + { 0x10540, 0x0 },
> > + { 0x10640, 0x0 },
> > + { 0x10740, 0x0 },
> > + { 0x10840, 0x0 },
> > + { 0x10030, 0x0 },
> > + { 0x10130, 0x0 },
> > + { 0x10230, 0x0 },
> > + { 0x10330, 0x0 },
> > + { 0x10430, 0x0 },
> > + { 0x10530, 0x0 },
> > + { 0x10630, 0x0 },
> > + { 0x10730, 0x0 },
> > + { 0x10830, 0x0 },
> > + { 0x11040, 0x0 },
> > + { 0x11140, 0x0 },
> > + { 0x11240, 0x0 },
> > + { 0x11340, 0x0 },
> > + { 0x11440, 0x0 },
> > + { 0x11540, 0x0 },
> > + { 0x11640, 0x0 },
> > + { 0x11740, 0x0 },
> > + { 0x11840, 0x0 },
> > + { 0x11030, 0x0 },
> > + { 0x11130, 0x0 },
> > + { 0x11230, 0x0 },
> > + { 0x11330, 0x0 },
> > + { 0x11430, 0x0 },
> > + { 0x11530, 0x0 },
> > + { 0x11630, 0x0 },
> > + { 0x11730, 0x0 },
> > + { 0x11830, 0x0 },
> > + { 0x12040, 0x0 },
> > + { 0x12140, 0x0 },
> > + { 0x12240, 0x0 },
> > + { 0x12340, 0x0 },
> > + { 0x12440, 0x0 },
> > + { 0x12540, 0x0 },
> > + { 0x12640, 0x0 },
> > + { 0x12740, 0x0 },
> > + { 0x12840, 0x0 },
> > + { 0x12030, 0x0 },
> > + { 0x12130, 0x0 },
> > + { 0x12230, 0x0 },
> > + { 0x12330, 0x0 },
> > + { 0x12430, 0x0 },
> > + { 0x12530, 0x0 },
> > + { 0x12630, 0x0 },
> > + { 0x12730, 0x0 },
> > + { 0x12830, 0x0 },
> > + { 0x13040, 0x0 },
> > + { 0x13140, 0x0 },
> > + { 0x13240, 0x0 },
> > + { 0x13340, 0x0 },
> > + { 0x13440, 0x0 },
> > + { 0x13540, 0x0 },
> > + { 0x13640, 0x0 },
> > + { 0x13740, 0x0 },
> > + { 0x13840, 0x0 },
> > + { 0x13030, 0x0 },
> > + { 0x13130, 0x0 },
> > + { 0x13230, 0x0 },
> > + { 0x13330, 0x0 },
> > + { 0x13430, 0x0 },
> > + { 0x13530, 0x0 },
> > + { 0x13630, 0x0 },
> > + { 0x13730, 0x0 },
> > + { 0x13830, 0x0 },
> > +};
>
> The same as above. Please look into imx6q DDR3 training code.
>
> > +
> > +/* P0 message block paremeter for training firmware */
> > +struct dram_cfg_param lpddr4_fsp0_cfg[] = {
> > + { 0xd0000, 0x0 },
> > + { 0x54000, 0x0 },
> > + { 0x54001, 0x0 },
> > + { 0x54002, 0x0 },
> > + { 0x54003, 0xbb8 },
> > + { 0x54004, 0x2 },
> > + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY
> > Ron/Rtt
> > + { 0x54006, LPDDR4_PHY_VREF_VALUE },
> > + { 0x54007, 0x0 },
> > + { 0x54008, 0x131f },
> > + { 0x54009, 0xc8 },
> > + { 0x5400a, 0x0 },
> > + { 0x5400b, 0x2 },
> > + { 0x5400c, 0x0 },
> > + { 0x5400d, 0x0 },
> > + { 0x5400e, 0x0 },
> > + { 0x5400f, 0x0 },
> > + { 0x54010, 0x0 },
> > + { 0x54011, 0x0 },
> > + { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
> > + { 0x54013, 0x0 },
> > + { 0x54014, 0x0 },
> > + { 0x54015, 0x0 },
> > + { 0x54016, 0x0 },
> > + { 0x54017, 0x0 },
> > + { 0x54018, 0x0 },
> > + { 0x54019, 0x2dd4 },
> > + { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
> > + { 0x5401b, 0x4d66 },
> > + { 0x5401c, 0x4d08 },
> > + { 0x5401d, 0x0 },
> > + { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
> > + { 0x5401f, 0x2dd4 },
> > + { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
> > + { 0x54021, 0x4d66 },
> > + { 0x54022, 0x4d08 },
> > + { 0x54023, 0x0 },
> > + { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
> > + { 0x54025, 0x0 },
> > + { 0x54026, 0x0 },
> > + { 0x54027, 0x0 },
> > + { 0x54028, 0x0 },
> > + { 0x54029, 0x0 },
> > + { 0x5402a, 0x0 },
> > + { 0x5402b, 0x1000 },
> > + { 0x5402c, LPDDR4_CS },
> > + { 0x5402d, 0x0 },
> > + { 0x5402e, 0x0 },
> > + { 0x5402f, 0x0 },
> > + { 0x54030, 0x0 },
> > + { 0x54031, 0x0 },
> > + { 0x54032, 0xd400 },
> > + { 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
> > + { 0x54034, 0x6600 },
> > + { 0x54035, 0x84d },
> > + { 0x54036, 0x4d },
> > + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
> > + { 0x54038, 0xd400 },
> > + { 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
> > + { 0x5403a, 0x6600 },
> > + { 0x5403b, 0x84d },
> > + { 0x5403c, 0x4d },
> > + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
> > + { 0x5403e, 0x0 },
> > + { 0x5403f, 0x0 },
> > + { 0x54040, 0x0 },
> > + { 0x54041, 0x0 },
> > + { 0x54042, 0x0 },
> > + { 0x54043, 0x0 },
> > + { 0x54044, 0x0 },
> > + { 0xd0000, 0x1 },
> > +};
> > +
> > +/* P1 message block paremeter for training firmware */
> > +struct dram_cfg_param lpddr4_fsp1_cfg[] = {
> > + { 0xd0000, 0x0 },
> > + { 0x54000, 0x0 },
> > + { 0x54001, 0x0 },
> > + { 0x54002, 0x101 },
> > + { 0x54003, 0x190 },
> > + { 0x54004, 0x2 },
> > + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY
> > Ron/Rtt
> > + { 0x54006, LPDDR4_PHY_VREF_VALUE },
> > + { 0x54007, 0x0 },
> > + { 0x54008, 0x121f },
> > + { 0x54009, 0xc8 },
> > + { 0x5400a, 0x0 },
> > + { 0x5400b, 0x2 },
> > + { 0x5400c, 0x0 },
> > + { 0x5400d, 0x0 },
> > + { 0x5400e, 0x0 },
> > + { 0x5400f, 0x0 },
> > + { 0x54010, 0x0 },
> > + { 0x54011, 0x0 },
> > + { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
> > + { 0x54013, 0x0 },
> > + { 0x54014, 0x0 },
> > + { 0x54015, 0x0 },
> > + { 0x54016, 0x0 },
> > + { 0x54017, 0x0 },
> > + { 0x54018, 0x0 },
> > + { 0x54019, 0x84 },
> > + { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
> > + { 0x5401b, 0x4d66 },
> > + { 0x5401c, 0x4d08 },
> > + { 0x5401d, 0x0 },
> > + { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
> > + { 0x5401f, 0x84 },
> > + { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
> > + { 0x54021, 0x4d66 },
> > + { 0x54022, 0x4d08 },
> > + { 0x54023, 0x0 },
> > + { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
> > + { 0x54025, 0x0 },
> > + { 0x54026, 0x0 },
> > + { 0x54027, 0x0 },
> > + { 0x54028, 0x0 },
> > + { 0x54029, 0x0 },
> > + { 0x5402a, 0x0 },
> > + { 0x5402b, 0x1000 },
> > + { 0x5402c, LPDDR4_CS },
> > + { 0x5402d, 0x0 },
> > + { 0x5402e, 0x0 },
> > + { 0x5402f, 0x0 },
> > + { 0x54030, 0x0 },
> > + { 0x54031, 0x0 },
> > + { 0x54032, 0x8400 },
> > + { 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
> > + { 0x54034, 0x6600 },
> > + { 0x54035, 0x84d },
> > + { 0x54036, 0x4d },
> > + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
> > + { 0x54038, 0x8400 },
> > + { 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
> > + { 0x5403a, 0x6600 },
> > + { 0x5403b, 0x84d },
> > + { 0x5403c, 0x4d },
> > + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
> > + { 0x5403e, 0x0 },
> > + { 0x5403f, 0x0 },
> > + { 0x54040, 0x0 },
> > + { 0x54041, 0x0 },
> > + { 0x54042, 0x0 },
> > + { 0x54043, 0x0 },
> > + { 0x54044, 0x0 },
> > + { 0xd0000, 0x1 },
> > +};
> > +
> > +/* P1 message block paremeter for training firmware */
> > +struct dram_cfg_param lpddr4_fsp2_cfg[] = {
> > + { 0xd0000, 0x0 },
> > + { 0x54000, 0x0 },
> > + { 0x54001, 0x0 },
> > + { 0x54002, 0x102 },
> > + { 0x54003, 0x64 },
> > + { 0x54004, 0x2 },
> > + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY
> > Ron/Rtt
> > + { 0x54006, LPDDR4_PHY_VREF_VALUE },
> > + { 0x54007, 0x0 },
> > + { 0x54008, 0x121f },
> > + { 0x54009, 0xc8 },
> > + { 0x5400a, 0x0 },
> > + { 0x5400b, 0x2 },
> > + { 0x5400c, 0x0 },
> > + { 0x5400d, 0x0 },
> > + { 0x5400e, 0x0 },
> > + { 0x5400f, 0x0 },
> > + { 0x54010, 0x0 },
> > + { 0x54011, 0x0 },
> > + { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
> > + { 0x54013, 0x0 },
> > + { 0x54014, 0x0 },
> > + { 0x54015, 0x0 },
> > + { 0x54016, 0x0 },
> > + { 0x54017, 0x0 },
> > + { 0x54018, 0x0 },
> > + { 0x54019, 0x84 },
> > + { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
> > + { 0x5401b, 0x4d66 },
> > + { 0x5401c, 0x4d08 },
> > + { 0x5401d, 0x0 },
> > + { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
> > + { 0x5401f, 0x84 },
> > + { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
> > + { 0x54021, 0x4d66 },
> > + { 0x54022, 0x4d08 },
> > + { 0x54023, 0x0 },
> > + { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
> > + { 0x54025, 0x0 },
> > + { 0x54026, 0x0 },
> > + { 0x54027, 0x0 },
> > + { 0x54028, 0x0 },
> > + { 0x54029, 0x0 },
> > + { 0x5402a, 0x0 },
> > + { 0x5402b, 0x1000 },
> > + { 0x5402c, LPDDR4_CS },
> > + { 0x5402d, 0x0 },
> > + { 0x5402e, 0x0 },
> > + { 0x5402f, 0x0 },
> > + { 0x54030, 0x0 },
> > + { 0x54031, 0x0 },
> > + { 0x54032, 0x8400 },
> > + { 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
> > + { 0x54034, 0x6600 },
> > + { 0x54035, 0x84d },
> > + { 0x54036, 0x4d },
> > + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
> > + { 0x54038, 0x8400 },
> > + { 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
> > + { 0x5403a, 0x6600 },
> > + { 0x5403b, 0x84d },
> > + { 0x5403c, 0x4d },
> > + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
> > + { 0x5403e, 0x0 },
> > + { 0x5403f, 0x0 },
> > + { 0x54040, 0x0 },
> > + { 0x54041, 0x0 },
> > + { 0x54042, 0x0 },
> > + { 0x54043, 0x0 },
> > + { 0x54044, 0x0 },
> > + { 0xd0000, 0x1 },
> > +};
> > +
> > +/* P0 2D message block paremeter for training firmware */
> > +struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
> > + { 0xd0000, 0x0 },
> > + { 0x54000, 0x0 },
> > + { 0x54001, 0x0 },
> > + { 0x54002, 0x0 },
> > + { 0x54003, 0xbb8 },
> > + { 0x54004, 0x2 },
> > + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY
> > Ron/Rtt
> > + { 0x54006, LPDDR4_PHY_VREF_VALUE },
> > + { 0x54007, 0x0 },
> > + { 0x54008, 0x61 },
> > + { 0x54009, 0xc8 },
> > + { 0x5400a, 0x0 },
> > + { 0x5400b, 0x2 },
> > + { 0x5400c, 0x0 },
> > + { 0x5400d, 0x0 },
> > + { 0x5400e, 0x0 },
> > + { 0x5400f, 0x100 },
> > + { 0x54010, 0x1f7f },
> > + { 0x54011, 0x0 },
> > + { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
> > + { 0x54013, 0x0 },
> > + { 0x54014, 0x0 },
> > + { 0x54015, 0x0 },
> > + { 0x54016, 0x0 },
> > + { 0x54017, 0x0 },
> > + { 0x54018, 0x0 },
> > + { 0x54019, 0x2dd4 },
> > + { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
> > + { 0x5401b, 0x4d66 },
> > + { 0x5401c, 0x4d08 },
> > + { 0x5401d, 0x0 },
> > + { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
> > + { 0x5401f, 0x2dd4 },
> > + { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
> > + { 0x54021, 0x4d66 },
> > + { 0x54022, 0x4d08 },
> > + { 0x54023, 0x0 },
> > + { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
> > + { 0x54025, 0x0 },
> > + { 0x54026, 0x0 },
> > + { 0x54027, 0x0 },
> > + { 0x54028, 0x0 },
> > + { 0x54029, 0x0 },
> > + { 0x5402a, 0x0 },
> > + { 0x5402b, 0x1000 },
> > + { 0x5402c, LPDDR4_CS },
> > + { 0x5402d, 0x0 },
> > + { 0x5402e, 0x0 },
> > + { 0x5402f, 0x0 },
> > + { 0x54030, 0x0 },
> > + { 0x54031, 0x0 },
> > + { 0x54032, 0xd400 },
> > + { 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
> > + { 0x54034, 0x6600 },
> > + { 0x54035, 0x84d },
> > + { 0x54036, 0x4d },
> > + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
> > + { 0x54038, 0xd400 },
> > + { 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
> > + { 0x5403a, 0x6600 },
> > + { 0x5403b, 0x84d },
> > + { 0x5403c, 0x4d },
> > + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
> > + { 0x5403e, 0x0 },
> > + { 0x5403f, 0x0 },
> > + { 0x54040, 0x0 },
> > + { 0x54041, 0x0 },
> > + { 0x54042, 0x0 },
> > + { 0x54043, 0x0 },
> > + { 0x54044, 0x0 },
> > + { 0xd0000, 0x1 },
> > +};
> > +
> > +/* DRAM PHY init engine image */
> > +struct dram_cfg_param lpddr4_phy_pie[] = {
> > + { 0xd0000, 0x0 },
> > + { 0x90000, 0x10 },
> > + { 0x90001, 0x400 },
> > + { 0x90002, 0x10e },
> > + { 0x90003, 0x0 },
> > + { 0x90004, 0x0 },
> > + { 0x90005, 0x8 },
> > + { 0x90029, 0xb },
> > + { 0x9002a, 0x480 },
> > + { 0x9002b, 0x109 },
> > + { 0x9002c, 0x8 },
> > + { 0x9002d, 0x448 },
> > + { 0x9002e, 0x139 },
> > + { 0x9002f, 0x8 },
> > + { 0x90030, 0x478 },
> > + { 0x90031, 0x109 },
> > + { 0x90032, 0x0 },
> > + { 0x90033, 0xe8 },
> > + { 0x90034, 0x109 },
> > + { 0x90035, 0x2 },
> > + { 0x90036, 0x10 },
> > + { 0x90037, 0x139 },
> > + { 0x90038, 0xf },
> > + { 0x90039, 0x7c0 },
> > + { 0x9003a, 0x139 },
> > + { 0x9003b, 0x44 },
> > + { 0x9003c, 0x630 },
> > + { 0x9003d, 0x159 },
> > + { 0x9003e, 0x14f },
> > + { 0x9003f, 0x630 },
> > + { 0x90040, 0x159 },
> > + { 0x90041, 0x47 },
> > + { 0x90042, 0x630 },
> > + { 0x90043, 0x149 },
> > + { 0x90044, 0x4f },
> > + { 0x90045, 0x630 },
> > + { 0x90046, 0x179 },
> > + { 0x90047, 0x8 },
> > + { 0x90048, 0xe0 },
> > + { 0x90049, 0x109 },
> > + { 0x9004a, 0x0 },
> > + { 0x9004b, 0x7c8 },
> > + { 0x9004c, 0x109 },
> > + { 0x9004d, 0x0 },
> > + { 0x9004e, 0x1 },
> > + { 0x9004f, 0x8 },
> > + { 0x90050, 0x0 },
> > + { 0x90051, 0x45a },
> > + { 0x90052, 0x9 },
> > + { 0x90053, 0x0 },
> > + { 0x90054, 0x448 },
> > + { 0x90055, 0x109 },
> > + { 0x90056, 0x40 },
> > + { 0x90057, 0x630 },
> > + { 0x90058, 0x179 },
> > + { 0x90059, 0x1 },
> > + { 0x9005a, 0x618 },
> > + { 0x9005b, 0x109 },
> > + { 0x9005c, 0x40c0 },
> > + { 0x9005d, 0x630 },
> > + { 0x9005e, 0x149 },
> > + { 0x9005f, 0x8 },
> > + { 0x90060, 0x4 },
> > + { 0x90061, 0x48 },
> > + { 0x90062, 0x4040 },
> > + { 0x90063, 0x630 },
> > + { 0x90064, 0x149 },
> > + { 0x90065, 0x0 },
> > + { 0x90066, 0x4 },
> > + { 0x90067, 0x48 },
> > + { 0x90068, 0x40 },
> > + { 0x90069, 0x630 },
> > + { 0x9006a, 0x149 },
> > + { 0x9006b, 0x10 },
> > + { 0x9006c, 0x4 },
> > + { 0x9006d, 0x18 },
> > + { 0x9006e, 0x0 },
> > + { 0x9006f, 0x4 },
> > + { 0x90070, 0x78 },
> > + { 0x90071, 0x549 },
> > + { 0x90072, 0x630 },
> > + { 0x90073, 0x159 },
> > + { 0x90074, 0xd49 },
> > + { 0x90075, 0x630 },
> > + { 0x90076, 0x159 },
> > + { 0x90077, 0x94a },
> > + { 0x90078, 0x630 },
> > + { 0x90079, 0x159 },
> > + { 0x9007a, 0x441 },
> > + { 0x9007b, 0x630 },
> > + { 0x9007c, 0x149 },
> > + { 0x9007d, 0x42 },
> > + { 0x9007e, 0x630 },
> > + { 0x9007f, 0x149 },
> > + { 0x90080, 0x1 },
> > + { 0x90081, 0x630 },
> > + { 0x90082, 0x149 },
> > + { 0x90083, 0x0 },
> > + { 0x90084, 0xe0 },
> > + { 0x90085, 0x109 },
> > + { 0x90086, 0xa },
> > + { 0x90087, 0x10 },
> > + { 0x90088, 0x109 },
> > + { 0x90089, 0x9 },
> > + { 0x9008a, 0x3c0 },
> > + { 0x9008b, 0x149 },
> > + { 0x9008c, 0x9 },
> > + { 0x9008d, 0x3c0 },
> > + { 0x9008e, 0x159 },
> > + { 0x9008f, 0x18 },
> > + { 0x90090, 0x10 },
> > + { 0x90091, 0x109 },
> > + { 0x90092, 0x0 },
> > + { 0x90093, 0x3c0 },
> > + { 0x90094, 0x109 },
> > + { 0x90095, 0x18 },
> > + { 0x90096, 0x4 },
> > + { 0x90097, 0x48 },
> > + { 0x90098, 0x18 },
> > + { 0x90099, 0x4 },
> > + { 0x9009a, 0x58 },
> > + { 0x9009b, 0xa },
> > + { 0x9009c, 0x10 },
> > + { 0x9009d, 0x109 },
> > + { 0x9009e, 0x2 },
> > + { 0x9009f, 0x10 },
> > + { 0x900a0, 0x109 },
> > + { 0x900a1, 0x5 },
> > + { 0x900a2, 0x7c0 },
> > + { 0x900a3, 0x109 },
> > + { 0x900a4, 0x10 },
> > + { 0x900a5, 0x10 },
> > + { 0x900a6, 0x109 },
> > + { 0x40000, 0x811 },
> > + { 0x40020, 0x880 },
> > + { 0x40040, 0x0 },
> > + { 0x40060, 0x0 },
> > + { 0x40001, 0x4008 },
> > + { 0x40021, 0x83 },
> > + { 0x40041, 0x4f },
> > + { 0x40061, 0x0 },
> > + { 0x40002, 0x4040 },
> > + { 0x40022, 0x83 },
> > + { 0x40042, 0x51 },
> > + { 0x40062, 0x0 },
> > + { 0x40003, 0x811 },
> > + { 0x40023, 0x880 },
> > + { 0x40043, 0x0 },
> > + { 0x40063, 0x0 },
> > + { 0x40004, 0x720 },
> > + { 0x40024, 0xf },
> > + { 0x40044, 0x1740 },
> > + { 0x40064, 0x0 },
> > + { 0x40005, 0x16 },
> > + { 0x40025, 0x83 },
> > + { 0x40045, 0x4b },
> > + { 0x40065, 0x0 },
> > + { 0x40006, 0x716 },
> > + { 0x40026, 0xf },
> > + { 0x40046, 0x2001 },
> > + { 0x40066, 0x0 },
> > + { 0x40007, 0x716 },
> > + { 0x40027, 0xf },
> > + { 0x40047, 0x2800 },
> > + { 0x40067, 0x0 },
> > + { 0x40008, 0x716 },
> > + { 0x40028, 0xf },
> > + { 0x40048, 0xf00 },
> > + { 0x40068, 0x0 },
> > + { 0x40009, 0x720 },
> > + { 0x40029, 0xf },
> > + { 0x40049, 0x1400 },
> > + { 0x40069, 0x0 },
> > + { 0x4000a, 0xe08 },
> > + { 0x4002a, 0xc15 },
> > + { 0x4004a, 0x0 },
> > + { 0x4006a, 0x0 },
> > + { 0x4000b, 0x623 },
> > + { 0x4002b, 0x15 },
> > + { 0x4004b, 0x0 },
> > + { 0x4006b, 0x0 },
> > + { 0x4000c, 0x4028 },
> > + { 0x4002c, 0x80 },
> > + { 0x4004c, 0x0 },
> > + { 0x4006c, 0x0 },
> > + { 0x4000d, 0xe08 },
> > + { 0x4002d, 0xc1a },
> > + { 0x4004d, 0x0 },
> > + { 0x4006d, 0x0 },
> > + { 0x4000e, 0x623 },
> > + { 0x4002e, 0x1a },
> > + { 0x4004e, 0x0 },
> > + { 0x4006e, 0x0 },
> > + { 0x4000f, 0x4040 },
> > + { 0x4002f, 0x80 },
> > + { 0x4004f, 0x0 },
> > + { 0x4006f, 0x0 },
> > + { 0x40010, 0x2604 },
> > + { 0x40030, 0x15 },
> > + { 0x40050, 0x0 },
> > + { 0x40070, 0x0 },
> > + { 0x40011, 0x708 },
> > + { 0x40031, 0x5 },
> > + { 0x40051, 0x0 },
> > + { 0x40071, 0x2002 },
> > + { 0x40012, 0x8 },
> > + { 0x40032, 0x80 },
> > + { 0x40052, 0x0 },
> > + { 0x40072, 0x0 },
> > + { 0x40013, 0x2604 },
> > + { 0x40033, 0x1a },
> > + { 0x40053, 0x0 },
> > + { 0x40073, 0x0 },
> > + { 0x40014, 0x708 },
> > + { 0x40034, 0xa },
> > + { 0x40054, 0x0 },
> > + { 0x40074, 0x2002 },
> > + { 0x40015, 0x4040 },
> > + { 0x40035, 0x80 },
> > + { 0x40055, 0x0 },
> > + { 0x40075, 0x0 },
> > + { 0x40016, 0x60a },
> > + { 0x40036, 0x15 },
> > + { 0x40056, 0x1200 },
> > + { 0x40076, 0x0 },
> > + { 0x40017, 0x61a },
> > + { 0x40037, 0x15 },
> > + { 0x40057, 0x1300 },
> > + { 0x40077, 0x0 },
> > + { 0x40018, 0x60a },
> > + { 0x40038, 0x1a },
> > + { 0x40058, 0x1200 },
> > + { 0x40078, 0x0 },
> > + { 0x40019, 0x642 },
> > + { 0x40039, 0x1a },
> > + { 0x40059, 0x1300 },
> > + { 0x40079, 0x0 },
> > + { 0x4001a, 0x4808 },
> > + { 0x4003a, 0x880 },
> > + { 0x4005a, 0x0 },
> > + { 0x4007a, 0x0 },
> > + { 0x900a7, 0x0 },
> > + { 0x900a8, 0x790 },
> > + { 0x900a9, 0x11a },
> > + { 0x900aa, 0x8 },
> > + { 0x900ab, 0x7aa },
> > + { 0x900ac, 0x2a },
> > + { 0x900ad, 0x10 },
> > + { 0x900ae, 0x7b2 },
> > + { 0x900af, 0x2a },
> > + { 0x900b0, 0x0 },
> > + { 0x900b1, 0x7c8 },
> > + { 0x900b2, 0x109 },
> > + { 0x900b3, 0x10 },
> > + { 0x900b4, 0x2a8 },
> > + { 0x900b5, 0x129 },
> > + { 0x900b6, 0x8 },
> > + { 0x900b7, 0x370 },
> > + { 0x900b8, 0x129 },
> > + { 0x900b9, 0xa },
> > + { 0x900ba, 0x3c8 },
> > + { 0x900bb, 0x1a9 },
> > + { 0x900bc, 0xc },
> > + { 0x900bd, 0x408 },
> > + { 0x900be, 0x199 },
> > + { 0x900bf, 0x14 },
> > + { 0x900c0, 0x790 },
> > + { 0x900c1, 0x11a },
> > + { 0x900c2, 0x8 },
> > + { 0x900c3, 0x4 },
> > + { 0x900c4, 0x18 },
> > + { 0x900c5, 0xe },
> > + { 0x900c6, 0x408 },
> > + { 0x900c7, 0x199 },
> > + { 0x900c8, 0x8 },
> > + { 0x900c9, 0x8568 },
> > + { 0x900ca, 0x108 },
> > + { 0x900cb, 0x18 },
> > + { 0x900cc, 0x790 },
> > + { 0x900cd, 0x16a },
> > + { 0x900ce, 0x8 },
> > + { 0x900cf, 0x1d8 },
> > + { 0x900d0, 0x169 },
> > + { 0x900d1, 0x10 },
> > + { 0x900d2, 0x8558 },
> > + { 0x900d3, 0x168 },
> > + { 0x900d4, 0x70 },
> > + { 0x900d5, 0x788 },
> > + { 0x900d6, 0x16a },
> > + { 0x900d7, 0x1ff8 },
> > + { 0x900d8, 0x85a8 },
> > + { 0x900d9, 0x1e8 },
> > + { 0x900da, 0x50 },
> > + { 0x900db, 0x798 },
> > + { 0x900dc, 0x16a },
> > + { 0x900dd, 0x60 },
> > + { 0x900de, 0x7a0 },
> > + { 0x900df, 0x16a },
> > + { 0x900e0, 0x8 },
> > + { 0x900e1, 0x8310 },
> > + { 0x900e2, 0x168 },
> > + { 0x900e3, 0x8 },
> > + { 0x900e4, 0xa310 },
> > + { 0x900e5, 0x168 },
> > + { 0x900e6, 0xa },
> > + { 0x900e7, 0x408 },
> > + { 0x900e8, 0x169 },
> > + { 0x900e9, 0x6e },
> > + { 0x900ea, 0x0 },
> > + { 0x900eb, 0x68 },
> > + { 0x900ec, 0x0 },
> > + { 0x900ed, 0x408 },
> > + { 0x900ee, 0x169 },
> > + { 0x900ef, 0x0 },
> > + { 0x900f0, 0x8310 },
> > + { 0x900f1, 0x168 },
> > + { 0x900f2, 0x0 },
> > + { 0x900f3, 0xa310 },
> > + { 0x900f4, 0x168 },
> > + { 0x900f5, 0x1ff8 },
> > + { 0x900f6, 0x85a8 },
> > + { 0x900f7, 0x1e8 },
> > + { 0x900f8, 0x68 },
> > + { 0x900f9, 0x798 },
> > + { 0x900fa, 0x16a },
> > + { 0x900fb, 0x78 },
> > + { 0x900fc, 0x7a0 },
> > + { 0x900fd, 0x16a },
> > + { 0x900fe, 0x68 },
> > + { 0x900ff, 0x790 },
> > + { 0x90100, 0x16a },
> > + { 0x90101, 0x8 },
> > + { 0x90102, 0x8b10 },
> > + { 0x90103, 0x168 },
> > + { 0x90104, 0x8 },
> > + { 0x90105, 0xab10 },
> > + { 0x90106, 0x168 },
> > + { 0x90107, 0xa },
> > + { 0x90108, 0x408 },
> > + { 0x90109, 0x169 },
> > + { 0x9010a, 0x58 },
> > + { 0x9010b, 0x0 },
> > + { 0x9010c, 0x68 },
> > + { 0x9010d, 0x0 },
> > + { 0x9010e, 0x408 },
> > + { 0x9010f, 0x169 },
> > + { 0x90110, 0x0 },
> > + { 0x90111, 0x8b10 },
> > + { 0x90112, 0x168 },
> > + { 0x90113, 0x0 },
> > + { 0x90114, 0xab10 },
> > + { 0x90115, 0x168 },
> > + { 0x90116, 0x0 },
> > + { 0x90117, 0x1d8 },
> > + { 0x90118, 0x169 },
> > + { 0x90119, 0x80 },
> > + { 0x9011a, 0x790 },
> > + { 0x9011b, 0x16a },
> > + { 0x9011c, 0x18 },
> > + { 0x9011d, 0x7aa },
> > + { 0x9011e, 0x6a },
> > + { 0x9011f, 0xa },
> > + { 0x90120, 0x0 },
> > + { 0x90121, 0x1e9 },
> > + { 0x90122, 0x8 },
> > + { 0x90123, 0x8080 },
> > + { 0x90124, 0x108 },
> > + { 0x90125, 0xf },
> > + { 0x90126, 0x408 },
> > + { 0x90127, 0x169 },
> > + { 0x90128, 0xc },
> > + { 0x90129, 0x0 },
> > + { 0x9012a, 0x68 },
> > + { 0x9012b, 0x9 },
> > + { 0x9012c, 0x0 },
> > + { 0x9012d, 0x1a9 },
> > + { 0x9012e, 0x0 },
> > + { 0x9012f, 0x408 },
> > + { 0x90130, 0x169 },
> > + { 0x90131, 0x0 },
> > + { 0x90132, 0x8080 },
> > + { 0x90133, 0x108 },
> > + { 0x90134, 0x8 },
> > + { 0x90135, 0x7aa },
> > + { 0x90136, 0x6a },
> > + { 0x90137, 0x0 },
> > + { 0x90138, 0x8568 },
> > + { 0x90139, 0x108 },
> > + { 0x9013a, 0xb7 },
> > + { 0x9013b, 0x790 },
> > + { 0x9013c, 0x16a },
> > + { 0x9013d, 0x1f },
> > + { 0x9013e, 0x0 },
> > + { 0x9013f, 0x68 },
> > + { 0x90140, 0x8 },
> > + { 0x90141, 0x8558 },
> > + { 0x90142, 0x168 },
> > + { 0x90143, 0xf },
> > + { 0x90144, 0x408 },
> > + { 0x90145, 0x169 },
> > + { 0x90146, 0xc },
> > + { 0x90147, 0x0 },
> > + { 0x90148, 0x68 },
> > + { 0x90149, 0x0 },
> > + { 0x9014a, 0x408 },
> > + { 0x9014b, 0x169 },
> > + { 0x9014c, 0x0 },
> > + { 0x9014d, 0x8558 },
> > + { 0x9014e, 0x168 },
> > + { 0x9014f, 0x8 },
> > + { 0x90150, 0x3c8 },
> > + { 0x90151, 0x1a9 },
> > + { 0x90152, 0x3 },
> > + { 0x90153, 0x370 },
> > + { 0x90154, 0x129 },
> > + { 0x90155, 0x20 },
> > + { 0x90156, 0x2aa },
> > + { 0x90157, 0x9 },
> > + { 0x90158, 0x0 },
> > + { 0x90159, 0x400 },
> > + { 0x9015a, 0x10e },
> > + { 0x9015b, 0x8 },
> > + { 0x9015c, 0xe8 },
> > + { 0x9015d, 0x109 },
> > + { 0x9015e, 0x0 },
> > + { 0x9015f, 0x8140 },
> > + { 0x90160, 0x10c },
> > + { 0x90161, 0x10 },
> > + { 0x90162, 0x8138 },
> > + { 0x90163, 0x10c },
> > + { 0x90164, 0x8 },
> > + { 0x90165, 0x7c8 },
> > + { 0x90166, 0x101 },
> > + { 0x90167, 0x8 },
> > + { 0x90168, 0x0 },
> > + { 0x90169, 0x8 },
> > + { 0x9016a, 0x8 },
> > + { 0x9016b, 0x448 },
> > + { 0x9016c, 0x109 },
> > + { 0x9016d, 0xf },
> > + { 0x9016e, 0x7c0 },
> > + { 0x9016f, 0x109 },
> > + { 0x90170, 0x0 },
> > + { 0x90171, 0xe8 },
> > + { 0x90172, 0x109 },
> > + { 0x90173, 0x47 },
> > + { 0x90174, 0x630 },
> > + { 0x90175, 0x109 },
> > + { 0x90176, 0x8 },
> > + { 0x90177, 0x618 },
> > + { 0x90178, 0x109 },
> > + { 0x90179, 0x8 },
> > + { 0x9017a, 0xe0 },
> > + { 0x9017b, 0x109 },
> > + { 0x9017c, 0x0 },
> > + { 0x9017d, 0x7c8 },
> > + { 0x9017e, 0x109 },
> > + { 0x9017f, 0x8 },
> > + { 0x90180, 0x8140 },
> > + { 0x90181, 0x10c },
> > + { 0x90182, 0x0 },
> > + { 0x90183, 0x1 },
> > + { 0x90184, 0x8 },
> > + { 0x90185, 0x8 },
> > + { 0x90186, 0x4 },
> > + { 0x90187, 0x8 },
> > + { 0x90188, 0x8 },
> > + { 0x90189, 0x7c8 },
> > + { 0x9018a, 0x101 },
> > + { 0x90006, 0x0 },
> > + { 0x90007, 0x0 },
> > + { 0x90008, 0x8 },
> > + { 0x90009, 0x0 },
> > + { 0x9000a, 0x0 },
> > + { 0x9000b, 0x0 },
> > + { 0xd00e7, 0x400 },
> > + { 0x90017, 0x0 },
> > + { 0x9001f, 0x2a },
> > + { 0x90026, 0x6a },
> > + { 0x400d0, 0x0 },
> > + { 0x400d1, 0x101 },
> > + { 0x400d2, 0x105 },
> > + { 0x400d3, 0x107 },
> > + { 0x400d4, 0x10f },
> > + { 0x400d5, 0x202 },
> > + { 0x400d6, 0x20a },
> > + { 0x400d7, 0x20b },
> > + { 0x2003a, 0x2 },
> > + { 0x2000b, 0x5d },
> > + { 0x2000c, 0xbb },
> > + { 0x2000d, 0x753 },
> > + { 0x2000e, 0x2c },
> > + { 0x12000b, 0xc },
> > + { 0x12000c, 0x19 },
> > + { 0x12000d, 0xfa },
> > + { 0x12000e, 0x10 },
> > + { 0x22000b, 0x3 },
> > + { 0x22000c, 0x6 },
> > + { 0x22000d, 0x3e },
> > + { 0x22000e, 0x10 },
> > + { 0x9000c, 0x0 },
> > + { 0x9000d, 0x173 },
> > + { 0x9000e, 0x60 },
> > + { 0x9000f, 0x6110 },
> > + { 0x90010, 0x2152 },
> > + { 0x90011, 0xdfbd },
> > + { 0x90012, 0x60 },
> > + { 0x90013, 0x6152 },
> > + { 0x20010, 0x5a },
> > + { 0x20011, 0x3 },
> > + { 0x40080, 0xe0 },
> > + { 0x40081, 0x12 },
> > + { 0x40082, 0xe0 },
> > + { 0x40083, 0x12 },
> > + { 0x40084, 0xe0 },
> > + { 0x40085, 0x12 },
> > + { 0x140080, 0xe0 },
> > + { 0x140081, 0x12 },
> > + { 0x140082, 0xe0 },
> > + { 0x140083, 0x12 },
> > + { 0x140084, 0xe0 },
> > + { 0x140085, 0x12 },
> > + { 0x240080, 0xe0 },
> > + { 0x240081, 0x12 },
> > + { 0x240082, 0xe0 },
> > + { 0x240083, 0x12 },
> > + { 0x240084, 0xe0 },
> > + { 0x240085, 0x12 },
> > + { 0x400fd, 0xf },
> > + { 0x10011, 0x1 },
> > + { 0x10012, 0x1 },
> > + { 0x10013, 0x180 },
> > + { 0x10018, 0x1 },
> > + { 0x10002, 0x6209 },
> > + { 0x100b2, 0x1 },
> > + { 0x101b4, 0x1 },
> > + { 0x102b4, 0x1 },
> > + { 0x103b4, 0x1 },
> > + { 0x104b4, 0x1 },
> > + { 0x105b4, 0x1 },
> > + { 0x106b4, 0x1 },
> > + { 0x107b4, 0x1 },
> > + { 0x108b4, 0x1 },
> > + { 0x11011, 0x1 },
> > + { 0x11012, 0x1 },
> > + { 0x11013, 0x180 },
> > + { 0x11018, 0x1 },
> > + { 0x11002, 0x6209 },
> > + { 0x110b2, 0x1 },
> > + { 0x111b4, 0x1 },
> > + { 0x112b4, 0x1 },
> > + { 0x113b4, 0x1 },
> > + { 0x114b4, 0x1 },
> > + { 0x115b4, 0x1 },
> > + { 0x116b4, 0x1 },
> > + { 0x117b4, 0x1 },
> > + { 0x118b4, 0x1 },
> > + { 0x12011, 0x1 },
> > + { 0x12012, 0x1 },
> > + { 0x12013, 0x180 },
> > + { 0x12018, 0x1 },
> > + { 0x12002, 0x6209 },
> > + { 0x120b2, 0x1 },
> > + { 0x121b4, 0x1 },
> > + { 0x122b4, 0x1 },
> > + { 0x123b4, 0x1 },
> > + { 0x124b4, 0x1 },
> > + { 0x125b4, 0x1 },
> > + { 0x126b4, 0x1 },
> > + { 0x127b4, 0x1 },
> > + { 0x128b4, 0x1 },
> > + { 0x13011, 0x1 },
> > + { 0x13012, 0x1 },
> > + { 0x13013, 0x180 },
> > + { 0x13018, 0x1 },
> > + { 0x13002, 0x6209 },
> > + { 0x130b2, 0x1 },
> > + { 0x131b4, 0x1 },
> > + { 0x132b4, 0x1 },
> > + { 0x133b4, 0x1 },
> > + { 0x134b4, 0x1 },
> > + { 0x135b4, 0x1 },
> > + { 0x136b4, 0x1 },
> > + { 0x137b4, 0x1 },
> > + { 0x138b4, 0x1 },
> > + { 0x2003a, 0x2 },
> > + { 0xc0080, 0x2 },
> > + { 0xd0000, 0x1 },
> > +};
>
> The same as above.
>
> > +
> > +struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
> > + {
> > + /* P0 3000mts 1D */
> > + .drate = 3000,
> > + .fw_type = FW_1D_IMAGE,
> > + .fsp_cfg = lpddr4_fsp0_cfg,
> > + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg),
> > + },
> > + {
> > + /* P0 3000mts 2D */
> > + .drate = 3000,
> > + .fw_type = FW_2D_IMAGE,
> > + .fsp_cfg = lpddr4_fsp0_2d_cfg,
> > + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg),
> > + },
> > + {
> > + /* P1 400mts 1D */
> > + .drate = 400,
> > + .fw_type = FW_1D_IMAGE,
> > + .fsp_cfg = lpddr4_fsp1_cfg,
> > + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg),
> > + },
> > + {
> > + /* P1 100mts 1D */
> > + .drate = 100,
> > + .fw_type = FW_1D_IMAGE,
> > + .fsp_cfg = lpddr4_fsp2_cfg,
> > + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg),
> > + },
> > +};
> > +
> > +/* lpddr4 timing config params on EVK board */
> > +struct dram_timing_info dram_timing = {
> > + .ddrc_cfg = lpddr4_ddrc_cfg,
> > + .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
> > + .ddrphy_cfg = lpddr4_ddrphy_cfg,
> > + .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg),
> > + .fsp_msg = lpddr4_dram_fsp_msg,
> > + .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg),
> > + .ddrphy_trained_csr = lpddr4_ddrphy_trained_csr,
> > + .ddrphy_trained_csr_num =
> > ARRAY_SIZE(lpddr4_ddrphy_trained_csr),
> > + .ddrphy_pie = lpddr4_phy_pie,
> > + .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
>
> It would be best to get the above values calculated dynamically for
> this SoC.
>
> > +};
> > diff --git a/board/freescale/imx8mm_evk/spl.c
> > b/board/freescale/imx8mm_evk/spl.c new file mode 100644
> > index 0000000000..cf1dfc2c2a
> > --- /dev/null
> > +++ b/board/freescale/imx8mm_evk/spl.c
> > @@ -0,0 +1,187 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright 2019 NXP
> > + */
> > +
> > +#include <common.h>
> > +#include <spl.h>
> > +#include <asm/io.h>
> > +#include <errno.h>
> > +#include <asm/io.h>
> > +#include <asm/mach-imx/iomux-v3.h>
> > +#include <asm/arch/imx8mm_pins.h>
> > +#include <asm/arch/sys_proto.h>
> > +#include <power/pmic.h>
> > +#include <asm/arch/clock.h>
> > +#include <asm/mach-imx/gpio.h>
> > +#include <asm/mach-imx/mxc_i2c.h>
> > +#include <fsl_esdhc.h>
> > +#include <mmc.h>
> > +#include <asm/arch/ddr.h>
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +void spl_dram_init(void)
> > +{
> > + ddr_init(&dram_timing);
> > +}
> > +
> > +#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 18)
> > +#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
> > +
> > +#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS |
> PAD_CTL_PUE | \
> > + PAD_CTL_PE | PAD_CTL_FSEL2)
> > +#define USDHC_GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE1)
> > +
> > +static iomux_v3_cfg_t const usdhc3_pads[] = {
> > + IMX8MM_PAD_NAND_WE_B_USDHC3_CLK |
> > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > + IMX8MM_PAD_NAND_WP_B_USDHC3_CMD |
> > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > + IMX8MM_PAD_NAND_DATA04_USDHC3_DATA0 |
> > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > + IMX8MM_PAD_NAND_DATA05_USDHC3_DATA1 |
> > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > + IMX8MM_PAD_NAND_DATA06_USDHC3_DATA2 |
> > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > + IMX8MM_PAD_NAND_DATA07_USDHC3_DATA3 |
> > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > + IMX8MM_PAD_NAND_RE_B_USDHC3_DATA4 |
> > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > + IMX8MM_PAD_NAND_CE2_B_USDHC3_DATA5 |
> > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > + IMX8MM_PAD_NAND_CE3_B_USDHC3_DATA6 |
> > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > + IMX8MM_PAD_NAND_CLE_USDHC3_DATA7 |
> > MUX_PAD_CTRL(USDHC_PAD_CTRL), +};
> > +
> > +static iomux_v3_cfg_t const usdhc2_pads[] = {
> > + IMX8MM_PAD_SD2_CLK_USDHC2_CLK |
> MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > + IMX8MM_PAD_SD2_CMD_USDHC2_CMD |
> MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > + IMX8MM_PAD_SD2_DATA0_USDHC2_DATA0 |
> > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > + IMX8MM_PAD_SD2_DATA1_USDHC2_DATA1 |
> > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > + IMX8MM_PAD_SD2_DATA2_USDHC2_DATA2 |
> > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > + IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 |
> > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > + IMX8MM_PAD_SD2_RESET_B_GPIO2_IO19 |
> > MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), +};
> > +
> > +/*
> > + * The evk board uses DAT3 to detect CD card plugin,
> > + * in u-boot we mux the pin to GPIO when doing board_mmc_getcd.
> > + */
> > +static iomux_v3_cfg_t const usdhc2_cd_pad =
> > + IMX8MM_PAD_SD2_DATA3_GPIO2_IO18 |
> > MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL); +
> > +static iomux_v3_cfg_t const usdhc2_dat3_pad =
> > + IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 |
> > + MUX_PAD_CTRL(USDHC_PAD_CTRL);
> > +
> > +static struct fsl_esdhc_cfg usdhc_cfg[2] = {
> > + {USDHC2_BASE_ADDR, 0, 1},
> > + {USDHC3_BASE_ADDR, 0, 1},
> > +};
> > +
> > +int board_mmc_init(bd_t *bis)
> > +{
> > + int i, ret;
> > + /*
> > + * According to the board_mmc_init() the following map is
> > done:
> > + * (U-Boot device node) (Physical Port)
> > + * mmc0 USDHC1
> > + * mmc1 USDHC2
> > + */
> > + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
> > + switch (i) {
> > + case 0:
> > + usdhc_cfg[0].sdhc_clk =
> > mxc_get_clock(MXC_ESDHC2_CLK);
> > + imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
> > +
> > ARRAY_SIZE(usdhc2_pads));
> > + gpio_request(USDHC2_PWR_GPIO,
> > "usdhc2_reset");
> > + gpio_direction_output(USDHC2_PWR_GPIO, 0);
> > + udelay(500);
> > + gpio_direction_output(USDHC2_PWR_GPIO, 1);
> > + break;
> > + case 1:
> > + usdhc_cfg[1].sdhc_clk =
> > mxc_get_clock(MXC_ESDHC3_CLK);
> > + imx_iomux_v3_setup_multiple_pads(usdhc3_pads,
> > +
> > ARRAY_SIZE(usdhc3_pads));
> > + break;
>
> It would be best if you could enable DM/DTS in SPL too from the outset
> (and share the SPL size).
>
> Do you have any timeline for converting SPL to DM/DTS?
>
> > + default:
> > + printf("USDHC controllers %d not supported
> > \n", i + 1);
> > + return -EINVAL;
> > + }
> > +
> > + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +int board_mmc_getcd(struct mmc *mmc)
> > +{
> > + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg
> > *)mmc->priv;
> > + int ret = 0;
> > +
> > + switch (cfg->esdhc_base) {
> > + case USDHC3_BASE_ADDR:
> > + ret = 1;
> > + break;
> > + case USDHC2_BASE_ADDR:
> > + imx_iomux_v3_setup_pad(usdhc2_cd_pad);
> > + gpio_request(USDHC2_CD_GPIO, "usdhc2 cd");
> > + gpio_direction_input(USDHC2_CD_GPIO);
> > +
> > + /*
> > + * Since it is the DAT3 pin, this pin is pulled to
> > + * low voltage if no card
> > + */
> > + ret = gpio_get_value(USDHC2_CD_GPIO);
> > +
> > + imx_iomux_v3_setup_pad(usdhc2_dat3_pad);
> > + return ret;
> > + }
> > +
> > + return 1;
> > +}
> > +
> > +void spl_board_init(void)
> > +{
> > + puts("Normal Boot\n");
> > +}
> > +
> > +#ifdef CONFIG_SPL_LOAD_FIT
> > +int board_fit_config_name_match(const char *name)
> > +{
> > + /* Just empty function now - can't decide what to choose */
> > + debug("%s: %s\n", __func__, name);
> > +
> > + return 0;
> > +}
> > +#endif
> > +
> > +void board_init_f(ulong dummy)
> > +{
> > + int ret;
> > +
> > + /* Clear global data */
> > + memset((void *)gd, 0, sizeof(gd_t));
> > +
> > + arch_cpu_init();
> > +
> > + init_uart_clk(1);
> > +
> > + board_early_init_f();
> > +
> > + timer_init();
> > +
> > + preloader_console_init();
> > +
> > + /* Clear the BSS. */
> > + memset(__bss_start, 0, __bss_end - __bss_start);
> > +
> > + ret = spl_init();
> > + if (ret) {
> > + debug("spl_init() failed: %d\n", ret);
> > + hang();
> > + }
> > +
> > + enable_tzc380();
> > +
> > + /* DDR initialization */
> > + spl_dram_init();
> > +
> > + board_init_r(NULL, 0);
> > +}
> > diff --git a/configs/imx8mm_evk_defconfig
> > b/configs/imx8mm_evk_defconfig new file mode 100644
> > index 0000000000..6110f23e38
> > --- /dev/null
> > +++ b/configs/imx8mm_evk_defconfig
> > @@ -0,0 +1,41 @@
> > +CONFIG_ARM=y
> > +CONFIG_ARCH_IMX8M=y
> > +CONFIG_SYS_TEXT_BASE=0x40200000
> > +CONFIG_SPL_GPIO_SUPPORT=y
> > +CONFIG_SYS_MALLOC_F_LEN=0x2000
> > +CONFIG_TARGET_IMX8MM_EVK=y
> > +CONFIG_SPL_MMC_SUPPORT=y
> > +CONFIG_SPL_SERIAL_SUPPORT=y
> > +CONFIG_SPL=y
> > +CONFIG_FIT=y
> > +CONFIG_FIT_EXTERNAL_OFFSET=0x3000
> > +CONFIG_SPL_LOAD_FIT=y
> > +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
> >
> +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m
> /imximage.cfg,SPL_TEXT_BASE=0x7E1000"
> > +CONFIG_DEFAULT_FDT_FILE="fsl-imx8mm-evk.dtb"
> > +CONFIG_SPL_BOARD_INIT=y
> > +CONFIG_SPL_I2C_SUPPORT=y
> > +CONFIG_HUSH_PARSER=y
> > +CONFIG_CMD_GPIO=y
> > +CONFIG_CMD_I2C=y
> > +CONFIG_CMD_CACHE=y
> > +CONFIG_CMD_REGULATOR=y
> > +CONFIG_CMD_EXT2=y
> > +CONFIG_CMD_EXT4=y
> > +CONFIG_CMD_EXT4_WRITE=y
> > +CONFIG_CMD_FAT=y
> > +CONFIG_OF_CONTROL=y
> > +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mm-evk"
> > +CONFIG_DM_GPIO=y
> > +CONFIG_MXC_GPIO=y
> > +CONFIG_DM_I2C=y
> > +CONFIG_SYS_I2C_MXC=y
> > +CONFIG_DM_MMC=y
> > +CONFIG_DM_ETH=y
>
> Here you enable the DM_ETH, but the welcome u-boot info says:
>
> "Net: No ethernet found."
>
> > +CONFIG_PINCTRL=y
> > +CONFIG_PINCTRL_IMX8M=y
> > +CONFIG_DM_REGULATOR=y
> > +CONFIG_DM_REGULATOR_FIXED=y
> > +CONFIG_DM_REGULATOR_GPIO=y
> > +CONFIG_MXC_UART=y
> > +CONFIG_DM_THERMAL=y
> > diff --git a/include/configs/imx8mm_evk.h
> > b/include/configs/imx8mm_evk.h new file mode 100644
> > index 0000000000..f944308757
> > --- /dev/null
> > +++ b/include/configs/imx8mm_evk.h
> > @@ -0,0 +1,221 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * Copyright 2018 NXP
> > + */
> > +
> > +#ifndef __IMX8MM_EVK_H
> > +#define __IMX8MM_EVK_H
> > +
> > +#include <linux/sizes.h>
> > +#include <asm/arch/imx-regs.h>
> > +
> > +#ifdef CONFIG_SECURE_BOOT
> > +#define CONFIG_CSF_SIZE 0x2000 /* 8K region */
> > +#endif
> > +
> > +#define CONFIG_SPL_MAX_SIZE (148 * 1024)
> > +#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
> > +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
> > +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
> > +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
> > +#define CONFIG_SYS_UBOOT_BASE \
> > + (QSPI0_AMBA_BASE +
> CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR *
> > 512) +
> > +#ifdef CONFIG_SPL_BUILD
> > +/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
> > +#define CONFIG_SPL_WATCHDOG_SUPPORT
> > +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
> > +#define CONFIG_SPL_POWER_SUPPORT
> > +#define
> > CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
> > +#define CONFIG_SPL_STACK 0x91fff0 +#define
> > CONFIG_SPL_LIBCOMMON_SUPPORT +#define
> CONFIG_SPL_LIBGENERIC_SUPPORT
> > +#define CONFIG_SPL_BSS_START_ADDR 0x00910000
> > +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
> > +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
> > +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */
> > +#define CONFIG_SYS_ICACHE_OFF
> > +#define CONFIG_SYS_DCACHE_OFF
> > +
> > +#define CONFIG_MALLOC_F_ADDR 0x912000 /* malloc f
> > used before GD_FLG_FULL_MALLOC_INIT set */ +
> > +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a
> error
> > info not panic */ +
> > +#undef CONFIG_DM_MMC
> > +#undef CONFIG_DM_PMIC
> > +#undef CONFIG_DM_PMIC_PFUZE100
>
> Why do you need to undef those config options?
>
> > +
> > +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> > +
> > +#endif
> > +
> > +#define CONFIG_REMAKE_ELF
> > +
> > +#define CONFIG_BOARD_EARLY_INIT_F
> > +#define CONFIG_BOARD_POSTCLK_INIT
> > +#define CONFIG_BOARD_LATE_INIT
> > +
> > +/* Flat Device Tree Definitions */
> > +#define CONFIG_OF_BOARD_SETUP
> > +
> > +#undef CONFIG_CMD_EXPORTENV
> > +#undef CONFIG_CMD_IMPORTENV
> > +#undef CONFIG_CMD_IMLS
> > +
> > +#undef CONFIG_CMD_CRC32
> > +#undef CONFIG_BOOTM_NETBSD
>
> There seems to be some issue with inheritance, as you need to undef
> those values manually.
>
> Why is it needed?
>
> > +
> > +/* ENET Config */
> > +/* ENET1 */
> > +#if defined(CONFIG_CMD_NET)
> > +#define CONFIG_CMD_PING
> > +#define CONFIG_CMD_DHCP
> > +#define CONFIG_CMD_MII
> > +#define CONFIG_MII
> > +#define CONFIG_ETHPRIME "FEC"
> > +
> > +#define CONFIG_FEC_MXC
> > +#define CONFIG_FEC_XCV_TYPE RGMII
> > +#define CONFIG_FEC_MXC_PHYADDR 0
> > +#define FEC_QUIRK_ENET_MAC
> > +
> > +#define CONFIG_PHY_GIGE
> > +#define IMX_FEC_BASE 0x30BE0000
> > +
> > +#define CONFIG_PHYLIB
> > +#define CONFIG_PHY_ATHEROS
> > +#endif
> > +
> > +/* Initial environment variables */
> > +#define CONFIG_EXTRA_ENV_SETTINGS \
> > + "script=boot.scr\0" \
> > + "image=Image\0" \
> > + "console=ttymxc1,115200
> > earlycon=ec_imx6q,0x30890000,115200\0" \
> > + "fdt_addr=0x43000000\0" \
> > + "fdt_high=0xffffffffffffffff\0" \
> > + "boot_fdt=try\0" \
> > + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
> > + "initrd_addr=0x43800000\0" \
> > + "initrd_high=0xffffffffffffffff\0" \
> > + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
> > + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
> > + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
> > + "mmcautodetect=yes\0" \
> > + "mmcargs=setenv bootargs ${jh_clk} console=${console}
> > root=${mmcroot}\0 " \
> > + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}
> > ${script};\0" \
> > + "bootscript=echo Running bootscript from mmc ...; " \
> > + "source\0" \
> > + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}
> > ${image}\0" \
> > + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr}
> > ${fdt_file}\0" \
> > + "mmcboot=echo Booting from mmc ...; " \
> > + "run mmcargs; " \
> > + "if test ${boot_fdt} = yes || test ${boot_fdt} =
> > try; then " \
> > + "if run loadfdt; then " \
> > + "booti ${loadaddr} - ${fdt_addr}; " \
> > + "else " \
> > + "echo WARN: Cannot load the DT; " \
> > + "fi; " \
> > + "else " \
> > + "echo wait for boot; " \
> > + "fi;\0" \
> > + "netargs=setenv bootargs ${jh_clk} console=${console} " \
> > + "root=/dev/nfs " \
> > + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
> > + "netboot=echo Booting from net ...; " \
> > + "run netargs; " \
> > + "if test ${ip_dyn} = yes; then " \
> > + "setenv get_cmd dhcp; " \
> > + "else " \
> > + "setenv get_cmd tftp; " \
> > + "fi; " \
> > + "${get_cmd} ${loadaddr} ${image}; " \
> > + "if test ${boot_fdt} = yes || test ${boot_fdt} =
> > try; then " \
> > + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then
> > " \
> > + "booti ${loadaddr} - ${fdt_addr}; " \
> > + "else " \
> > + "echo WARN: Cannot load the DT; " \
> > + "fi; " \
> > + "else " \
> > + "booti; " \
> > + "fi;\0"
> > +
> > +#define CONFIG_BOOTCOMMAND \
> > + "mmc dev ${mmcdev}; if mmc rescan; then " \
> > + "if run loadbootscript; then " \
> > + "run bootscript; " \
> > + "else " \
> > + "if run loadimage; then " \
> > + "run mmcboot; " \
> > + "else run netboot; " \
> > + "fi; " \
> > + "fi; " \
> > + "else booti ${loadaddr} - ${fdt_addr}; fi"
> > +
> > +/* Link Definitions */
> > +#define CONFIG_LOADADDR 0x40480000
> > +
> > +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
> > +
> > +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
> > +#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
> > +#define CONFIG_SYS_INIT_SP_OFFSET \
> > + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> > +#define CONFIG_SYS_INIT_SP_ADDR \
> > + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
> > +
> > +#define CONFIG_ENV_OVERWRITE
> > +#if defined(CONFIG_ENV_IS_IN_MMC)
> > +#define CONFIG_ENV_OFFSET (64 * SZ_64K)
> > +#endif
> > +#define CONFIG_ENV_SIZE 0x1000
> > +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC2 */
> > +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /*
> > USDHC2 */ +
> > +/* Size of malloc() pool */
> > +#define CONFIG_SYS_MALLOC_LEN SZ_32M
> > +
> > +#define CONFIG_SYS_SDRAM_BASE 0x40000000
> > +#define PHYS_SDRAM 0x40000000
> > +#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR
> > */ +
> > +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
> > +#define CONFIG_SYS_MEMTEST_END
> (CONFIG_SYS_MEMTEST_START +
> > (PHYS_SDRAM_SIZE >> 1)) +
> > +#define CONFIG_BAUDRATE 115200
> > +
> > +#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
> > +
> > +/* Monitor Command Prompt */
> > +#undef CONFIG_SYS_PROMPT
> > +#define CONFIG_SYS_PROMPT "u-boot=> "
> > +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
> > +#define CONFIG_SYS_CBSIZE 2048
> > +#define CONFIG_SYS_MAXARGS 64
> > +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
> > +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
> > + sizeof(CONFIG_SYS_PROMPT) +
> > 16) +
> > +#define CONFIG_IMX_BOOTAUX
> > +
> > +/* USDHC */
> > +#define CONFIG_CMD_MMC
> > +#define CONFIG_FSL_ESDHC
> > +#define CONFIG_FSL_USDHC
> > +
> > +#define CONFIG_SYS_FSL_USDHC_NUM 2
> > +#define CONFIG_SYS_FSL_ESDHC_ADDR 0
> > +
> > +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
> > +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
> > +
> > +#define CONFIG_MXC_OCOTP
> > +#define CONFIG_CMD_FUSE
> > +
> > +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
> > +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
> > +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
> > +#define CONFIG_SYS_I2C_SPEED 100000
>
> Some of those values are (SYS_I2C_*, MXC_OCOTP, FSL_*) are already
> supported by Kconfig. Please use Kconfig instead.
>
> > +
> > +#define CONFIG_OF_SYSTEM_SETUP
> > +
> > +#endif
>
>
> Best regards,
>
> Lukasz Majewski
>
> --
>
> DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> lukma at denx.de
^ permalink raw reply [flat|nested] 39+ messages in thread* [U-Boot] [PATCH 20/20] imx: add i.MX8MM EVK board support
2019-01-30 5:49 ` Peng Fan
@ 2019-01-30 6:53 ` Lukasz Majewski
2019-01-30 7:07 ` Peng Fan
0 siblings, 1 reply; 39+ messages in thread
From: Lukasz Majewski @ 2019-01-30 6:53 UTC (permalink / raw)
To: u-boot
Hi Peng,
> > -----Original Message-----
> > From: Lukasz Majewski [mailto:lukma at denx.de]
> > Sent: 2019年1月30日 7:19
> > To: Peng Fan <peng.fan@nxp.com>
> > Cc: sbabic at denx.de; Fabio Estevam <fabio.estevam@nxp.com>;
> > dl-uboot-imx <uboot-imx@nxp.com>; u-boot at lists.denx.de
> > Subject: Re: [U-Boot] [PATCH 20/20] imx: add i.MX8MM EVK board
> > support
> >
> > Hi Peng,
> >
> > > Add i.MX8MM EVK board support.
> > >
> > > Add board and SoC dts
> > > Add ddr training code
> > > support SD/MMC/GPIO/PINCTRL/UART
> > >
> > > U-Boot SPL 2019.01-00148-g1179cffe66 (Jan 28 2019 - 17:37:34
> > > +0800) Normal Boot
> > > Trying to boot from MMC1
> > >
> > > U-Boot 2019.01-00148-g1179cffe66 (Jan 28 2019 - 17:37:34 +0800)
> > >
> > > CPU: Freescale i.MX8MMQ rev1.0 at 1200 MHz
> > > Reset cause: POR
> > > Model: NXP i.MX8MM EVK board
> > > DRAM: 2 GiB
> > > MMC: FSL_SDHC: 1, FSL_SDHC: 2
> > > In: serial
> > > Out: serial
> > > Err: serial
> > > DM
> >
> > You set/adjust latter in the code the fec network driver. Why it is
> > not found?
>
> I dropped network support, could add it in V2.
From the patch it seems like the ETH is fully supported, at lease from
the source code point of view.
>
> >
> > Could you also share the output of "dm tree" command?
>
> Sure.
>
> >
> > I suppose/guess that this board shall support as much as possible of
> > the DT/DM conversions?
>
> Ok.
And I would like to emphasize the need of DDR training code (as a
functions, not pair of offset and value).
Are you able to provide such code in the next version of the patch?
>
> Regards,
> Peng.
>
> >
> > > Hit any key to stop autoboot: 2
> > >
> > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > ---
> > > arch/arm/dts/fsl-imx8mm-evk.dts | 203 +++
> > > arch/arm/dts/fsl-imx8mm.dtsi | 586 ++++++++
> > > arch/arm/mach-imx/imx8m/Kconfig | 7 +
> > > board/freescale/imx8mm_evk/Kconfig | 12 +
> > > board/freescale/imx8mm_evk/MAINTAINERS | 6 +
> > > board/freescale/imx8mm_evk/Makefile | 12 +
> > > board/freescale/imx8mm_evk/imx8mm_evk.c | 144 ++
> > > board/freescale/imx8mm_evk/lpddr4_timing.c | 1980
> > > ++++++++++++++++++++++++++++
> > > board/freescale/imx8mm_evk/spl.c | 187 +++
> > > configs/imx8mm_evk_defconfig | 41 +
> > > include/configs/imx8mm_evk.h | 221 ++++ 11 files
> > > changed, 3399 insertions(+) create mode 100644
> > > arch/arm/dts/fsl-imx8mm-evk.dts create mode 100644
> > > arch/arm/dts/fsl-imx8mm.dtsi create mode 100644
> > > board/freescale/imx8mm_evk/Kconfig create mode 100644
> > > board/freescale/imx8mm_evk/MAINTAINERS create mode 100644
> > > board/freescale/imx8mm_evk/Makefile create mode 100644
> > > board/freescale/imx8mm_evk/imx8mm_evk.c create mode 100644
> > > board/freescale/imx8mm_evk/lpddr4_timing.c create mode 100644
> > > board/freescale/imx8mm_evk/spl.c create mode 100644
> > > configs/imx8mm_evk_defconfig create mode 100644
> > > include/configs/imx8mm_evk.h
> > >
> > > diff --git a/arch/arm/dts/fsl-imx8mm-evk.dts
> > > b/arch/arm/dts/fsl-imx8mm-evk.dts new file mode 100644
> > > index 0000000000..df409eca47
> > > --- /dev/null
> > > +++ b/arch/arm/dts/fsl-imx8mm-evk.dts
> > > @@ -0,0 +1,203 @@
> > > +// SPDX-License-Identifier: GPL-2.0+
> > > +/*
> > > + * Copyright 2019 NXP
> > > + */
> > > +
> > > +/dts-v1/;
> > > +
> > > +#include "fsl-imx8mm.dtsi"
> > > +
> > > +/ {
> > > + model = "NXP i.MX8MM EVK board";
> > > + compatible = "fsl,imx8mm-evk", "fsl,imx8mm";
> > > +
> > > + chosen {
> > > + stdout-path = &uart2;
> > > + };
> > > +
> > > + regulators {
> > > + compatible = "simple-bus";
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > +
> > > + reg_usdhc2_vmmc: regulator-usdhc2 {
> > > + compatible = "regulator-fixed";
> > > + regulator-name = "VSD_3V3";
> > > + regulator-min-microvolt = <3300000>;
> > > + regulator-max-microvolt = <3300000>;
> > > + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
> > > + off-on-delay = <20000>;
> > > + enable-active-high;
> > > + };
> > > + };
> > > +};
> > > +
> > > +&iomuxc {
> > > + pinctrl-names = "default";
> > > +
> > > + imx8mm-evk {
> > > + pinctrl_fec1: fec1grp {
> > > + fsl,pins = <
> > > +
> > > MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
> > > +
> > > MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
> > > +
> > > MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
> > > +
> > > MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
> > > +
> > > MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
> > > +
> > > MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
> > > +
> > > MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
> > > +
> > > MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
> > > +
> > > MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
> > > +
> > > MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
> > > +
> > > MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
> > > +
> > > MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
> > > +
> > > MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
> > > +
> > > MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
> > > +
> > > MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
> > > + >;
> > > + };
> > > +
> > > + pinctrl_gpio_led: gpioledgrp {
> > > + fsl,pins = <
> > > +
> > > MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
> > > + >;
> > > + };
> > > +
> > > + pinctrl_uart2: uart2grp {
> > > + fsl,pins = <
> > > +
> > > MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
> > > +
> > > MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
> > > + >;
> > > + };
> > > +
> > > + pinctrl_usdhc2_gpio: usdhc2grpgpio {
> > > + fsl,pins = <
> > > +
> > > MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
> > > +
> > > MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
> > > + >;
> > > + };
> > > +
> > > + pinctrl_usdhc2: usdhc2grp {
> > > + fsl,pins = <
> > > +
> > > MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
> > > +
> > > MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
> > > +
> > > MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
> > > +
> > > MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
> > > +
> > > MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
> > > +
> > > MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
> > > +
> > > MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
> > > + >;
> > > + };
> > > +
> > > + pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
> > > + fsl,pins = <
> > > +
> > > MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
> > > +
> > > MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
> > > +
> > > MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
> > > +
> > > MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
> > > +
> > > MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
> > > +
> > > MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
> > > +
> > > MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
> > > + >;
> > > + };
> > > +
> > > + pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
> > > + fsl,pins = <
> > > +
> > > MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
> > > +
> > > MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
> > > +
> > > MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
> > > +
> > > MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
> > > +
> > > MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
> > > +
> > > MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
> > > +
> > > MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
> > > + >;
> > > + };
> > > +
> > > + pinctrl_usdhc3: usdhc3grp {
> > > + fsl,pins = <
> > > +
> > > MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
> > > +
> > > MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
> > > +
> > > MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
> > > +
> > > MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
> > > +
> > > MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
> > > +
> > > MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
> > > +
> > > MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
> > > +
> > > MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
> > > +
> > > MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
> > > +
> > > MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
> > > +
> > > MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
> > > + >;
> > > + };
> > > +
> > > + pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
> > > + fsl,pins = <
> > > +
> > > MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
> > > +
> > > MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
> > > +
> > > MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
> > > +
> > > MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
> > > +
> > > MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
> > > +
> > > MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
> > > +
> > > MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
> > > +
> > > MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
> > > +
> > > MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
> > > +
> > > MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
> > > +
> > > MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
> > > + >;
> > > + };
> > > +
> > > + pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
> > > + fsl,pins = <
> > > +
> > > MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
> > > +
> > > MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
> > > +
> > > MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
> > > +
> > > MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
> > > +
> > > MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
> > > +
> > > MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
> > > +
> > > MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
> > > +
> > > MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
> > > +
> > > MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
> > > +
> > > MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
> > > +
> > > MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
> > > + >;
> > > + };
> > > +
> > > + pinctrl_wdog: wdoggrp {
> > > + fsl,pins = <
> > > +
> > > MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
> > > + >;
> > > + };
> > > + };
> > > +};
> > > +
> > > +&uart2 { /* console */
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&pinctrl_uart2>;
> > > + status = "okay";
> > > +};
> > > +
> > > +&usdhc2 {
> > > + pinctrl-names = "default", "state_100mhz",
> > > "state_200mhz";
> > > + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
> > > + pinctrl-1 = <&pinctrl_usdhc2_100mhz>,
> > > <&pinctrl_usdhc2_gpio>;
> > > + pinctrl-2 = <&pinctrl_usdhc2_200mhz>,
> > > <&pinctrl_usdhc2_gpio>;
> > > + cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
> > > + bus-width = <4>;
> > > + vmmc-supply = <®_usdhc2_vmmc>;
> > > + status = "okay";
> > > +};
> > > +
> > > +&usdhc3 {
> > > + pinctrl-names = "default", "state_100mhz",
> > > "state_200mhz";
> > > + pinctrl-0 = <&pinctrl_usdhc3>;
> > > + pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
> > > + pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
> > > + bus-width = <8>;
> > > + non-removable;
> > > + status = "okay";
> > > +};
> > > +
> > > +&wdog1 {
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&pinctrl_wdog>;
> > > + fsl,ext-reset-output;
> > > + status = "okay";
> > > +};
> > > diff --git a/arch/arm/dts/fsl-imx8mm.dtsi
> > > b/arch/arm/dts/fsl-imx8mm.dtsi new file mode 100644
> > > index 0000000000..8a808f856d
> > > --- /dev/null
> > > +++ b/arch/arm/dts/fsl-imx8mm.dtsi
> > > @@ -0,0 +1,586 @@
> > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > > +/*
> > > + * Copyright 2017-2019 NXP
> > > + */
> > > +
> > > +#include <dt-bindings/clock/imx8mm-clock.h>
> > > +#include <dt-bindings/gpio/gpio.h>
> > > +#include <dt-bindings/input/input.h>
> > > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > > +#include <dt-bindings/pinctrl/pins-imx8mm.h>
> > > +#include <dt-bindings/thermal/thermal.h>
> > > +
> > > +/ {
> > > + compatible = "fsl,imx8mm";
> > > + interrupt-parent = <&gic>;
> > > + #address-cells = <2>;
> > > + #size-cells = <2>;
> > > +
> > > + aliases {
> > > + i2c0 = &i2c1;
> > > + i2c1 = &i2c2;
> > > + i2c2 = &i2c3;
> > > + i2c3 = &i2c4;
> > > + serial0 = &uart1;
> > > + serial1 = &uart2;
> > > + serial2 = &uart3;
> > > + serial3 = &uart4;
> > > + spi0 = &ecspi1;
> > > + spi1 = &ecspi2;
> > > + spi2 = &ecspi3;
> > > + mmc0 = &usdhc1;
> > > + mmc1 = &usdhc2;
> > > + mmc2 = &usdhc3;
> > > + gpio0 = &gpio1;
> > > + gpio1 = &gpio2;
> > > + gpio2 = &gpio3;
> > > + gpio3 = &gpio4;
> > > + gpio4 = &gpio5;
> > > + };
> > > +
> > > + cpus {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > +
> > > + A53_0: cpu at 0 {
> > > + device_type = "cpu";
> > > + compatible = "arm,cortex-a53";
> > > + reg = <0x0>;
> > > + enable-method = "psci";
> > > + next-level-cache = <&A53_L2>;
> > > + };
> > > +
> > > + A53_1: cpu at 1 {
> > > + device_type = "cpu";
> > > + compatible = "arm,cortex-a53";
> > > + reg = <0x1>;
> > > + enable-method = "psci";
> > > + next-level-cache = <&A53_L2>;
> > > + };
> > > +
> > > + A53_2: cpu at 2 {
> > > + device_type = "cpu";
> > > + compatible = "arm,cortex-a53";
> > > + reg = <0x2>;
> > > + enable-method = "psci";
> > > + next-level-cache = <&A53_L2>;
> > > + };
> > > +
> > > + A53_3: cpu at 3 {
> > > + device_type = "cpu";
> > > + compatible = "arm,cortex-a53";
> > > + reg = <0x3>;
> > > + enable-method = "psci";
> > > + next-level-cache = <&A53_L2>;
> > > + };
> > > +
> > > + A53_L2: l2-cache0 {
> > > + compatible = "cache";
> > > + };
> > > + };
> > > +
> > > + memory at 40000000 {
> > > + device_type = "memory";
> > > + reg = <0x0 0x40000000 0 0x80000000>;
> > > + };
> > > +
> > > + clocks {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > +
> > > + osc_32k: clock at 0 {
> > > + compatible = "fixed-clock";
> > > + reg = <0>;
> > > + #clock-cells = <0>;
> > > + clock-frequency = <32768>;
> > > + clock-output-names = "osc_32k";
> > > + };
> > > +
> > > + osc_24m: clock at 1 {
> > > + compatible = "fixed-clock";
> > > + reg = <1>;
> > > + #clock-cells = <0>;
> > > + clock-frequency = <24000000>;
> > > + clock-output-names = "osc_24m";
> > > + };
> > > +
> > > + clk_ext1: clock at 2 {
> > > + compatible = "fixed-clock";
> > > + reg = <3>;
> > > + #clock-cells = <0>;
> > > + clock-frequency = <133000000>;
> > > + clock-output-names = "clk_ext1";
> > > + };
> > > +
> > > + clk_ext2: clock at 3 {
> > > + compatible = "fixed-clock";
> > > + reg = <4>;
> > > + #clock-cells = <0>;
> > > + clock-frequency = <133000000>;
> > > + clock-output-names = "clk_ext2";
> > > + };
> > > +
> > > + clk_ext3: clock at 4 {
> > > + compatible = "fixed-clock";
> > > + reg = <5>;
> > > + #clock-cells = <0>;
> > > + clock-frequency = <133000000>;
> > > + clock-output-names = "clk_ext3";
> > > + };
> > > +
> > > + clk_ext4: clock at 5 {
> > > + compatible = "fixed-clock";
> > > + reg = <6>;
> > > + #clock-cells = <0>;
> > > + clock-frequency= <133000000>;
> > > + clock-output-names = "clk_ext4";
> > > + };
> > > + };
> > > +
> > > + gic: interrupt-controller at 38800000 {
> > > + compatible = "arm,gic-v3";
> > > + reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */
> > > + <0x0 0x38880000 0 0xC0000>; /* GICR
> > > (RD_base + SGI_base) */
> > > + #interrupt-cells = <3>;
> > > + interrupt-controller;
> > > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> > > + };
> > > +
> > > + psci {
> > > + compatible = "arm,psci-1.0";
> > > + method = "smc";
> > > + };
> > > +
> > > + pmu {
> > > + compatible = "arm,armv8-pmuv3";
> > > + interrupts = <GIC_PPI 7
> > > + (GIC_CPU_MASK_SIMPLE(6) |
> > > IRQ_TYPE_LEVEL_HIGH)>;
> > > + interrupt-affinity = <&A53_0>, <&A53_1>,
> > > <&A53_2>, <&A53_3>;
> > > + };
> > > +
> > > + timer {
> > > + compatible = "arm,armv8-timer";
> > > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6)
> > > | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
> > > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6)
> > > | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
> > > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6)
> > > | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
> > > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6)
> > > | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
> > > + clock-frequency = <8000000>;
> > > + arm,no-tick-in-suspend;
> > > + };
> > > +
> > > + soc at 0 {
> > > + compatible = "simple-bus";
> > > + #address-cells = <2>;
> > > + #size-cells = <2>;
> > > + ranges;
> > > +
> > > + aips1: bus at 30000000 {
> > > + compatible = "fsl,aips-bus",
> > > "simple-bus";
> > > + #address-cells = <2>;
> > > + #size-cells = <2>;
> > > + reg = <0x0 0x30000000 0x0 0x400000>;
> > > + ranges;
> > > +
> > > + gpio1: gpio at 30200000 {
> > > + compatible = "fsl,imx8mm-gpio",
> > > "fsl,imx35-gpio";
> > > + reg = <0x0 0x30200000 0x0
> > > 0x10000>;
> > > + interrupts = <GIC_SPI 64
> > > IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 65
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + gpio-controller;
> > > + #gpio-cells = <2>;
> > > + interrupt-controller;
> > > + #interrupt-cells = <2>;
> > > + };
> > > +
> > > + gpio2: gpio at 30210000 {
> > > + compatible = "fsl,imx8mm-gpio",
> > > "fsl,imx35-gpio";
> > > + reg = <0x0 0x30210000 0x0
> > > 0x10000>;
> > > + interrupts = <GIC_SPI 66
> > > IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 67
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + gpio-controller;
> > > + #gpio-cells = <2>;
> > > + interrupt-controller;
> > > + #interrupt-cells = <2>;
> > > + };
> > > +
> > > + gpio3: gpio at 30220000 {
> > > + compatible = "fsl,imx8mm-gpio",
> > > "fsl,imx35-gpio";
> > > + reg = <0x0 0x30220000 0x0
> > > 0x10000>;
> > > + interrupts = <GIC_SPI 68
> > > IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 69
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + gpio-controller;
> > > + #gpio-cells = <2>;
> > > + interrupt-controller;
> > > + #interrupt-cells = <2>;
> > > + };
> > > +
> > > + gpio4: gpio at 30230000 {
> > > + compatible = "fsl,imx8mm-gpio",
> > > "fsl,imx35-gpio";
> > > + reg = <0x0 0x30230000 0x0
> > > 0x10000>;
> > > + interrupts = <GIC_SPI 70
> > > IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 71
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + gpio-controller;
> > > + #gpio-cells = <2>;
> > > + interrupt-controller;
> > > + #interrupt-cells = <2>;
> > > + };
> > > +
> > > + gpio5: gpio at 30240000 {
> > > + compatible = "fsl,imx8mm-gpio",
> > > "fsl,imx35-gpio";
> > > + reg = <0x0 0x30240000 0x0
> > > 0x10000>;
> > > + interrupts = <GIC_SPI 72
> > > IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 73
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + gpio-controller;
> > > + #gpio-cells = <2>;
> > > + interrupt-controller;
> > > + #interrupt-cells = <2>;
> > > + };
> > > +
> > > + wdog1: wdog at 30280000 {
> > > + compatible = "fsl,imx21-wdt";
> > > + reg = <0 0x30280000 0 0x10000>;
> > > + interrupts = <GIC_SPI 78
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clk
> > > IMX8MM_CLK_WDOG1_ROOT>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + wdog2: wdog at 30290000 {
> > > + compatible = "fsl,imx21-wdt";
> > > + reg = <0 0x30290000 0 0x10000>;
> > > + interrupts = <GIC_SPI 79
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clk
> > > IMX8MM_CLK_WDOG2_ROOT>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + wdog3: wdog at 302a0000 {
> > > + compatible = "fsl,imx21-wdt";
> > > + reg = <0 0x302a0000 0 0x10000>;
> > > + interrupts = <GIC_SPI 10
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clk
> > > IMX8MM_CLK_WDOG3_ROOT>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + sdma2: dma-controller at 302c0000 {
> > > + compatible = "fsl,imx8mq-sdma",
> > > "fsl,imx7d-sdma";
> > > + reg = <0x0 0x302c0000 0x0
> > > 0x10000>;
> > > + interrupts = <GIC_SPI 103
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clk
> > > IMX8MM_CLK_SDMA2_ROOT>,
> > > + <&clk
> > > IMX8MM_CLK_SDMA2_ROOT>;
> > > + clock-names = "ipg", "ahb";
> > > + #dma-cells = <3>;
> > > + fsl,sdma-ram-script-name =
> > > "imx/sdma/sdma-imx7d.bin";
> > > + fsl,ratio-1-1;
> > > + status = "okay";
> > > + };
> > > +
> > > + sdma3: dma-controller at 302b0000 {
> > > + compatible = "fsl,imx8mq-sdma",
> > > "fsl,imx7d-sdma";
> > > + reg = <0x0 0x302b0000 0x0
> > > 0x10000>;
> > > + interrupts = <GIC_SPI 34
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clk
> > > IMX8MM_CLK_SDMA3_ROOT>,
> > > + <&clk IMX8MM_CLK_SDMA3_ROOT>;
> > > + clock-names = "ipg", "ahb";
> > > + #dma-cells = <3>;
> > > + fsl,sdma-ram-script-name =
> > > "imx/sdma/sdma-imx7d.bin";
> > > + fsl,ratio-1-1;
> > > + status = "okay";
> > > + };
> > > +
> > > + iomuxc: pinctrl at 30330000 {
> > > + compatible = "fsl,imx8mm-iomuxc";
> > > + reg = <0x0 0x30330000 0x0
> > > 0x10000>;
> > > + };
> > > +
> > > + gpr: iomuxc-gpr at 30340000 {
> > > + compatible =
> > > "fsl,imx8mm-iomuxc-gpr", "syscon";
> > > + reg = <0x0 0x30340000 0x0
> > > 0x10000>;
> > > + };
> > > +
> > > + ocotp: ocotp-ctrl at 30350000 {
> > > + compatible = "fsl,imx8mq-ocotp",
> > > "fsl,imx7d-ocotp", "syscon";
> > > + reg = <0 0x30350000 0 0x10000>;
> > > + clocks = <&clk
> > > IMX8MM_CLK_OCOTP_ROOT>;
> > > + /* For nvmem subnodes */
> > > + #address-cells = <1>;
> > > + #size-cells = <1>;
> > > + };
> > > +
> > > + anatop: anatop at 30360000 {
> > > + compatible = "fsl,imx8mm-anatop",
> > > "syscon", "simple-bus";
> > > + reg = <0x0 0x30360000 0x0
> > > 0x10000>;
> > > + };
> > > +
> > > + snvs: snvs at 30370000 {
> > > + compatible =
> > > "fsl,sec-v4.0-mon","syscon", "simple-mfd";
> > > + reg = <0x0 0x30370000 0x0
> > > 0x10000>; +
> > > + snvs_rtc: snvs-rtc-lp{
> > > + compatible =
> > > "fsl,sec-v4.0-mon-rtc-lp";
> > > + regmap =<&snvs>;
> > > + offset = <0x34>;
> > > + interrupts = <GIC_SPI
> > > 19 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI
> > > 20 IRQ_TYPE_LEVEL_HIGH>;
> > > + };
> > > +
> > > + snvs_pwrkey: snvs-powerkey {
> > > + compatible =
> > > "fsl,sec-v4.0-pwrkey";
> > > + regmap = <&snvs>;
> > > + interrupts = <GIC_SPI 4
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + linux,keycode =
> > > <KEY_POWER>;
> > > + wakeup-source;
> > > + };
> > > + };
> > > +
> > > + clk: clock-controller at 30380000 {
> > > + compatible = "fsl,imx8mm-ccm";
> > > + reg = <0x0 0x30380000 0x0
> > > 0x10000>;
> > > + #clock-cells = <1>;
> > > + clocks = <&osc_32k>, <&osc_24m>,
> > > <&clk_ext1>, <&clk_ext2>,
> > > + <&clk_ext3>,
> > > <&clk_ext4>;
> > > + clock-names = "osc_32k",
> > > "osc_24m", "clk_ext1", "clk_ext2",
> > > + "clk_ext3",
> > > "clk_ext4";
> > > + };
> > > +
> > > + src: src at 30390000 {
> > > + compatible = "fsl,imx8mm-src",
> > > "syscon";
> > > + reg = <0x0 0x30390000 0x0
> > > 0x10000>;
> > > + interrupts = <GIC_SPI 89
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + #reset-cells = <1>;
> > > + };
> > > +
> > > + gpc: gpc at 303a0000 {
> > > + compatible = "fsl,imx8mm-gpc",
> > > "syscon";
> > > + reg = <0x0 0x303a0000 0x0
> > > 0x10000>;
> > > + interrupt-controller;
> > > + interrupts = <GIC_SPI 87
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + #interrupt-cells = <3>;
> > > + };
> > > + };
> > > +
> > > + aips2: bus at 30400000 {
> > > + compatible = "fsl,aips-bus",
> > > "simple-bus";
> > > + #address-cells = <2>;
> > > + #size-cells = <2>;
> > > + reg = <0x0 0x30400000 0x0 0x400000>;
> > > + ranges;
> > > +
> > > + pwm1: pwm at 30660000 {
> > > + compatible = "fsl,imx8mm-pwm",
> > > "fsl,imx27-pwm";
> > > + reg = <0x0 0x30660000 0x0
> > > 0x10000>;
> > > + interrupts = <GIC_SPI 81
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clk
> > > IMX8MM_CLK_PWM1_ROOT>,
> > > + <&clk
> > > IMX8MM_CLK_PWM1_ROOT>;
> > > + clock-names = "ipg", "per";
> > > + #pwm-cells = <2>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + pwm2: pwm at 30670000 {
> > > + compatible = "fsl,imx8mm-pwm",
> > > "fsl,imx27-pwm";
> > > + reg = <0x0 0x30670000 0x0
> > > 0x10000>;
> > > + interrupts = <GIC_SPI 82
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clk
> > > IMX8MM_CLK_PWM2_ROOT>,
> > > + <&clk
> > > IMX8MM_CLK_PWM2_ROOT>;
> > > + clock-names = "ipg", "per";
> > > + #pwm-cells = <2>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + pwm3: pwm at 30680000 {
> > > + compatible = "fsl,imx8mm-pwm",
> > > "fsl,imx27-pwm";
> > > + reg = <0x0 0x30680000 0x0
> > > 0x10000>;
> > > + interrupts = <GIC_SPI 83
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clk
> > > IMX8MM_CLK_PWM3_ROOT>,
> > > + <&clk
> > > IMX8MM_CLK_PWM3_ROOT>;
> > > + clock-names = "ipg", "per";
> > > + #pwm-cells = <2>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + pwm4: pwm at 30690000 {
> > > + compatible = "fsl,imx8mm-pwm",
> > > "fsl,imx27-pwm";
> > > + reg = <0x0 0x30690000 0x0
> > > 0x10000>;
> > > + interrupts = <GIC_SPI 84
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clk
> > > IMX8MM_CLK_PWM4_ROOT>,
> > > + <&clk
> > > IMX8MM_CLK_PWM4_ROOT>;
> > > + clock-names = "ipg", "per";
> > > + #pwm-cells = <2>;
> > > + status = "disabled";
> > > + };
> > > + };
> > > +
> > > + aips3: bus at 30800000 {
> > > + compatible = "fsl,aips-bus",
> > > "simple-bus";
> > > + #address-cells = <2>;
> > > + #size-cells = <2>;
> > > + reg = <0x0 0x30800000 0x0 0x400000>;
> > > + ranges;
> > > +
> > > + ecspi1: ecspi at 30820000 {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > + compatible = "fsl,imx8mm-ecspi",
> > > "fsl,imx51-ecspi";
> > > + reg = <0x0 0x30820000 0x0
> > > 0x10000>;
> > > + interrupts = <GIC_SPI 31
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clk
> > > IMX8MM_CLK_ECSPI1_ROOT>,
> > > + <&clk
> > > IMX8MM_CLK_ECSPI1_ROOT>;
> > > + clock-names = "ipg", "per";
> > > + status = "disabled";
> > > + };
> > > +
> > > + ecspi2: ecspi at 30830000 {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > + compatible = "fsl,imx8mm-ecspi",
> > > "fsl,imx51-ecspi";
> > > + reg = <0x0 0x30830000 0x0
> > > 0x10000>;
> > > + interrupts = <GIC_SPI 32
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clk
> > > IMX8MM_CLK_ECSPI2_ROOT>,
> > > + <&clk
> > > IMX8MM_CLK_ECSPI2_ROOT>;
> > > + clock-names = "ipg", "per";
> > > + status = "disabled";
> > > + };
> > > +
> > > + ecspi3: ecspi at 30840000 {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > + compatible = "fsl,imx8mm-ecspi",
> > > "fsl,imx51-ecspi";
> > > + reg = <0x0 0x30840000 0x0
> > > 0x10000>;
> > > + interrupts = <GIC_SPI 33
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clk
> > > IMX8MM_CLK_ECSPI3_ROOT>,
> > > + <&clk
> > > IMX8MM_CLK_ECSPI3_ROOT>;
> > > + clock-names = "ipg", "per";
> > > + status = "disabled";
> > > + };
> > > +
> > > + uart1: serial at 30860000 {
> > > + compatible = "fsl,imx8mm-uart",
> > > + "fsl,imx6q-uart",
> > > "fsl,imx21-uart";
> > > + reg = <0x0 0x30860000 0x0
> > > 0x10000>;
> > > + interrupts = <GIC_SPI 26
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clk
> > > IMX8MM_CLK_UART1_ROOT>,
> > > + <&clk
> > > IMX8MM_CLK_UART1_ROOT>;
> > > + clock-names = "ipg", "per";
> > > + status = "disabled";
> > > + };
> > > +
> > > + uart3: serial at 30880000 {
> > > + compatible = "fsl,imx8mm-uart",
> > > + "fsl,imx6q-uart",
> > > "fsl,imx21-uart";
> > > + reg = <0x0 0x30880000 0x0
> > > 0x10000>;
> > > + interrupts = <GIC_SPI 28
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clk
> > > IMX8MM_CLK_UART3_ROOT>,
> > > + <&clk
> > > IMX8MM_CLK_UART3_ROOT>;
> > > + clock-names = "ipg", "per";
> > > + status = "disabled";
> > > + };
> > > +
> > > + uart2: serial at 30890000 {
> > > + compatible = "fsl,imx8mm-uart",
> > > + "fsl,imx6q-uart",
> > > "fsl,imx21-uart";
> > > + reg = <0x0 0x30890000 0x0
> > > 0x10000>;
> > > + interrupts = <GIC_SPI 27
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clk
> > > IMX8MM_CLK_UART2_ROOT>,
> > > + <&clk
> > > IMX8MM_CLK_UART2_ROOT>;
> > > + clock-names = "ipg", "per";
> > > + status = "disabled";
> > > + };
> > > +
> > > + i2c1: i2c at 30a20000 {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > + compatible = "fsl,imx8mm-i2c",
> > > "fsl,imx21-i2c";
> > > + reg = <0x0 0x30a20000 0x0
> > > 0x10000>;
> > > + interrupts = <GIC_SPI 35
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clk
> > > IMX8MM_CLK_I2C1_ROOT>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + i2c2: i2c at 30a30000 {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > + compatible = "fsl,imx8mm-i2c",
> > > "fsl,imx21-i2c";
> > > + reg = <0x0 0x30a30000 0x0
> > > 0x10000>;
> > > + interrupts = <GIC_SPI 36
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clk
> > > IMX8MM_CLK_I2C2_ROOT>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + i2c3: i2c at 30a40000 {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > + compatible = "fsl,imx8mm-i2c",
> > > "fsl,imx21-i2c";
> > > + reg = <0x0 0x30a40000 0x0
> > > 0x10000>;
> > > + interrupts = <GIC_SPI 37
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clk
> > > IMX8MM_CLK_I2C3_ROOT>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + i2c4: i2c at 30a50000 {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > + compatible = "fsl,imx8mm-i2c",
> > > "fsl,imx21-i2c";
> > > + reg = <0x0 0x30a50000 0x0
> > > 0x10000>;
> > > + interrupts = <GIC_SPI 38
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clk
> > > IMX8MM_CLK_I2C4_ROOT>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + uart4: serial at 30a60000 {
> > > + compatible = "fsl,imx8mq-uart",
> > > + "fsl,imx6q-uart",
> > > "fsl,imx21-uart";
> > > + reg = <0x0 0x30a60000 0x0
> > > 0x10000>;
> > > + interrupts = <GIC_SPI 29
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clk
> > > IMX8MM_CLK_UART4_ROOT>,
> > > + <&clk
> > > IMX8MM_CLK_UART4_ROOT>;
> > > + clock-names = "ipg", "per";
> > > + status = "disabled";
> > > + };
> > > +
> > > + usdhc1: mmc at 30b40000 {
> > > + compatible = "fsl,imx8mq-usdhc",
> > > "fsl,imx7d-usdhc";
> > > + reg = <0x0 0x30b40000 0x0
> > > 0x10000>;
> > > + interrupts = <GIC_SPI 22
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clk IMX8MM_CLK_DUMMY>,
> > > + <&clk
> > > IMX8MM_CLK_NAND_USDHC_BUS>,
> > > + <&clk
> > > IMX8MM_CLK_USDHC1_ROOT>;
> > > + clock-names = "ipg", "ahb",
> > > "per";
> > > + assigned-clocks = <&clk
> > > IMX8MM_CLK_USDHC1>;
> > > + assigned-clock-rates =
> > > <400000000>;
> > > + fsl,tuning-start-tap = <20>;
> > > + fsl,tuning-step= <2>;
> > > + bus-width = <4>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + usdhc2: mmc at 30b50000 {
> > > + compatible = "fsl,imx8mq-usdhc",
> > > "fsl,imx7d-usdhc";
> > > + reg = <0x0 0x30b50000 0x0
> > > 0x10000>;
> > > + interrupts = <GIC_SPI 23
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clk IMX8MM_CLK_DUMMY>,
> > > + <&clk
> > > IMX8MM_CLK_NAND_USDHC_BUS>,
> > > + <&clk
> > > IMX8MM_CLK_USDHC2_ROOT>;
> > > + clock-names = "ipg", "ahb",
> > > "per";
> > > + fsl,tuning-start-tap = <20>;
> > > + fsl,tuning-step= <2>;
> > > + bus-width = <4>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + usdhc3: mmc at 30b60000 {
> > > + compatible = "fsl,imx8mq-usdhc",
> > > "fsl,imx7d-usdhc";
> > > + reg = <0x0 0x30b60000 0x0
> > > 0x10000>;
> > > + interrupts = <GIC_SPI 24
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clk IMX8MM_CLK_DUMMY>,
> > > + <&clk
> > > IMX8MM_CLK_NAND_USDHC_BUS>,
> > > + <&clk
> > > IMX8MM_CLK_USDHC3_ROOT>;
> > > + clock-names = "ipg", "ahb",
> > > "per";
> > > + assigned-clocks = <&clk
> > > IMX8MM_CLK_USDHC3_ROOT>;
> > > + assigned-clock-rates =
> > > <400000000>;
> > > + fsl,tuning-start-tap = <20>;
> > > + fsl,tuning-step= <2>;
> > > + bus-width = <4>;
> > > + status = "disabled";
> > > + };
> > > + };
> > > + };
> > > +};
> > > diff --git a/arch/arm/mach-imx/imx8m/Kconfig
> > > b/arch/arm/mach-imx/imx8m/Kconfig index 35c978e863..f520075875
> > 100644
> > > --- a/arch/arm/mach-imx/imx8m/Kconfig
> > > +++ b/arch/arm/mach-imx/imx8m/Kconfig
> > > @@ -24,8 +24,15 @@ config TARGET_IMX8MQ_EVK
> > > select IMX8MQ
> > > select IMX8M_LPDDR4
> > >
> > > +config TARGET_IMX8MM_EVK
> > > + bool "imx8mm LPDDR4 EVK board"
> > > + select IMX8MM
> > > + select SUPPORT_SPL
> > > + select IMX8M_LPDDR4
> >
> > Here you shall put the select DM_{UART,USDHC, etc}
> >
> > > +
> > > endchoice
> > >
> > > source "board/freescale/imx8mq_evk/Kconfig"
> > > +source "board/freescale/imx8mm_evk/Kconfig"
> > >
> > > endif
> > > diff --git a/board/freescale/imx8mm_evk/Kconfig
> > > b/board/freescale/imx8mm_evk/Kconfig new file mode 100644
> > > index 0000000000..299691a619
> > > --- /dev/null
> > > +++ b/board/freescale/imx8mm_evk/Kconfig
> > > @@ -0,0 +1,12 @@
> > > +if TARGET_IMX8MM_EVK
> > > +
> > > +config SYS_BOARD
> > > + default "imx8mm_evk"
> > > +
> > > +config SYS_VENDOR
> > > + default "freescale"
> > > +
> > > +config SYS_CONFIG_NAME
> > > + default "imx8mm_evk"
> > > +
> > > +endif
> > > diff --git a/board/freescale/imx8mm_evk/MAINTAINERS
> > > b/board/freescale/imx8mm_evk/MAINTAINERS new file mode 100644
> > > index 0000000000..b031bb0674
> > > --- /dev/null
> > > +++ b/board/freescale/imx8mm_evk/MAINTAINERS
> > > @@ -0,0 +1,6 @@
> > > +i.MX8MM EVK BOARD
> > > +M: Peng Fan <peng.fan@nxp.com>
> > > +S: Maintained
> > > +F: board/freescale/imx8mm_evk/
> > > +F: include/configs/imx8mm_evk.h
> > > +F: configs/imx8mm_evk_defconfig
> > > diff --git a/board/freescale/imx8mm_evk/Makefile
> > > b/board/freescale/imx8mm_evk/Makefile new file mode 100644
> > > index 0000000000..1db7b62caf
> > > --- /dev/null
> > > +++ b/board/freescale/imx8mm_evk/Makefile
> > > @@ -0,0 +1,12 @@
> > > +#
> > > +# Copyright 2018 NXP
> > > +#
> > > +# SPDX-License-Identifier: GPL-2.0+
> > > +#
> > > +
> > > +obj-y += imx8mm_evk.o
> > > +
> > > +ifdef CONFIG_SPL_BUILD
> > > +obj-y += spl.o
> > > +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
> > > +endif
> > > diff --git a/board/freescale/imx8mm_evk/imx8mm_evk.c
> > > b/board/freescale/imx8mm_evk/imx8mm_evk.c new file mode 100644
> > > index 0000000000..a681aca04d
> > > --- /dev/null
> > > +++ b/board/freescale/imx8mm_evk/imx8mm_evk.c
> > > @@ -0,0 +1,144 @@
> > > +// SPDX-License-Identifier: GPL-2.0+
> > > +/*
> > > + * Copyright 2018 NXP
> > > + */
> > > +
> > > +#include <common.h>
> > > +#include <malloc.h>
> > > +#include <errno.h>
> > > +#include <asm/io.h>
> > > +#include <miiphy.h>
> > > +#include <netdev.h>
> > > +#include <asm/mach-imx/iomux-v3.h>
> > > +#include <asm-generic/gpio.h>
> > > +#include <fsl_esdhc.h>
> > > +#include <mmc.h>
> > > +#include <asm/arch/imx8mm_pins.h>
> > > +#include <asm/arch/sys_proto.h>
> > > +#include <asm/mach-imx/gpio.h>
> > > +#include <asm/mach-imx/mxc_i2c.h>
> > > +#include <asm/arch/clock.h>
> > > +#include <spl.h>
> > > +#include <asm/mach-imx/dma.h>
> > > +
> > > +DECLARE_GLOBAL_DATA_PTR;
> > > +
> > > +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
> > > +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE |
> > > PAD_CTL_PUE | PAD_CTL_PE) +
> > > +static iomux_v3_cfg_t const uart_pads[] = {
> > > + IMX8MM_PAD_UART2_RXD_UART2_RX |
> > MUX_PAD_CTRL(UART_PAD_CTRL),
> > > + IMX8MM_PAD_UART2_TXD_UART2_TX |
> > MUX_PAD_CTRL(UART_PAD_CTRL),
> > > +};
> > > +
> > > +static iomux_v3_cfg_t const wdog_pads[] = {
> > > + IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B |
> > > MUX_PAD_CTRL(WDOG_PAD_CTRL), +};
> > > +
> > > +int board_early_init_f(void)
> > > +{
> > > + struct wdog_regs *wdog = (struct wdog_regs
> > > *)WDOG1_BASE_ADDR; +
> > > + imx_iomux_v3_setup_multiple_pads(wdog_pads,
> > > ARRAY_SIZE(wdog_pads)); +
> > > + set_wdog_reset(wdog);
> > > +
> > > + imx_iomux_v3_setup_multiple_pads(uart_pads,
> > > ARRAY_SIZE(uart_pads)); +
> > > + return 0;
> > > +}
> > > +
> > > +#ifdef CONFIG_BOARD_POSTCLK_INIT
> > > +int board_postclk_init(void)
> > > +{
> > > + /* TODO */
> > > + return 0;
> > > +}
> > > +#endif
> > > +
> > > +int dram_init(void)
> > > +{
> > > + /* rom_pointer[1] contains the size of TEE occupies */
> > > + if (rom_pointer[1])
> > > + gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
> > > + else
> > > + gd->ram_size = PHYS_SDRAM_SIZE;
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +#ifdef CONFIG_OF_BOARD_SETUP
> > > +int ft_board_setup(void *blob, bd_t *bd)
> > ^^^ - fdt_board_setup ?
> > > +{
> > > + return 0;
> > > +}
> > > +#endif
> > > +
> > > +#ifdef CONFIG_FEC_MXC
> > > +#define FEC_RST_PAD IMX_GPIO_NR(4, 22)
> > > +static iomux_v3_cfg_t const fec1_rst_pads[] = {
> > > + IMX8MM_PAD_SAI2_RXC_GPIO4_IO22 |
> > MUX_PAD_CTRL(NO_PAD_CTRL),
> >
> > This shall be done with fsl_fec.c DM driver - there is support for
> > adding reset pin (to dts).
> >
> > > +};
> > > +
> > > +static void setup_iomux_fec(void)
> > > +{
> > > + imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
> > > +
> > > ARRAY_SIZE(fec1_rst_pads)); +
> > > + gpio_request(FEC_RST_PAD, "fec1_rst");
> > > + gpio_direction_output(FEC_RST_PAD, 0);
> > > + udelay(500);
> > > + gpio_direction_output(FEC_RST_PAD, 1);
> > > +}
> >
> > This shall be replaced with DM/DTS of the fsl_fec.c driver. Please
> > also note that there are (at least on imx6q) some timing issues
> > when we move the code to DM/DTS (some delay is needed).
> >
> > > +
> > > +static int setup_fec(void)
> > > +{
> > > + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
> > > + = (struct iomuxc_gpr_base_regs
> > > *)IOMUXC_GPR_BASE_ADDR; +
> > > + setup_iomux_fec();
> > > +
> > > + /* Use 125M anatop REF_CLK1 for ENET1, not from external
> > > */
> > > + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
> > > +
> > > IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT, 0);
> > > + return set_clk_enet(ENET_125MHZ);
> > > +}
> > > +
> > > +int board_phy_config(struct phy_device *phydev)
> > > +{
> > > + /* enable rgmii rxc skew and phy mode select to RGMII
> > > copper */
> > > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
> > > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
> > > +
> > > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
> > > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
> > > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
> > > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
> > > +
> > > + if (phydev->drv->config)
> > > + phydev->drv->config(phydev);
> > > + return 0;
> >
> > Which PHY do you use? E.g. KSZ... support passing those values via
> > DTS.
> > > +}
> > > +#endif
> > > +
> > > +int board_init(void)
> > > +{
> > > +#ifdef CONFIG_FEC_MXC
> > > + setup_fec();
> > > +#endif
> > > + return 0;
> > > +}
> > > +
> > > +int board_mmc_get_env_dev(int devno)
> > > +{
> > > + return devno - 1;
> > > +}
> > > +
> > > +int board_late_init(void)
> > > +{
> > > +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> > > + env_set("board_name", "EVK");
> > > + env_set("board_rev", "iMX8MM");
> > > +#endif
> > > + return 0;
> > > +}
> > > diff --git a/board/freescale/imx8mm_evk/lpddr4_timing.c
> > > b/board/freescale/imx8mm_evk/lpddr4_timing.c new file mode 100644
> > > index 0000000000..4bade5bf74
> > > --- /dev/null
> > > +++ b/board/freescale/imx8mm_evk/lpddr4_timing.c
> > > @@ -0,0 +1,1980 @@
> > > +// SPDX-License-Identifier: GPL-2.0+
> > > +/*
> > > + * Copyright 2018 NXP
> >
> > Author is missing.
> >
> > > + */
> > > +
> > > +#include <linux/kernel.h>
> > > +#include <common.h>
> > > +#include <asm/arch/ddr.h>
> > > +#include <asm/arch/lpddr4_define.h>
> > > +
> > > +struct dram_cfg_param lpddr4_ddrc_cfg[] = {
> > > + /* Start to config, default 3200mbps */
> > > + { DDRC_DBG1(0), 0x00000001 },
> > > + { DDRC_PWRCTL(0), 0x00000001 },
> > > + { DDRC_MSTR(0), 0xa1080020 },
> > > + { DDRC_RFSHTMG(0), 0x005b00d2 },
> > > + { DDRC_INIT0(0), 0xC003061B },
> > > + { DDRC_INIT1(0), 0x009D0000 },
> > > + { DDRC_INIT3(0), 0x00D4002D },
> > > + { DDRC_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 },
> > > + { DDRC_INIT6(0), 0x0066004a },
> > > + { DDRC_INIT7(0), 0x0006004a },
> > > +
> > > + { DDRC_DRAMTMG0(0), 0x1A201B22 },
> > > + { DDRC_DRAMTMG1(0), 0x00060633 },
> > > + { DDRC_DRAMTMG3(0), 0x00C0C000 },
> > > + { DDRC_DRAMTMG4(0), 0x0F04080F },
> > > + { DDRC_DRAMTMG5(0), 0x02040C0C },
> > > + { DDRC_DRAMTMG6(0), 0x01010007 },
> > > + { DDRC_DRAMTMG7(0), 0x00000401 },
> > > + { DDRC_DRAMTMG12(0), 0x00020600 },
> > > + { DDRC_DRAMTMG13(0), 0x0C100002 },
> > > + { DDRC_DRAMTMG14(0), 0x000000E6 },
> > > + { DDRC_DRAMTMG17(0), 0x00A00050 },
> > > +
> > > + { DDRC_ZQCTL0(0), 0x03200018 },
> > > + { DDRC_ZQCTL1(0), 0x028061A8 },
> > > + { DDRC_ZQCTL2(0), 0x00000000 },
> > > +
> > > + { DDRC_DFITMG0(0), 0x0497820A },
> > > + { DDRC_DFITMG2(0), 0x0000170A },
> > > + { DDRC_DRAMTMG2(0), 0x070E171a },
> > > + { DDRC_DBICTL(0), 0x00000001 },
> > > +
> > > + { DDRC_DFITMG1(0), 0x00080303 },
> > > + { DDRC_DFIUPD0(0), 0xE0400018 },
> > > + { DDRC_DFIUPD1(0), 0x00DF00E4 },
> > > + { DDRC_DFIUPD2(0), 0x80000000 },
> > > + { DDRC_DFIMISC(0), 0x00000011 },
> > > +
> > > + { DDRC_DFIPHYMSTR(0), 0x00000000 },
> > > + { DDRC_RANKCTL(0), 0x00000c99 },
> > > +
> > > + /* address mapping */
> > > + { DDRC_ADDRMAP0(0), 0x0000001f },
> > > + { DDRC_ADDRMAP1(0), 0x00080808 },
> > > + { DDRC_ADDRMAP2(0), 0x00000000 },
> > > + { DDRC_ADDRMAP3(0), 0x00000000 },
> > > + { DDRC_ADDRMAP4(0), 0x00001f1f },
> > > + { DDRC_ADDRMAP5(0), 0x07070707 },
> > > + { DDRC_ADDRMAP6(0), 0x07070707 },
> > > + { DDRC_ADDRMAP7(0), 0x00000f0f },
> > > +
> > > + /* performance setting */
> > > + { DDRC_SCHED(0), 0x29001701 },
> > > + { DDRC_SCHED1(0), 0x0000002c },
> > > + { DDRC_PERFHPR1(0), 0x04000030 },
> > > + { DDRC_PERFLPR1(0), 0x900093e7 },
> > > + { DDRC_PERFWR1(0), 0x20005574 },
> > > + { DDRC_PCCFG(0), 0x00000111 },
> > > + { DDRC_PCFGW_0(0), 0x000072ff },
> > > + { DDRC_PCFGQOS0_0(0), 0x02100e07 },
> > > + { DDRC_PCFGQOS1_0(0), 0x00620096 },
> > > + { DDRC_PCFGWQOS0_0(0), 0x01100e07 },
> > > + { DDRC_PCFGWQOS1_0(0), 0x00c8012c },
> > > +
> > > + /* frequency P1&P2 */
> > > + /* Frequency 1: 400mbps */
> > > + { DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c },
> > > + { DDRC_FREQ1_DRAMTMG1(0), 0x00030410 },
> > > + { DDRC_FREQ1_DRAMTMG2(0), 0x0203090c },
> > > + { DDRC_FREQ1_DRAMTMG3(0), 0x00505006 },
> > > + { DDRC_FREQ1_DRAMTMG4(0), 0x05040305 },
> > > + { DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504 },
> > > + { DDRC_FREQ1_DRAMTMG6(0), 0x0a060004 },
> > > + { DDRC_FREQ1_DRAMTMG7(0), 0x0000090e },
> > > + { DDRC_FREQ1_DRAMTMG14(0), 0x00000032 },
> > > + { DDRC_FREQ1_DRAMTMG15(0), 0x00000000 },
> > > + { DDRC_FREQ1_DRAMTMG17(0), 0x0036001b },
> > > + { DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1 },
> > > + { DDRC_FREQ1_DFITMG0(0), 0x03818200 },
> > > + { DDRC_FREQ1_DFITMG2(0), 0x00000000 },
> > > + { DDRC_FREQ1_RFSHTMG(0), 0x000C001c },
> > > + { DDRC_FREQ1_INIT3(0), 0x00840000 },
> > > + { DDRC_FREQ1_INIT4(0), 0x00310000 },
> > > + { DDRC_FREQ1_INIT6(0), 0x0066004a },
> > > + { DDRC_FREQ1_INIT7(0), 0x0006004a },
> > > +
> > > + /* Frequency 2: 100mbps */
> > > + { DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c },
> > > + { DDRC_FREQ2_DRAMTMG1(0), 0x00030410 },
> > > + { DDRC_FREQ2_DRAMTMG2(0), 0x0203090c },
> > > + { DDRC_FREQ2_DRAMTMG3(0), 0x00505006 },
> > > + { DDRC_FREQ2_DRAMTMG4(0), 0x05040305 },
> > > + { DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504 },
> > > + { DDRC_FREQ2_DRAMTMG6(0), 0x0a060004 },
> > > + { DDRC_FREQ2_DRAMTMG7(0), 0x0000090e },
> > > + { DDRC_FREQ2_DRAMTMG14(0), 0x00000032 },
> > > + { DDRC_FREQ2_DRAMTMG17(0), 0x0036001b },
> > > + { DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1 },
> > > + { DDRC_FREQ2_DFITMG0(0), 0x03818200 },
> > > + { DDRC_FREQ2_DFITMG2(0), 0x00000000 },
> > > + { DDRC_FREQ2_RFSHTMG(0), 0x0003800c },
> > > + { DDRC_FREQ2_RFSHTMG(0), 0x00030007 },
> > > + { DDRC_FREQ2_INIT3(0), 0x00840000 },
> > > + { DDRC_FREQ2_INIT4(0), 0x00310008 },
> > > + { DDRC_FREQ2_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 },
> > > + { DDRC_FREQ2_INIT6(0), 0x0066004a },
> > > + { DDRC_FREQ2_INIT7(0), 0x0006004a },
> > > +
> > > + /* boot start point */
> > > + { DDRC_MSTR2(0), 0x2 }, //DDRC_MSTR2
> > > +};
> > > +
> > > +/* PHY Initialize Configuration */
> > > +struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
> > > + { 0x1005f, 0x1ff },
> > > + { 0x1015f, 0x1ff },
> > > + { 0x1105f, 0x1ff },
> > > + { 0x1115f, 0x1ff },
> > > + { 0x1205f, 0x1ff },
> > > + { 0x1215f, 0x1ff },
> > > + { 0x1305f, 0x1ff },
> > > + { 0x1315f, 0x1ff },
> > > +
> > > + { 0x11005f, 0x1ff },
> > > + { 0x11015f, 0x1ff },
> > > + { 0x11105f, 0x1ff },
> > > + { 0x11115f, 0x1ff },
> > > + { 0x11205f, 0x1ff },
> > > + { 0x11215f, 0x1ff },
> > > + { 0x11305f, 0x1ff },
> > > + { 0x11315f, 0x1ff },
> > > +
> > > + { 0x21005f, 0x1ff },
> > > + { 0x21015f, 0x1ff },
> > > + { 0x21105f, 0x1ff },
> > > + { 0x21115f, 0x1ff },
> > > + { 0x21205f, 0x1ff },
> > > + { 0x21215f, 0x1ff },
> > > + { 0x21305f, 0x1ff },
> > > + { 0x21315f, 0x1ff },
> > > +
> > > + { 0x55, 0x1ff },
> > > + { 0x1055, 0x1ff },
> > > + { 0x2055, 0x1ff },
> > > + { 0x3055, 0x1ff },
> > > + { 0x4055, 0x1ff },
> > > + { 0x5055, 0x1ff },
> > > + { 0x6055, 0x1ff },
> > > + { 0x7055, 0x1ff },
> > > + { 0x8055, 0x1ff },
> > > + { 0x9055, 0x1ff },
> > > +
> > > + { 0x200c5, 0x19 },
> > > + { 0x1200c5, 0x7 },
> > > + { 0x2200c5, 0x7 },
> > > +
> > > + { 0x2002e, 0x2 },
> > > + { 0x12002e, 0x2 },
> > > + { 0x22002e, 0x2 },
> > > +
> > > + { 0x90204, 0x0 },
> > > + { 0x190204, 0x0 },
> > > + { 0x290204, 0x0 },
> > > +
> > > + { 0x20024, 0xab },
> > > + { 0x2003a, 0x0 },
> > > +
> > > + { 0x120024, 0xab },
> > > + { 0x2003a, 0x0 },
> > > +
> > > + { 0x220024, 0xab },
> > > + { 0x2003a, 0x0 },
> > > +
> > > + { 0x20056, 0x3 },
> > > + { 0x120056, 0xa },
> > > + { 0x220056, 0xa },
> > > +
> > > + { 0x1004d, 0xe00 },
> > > + { 0x1014d, 0xe00 },
> > > + { 0x1104d, 0xe00 },
> > > + { 0x1114d, 0xe00 },
> > > + { 0x1204d, 0xe00 },
> > > + { 0x1214d, 0xe00 },
> > > + { 0x1304d, 0xe00 },
> > > + { 0x1314d, 0xe00 },
> > > +
> > > + { 0x11004d, 0xe00 },
> > > + { 0x11014d, 0xe00 },
> > > + { 0x11104d, 0xe00 },
> > > + { 0x11114d, 0xe00 },
> > > + { 0x11204d, 0xe00 },
> > > + { 0x11214d, 0xe00 },
> > > + { 0x11304d, 0xe00 },
> > > + { 0x11314d, 0xe00 },
> > > +
> > > + { 0x21004d, 0xe00 },
> > > + { 0x21014d, 0xe00 },
> > > + { 0x21104d, 0xe00 },
> > > + { 0x21114d, 0xe00 },
> > > + { 0x21204d, 0xe00 },
> > > + { 0x21214d, 0xe00 },
> > > + { 0x21304d, 0xe00 },
> > > + { 0x21314d, 0xe00 },
> > > +
> > > + { 0x10049, 0xfbe },
> > > + { 0x10149, 0xfbe },
> > > + { 0x11049, 0xfbe },
> > > + { 0x11149, 0xfbe },
> > > + { 0x12049, 0xfbe },
> > > + { 0x12149, 0xfbe },
> > > + { 0x13049, 0xfbe },
> > > + { 0x13149, 0xfbe },
> > > +
> > > + { 0x110049, 0xfbe },
> > > + { 0x110149, 0xfbe },
> > > + { 0x111049, 0xfbe },
> > > + { 0x111149, 0xfbe },
> > > + { 0x112049, 0xfbe },
> > > + { 0x112149, 0xfbe },
> > > + { 0x113049, 0xfbe },
> > > + { 0x113149, 0xfbe },
> > > +
> > > + { 0x210049, 0xfbe },
> > > + { 0x210149, 0xfbe },
> > > + { 0x211049, 0xfbe },
> > > + { 0x211149, 0xfbe },
> > > + { 0x212049, 0xfbe },
> > > + { 0x212149, 0xfbe },
> > > + { 0x213049, 0xfbe },
> > > + { 0x213149, 0xfbe },
> > > +
> > > + { 0x43, 0x63 },
> > > + { 0x1043, 0x63 },
> > > + { 0x2043, 0x63 },
> > > + { 0x3043, 0x63 },
> > > + { 0x4043, 0x63 },
> > > + { 0x5043, 0x63 },
> > > + { 0x6043, 0x63 },
> > > + { 0x7043, 0x63 },
> > > + { 0x8043, 0x63 },
> > > + { 0x9043, 0x63 },
> > > +
> > > + { 0x20018, 0x3 },
> > > + { 0x20075, 0x4 },
> > > + { 0x20050, 0x0 },
> > > + { 0x20008, 0x2ee },
> > > + { 0x120008, 0x64 },
> > > + { 0x220008, 0x19 },
> > > + { 0x20088, 0x9 },
> > > +
> > > + { 0x200b2, 0x1d4 },
> > > + { 0x10043, 0x5a1 },
> > > + { 0x10143, 0x5a1 },
> > > + { 0x11043, 0x5a1 },
> > > + { 0x11143, 0x5a1 },
> > > + { 0x12043, 0x5a1 },
> > > + { 0x12143, 0x5a1 },
> > > + { 0x13043, 0x5a1 },
> > > + { 0x13143, 0x5a1 },
> > > +
> > > + { 0x1200b2, 0xdc },
> > > + { 0x110043, 0x5a1 },
> > > + { 0x110143, 0x5a1 },
> > > + { 0x111043, 0x5a1 },
> > > + { 0x111143, 0x5a1 },
> > > + { 0x112043, 0x5a1 },
> > > + { 0x112143, 0x5a1 },
> > > + { 0x113043, 0x5a1 },
> > > + { 0x113143, 0x5a1 },
> > > +
> > > + { 0x2200b2, 0xdc },
> > > + { 0x210043, 0x5a1 },
> > > + { 0x210143, 0x5a1 },
> > > + { 0x211043, 0x5a1 },
> > > + { 0x211143, 0x5a1 },
> > > + { 0x212043, 0x5a1 },
> > > + { 0x212143, 0x5a1 },
> > > + { 0x213043, 0x5a1 },
> > > + { 0x213143, 0x5a1 },
> > > +
> > > + { 0x200fa, 0x1 },
> > > + { 0x1200fa, 0x1 },
> > > + { 0x2200fa, 0x1 },
> > > +
> > > + { 0x20019, 0x1 },
> > > + { 0x120019, 0x1 },
> > > + { 0x220019, 0x1 },
> > > +
> > > + { 0x200f0, 0x660 },
> > > + { 0x200f1, 0x0 },
> > > + { 0x200f2, 0x4444 },
> > > + { 0x200f3, 0x8888 },
> > > + { 0x200f4, 0x5665 },
> > > + { 0x200f5, 0x0 },
> > > + { 0x200f6, 0x0 },
> > > + { 0x200f7, 0xf000 },
> > > +
> > > + { 0x20025, 0x0 },
> > > + { 0x2002d, LPDDR4_PHY_DMIPinPresent },
> > > + { 0x12002d, LPDDR4_PHY_DMIPinPresent },
> > > + { 0x22002d, LPDDR4_PHY_DMIPinPresent },
> > > + { 0x200c7, 0x21 },
> > > + { 0x200ca, 0x24 },
> > > + { 0x1200c7, 0x21 },
> > > + { 0x1200ca, 0x24 },
> > > + { 0x2200c7, 0x21 },
> > > + { 0x2200ca, 0x24 },
> >
> > Why do you add tuple - offset and value? Shouldn't we have the
> > DDR training functions here?
> >
> > It is possible to train IMX6Q and Vybrid's DDR3 (as fair as I know).
> > Would it be also possible to add the DDR4 training code for IMX8?
> >
> > > +};
> > > +
> > > +/* ddr phy trained csr */
> > > +struct dram_cfg_param lpddr4_ddrphy_trained_csr[] = {
> > > + { 0x200b2, 0x0 },
> > > + { 0x1200b2, 0x0 },
> > > + { 0x2200b2, 0x0 },
> > > + { 0x200cb, 0x0 },
> > > + { 0x10043, 0x0 },
> > > + { 0x110043, 0x0 },
> > > + { 0x210043, 0x0 },
> > > + { 0x10143, 0x0 },
> > > + { 0x110143, 0x0 },
> > > + { 0x210143, 0x0 },
> > > + { 0x11043, 0x0 },
> > > + { 0x111043, 0x0 },
> > > + { 0x211043, 0x0 },
> > > + { 0x11143, 0x0 },
> > > + { 0x111143, 0x0 },
> > > + { 0x211143, 0x0 },
> > > + { 0x12043, 0x0 },
> > > + { 0x112043, 0x0 },
> > > + { 0x212043, 0x0 },
> > > + { 0x12143, 0x0 },
> > > + { 0x112143, 0x0 },
> > > + { 0x212143, 0x0 },
> > > + { 0x13043, 0x0 },
> > > + { 0x113043, 0x0 },
> > > + { 0x213043, 0x0 },
> > > + { 0x13143, 0x0 },
> > > + { 0x113143, 0x0 },
> > > + { 0x213143, 0x0 },
> > > + { 0x80, 0x0 },
> > > + { 0x100080, 0x0 },
> > > + { 0x200080, 0x0 },
> > > + { 0x1080, 0x0 },
> > > + { 0x101080, 0x0 },
> > > + { 0x201080, 0x0 },
> > > + { 0x2080, 0x0 },
> > > + { 0x102080, 0x0 },
> > > + { 0x202080, 0x0 },
> > > + { 0x3080, 0x0 },
> > > + { 0x103080, 0x0 },
> > > + { 0x203080, 0x0 },
> > > + { 0x4080, 0x0 },
> > > + { 0x104080, 0x0 },
> > > + { 0x204080, 0x0 },
> > > + { 0x5080, 0x0 },
> > > + { 0x105080, 0x0 },
> > > + { 0x205080, 0x0 },
> > > + { 0x6080, 0x0 },
> > > + { 0x106080, 0x0 },
> > > + { 0x206080, 0x0 },
> > > + { 0x7080, 0x0 },
> > > + { 0x107080, 0x0 },
> > > + { 0x207080, 0x0 },
> > > + { 0x8080, 0x0 },
> > > + { 0x108080, 0x0 },
> > > + { 0x208080, 0x0 },
> > > + { 0x9080, 0x0 },
> > > + { 0x109080, 0x0 },
> > > + { 0x209080, 0x0 },
> > > + { 0x10080, 0x0 },
> > > + { 0x110080, 0x0 },
> > > + { 0x210080, 0x0 },
> > > + { 0x10180, 0x0 },
> > > + { 0x110180, 0x0 },
> > > + { 0x210180, 0x0 },
> > > + { 0x11080, 0x0 },
> > > + { 0x111080, 0x0 },
> > > + { 0x211080, 0x0 },
> > > + { 0x11180, 0x0 },
> > > + { 0x111180, 0x0 },
> > > + { 0x211180, 0x0 },
> > > + { 0x12080, 0x0 },
> > > + { 0x112080, 0x0 },
> > > + { 0x212080, 0x0 },
> > > + { 0x12180, 0x0 },
> > > + { 0x112180, 0x0 },
> > > + { 0x212180, 0x0 },
> > > + { 0x13080, 0x0 },
> > > + { 0x113080, 0x0 },
> > > + { 0x213080, 0x0 },
> > > + { 0x13180, 0x0 },
> > > + { 0x113180, 0x0 },
> > > + { 0x213180, 0x0 },
> > > + { 0x10081, 0x0 },
> > > + { 0x110081, 0x0 },
> > > + { 0x210081, 0x0 },
> > > + { 0x10181, 0x0 },
> > > + { 0x110181, 0x0 },
> > > + { 0x210181, 0x0 },
> > > + { 0x11081, 0x0 },
> > > + { 0x111081, 0x0 },
> > > + { 0x211081, 0x0 },
> > > + { 0x11181, 0x0 },
> > > + { 0x111181, 0x0 },
> > > + { 0x211181, 0x0 },
> > > + { 0x12081, 0x0 },
> > > + { 0x112081, 0x0 },
> > > + { 0x212081, 0x0 },
> > > + { 0x12181, 0x0 },
> > > + { 0x112181, 0x0 },
> > > + { 0x212181, 0x0 },
> > > + { 0x13081, 0x0 },
> > > + { 0x113081, 0x0 },
> > > + { 0x213081, 0x0 },
> > > + { 0x13181, 0x0 },
> > > + { 0x113181, 0x0 },
> > > + { 0x213181, 0x0 },
> > > + { 0x100d0, 0x0 },
> > > + { 0x1100d0, 0x0 },
> > > + { 0x2100d0, 0x0 },
> > > + { 0x101d0, 0x0 },
> > > + { 0x1101d0, 0x0 },
> > > + { 0x2101d0, 0x0 },
> > > + { 0x110d0, 0x0 },
> > > + { 0x1110d0, 0x0 },
> > > + { 0x2110d0, 0x0 },
> > > + { 0x111d0, 0x0 },
> > > + { 0x1111d0, 0x0 },
> > > + { 0x2111d0, 0x0 },
> > > + { 0x120d0, 0x0 },
> > > + { 0x1120d0, 0x0 },
> > > + { 0x2120d0, 0x0 },
> > > + { 0x121d0, 0x0 },
> > > + { 0x1121d0, 0x0 },
> > > + { 0x2121d0, 0x0 },
> > > + { 0x130d0, 0x0 },
> > > + { 0x1130d0, 0x0 },
> > > + { 0x2130d0, 0x0 },
> > > + { 0x131d0, 0x0 },
> > > + { 0x1131d0, 0x0 },
> > > + { 0x2131d0, 0x0 },
> > > + { 0x100d1, 0x0 },
> > > + { 0x1100d1, 0x0 },
> > > + { 0x2100d1, 0x0 },
> > > + { 0x101d1, 0x0 },
> > > + { 0x1101d1, 0x0 },
> > > + { 0x2101d1, 0x0 },
> > > + { 0x110d1, 0x0 },
> > > + { 0x1110d1, 0x0 },
> > > + { 0x2110d1, 0x0 },
> > > + { 0x111d1, 0x0 },
> > > + { 0x1111d1, 0x0 },
> > > + { 0x2111d1, 0x0 },
> > > + { 0x120d1, 0x0 },
> > > + { 0x1120d1, 0x0 },
> > > + { 0x2120d1, 0x0 },
> > > + { 0x121d1, 0x0 },
> > > + { 0x1121d1, 0x0 },
> > > + { 0x2121d1, 0x0 },
> > > + { 0x130d1, 0x0 },
> > > + { 0x1130d1, 0x0 },
> > > + { 0x2130d1, 0x0 },
> > > + { 0x131d1, 0x0 },
> > > + { 0x1131d1, 0x0 },
> > > + { 0x2131d1, 0x0 },
> > > + { 0x10068, 0x0 },
> > > + { 0x10168, 0x0 },
> > > + { 0x10268, 0x0 },
> > > + { 0x10368, 0x0 },
> > > + { 0x10468, 0x0 },
> > > + { 0x10568, 0x0 },
> > > + { 0x10668, 0x0 },
> > > + { 0x10768, 0x0 },
> > > + { 0x10868, 0x0 },
> > > + { 0x11068, 0x0 },
> > > + { 0x11168, 0x0 },
> > > + { 0x11268, 0x0 },
> > > + { 0x11368, 0x0 },
> > > + { 0x11468, 0x0 },
> > > + { 0x11568, 0x0 },
> > > + { 0x11668, 0x0 },
> > > + { 0x11768, 0x0 },
> > > + { 0x11868, 0x0 },
> > > + { 0x12068, 0x0 },
> > > + { 0x12168, 0x0 },
> > > + { 0x12268, 0x0 },
> > > + { 0x12368, 0x0 },
> > > + { 0x12468, 0x0 },
> > > + { 0x12568, 0x0 },
> > > + { 0x12668, 0x0 },
> > > + { 0x12768, 0x0 },
> > > + { 0x12868, 0x0 },
> > > + { 0x13068, 0x0 },
> > > + { 0x13168, 0x0 },
> > > + { 0x13268, 0x0 },
> > > + { 0x13368, 0x0 },
> > > + { 0x13468, 0x0 },
> > > + { 0x13568, 0x0 },
> > > + { 0x13668, 0x0 },
> > > + { 0x13768, 0x0 },
> > > + { 0x13868, 0x0 },
> > > + { 0x10069, 0x0 },
> > > + { 0x10169, 0x0 },
> > > + { 0x10269, 0x0 },
> > > + { 0x10369, 0x0 },
> > > + { 0x10469, 0x0 },
> > > + { 0x10569, 0x0 },
> > > + { 0x10669, 0x0 },
> > > + { 0x10769, 0x0 },
> > > + { 0x10869, 0x0 },
> > > + { 0x11069, 0x0 },
> > > + { 0x11169, 0x0 },
> > > + { 0x11269, 0x0 },
> > > + { 0x11369, 0x0 },
> > > + { 0x11469, 0x0 },
> > > + { 0x11569, 0x0 },
> > > + { 0x11669, 0x0 },
> > > + { 0x11769, 0x0 },
> > > + { 0x11869, 0x0 },
> > > + { 0x12069, 0x0 },
> > > + { 0x12169, 0x0 },
> > > + { 0x12269, 0x0 },
> > > + { 0x12369, 0x0 },
> > > + { 0x12469, 0x0 },
> > > + { 0x12569, 0x0 },
> > > + { 0x12669, 0x0 },
> > > + { 0x12769, 0x0 },
> > > + { 0x12869, 0x0 },
> > > + { 0x13069, 0x0 },
> > > + { 0x13169, 0x0 },
> > > + { 0x13269, 0x0 },
> > > + { 0x13369, 0x0 },
> > > + { 0x13469, 0x0 },
> > > + { 0x13569, 0x0 },
> > > + { 0x13669, 0x0 },
> > > + { 0x13769, 0x0 },
> > > + { 0x13869, 0x0 },
> > > + { 0x1008c, 0x0 },
> > > + { 0x11008c, 0x0 },
> > > + { 0x21008c, 0x0 },
> > > + { 0x1018c, 0x0 },
> > > + { 0x11018c, 0x0 },
> > > + { 0x21018c, 0x0 },
> > > + { 0x1108c, 0x0 },
> > > + { 0x11108c, 0x0 },
> > > + { 0x21108c, 0x0 },
> > > + { 0x1118c, 0x0 },
> > > + { 0x11118c, 0x0 },
> > > + { 0x21118c, 0x0 },
> > > + { 0x1208c, 0x0 },
> > > + { 0x11208c, 0x0 },
> > > + { 0x21208c, 0x0 },
> > > + { 0x1218c, 0x0 },
> > > + { 0x11218c, 0x0 },
> > > + { 0x21218c, 0x0 },
> > > + { 0x1308c, 0x0 },
> > > + { 0x11308c, 0x0 },
> > > + { 0x21308c, 0x0 },
> > > + { 0x1318c, 0x0 },
> > > + { 0x11318c, 0x0 },
> > > + { 0x21318c, 0x0 },
> > > + { 0x1008d, 0x0 },
> > > + { 0x11008d, 0x0 },
> > > + { 0x21008d, 0x0 },
> > > + { 0x1018d, 0x0 },
> > > + { 0x11018d, 0x0 },
> > > + { 0x21018d, 0x0 },
> > > + { 0x1108d, 0x0 },
> > > + { 0x11108d, 0x0 },
> > > + { 0x21108d, 0x0 },
> > > + { 0x1118d, 0x0 },
> > > + { 0x11118d, 0x0 },
> > > + { 0x21118d, 0x0 },
> > > + { 0x1208d, 0x0 },
> > > + { 0x11208d, 0x0 },
> > > + { 0x21208d, 0x0 },
> > > + { 0x1218d, 0x0 },
> > > + { 0x11218d, 0x0 },
> > > + { 0x21218d, 0x0 },
> > > + { 0x1308d, 0x0 },
> > > + { 0x11308d, 0x0 },
> > > + { 0x21308d, 0x0 },
> > > + { 0x1318d, 0x0 },
> > > + { 0x11318d, 0x0 },
> > > + { 0x21318d, 0x0 },
> > > + { 0x100c0, 0x0 },
> > > + { 0x1100c0, 0x0 },
> > > + { 0x2100c0, 0x0 },
> > > + { 0x101c0, 0x0 },
> > > + { 0x1101c0, 0x0 },
> > > + { 0x2101c0, 0x0 },
> > > + { 0x102c0, 0x0 },
> > > + { 0x1102c0, 0x0 },
> > > + { 0x2102c0, 0x0 },
> > > + { 0x103c0, 0x0 },
> > > + { 0x1103c0, 0x0 },
> > > + { 0x2103c0, 0x0 },
> > > + { 0x104c0, 0x0 },
> > > + { 0x1104c0, 0x0 },
> > > + { 0x2104c0, 0x0 },
> > > + { 0x105c0, 0x0 },
> > > + { 0x1105c0, 0x0 },
> > > + { 0x2105c0, 0x0 },
> > > + { 0x106c0, 0x0 },
> > > + { 0x1106c0, 0x0 },
> > > + { 0x2106c0, 0x0 },
> > > + { 0x107c0, 0x0 },
> > > + { 0x1107c0, 0x0 },
> > > + { 0x2107c0, 0x0 },
> > > + { 0x108c0, 0x0 },
> > > + { 0x1108c0, 0x0 },
> > > + { 0x2108c0, 0x0 },
> > > + { 0x110c0, 0x0 },
> > > + { 0x1110c0, 0x0 },
> > > + { 0x2110c0, 0x0 },
> > > + { 0x111c0, 0x0 },
> > > + { 0x1111c0, 0x0 },
> > > + { 0x2111c0, 0x0 },
> > > + { 0x112c0, 0x0 },
> > > + { 0x1112c0, 0x0 },
> > > + { 0x2112c0, 0x0 },
> > > + { 0x113c0, 0x0 },
> > > + { 0x1113c0, 0x0 },
> > > + { 0x2113c0, 0x0 },
> > > + { 0x114c0, 0x0 },
> > > + { 0x1114c0, 0x0 },
> > > + { 0x2114c0, 0x0 },
> > > + { 0x115c0, 0x0 },
> > > + { 0x1115c0, 0x0 },
> > > + { 0x2115c0, 0x0 },
> > > + { 0x116c0, 0x0 },
> > > + { 0x1116c0, 0x0 },
> > > + { 0x2116c0, 0x0 },
> > > + { 0x117c0, 0x0 },
> > > + { 0x1117c0, 0x0 },
> > > + { 0x2117c0, 0x0 },
> > > + { 0x118c0, 0x0 },
> > > + { 0x1118c0, 0x0 },
> > > + { 0x2118c0, 0x0 },
> > > + { 0x120c0, 0x0 },
> > > + { 0x1120c0, 0x0 },
> > > + { 0x2120c0, 0x0 },
> > > + { 0x121c0, 0x0 },
> > > + { 0x1121c0, 0x0 },
> > > + { 0x2121c0, 0x0 },
> > > + { 0x122c0, 0x0 },
> > > + { 0x1122c0, 0x0 },
> > > + { 0x2122c0, 0x0 },
> > > + { 0x123c0, 0x0 },
> > > + { 0x1123c0, 0x0 },
> > > + { 0x2123c0, 0x0 },
> > > + { 0x124c0, 0x0 },
> > > + { 0x1124c0, 0x0 },
> > > + { 0x2124c0, 0x0 },
> > > + { 0x125c0, 0x0 },
> > > + { 0x1125c0, 0x0 },
> > > + { 0x2125c0, 0x0 },
> > > + { 0x126c0, 0x0 },
> > > + { 0x1126c0, 0x0 },
> > > + { 0x2126c0, 0x0 },
> > > + { 0x127c0, 0x0 },
> > > + { 0x1127c0, 0x0 },
> > > + { 0x2127c0, 0x0 },
> > > + { 0x128c0, 0x0 },
> > > + { 0x1128c0, 0x0 },
> > > + { 0x2128c0, 0x0 },
> > > + { 0x130c0, 0x0 },
> > > + { 0x1130c0, 0x0 },
> > > + { 0x2130c0, 0x0 },
> > > + { 0x131c0, 0x0 },
> > > + { 0x1131c0, 0x0 },
> > > + { 0x2131c0, 0x0 },
> > > + { 0x132c0, 0x0 },
> > > + { 0x1132c0, 0x0 },
> > > + { 0x2132c0, 0x0 },
> > > + { 0x133c0, 0x0 },
> > > + { 0x1133c0, 0x0 },
> > > + { 0x2133c0, 0x0 },
> > > + { 0x134c0, 0x0 },
> > > + { 0x1134c0, 0x0 },
> > > + { 0x2134c0, 0x0 },
> > > + { 0x135c0, 0x0 },
> > > + { 0x1135c0, 0x0 },
> > > + { 0x2135c0, 0x0 },
> > > + { 0x136c0, 0x0 },
> > > + { 0x1136c0, 0x0 },
> > > + { 0x2136c0, 0x0 },
> > > + { 0x137c0, 0x0 },
> > > + { 0x1137c0, 0x0 },
> > > + { 0x2137c0, 0x0 },
> > > + { 0x138c0, 0x0 },
> > > + { 0x1138c0, 0x0 },
> > > + { 0x2138c0, 0x0 },
> > > + { 0x100c1, 0x0 },
> > > + { 0x1100c1, 0x0 },
> > > + { 0x2100c1, 0x0 },
> > > + { 0x101c1, 0x0 },
> > > + { 0x1101c1, 0x0 },
> > > + { 0x2101c1, 0x0 },
> > > + { 0x102c1, 0x0 },
> > > + { 0x1102c1, 0x0 },
> > > + { 0x2102c1, 0x0 },
> > > + { 0x103c1, 0x0 },
> > > + { 0x1103c1, 0x0 },
> > > + { 0x2103c1, 0x0 },
> > > + { 0x104c1, 0x0 },
> > > + { 0x1104c1, 0x0 },
> > > + { 0x2104c1, 0x0 },
> > > + { 0x105c1, 0x0 },
> > > + { 0x1105c1, 0x0 },
> > > + { 0x2105c1, 0x0 },
> > > + { 0x106c1, 0x0 },
> > > + { 0x1106c1, 0x0 },
> > > + { 0x2106c1, 0x0 },
> > > + { 0x107c1, 0x0 },
> > > + { 0x1107c1, 0x0 },
> > > + { 0x2107c1, 0x0 },
> > > + { 0x108c1, 0x0 },
> > > + { 0x1108c1, 0x0 },
> > > + { 0x2108c1, 0x0 },
> > > + { 0x110c1, 0x0 },
> > > + { 0x1110c1, 0x0 },
> > > + { 0x2110c1, 0x0 },
> > > + { 0x111c1, 0x0 },
> > > + { 0x1111c1, 0x0 },
> > > + { 0x2111c1, 0x0 },
> > > + { 0x112c1, 0x0 },
> > > + { 0x1112c1, 0x0 },
> > > + { 0x2112c1, 0x0 },
> > > + { 0x113c1, 0x0 },
> > > + { 0x1113c1, 0x0 },
> > > + { 0x2113c1, 0x0 },
> > > + { 0x114c1, 0x0 },
> > > + { 0x1114c1, 0x0 },
> > > + { 0x2114c1, 0x0 },
> > > + { 0x115c1, 0x0 },
> > > + { 0x1115c1, 0x0 },
> > > + { 0x2115c1, 0x0 },
> > > + { 0x116c1, 0x0 },
> > > + { 0x1116c1, 0x0 },
> > > + { 0x2116c1, 0x0 },
> > > + { 0x117c1, 0x0 },
> > > + { 0x1117c1, 0x0 },
> > > + { 0x2117c1, 0x0 },
> > > + { 0x118c1, 0x0 },
> > > + { 0x1118c1, 0x0 },
> > > + { 0x2118c1, 0x0 },
> > > + { 0x120c1, 0x0 },
> > > + { 0x1120c1, 0x0 },
> > > + { 0x2120c1, 0x0 },
> > > + { 0x121c1, 0x0 },
> > > + { 0x1121c1, 0x0 },
> > > + { 0x2121c1, 0x0 },
> > > + { 0x122c1, 0x0 },
> > > + { 0x1122c1, 0x0 },
> > > + { 0x2122c1, 0x0 },
> > > + { 0x123c1, 0x0 },
> > > + { 0x1123c1, 0x0 },
> > > + { 0x2123c1, 0x0 },
> > > + { 0x124c1, 0x0 },
> > > + { 0x1124c1, 0x0 },
> > > + { 0x2124c1, 0x0 },
> > > + { 0x125c1, 0x0 },
> > > + { 0x1125c1, 0x0 },
> > > + { 0x2125c1, 0x0 },
> > > + { 0x126c1, 0x0 },
> > > + { 0x1126c1, 0x0 },
> > > + { 0x2126c1, 0x0 },
> > > + { 0x127c1, 0x0 },
> > > + { 0x1127c1, 0x0 },
> > > + { 0x2127c1, 0x0 },
> > > + { 0x128c1, 0x0 },
> > > + { 0x1128c1, 0x0 },
> > > + { 0x2128c1, 0x0 },
> > > + { 0x130c1, 0x0 },
> > > + { 0x1130c1, 0x0 },
> > > + { 0x2130c1, 0x0 },
> > > + { 0x131c1, 0x0 },
> > > + { 0x1131c1, 0x0 },
> > > + { 0x2131c1, 0x0 },
> > > + { 0x132c1, 0x0 },
> > > + { 0x1132c1, 0x0 },
> > > + { 0x2132c1, 0x0 },
> > > + { 0x133c1, 0x0 },
> > > + { 0x1133c1, 0x0 },
> > > + { 0x2133c1, 0x0 },
> > > + { 0x134c1, 0x0 },
> > > + { 0x1134c1, 0x0 },
> > > + { 0x2134c1, 0x0 },
> > > + { 0x135c1, 0x0 },
> > > + { 0x1135c1, 0x0 },
> > > + { 0x2135c1, 0x0 },
> > > + { 0x136c1, 0x0 },
> > > + { 0x1136c1, 0x0 },
> > > + { 0x2136c1, 0x0 },
> > > + { 0x137c1, 0x0 },
> > > + { 0x1137c1, 0x0 },
> > > + { 0x2137c1, 0x0 },
> > > + { 0x138c1, 0x0 },
> > > + { 0x1138c1, 0x0 },
> > > + { 0x2138c1, 0x0 },
> > > + { 0x10020, 0x0 },
> > > + { 0x110020, 0x0 },
> > > + { 0x210020, 0x0 },
> > > + { 0x11020, 0x0 },
> > > + { 0x111020, 0x0 },
> > > + { 0x211020, 0x0 },
> > > + { 0x12020, 0x0 },
> > > + { 0x112020, 0x0 },
> > > + { 0x212020, 0x0 },
> > > + { 0x13020, 0x0 },
> > > + { 0x113020, 0x0 },
> > > + { 0x213020, 0x0 },
> > > + { 0x20072, 0x0 },
> > > + { 0x20073, 0x0 },
> > > + { 0x20074, 0x0 },
> > > + { 0x100aa, 0x0 },
> > > + { 0x110aa, 0x0 },
> > > + { 0x120aa, 0x0 },
> > > + { 0x130aa, 0x0 },
> > > + { 0x20010, 0x0 },
> > > + { 0x120010, 0x0 },
> > > + { 0x220010, 0x0 },
> > > + { 0x20011, 0x0 },
> > > + { 0x120011, 0x0 },
> > > + { 0x220011, 0x0 },
> > > + { 0x100ae, 0x0 },
> > > + { 0x1100ae, 0x0 },
> > > + { 0x2100ae, 0x0 },
> > > + { 0x100af, 0x0 },
> > > + { 0x1100af, 0x0 },
> > > + { 0x2100af, 0x0 },
> > > + { 0x110ae, 0x0 },
> > > + { 0x1110ae, 0x0 },
> > > + { 0x2110ae, 0x0 },
> > > + { 0x110af, 0x0 },
> > > + { 0x1110af, 0x0 },
> > > + { 0x2110af, 0x0 },
> > > + { 0x120ae, 0x0 },
> > > + { 0x1120ae, 0x0 },
> > > + { 0x2120ae, 0x0 },
> > > + { 0x120af, 0x0 },
> > > + { 0x1120af, 0x0 },
> > > + { 0x2120af, 0x0 },
> > > + { 0x130ae, 0x0 },
> > > + { 0x1130ae, 0x0 },
> > > + { 0x2130ae, 0x0 },
> > > + { 0x130af, 0x0 },
> > > + { 0x1130af, 0x0 },
> > > + { 0x2130af, 0x0 },
> > > + { 0x20020, 0x0 },
> > > + { 0x120020, 0x0 },
> > > + { 0x220020, 0x0 },
> > > + { 0x100a0, 0x0 },
> > > + { 0x100a1, 0x0 },
> > > + { 0x100a2, 0x0 },
> > > + { 0x100a3, 0x0 },
> > > + { 0x100a4, 0x0 },
> > > + { 0x100a5, 0x0 },
> > > + { 0x100a6, 0x0 },
> > > + { 0x100a7, 0x0 },
> > > + { 0x110a0, 0x0 },
> > > + { 0x110a1, 0x0 },
> > > + { 0x110a2, 0x0 },
> > > + { 0x110a3, 0x0 },
> > > + { 0x110a4, 0x0 },
> > > + { 0x110a5, 0x0 },
> > > + { 0x110a6, 0x0 },
> > > + { 0x110a7, 0x0 },
> > > + { 0x120a0, 0x0 },
> > > + { 0x120a1, 0x0 },
> > > + { 0x120a2, 0x0 },
> > > + { 0x120a3, 0x0 },
> > > + { 0x120a4, 0x0 },
> > > + { 0x120a5, 0x0 },
> > > + { 0x120a6, 0x0 },
> > > + { 0x120a7, 0x0 },
> > > + { 0x130a0, 0x0 },
> > > + { 0x130a1, 0x0 },
> > > + { 0x130a2, 0x0 },
> > > + { 0x130a3, 0x0 },
> > > + { 0x130a4, 0x0 },
> > > + { 0x130a5, 0x0 },
> > > + { 0x130a6, 0x0 },
> > > + { 0x130a7, 0x0 },
> > > + { 0x2007c, 0x0 },
> > > + { 0x12007c, 0x0 },
> > > + { 0x22007c, 0x0 },
> > > + { 0x2007d, 0x0 },
> > > + { 0x12007d, 0x0 },
> > > + { 0x22007d, 0x0 },
> > > + { 0x400fd, 0x0 },
> > > + { 0x400c0, 0x0 },
> > > + { 0x90201, 0x0 },
> > > + { 0x190201, 0x0 },
> > > + { 0x290201, 0x0 },
> > > + { 0x90202, 0x0 },
> > > + { 0x190202, 0x0 },
> > > + { 0x290202, 0x0 },
> > > + { 0x90203, 0x0 },
> > > + { 0x190203, 0x0 },
> > > + { 0x290203, 0x0 },
> > > + { 0x90204, 0x0 },
> > > + { 0x190204, 0x0 },
> > > + { 0x290204, 0x0 },
> > > + { 0x90205, 0x0 },
> > > + { 0x190205, 0x0 },
> > > + { 0x290205, 0x0 },
> > > + { 0x90206, 0x0 },
> > > + { 0x190206, 0x0 },
> > > + { 0x290206, 0x0 },
> > > + { 0x90207, 0x0 },
> > > + { 0x190207, 0x0 },
> > > + { 0x290207, 0x0 },
> > > + { 0x90208, 0x0 },
> > > + { 0x190208, 0x0 },
> > > + { 0x290208, 0x0 },
> > > + { 0x10062, 0x0 },
> > > + { 0x10162, 0x0 },
> > > + { 0x10262, 0x0 },
> > > + { 0x10362, 0x0 },
> > > + { 0x10462, 0x0 },
> > > + { 0x10562, 0x0 },
> > > + { 0x10662, 0x0 },
> > > + { 0x10762, 0x0 },
> > > + { 0x10862, 0x0 },
> > > + { 0x11062, 0x0 },
> > > + { 0x11162, 0x0 },
> > > + { 0x11262, 0x0 },
> > > + { 0x11362, 0x0 },
> > > + { 0x11462, 0x0 },
> > > + { 0x11562, 0x0 },
> > > + { 0x11662, 0x0 },
> > > + { 0x11762, 0x0 },
> > > + { 0x11862, 0x0 },
> > > + { 0x12062, 0x0 },
> > > + { 0x12162, 0x0 },
> > > + { 0x12262, 0x0 },
> > > + { 0x12362, 0x0 },
> > > + { 0x12462, 0x0 },
> > > + { 0x12562, 0x0 },
> > > + { 0x12662, 0x0 },
> > > + { 0x12762, 0x0 },
> > > + { 0x12862, 0x0 },
> > > + { 0x13062, 0x0 },
> > > + { 0x13162, 0x0 },
> > > + { 0x13262, 0x0 },
> > > + { 0x13362, 0x0 },
> > > + { 0x13462, 0x0 },
> > > + { 0x13562, 0x0 },
> > > + { 0x13662, 0x0 },
> > > + { 0x13762, 0x0 },
> > > + { 0x13862, 0x0 },
> > > + { 0x20077, 0x0 },
> > > + { 0x10001, 0x0 },
> > > + { 0x11001, 0x0 },
> > > + { 0x12001, 0x0 },
> > > + { 0x13001, 0x0 },
> > > + { 0x10040, 0x0 },
> > > + { 0x10140, 0x0 },
> > > + { 0x10240, 0x0 },
> > > + { 0x10340, 0x0 },
> > > + { 0x10440, 0x0 },
> > > + { 0x10540, 0x0 },
> > > + { 0x10640, 0x0 },
> > > + { 0x10740, 0x0 },
> > > + { 0x10840, 0x0 },
> > > + { 0x10030, 0x0 },
> > > + { 0x10130, 0x0 },
> > > + { 0x10230, 0x0 },
> > > + { 0x10330, 0x0 },
> > > + { 0x10430, 0x0 },
> > > + { 0x10530, 0x0 },
> > > + { 0x10630, 0x0 },
> > > + { 0x10730, 0x0 },
> > > + { 0x10830, 0x0 },
> > > + { 0x11040, 0x0 },
> > > + { 0x11140, 0x0 },
> > > + { 0x11240, 0x0 },
> > > + { 0x11340, 0x0 },
> > > + { 0x11440, 0x0 },
> > > + { 0x11540, 0x0 },
> > > + { 0x11640, 0x0 },
> > > + { 0x11740, 0x0 },
> > > + { 0x11840, 0x0 },
> > > + { 0x11030, 0x0 },
> > > + { 0x11130, 0x0 },
> > > + { 0x11230, 0x0 },
> > > + { 0x11330, 0x0 },
> > > + { 0x11430, 0x0 },
> > > + { 0x11530, 0x0 },
> > > + { 0x11630, 0x0 },
> > > + { 0x11730, 0x0 },
> > > + { 0x11830, 0x0 },
> > > + { 0x12040, 0x0 },
> > > + { 0x12140, 0x0 },
> > > + { 0x12240, 0x0 },
> > > + { 0x12340, 0x0 },
> > > + { 0x12440, 0x0 },
> > > + { 0x12540, 0x0 },
> > > + { 0x12640, 0x0 },
> > > + { 0x12740, 0x0 },
> > > + { 0x12840, 0x0 },
> > > + { 0x12030, 0x0 },
> > > + { 0x12130, 0x0 },
> > > + { 0x12230, 0x0 },
> > > + { 0x12330, 0x0 },
> > > + { 0x12430, 0x0 },
> > > + { 0x12530, 0x0 },
> > > + { 0x12630, 0x0 },
> > > + { 0x12730, 0x0 },
> > > + { 0x12830, 0x0 },
> > > + { 0x13040, 0x0 },
> > > + { 0x13140, 0x0 },
> > > + { 0x13240, 0x0 },
> > > + { 0x13340, 0x0 },
> > > + { 0x13440, 0x0 },
> > > + { 0x13540, 0x0 },
> > > + { 0x13640, 0x0 },
> > > + { 0x13740, 0x0 },
> > > + { 0x13840, 0x0 },
> > > + { 0x13030, 0x0 },
> > > + { 0x13130, 0x0 },
> > > + { 0x13230, 0x0 },
> > > + { 0x13330, 0x0 },
> > > + { 0x13430, 0x0 },
> > > + { 0x13530, 0x0 },
> > > + { 0x13630, 0x0 },
> > > + { 0x13730, 0x0 },
> > > + { 0x13830, 0x0 },
> > > +};
> >
> > The same as above. Please look into imx6q DDR3 training code.
> >
> > > +
> > > +/* P0 message block paremeter for training firmware */
> > > +struct dram_cfg_param lpddr4_fsp0_cfg[] = {
> > > + { 0xd0000, 0x0 },
> > > + { 0x54000, 0x0 },
> > > + { 0x54001, 0x0 },
> > > + { 0x54002, 0x0 },
> > > + { 0x54003, 0xbb8 },
> > > + { 0x54004, 0x2 },
> > > + { 0x54005, ((LPDDR4_PHY_RON << 8) |
> > > LPDDR4_PHY_RTT) },//PHY Ron/Rtt
> > > + { 0x54006, LPDDR4_PHY_VREF_VALUE },
> > > + { 0x54007, 0x0 },
> > > + { 0x54008, 0x131f },
> > > + { 0x54009, 0xc8 },
> > > + { 0x5400a, 0x0 },
> > > + { 0x5400b, 0x2 },
> > > + { 0x5400c, 0x0 },
> > > + { 0x5400d, 0x0 },
> > > + { 0x5400e, 0x0 },
> > > + { 0x5400f, 0x0 },
> > > + { 0x54010, 0x0 },
> > > + { 0x54011, 0x0 },
> > > + { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
> > > + { 0x54013, 0x0 },
> > > + { 0x54014, 0x0 },
> > > + { 0x54015, 0x0 },
> > > + { 0x54016, 0x0 },
> > > + { 0x54017, 0x0 },
> > > + { 0x54018, 0x0 },
> > > + { 0x54019, 0x2dd4 },
> > > + { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
> > > + { 0x5401b, 0x4d66 },
> > > + { 0x5401c, 0x4d08 },
> > > + { 0x5401d, 0x0 },
> > > + { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
> > > + { 0x5401f, 0x2dd4 },
> > > + { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
> > > + { 0x54021, 0x4d66 },
> > > + { 0x54022, 0x4d08 },
> > > + { 0x54023, 0x0 },
> > > + { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
> > > + { 0x54025, 0x0 },
> > > + { 0x54026, 0x0 },
> > > + { 0x54027, 0x0 },
> > > + { 0x54028, 0x0 },
> > > + { 0x54029, 0x0 },
> > > + { 0x5402a, 0x0 },
> > > + { 0x5402b, 0x1000 },
> > > + { 0x5402c, LPDDR4_CS },
> > > + { 0x5402d, 0x0 },
> > > + { 0x5402e, 0x0 },
> > > + { 0x5402f, 0x0 },
> > > + { 0x54030, 0x0 },
> > > + { 0x54031, 0x0 },
> > > + { 0x54032, 0xd400 },
> > > + { 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
> > > + { 0x54034, 0x6600 },
> > > + { 0x54035, 0x84d },
> > > + { 0x54036, 0x4d },
> > > + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
> > > + { 0x54038, 0xd400 },
> > > + { 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
> > > + { 0x5403a, 0x6600 },
> > > + { 0x5403b, 0x84d },
> > > + { 0x5403c, 0x4d },
> > > + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
> > > + { 0x5403e, 0x0 },
> > > + { 0x5403f, 0x0 },
> > > + { 0x54040, 0x0 },
> > > + { 0x54041, 0x0 },
> > > + { 0x54042, 0x0 },
> > > + { 0x54043, 0x0 },
> > > + { 0x54044, 0x0 },
> > > + { 0xd0000, 0x1 },
> > > +};
> > > +
> > > +/* P1 message block paremeter for training firmware */
> > > +struct dram_cfg_param lpddr4_fsp1_cfg[] = {
> > > + { 0xd0000, 0x0 },
> > > + { 0x54000, 0x0 },
> > > + { 0x54001, 0x0 },
> > > + { 0x54002, 0x101 },
> > > + { 0x54003, 0x190 },
> > > + { 0x54004, 0x2 },
> > > + { 0x54005, ((LPDDR4_PHY_RON << 8) |
> > > LPDDR4_PHY_RTT) },//PHY Ron/Rtt
> > > + { 0x54006, LPDDR4_PHY_VREF_VALUE },
> > > + { 0x54007, 0x0 },
> > > + { 0x54008, 0x121f },
> > > + { 0x54009, 0xc8 },
> > > + { 0x5400a, 0x0 },
> > > + { 0x5400b, 0x2 },
> > > + { 0x5400c, 0x0 },
> > > + { 0x5400d, 0x0 },
> > > + { 0x5400e, 0x0 },
> > > + { 0x5400f, 0x0 },
> > > + { 0x54010, 0x0 },
> > > + { 0x54011, 0x0 },
> > > + { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
> > > + { 0x54013, 0x0 },
> > > + { 0x54014, 0x0 },
> > > + { 0x54015, 0x0 },
> > > + { 0x54016, 0x0 },
> > > + { 0x54017, 0x0 },
> > > + { 0x54018, 0x0 },
> > > + { 0x54019, 0x84 },
> > > + { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
> > > + { 0x5401b, 0x4d66 },
> > > + { 0x5401c, 0x4d08 },
> > > + { 0x5401d, 0x0 },
> > > + { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
> > > + { 0x5401f, 0x84 },
> > > + { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
> > > + { 0x54021, 0x4d66 },
> > > + { 0x54022, 0x4d08 },
> > > + { 0x54023, 0x0 },
> > > + { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
> > > + { 0x54025, 0x0 },
> > > + { 0x54026, 0x0 },
> > > + { 0x54027, 0x0 },
> > > + { 0x54028, 0x0 },
> > > + { 0x54029, 0x0 },
> > > + { 0x5402a, 0x0 },
> > > + { 0x5402b, 0x1000 },
> > > + { 0x5402c, LPDDR4_CS },
> > > + { 0x5402d, 0x0 },
> > > + { 0x5402e, 0x0 },
> > > + { 0x5402f, 0x0 },
> > > + { 0x54030, 0x0 },
> > > + { 0x54031, 0x0 },
> > > + { 0x54032, 0x8400 },
> > > + { 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
> > > + { 0x54034, 0x6600 },
> > > + { 0x54035, 0x84d },
> > > + { 0x54036, 0x4d },
> > > + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
> > > + { 0x54038, 0x8400 },
> > > + { 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
> > > + { 0x5403a, 0x6600 },
> > > + { 0x5403b, 0x84d },
> > > + { 0x5403c, 0x4d },
> > > + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
> > > + { 0x5403e, 0x0 },
> > > + { 0x5403f, 0x0 },
> > > + { 0x54040, 0x0 },
> > > + { 0x54041, 0x0 },
> > > + { 0x54042, 0x0 },
> > > + { 0x54043, 0x0 },
> > > + { 0x54044, 0x0 },
> > > + { 0xd0000, 0x1 },
> > > +};
> > > +
> > > +/* P1 message block paremeter for training firmware */
> > > +struct dram_cfg_param lpddr4_fsp2_cfg[] = {
> > > + { 0xd0000, 0x0 },
> > > + { 0x54000, 0x0 },
> > > + { 0x54001, 0x0 },
> > > + { 0x54002, 0x102 },
> > > + { 0x54003, 0x64 },
> > > + { 0x54004, 0x2 },
> > > + { 0x54005, ((LPDDR4_PHY_RON << 8) |
> > > LPDDR4_PHY_RTT) },//PHY Ron/Rtt
> > > + { 0x54006, LPDDR4_PHY_VREF_VALUE },
> > > + { 0x54007, 0x0 },
> > > + { 0x54008, 0x121f },
> > > + { 0x54009, 0xc8 },
> > > + { 0x5400a, 0x0 },
> > > + { 0x5400b, 0x2 },
> > > + { 0x5400c, 0x0 },
> > > + { 0x5400d, 0x0 },
> > > + { 0x5400e, 0x0 },
> > > + { 0x5400f, 0x0 },
> > > + { 0x54010, 0x0 },
> > > + { 0x54011, 0x0 },
> > > + { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
> > > + { 0x54013, 0x0 },
> > > + { 0x54014, 0x0 },
> > > + { 0x54015, 0x0 },
> > > + { 0x54016, 0x0 },
> > > + { 0x54017, 0x0 },
> > > + { 0x54018, 0x0 },
> > > + { 0x54019, 0x84 },
> > > + { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
> > > + { 0x5401b, 0x4d66 },
> > > + { 0x5401c, 0x4d08 },
> > > + { 0x5401d, 0x0 },
> > > + { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
> > > + { 0x5401f, 0x84 },
> > > + { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
> > > + { 0x54021, 0x4d66 },
> > > + { 0x54022, 0x4d08 },
> > > + { 0x54023, 0x0 },
> > > + { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
> > > + { 0x54025, 0x0 },
> > > + { 0x54026, 0x0 },
> > > + { 0x54027, 0x0 },
> > > + { 0x54028, 0x0 },
> > > + { 0x54029, 0x0 },
> > > + { 0x5402a, 0x0 },
> > > + { 0x5402b, 0x1000 },
> > > + { 0x5402c, LPDDR4_CS },
> > > + { 0x5402d, 0x0 },
> > > + { 0x5402e, 0x0 },
> > > + { 0x5402f, 0x0 },
> > > + { 0x54030, 0x0 },
> > > + { 0x54031, 0x0 },
> > > + { 0x54032, 0x8400 },
> > > + { 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
> > > + { 0x54034, 0x6600 },
> > > + { 0x54035, 0x84d },
> > > + { 0x54036, 0x4d },
> > > + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
> > > + { 0x54038, 0x8400 },
> > > + { 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
> > > + { 0x5403a, 0x6600 },
> > > + { 0x5403b, 0x84d },
> > > + { 0x5403c, 0x4d },
> > > + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
> > > + { 0x5403e, 0x0 },
> > > + { 0x5403f, 0x0 },
> > > + { 0x54040, 0x0 },
> > > + { 0x54041, 0x0 },
> > > + { 0x54042, 0x0 },
> > > + { 0x54043, 0x0 },
> > > + { 0x54044, 0x0 },
> > > + { 0xd0000, 0x1 },
> > > +};
> > > +
> > > +/* P0 2D message block paremeter for training firmware */
> > > +struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
> > > + { 0xd0000, 0x0 },
> > > + { 0x54000, 0x0 },
> > > + { 0x54001, 0x0 },
> > > + { 0x54002, 0x0 },
> > > + { 0x54003, 0xbb8 },
> > > + { 0x54004, 0x2 },
> > > + { 0x54005, ((LPDDR4_PHY_RON << 8) |
> > > LPDDR4_PHY_RTT) },//PHY Ron/Rtt
> > > + { 0x54006, LPDDR4_PHY_VREF_VALUE },
> > > + { 0x54007, 0x0 },
> > > + { 0x54008, 0x61 },
> > > + { 0x54009, 0xc8 },
> > > + { 0x5400a, 0x0 },
> > > + { 0x5400b, 0x2 },
> > > + { 0x5400c, 0x0 },
> > > + { 0x5400d, 0x0 },
> > > + { 0x5400e, 0x0 },
> > > + { 0x5400f, 0x100 },
> > > + { 0x54010, 0x1f7f },
> > > + { 0x54011, 0x0 },
> > > + { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
> > > + { 0x54013, 0x0 },
> > > + { 0x54014, 0x0 },
> > > + { 0x54015, 0x0 },
> > > + { 0x54016, 0x0 },
> > > + { 0x54017, 0x0 },
> > > + { 0x54018, 0x0 },
> > > + { 0x54019, 0x2dd4 },
> > > + { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
> > > + { 0x5401b, 0x4d66 },
> > > + { 0x5401c, 0x4d08 },
> > > + { 0x5401d, 0x0 },
> > > + { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
> > > + { 0x5401f, 0x2dd4 },
> > > + { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
> > > + { 0x54021, 0x4d66 },
> > > + { 0x54022, 0x4d08 },
> > > + { 0x54023, 0x0 },
> > > + { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
> > > + { 0x54025, 0x0 },
> > > + { 0x54026, 0x0 },
> > > + { 0x54027, 0x0 },
> > > + { 0x54028, 0x0 },
> > > + { 0x54029, 0x0 },
> > > + { 0x5402a, 0x0 },
> > > + { 0x5402b, 0x1000 },
> > > + { 0x5402c, LPDDR4_CS },
> > > + { 0x5402d, 0x0 },
> > > + { 0x5402e, 0x0 },
> > > + { 0x5402f, 0x0 },
> > > + { 0x54030, 0x0 },
> > > + { 0x54031, 0x0 },
> > > + { 0x54032, 0xd400 },
> > > + { 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
> > > + { 0x54034, 0x6600 },
> > > + { 0x54035, 0x84d },
> > > + { 0x54036, 0x4d },
> > > + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
> > > + { 0x54038, 0xd400 },
> > > + { 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
> > > + { 0x5403a, 0x6600 },
> > > + { 0x5403b, 0x84d },
> > > + { 0x5403c, 0x4d },
> > > + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
> > > + { 0x5403e, 0x0 },
> > > + { 0x5403f, 0x0 },
> > > + { 0x54040, 0x0 },
> > > + { 0x54041, 0x0 },
> > > + { 0x54042, 0x0 },
> > > + { 0x54043, 0x0 },
> > > + { 0x54044, 0x0 },
> > > + { 0xd0000, 0x1 },
> > > +};
> > > +
> > > +/* DRAM PHY init engine image */
> > > +struct dram_cfg_param lpddr4_phy_pie[] = {
> > > + { 0xd0000, 0x0 },
> > > + { 0x90000, 0x10 },
> > > + { 0x90001, 0x400 },
> > > + { 0x90002, 0x10e },
> > > + { 0x90003, 0x0 },
> > > + { 0x90004, 0x0 },
> > > + { 0x90005, 0x8 },
> > > + { 0x90029, 0xb },
> > > + { 0x9002a, 0x480 },
> > > + { 0x9002b, 0x109 },
> > > + { 0x9002c, 0x8 },
> > > + { 0x9002d, 0x448 },
> > > + { 0x9002e, 0x139 },
> > > + { 0x9002f, 0x8 },
> > > + { 0x90030, 0x478 },
> > > + { 0x90031, 0x109 },
> > > + { 0x90032, 0x0 },
> > > + { 0x90033, 0xe8 },
> > > + { 0x90034, 0x109 },
> > > + { 0x90035, 0x2 },
> > > + { 0x90036, 0x10 },
> > > + { 0x90037, 0x139 },
> > > + { 0x90038, 0xf },
> > > + { 0x90039, 0x7c0 },
> > > + { 0x9003a, 0x139 },
> > > + { 0x9003b, 0x44 },
> > > + { 0x9003c, 0x630 },
> > > + { 0x9003d, 0x159 },
> > > + { 0x9003e, 0x14f },
> > > + { 0x9003f, 0x630 },
> > > + { 0x90040, 0x159 },
> > > + { 0x90041, 0x47 },
> > > + { 0x90042, 0x630 },
> > > + { 0x90043, 0x149 },
> > > + { 0x90044, 0x4f },
> > > + { 0x90045, 0x630 },
> > > + { 0x90046, 0x179 },
> > > + { 0x90047, 0x8 },
> > > + { 0x90048, 0xe0 },
> > > + { 0x90049, 0x109 },
> > > + { 0x9004a, 0x0 },
> > > + { 0x9004b, 0x7c8 },
> > > + { 0x9004c, 0x109 },
> > > + { 0x9004d, 0x0 },
> > > + { 0x9004e, 0x1 },
> > > + { 0x9004f, 0x8 },
> > > + { 0x90050, 0x0 },
> > > + { 0x90051, 0x45a },
> > > + { 0x90052, 0x9 },
> > > + { 0x90053, 0x0 },
> > > + { 0x90054, 0x448 },
> > > + { 0x90055, 0x109 },
> > > + { 0x90056, 0x40 },
> > > + { 0x90057, 0x630 },
> > > + { 0x90058, 0x179 },
> > > + { 0x90059, 0x1 },
> > > + { 0x9005a, 0x618 },
> > > + { 0x9005b, 0x109 },
> > > + { 0x9005c, 0x40c0 },
> > > + { 0x9005d, 0x630 },
> > > + { 0x9005e, 0x149 },
> > > + { 0x9005f, 0x8 },
> > > + { 0x90060, 0x4 },
> > > + { 0x90061, 0x48 },
> > > + { 0x90062, 0x4040 },
> > > + { 0x90063, 0x630 },
> > > + { 0x90064, 0x149 },
> > > + { 0x90065, 0x0 },
> > > + { 0x90066, 0x4 },
> > > + { 0x90067, 0x48 },
> > > + { 0x90068, 0x40 },
> > > + { 0x90069, 0x630 },
> > > + { 0x9006a, 0x149 },
> > > + { 0x9006b, 0x10 },
> > > + { 0x9006c, 0x4 },
> > > + { 0x9006d, 0x18 },
> > > + { 0x9006e, 0x0 },
> > > + { 0x9006f, 0x4 },
> > > + { 0x90070, 0x78 },
> > > + { 0x90071, 0x549 },
> > > + { 0x90072, 0x630 },
> > > + { 0x90073, 0x159 },
> > > + { 0x90074, 0xd49 },
> > > + { 0x90075, 0x630 },
> > > + { 0x90076, 0x159 },
> > > + { 0x90077, 0x94a },
> > > + { 0x90078, 0x630 },
> > > + { 0x90079, 0x159 },
> > > + { 0x9007a, 0x441 },
> > > + { 0x9007b, 0x630 },
> > > + { 0x9007c, 0x149 },
> > > + { 0x9007d, 0x42 },
> > > + { 0x9007e, 0x630 },
> > > + { 0x9007f, 0x149 },
> > > + { 0x90080, 0x1 },
> > > + { 0x90081, 0x630 },
> > > + { 0x90082, 0x149 },
> > > + { 0x90083, 0x0 },
> > > + { 0x90084, 0xe0 },
> > > + { 0x90085, 0x109 },
> > > + { 0x90086, 0xa },
> > > + { 0x90087, 0x10 },
> > > + { 0x90088, 0x109 },
> > > + { 0x90089, 0x9 },
> > > + { 0x9008a, 0x3c0 },
> > > + { 0x9008b, 0x149 },
> > > + { 0x9008c, 0x9 },
> > > + { 0x9008d, 0x3c0 },
> > > + { 0x9008e, 0x159 },
> > > + { 0x9008f, 0x18 },
> > > + { 0x90090, 0x10 },
> > > + { 0x90091, 0x109 },
> > > + { 0x90092, 0x0 },
> > > + { 0x90093, 0x3c0 },
> > > + { 0x90094, 0x109 },
> > > + { 0x90095, 0x18 },
> > > + { 0x90096, 0x4 },
> > > + { 0x90097, 0x48 },
> > > + { 0x90098, 0x18 },
> > > + { 0x90099, 0x4 },
> > > + { 0x9009a, 0x58 },
> > > + { 0x9009b, 0xa },
> > > + { 0x9009c, 0x10 },
> > > + { 0x9009d, 0x109 },
> > > + { 0x9009e, 0x2 },
> > > + { 0x9009f, 0x10 },
> > > + { 0x900a0, 0x109 },
> > > + { 0x900a1, 0x5 },
> > > + { 0x900a2, 0x7c0 },
> > > + { 0x900a3, 0x109 },
> > > + { 0x900a4, 0x10 },
> > > + { 0x900a5, 0x10 },
> > > + { 0x900a6, 0x109 },
> > > + { 0x40000, 0x811 },
> > > + { 0x40020, 0x880 },
> > > + { 0x40040, 0x0 },
> > > + { 0x40060, 0x0 },
> > > + { 0x40001, 0x4008 },
> > > + { 0x40021, 0x83 },
> > > + { 0x40041, 0x4f },
> > > + { 0x40061, 0x0 },
> > > + { 0x40002, 0x4040 },
> > > + { 0x40022, 0x83 },
> > > + { 0x40042, 0x51 },
> > > + { 0x40062, 0x0 },
> > > + { 0x40003, 0x811 },
> > > + { 0x40023, 0x880 },
> > > + { 0x40043, 0x0 },
> > > + { 0x40063, 0x0 },
> > > + { 0x40004, 0x720 },
> > > + { 0x40024, 0xf },
> > > + { 0x40044, 0x1740 },
> > > + { 0x40064, 0x0 },
> > > + { 0x40005, 0x16 },
> > > + { 0x40025, 0x83 },
> > > + { 0x40045, 0x4b },
> > > + { 0x40065, 0x0 },
> > > + { 0x40006, 0x716 },
> > > + { 0x40026, 0xf },
> > > + { 0x40046, 0x2001 },
> > > + { 0x40066, 0x0 },
> > > + { 0x40007, 0x716 },
> > > + { 0x40027, 0xf },
> > > + { 0x40047, 0x2800 },
> > > + { 0x40067, 0x0 },
> > > + { 0x40008, 0x716 },
> > > + { 0x40028, 0xf },
> > > + { 0x40048, 0xf00 },
> > > + { 0x40068, 0x0 },
> > > + { 0x40009, 0x720 },
> > > + { 0x40029, 0xf },
> > > + { 0x40049, 0x1400 },
> > > + { 0x40069, 0x0 },
> > > + { 0x4000a, 0xe08 },
> > > + { 0x4002a, 0xc15 },
> > > + { 0x4004a, 0x0 },
> > > + { 0x4006a, 0x0 },
> > > + { 0x4000b, 0x623 },
> > > + { 0x4002b, 0x15 },
> > > + { 0x4004b, 0x0 },
> > > + { 0x4006b, 0x0 },
> > > + { 0x4000c, 0x4028 },
> > > + { 0x4002c, 0x80 },
> > > + { 0x4004c, 0x0 },
> > > + { 0x4006c, 0x0 },
> > > + { 0x4000d, 0xe08 },
> > > + { 0x4002d, 0xc1a },
> > > + { 0x4004d, 0x0 },
> > > + { 0x4006d, 0x0 },
> > > + { 0x4000e, 0x623 },
> > > + { 0x4002e, 0x1a },
> > > + { 0x4004e, 0x0 },
> > > + { 0x4006e, 0x0 },
> > > + { 0x4000f, 0x4040 },
> > > + { 0x4002f, 0x80 },
> > > + { 0x4004f, 0x0 },
> > > + { 0x4006f, 0x0 },
> > > + { 0x40010, 0x2604 },
> > > + { 0x40030, 0x15 },
> > > + { 0x40050, 0x0 },
> > > + { 0x40070, 0x0 },
> > > + { 0x40011, 0x708 },
> > > + { 0x40031, 0x5 },
> > > + { 0x40051, 0x0 },
> > > + { 0x40071, 0x2002 },
> > > + { 0x40012, 0x8 },
> > > + { 0x40032, 0x80 },
> > > + { 0x40052, 0x0 },
> > > + { 0x40072, 0x0 },
> > > + { 0x40013, 0x2604 },
> > > + { 0x40033, 0x1a },
> > > + { 0x40053, 0x0 },
> > > + { 0x40073, 0x0 },
> > > + { 0x40014, 0x708 },
> > > + { 0x40034, 0xa },
> > > + { 0x40054, 0x0 },
> > > + { 0x40074, 0x2002 },
> > > + { 0x40015, 0x4040 },
> > > + { 0x40035, 0x80 },
> > > + { 0x40055, 0x0 },
> > > + { 0x40075, 0x0 },
> > > + { 0x40016, 0x60a },
> > > + { 0x40036, 0x15 },
> > > + { 0x40056, 0x1200 },
> > > + { 0x40076, 0x0 },
> > > + { 0x40017, 0x61a },
> > > + { 0x40037, 0x15 },
> > > + { 0x40057, 0x1300 },
> > > + { 0x40077, 0x0 },
> > > + { 0x40018, 0x60a },
> > > + { 0x40038, 0x1a },
> > > + { 0x40058, 0x1200 },
> > > + { 0x40078, 0x0 },
> > > + { 0x40019, 0x642 },
> > > + { 0x40039, 0x1a },
> > > + { 0x40059, 0x1300 },
> > > + { 0x40079, 0x0 },
> > > + { 0x4001a, 0x4808 },
> > > + { 0x4003a, 0x880 },
> > > + { 0x4005a, 0x0 },
> > > + { 0x4007a, 0x0 },
> > > + { 0x900a7, 0x0 },
> > > + { 0x900a8, 0x790 },
> > > + { 0x900a9, 0x11a },
> > > + { 0x900aa, 0x8 },
> > > + { 0x900ab, 0x7aa },
> > > + { 0x900ac, 0x2a },
> > > + { 0x900ad, 0x10 },
> > > + { 0x900ae, 0x7b2 },
> > > + { 0x900af, 0x2a },
> > > + { 0x900b0, 0x0 },
> > > + { 0x900b1, 0x7c8 },
> > > + { 0x900b2, 0x109 },
> > > + { 0x900b3, 0x10 },
> > > + { 0x900b4, 0x2a8 },
> > > + { 0x900b5, 0x129 },
> > > + { 0x900b6, 0x8 },
> > > + { 0x900b7, 0x370 },
> > > + { 0x900b8, 0x129 },
> > > + { 0x900b9, 0xa },
> > > + { 0x900ba, 0x3c8 },
> > > + { 0x900bb, 0x1a9 },
> > > + { 0x900bc, 0xc },
> > > + { 0x900bd, 0x408 },
> > > + { 0x900be, 0x199 },
> > > + { 0x900bf, 0x14 },
> > > + { 0x900c0, 0x790 },
> > > + { 0x900c1, 0x11a },
> > > + { 0x900c2, 0x8 },
> > > + { 0x900c3, 0x4 },
> > > + { 0x900c4, 0x18 },
> > > + { 0x900c5, 0xe },
> > > + { 0x900c6, 0x408 },
> > > + { 0x900c7, 0x199 },
> > > + { 0x900c8, 0x8 },
> > > + { 0x900c9, 0x8568 },
> > > + { 0x900ca, 0x108 },
> > > + { 0x900cb, 0x18 },
> > > + { 0x900cc, 0x790 },
> > > + { 0x900cd, 0x16a },
> > > + { 0x900ce, 0x8 },
> > > + { 0x900cf, 0x1d8 },
> > > + { 0x900d0, 0x169 },
> > > + { 0x900d1, 0x10 },
> > > + { 0x900d2, 0x8558 },
> > > + { 0x900d3, 0x168 },
> > > + { 0x900d4, 0x70 },
> > > + { 0x900d5, 0x788 },
> > > + { 0x900d6, 0x16a },
> > > + { 0x900d7, 0x1ff8 },
> > > + { 0x900d8, 0x85a8 },
> > > + { 0x900d9, 0x1e8 },
> > > + { 0x900da, 0x50 },
> > > + { 0x900db, 0x798 },
> > > + { 0x900dc, 0x16a },
> > > + { 0x900dd, 0x60 },
> > > + { 0x900de, 0x7a0 },
> > > + { 0x900df, 0x16a },
> > > + { 0x900e0, 0x8 },
> > > + { 0x900e1, 0x8310 },
> > > + { 0x900e2, 0x168 },
> > > + { 0x900e3, 0x8 },
> > > + { 0x900e4, 0xa310 },
> > > + { 0x900e5, 0x168 },
> > > + { 0x900e6, 0xa },
> > > + { 0x900e7, 0x408 },
> > > + { 0x900e8, 0x169 },
> > > + { 0x900e9, 0x6e },
> > > + { 0x900ea, 0x0 },
> > > + { 0x900eb, 0x68 },
> > > + { 0x900ec, 0x0 },
> > > + { 0x900ed, 0x408 },
> > > + { 0x900ee, 0x169 },
> > > + { 0x900ef, 0x0 },
> > > + { 0x900f0, 0x8310 },
> > > + { 0x900f1, 0x168 },
> > > + { 0x900f2, 0x0 },
> > > + { 0x900f3, 0xa310 },
> > > + { 0x900f4, 0x168 },
> > > + { 0x900f5, 0x1ff8 },
> > > + { 0x900f6, 0x85a8 },
> > > + { 0x900f7, 0x1e8 },
> > > + { 0x900f8, 0x68 },
> > > + { 0x900f9, 0x798 },
> > > + { 0x900fa, 0x16a },
> > > + { 0x900fb, 0x78 },
> > > + { 0x900fc, 0x7a0 },
> > > + { 0x900fd, 0x16a },
> > > + { 0x900fe, 0x68 },
> > > + { 0x900ff, 0x790 },
> > > + { 0x90100, 0x16a },
> > > + { 0x90101, 0x8 },
> > > + { 0x90102, 0x8b10 },
> > > + { 0x90103, 0x168 },
> > > + { 0x90104, 0x8 },
> > > + { 0x90105, 0xab10 },
> > > + { 0x90106, 0x168 },
> > > + { 0x90107, 0xa },
> > > + { 0x90108, 0x408 },
> > > + { 0x90109, 0x169 },
> > > + { 0x9010a, 0x58 },
> > > + { 0x9010b, 0x0 },
> > > + { 0x9010c, 0x68 },
> > > + { 0x9010d, 0x0 },
> > > + { 0x9010e, 0x408 },
> > > + { 0x9010f, 0x169 },
> > > + { 0x90110, 0x0 },
> > > + { 0x90111, 0x8b10 },
> > > + { 0x90112, 0x168 },
> > > + { 0x90113, 0x0 },
> > > + { 0x90114, 0xab10 },
> > > + { 0x90115, 0x168 },
> > > + { 0x90116, 0x0 },
> > > + { 0x90117, 0x1d8 },
> > > + { 0x90118, 0x169 },
> > > + { 0x90119, 0x80 },
> > > + { 0x9011a, 0x790 },
> > > + { 0x9011b, 0x16a },
> > > + { 0x9011c, 0x18 },
> > > + { 0x9011d, 0x7aa },
> > > + { 0x9011e, 0x6a },
> > > + { 0x9011f, 0xa },
> > > + { 0x90120, 0x0 },
> > > + { 0x90121, 0x1e9 },
> > > + { 0x90122, 0x8 },
> > > + { 0x90123, 0x8080 },
> > > + { 0x90124, 0x108 },
> > > + { 0x90125, 0xf },
> > > + { 0x90126, 0x408 },
> > > + { 0x90127, 0x169 },
> > > + { 0x90128, 0xc },
> > > + { 0x90129, 0x0 },
> > > + { 0x9012a, 0x68 },
> > > + { 0x9012b, 0x9 },
> > > + { 0x9012c, 0x0 },
> > > + { 0x9012d, 0x1a9 },
> > > + { 0x9012e, 0x0 },
> > > + { 0x9012f, 0x408 },
> > > + { 0x90130, 0x169 },
> > > + { 0x90131, 0x0 },
> > > + { 0x90132, 0x8080 },
> > > + { 0x90133, 0x108 },
> > > + { 0x90134, 0x8 },
> > > + { 0x90135, 0x7aa },
> > > + { 0x90136, 0x6a },
> > > + { 0x90137, 0x0 },
> > > + { 0x90138, 0x8568 },
> > > + { 0x90139, 0x108 },
> > > + { 0x9013a, 0xb7 },
> > > + { 0x9013b, 0x790 },
> > > + { 0x9013c, 0x16a },
> > > + { 0x9013d, 0x1f },
> > > + { 0x9013e, 0x0 },
> > > + { 0x9013f, 0x68 },
> > > + { 0x90140, 0x8 },
> > > + { 0x90141, 0x8558 },
> > > + { 0x90142, 0x168 },
> > > + { 0x90143, 0xf },
> > > + { 0x90144, 0x408 },
> > > + { 0x90145, 0x169 },
> > > + { 0x90146, 0xc },
> > > + { 0x90147, 0x0 },
> > > + { 0x90148, 0x68 },
> > > + { 0x90149, 0x0 },
> > > + { 0x9014a, 0x408 },
> > > + { 0x9014b, 0x169 },
> > > + { 0x9014c, 0x0 },
> > > + { 0x9014d, 0x8558 },
> > > + { 0x9014e, 0x168 },
> > > + { 0x9014f, 0x8 },
> > > + { 0x90150, 0x3c8 },
> > > + { 0x90151, 0x1a9 },
> > > + { 0x90152, 0x3 },
> > > + { 0x90153, 0x370 },
> > > + { 0x90154, 0x129 },
> > > + { 0x90155, 0x20 },
> > > + { 0x90156, 0x2aa },
> > > + { 0x90157, 0x9 },
> > > + { 0x90158, 0x0 },
> > > + { 0x90159, 0x400 },
> > > + { 0x9015a, 0x10e },
> > > + { 0x9015b, 0x8 },
> > > + { 0x9015c, 0xe8 },
> > > + { 0x9015d, 0x109 },
> > > + { 0x9015e, 0x0 },
> > > + { 0x9015f, 0x8140 },
> > > + { 0x90160, 0x10c },
> > > + { 0x90161, 0x10 },
> > > + { 0x90162, 0x8138 },
> > > + { 0x90163, 0x10c },
> > > + { 0x90164, 0x8 },
> > > + { 0x90165, 0x7c8 },
> > > + { 0x90166, 0x101 },
> > > + { 0x90167, 0x8 },
> > > + { 0x90168, 0x0 },
> > > + { 0x90169, 0x8 },
> > > + { 0x9016a, 0x8 },
> > > + { 0x9016b, 0x448 },
> > > + { 0x9016c, 0x109 },
> > > + { 0x9016d, 0xf },
> > > + { 0x9016e, 0x7c0 },
> > > + { 0x9016f, 0x109 },
> > > + { 0x90170, 0x0 },
> > > + { 0x90171, 0xe8 },
> > > + { 0x90172, 0x109 },
> > > + { 0x90173, 0x47 },
> > > + { 0x90174, 0x630 },
> > > + { 0x90175, 0x109 },
> > > + { 0x90176, 0x8 },
> > > + { 0x90177, 0x618 },
> > > + { 0x90178, 0x109 },
> > > + { 0x90179, 0x8 },
> > > + { 0x9017a, 0xe0 },
> > > + { 0x9017b, 0x109 },
> > > + { 0x9017c, 0x0 },
> > > + { 0x9017d, 0x7c8 },
> > > + { 0x9017e, 0x109 },
> > > + { 0x9017f, 0x8 },
> > > + { 0x90180, 0x8140 },
> > > + { 0x90181, 0x10c },
> > > + { 0x90182, 0x0 },
> > > + { 0x90183, 0x1 },
> > > + { 0x90184, 0x8 },
> > > + { 0x90185, 0x8 },
> > > + { 0x90186, 0x4 },
> > > + { 0x90187, 0x8 },
> > > + { 0x90188, 0x8 },
> > > + { 0x90189, 0x7c8 },
> > > + { 0x9018a, 0x101 },
> > > + { 0x90006, 0x0 },
> > > + { 0x90007, 0x0 },
> > > + { 0x90008, 0x8 },
> > > + { 0x90009, 0x0 },
> > > + { 0x9000a, 0x0 },
> > > + { 0x9000b, 0x0 },
> > > + { 0xd00e7, 0x400 },
> > > + { 0x90017, 0x0 },
> > > + { 0x9001f, 0x2a },
> > > + { 0x90026, 0x6a },
> > > + { 0x400d0, 0x0 },
> > > + { 0x400d1, 0x101 },
> > > + { 0x400d2, 0x105 },
> > > + { 0x400d3, 0x107 },
> > > + { 0x400d4, 0x10f },
> > > + { 0x400d5, 0x202 },
> > > + { 0x400d6, 0x20a },
> > > + { 0x400d7, 0x20b },
> > > + { 0x2003a, 0x2 },
> > > + { 0x2000b, 0x5d },
> > > + { 0x2000c, 0xbb },
> > > + { 0x2000d, 0x753 },
> > > + { 0x2000e, 0x2c },
> > > + { 0x12000b, 0xc },
> > > + { 0x12000c, 0x19 },
> > > + { 0x12000d, 0xfa },
> > > + { 0x12000e, 0x10 },
> > > + { 0x22000b, 0x3 },
> > > + { 0x22000c, 0x6 },
> > > + { 0x22000d, 0x3e },
> > > + { 0x22000e, 0x10 },
> > > + { 0x9000c, 0x0 },
> > > + { 0x9000d, 0x173 },
> > > + { 0x9000e, 0x60 },
> > > + { 0x9000f, 0x6110 },
> > > + { 0x90010, 0x2152 },
> > > + { 0x90011, 0xdfbd },
> > > + { 0x90012, 0x60 },
> > > + { 0x90013, 0x6152 },
> > > + { 0x20010, 0x5a },
> > > + { 0x20011, 0x3 },
> > > + { 0x40080, 0xe0 },
> > > + { 0x40081, 0x12 },
> > > + { 0x40082, 0xe0 },
> > > + { 0x40083, 0x12 },
> > > + { 0x40084, 0xe0 },
> > > + { 0x40085, 0x12 },
> > > + { 0x140080, 0xe0 },
> > > + { 0x140081, 0x12 },
> > > + { 0x140082, 0xe0 },
> > > + { 0x140083, 0x12 },
> > > + { 0x140084, 0xe0 },
> > > + { 0x140085, 0x12 },
> > > + { 0x240080, 0xe0 },
> > > + { 0x240081, 0x12 },
> > > + { 0x240082, 0xe0 },
> > > + { 0x240083, 0x12 },
> > > + { 0x240084, 0xe0 },
> > > + { 0x240085, 0x12 },
> > > + { 0x400fd, 0xf },
> > > + { 0x10011, 0x1 },
> > > + { 0x10012, 0x1 },
> > > + { 0x10013, 0x180 },
> > > + { 0x10018, 0x1 },
> > > + { 0x10002, 0x6209 },
> > > + { 0x100b2, 0x1 },
> > > + { 0x101b4, 0x1 },
> > > + { 0x102b4, 0x1 },
> > > + { 0x103b4, 0x1 },
> > > + { 0x104b4, 0x1 },
> > > + { 0x105b4, 0x1 },
> > > + { 0x106b4, 0x1 },
> > > + { 0x107b4, 0x1 },
> > > + { 0x108b4, 0x1 },
> > > + { 0x11011, 0x1 },
> > > + { 0x11012, 0x1 },
> > > + { 0x11013, 0x180 },
> > > + { 0x11018, 0x1 },
> > > + { 0x11002, 0x6209 },
> > > + { 0x110b2, 0x1 },
> > > + { 0x111b4, 0x1 },
> > > + { 0x112b4, 0x1 },
> > > + { 0x113b4, 0x1 },
> > > + { 0x114b4, 0x1 },
> > > + { 0x115b4, 0x1 },
> > > + { 0x116b4, 0x1 },
> > > + { 0x117b4, 0x1 },
> > > + { 0x118b4, 0x1 },
> > > + { 0x12011, 0x1 },
> > > + { 0x12012, 0x1 },
> > > + { 0x12013, 0x180 },
> > > + { 0x12018, 0x1 },
> > > + { 0x12002, 0x6209 },
> > > + { 0x120b2, 0x1 },
> > > + { 0x121b4, 0x1 },
> > > + { 0x122b4, 0x1 },
> > > + { 0x123b4, 0x1 },
> > > + { 0x124b4, 0x1 },
> > > + { 0x125b4, 0x1 },
> > > + { 0x126b4, 0x1 },
> > > + { 0x127b4, 0x1 },
> > > + { 0x128b4, 0x1 },
> > > + { 0x13011, 0x1 },
> > > + { 0x13012, 0x1 },
> > > + { 0x13013, 0x180 },
> > > + { 0x13018, 0x1 },
> > > + { 0x13002, 0x6209 },
> > > + { 0x130b2, 0x1 },
> > > + { 0x131b4, 0x1 },
> > > + { 0x132b4, 0x1 },
> > > + { 0x133b4, 0x1 },
> > > + { 0x134b4, 0x1 },
> > > + { 0x135b4, 0x1 },
> > > + { 0x136b4, 0x1 },
> > > + { 0x137b4, 0x1 },
> > > + { 0x138b4, 0x1 },
> > > + { 0x2003a, 0x2 },
> > > + { 0xc0080, 0x2 },
> > > + { 0xd0000, 0x1 },
> > > +};
> >
> > The same as above.
> >
> > > +
> > > +struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
> > > + {
> > > + /* P0 3000mts 1D */
> > > + .drate = 3000,
> > > + .fw_type = FW_1D_IMAGE,
> > > + .fsp_cfg = lpddr4_fsp0_cfg,
> > > + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg),
> > > + },
> > > + {
> > > + /* P0 3000mts 2D */
> > > + .drate = 3000,
> > > + .fw_type = FW_2D_IMAGE,
> > > + .fsp_cfg = lpddr4_fsp0_2d_cfg,
> > > + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg),
> > > + },
> > > + {
> > > + /* P1 400mts 1D */
> > > + .drate = 400,
> > > + .fw_type = FW_1D_IMAGE,
> > > + .fsp_cfg = lpddr4_fsp1_cfg,
> > > + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg),
> > > + },
> > > + {
> > > + /* P1 100mts 1D */
> > > + .drate = 100,
> > > + .fw_type = FW_1D_IMAGE,
> > > + .fsp_cfg = lpddr4_fsp2_cfg,
> > > + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg),
> > > + },
> > > +};
> > > +
> > > +/* lpddr4 timing config params on EVK board */
> > > +struct dram_timing_info dram_timing = {
> > > + .ddrc_cfg = lpddr4_ddrc_cfg,
> > > + .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
> > > + .ddrphy_cfg = lpddr4_ddrphy_cfg,
> > > + .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg),
> > > + .fsp_msg = lpddr4_dram_fsp_msg,
> > > + .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg),
> > > + .ddrphy_trained_csr = lpddr4_ddrphy_trained_csr,
> > > + .ddrphy_trained_csr_num =
> > > ARRAY_SIZE(lpddr4_ddrphy_trained_csr),
> > > + .ddrphy_pie = lpddr4_phy_pie,
> > > + .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
> >
> > It would be best to get the above values calculated dynamically for
> > this SoC.
> >
> > > +};
> > > diff --git a/board/freescale/imx8mm_evk/spl.c
> > > b/board/freescale/imx8mm_evk/spl.c new file mode 100644
> > > index 0000000000..cf1dfc2c2a
> > > --- /dev/null
> > > +++ b/board/freescale/imx8mm_evk/spl.c
> > > @@ -0,0 +1,187 @@
> > > +// SPDX-License-Identifier: GPL-2.0+
> > > +/*
> > > + * Copyright 2019 NXP
> > > + */
> > > +
> > > +#include <common.h>
> > > +#include <spl.h>
> > > +#include <asm/io.h>
> > > +#include <errno.h>
> > > +#include <asm/io.h>
> > > +#include <asm/mach-imx/iomux-v3.h>
> > > +#include <asm/arch/imx8mm_pins.h>
> > > +#include <asm/arch/sys_proto.h>
> > > +#include <power/pmic.h>
> > > +#include <asm/arch/clock.h>
> > > +#include <asm/mach-imx/gpio.h>
> > > +#include <asm/mach-imx/mxc_i2c.h>
> > > +#include <fsl_esdhc.h>
> > > +#include <mmc.h>
> > > +#include <asm/arch/ddr.h>
> > > +
> > > +DECLARE_GLOBAL_DATA_PTR;
> > > +
> > > +void spl_dram_init(void)
> > > +{
> > > + ddr_init(&dram_timing);
> > > +}
> > > +
> > > +#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 18)
> > > +#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
> > > +
> > > +#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS |
> > PAD_CTL_PUE | \
> > > + PAD_CTL_PE | PAD_CTL_FSEL2)
> > > +#define USDHC_GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE1)
> > > +
> > > +static iomux_v3_cfg_t const usdhc3_pads[] = {
> > > + IMX8MM_PAD_NAND_WE_B_USDHC3_CLK |
> > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > + IMX8MM_PAD_NAND_WP_B_USDHC3_CMD |
> > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > + IMX8MM_PAD_NAND_DATA04_USDHC3_DATA0 |
> > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > + IMX8MM_PAD_NAND_DATA05_USDHC3_DATA1 |
> > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > + IMX8MM_PAD_NAND_DATA06_USDHC3_DATA2 |
> > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > + IMX8MM_PAD_NAND_DATA07_USDHC3_DATA3 |
> > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > + IMX8MM_PAD_NAND_RE_B_USDHC3_DATA4 |
> > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > + IMX8MM_PAD_NAND_CE2_B_USDHC3_DATA5 |
> > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > + IMX8MM_PAD_NAND_CE3_B_USDHC3_DATA6 |
> > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > + IMX8MM_PAD_NAND_CLE_USDHC3_DATA7 |
> > > MUX_PAD_CTRL(USDHC_PAD_CTRL), +};
> > > +
> > > +static iomux_v3_cfg_t const usdhc2_pads[] = {
> > > + IMX8MM_PAD_SD2_CLK_USDHC2_CLK |
> > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > + IMX8MM_PAD_SD2_CMD_USDHC2_CMD |
> > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > + IMX8MM_PAD_SD2_DATA0_USDHC2_DATA0 |
> > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > + IMX8MM_PAD_SD2_DATA1_USDHC2_DATA1 |
> > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > + IMX8MM_PAD_SD2_DATA2_USDHC2_DATA2 |
> > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > + IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 |
> > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > + IMX8MM_PAD_SD2_RESET_B_GPIO2_IO19 |
> > > MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), +};
> > > +
> > > +/*
> > > + * The evk board uses DAT3 to detect CD card plugin,
> > > + * in u-boot we mux the pin to GPIO when doing board_mmc_getcd.
> > > + */
> > > +static iomux_v3_cfg_t const usdhc2_cd_pad =
> > > + IMX8MM_PAD_SD2_DATA3_GPIO2_IO18 |
> > > MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL); +
> > > +static iomux_v3_cfg_t const usdhc2_dat3_pad =
> > > + IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 |
> > > + MUX_PAD_CTRL(USDHC_PAD_CTRL);
> > > +
> > > +static struct fsl_esdhc_cfg usdhc_cfg[2] = {
> > > + {USDHC2_BASE_ADDR, 0, 1},
> > > + {USDHC3_BASE_ADDR, 0, 1},
> > > +};
> > > +
> > > +int board_mmc_init(bd_t *bis)
> > > +{
> > > + int i, ret;
> > > + /*
> > > + * According to the board_mmc_init() the following map is
> > > done:
> > > + * (U-Boot device node) (Physical Port)
> > > + * mmc0 USDHC1
> > > + * mmc1 USDHC2
> > > + */
> > > + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
> > > + switch (i) {
> > > + case 0:
> > > + usdhc_cfg[0].sdhc_clk =
> > > mxc_get_clock(MXC_ESDHC2_CLK);
> > > +
> > > imx_iomux_v3_setup_multiple_pads(usdhc2_pads, +
> > > ARRAY_SIZE(usdhc2_pads));
> > > + gpio_request(USDHC2_PWR_GPIO,
> > > "usdhc2_reset");
> > > + gpio_direction_output(USDHC2_PWR_GPIO,
> > > 0);
> > > + udelay(500);
> > > + gpio_direction_output(USDHC2_PWR_GPIO,
> > > 1);
> > > + break;
> > > + case 1:
> > > + usdhc_cfg[1].sdhc_clk =
> > > mxc_get_clock(MXC_ESDHC3_CLK);
> > > +
> > > imx_iomux_v3_setup_multiple_pads(usdhc3_pads, +
> > > ARRAY_SIZE(usdhc3_pads));
> > > + break;
> >
> > It would be best if you could enable DM/DTS in SPL too from the
> > outset (and share the SPL size).
> >
> > Do you have any timeline for converting SPL to DM/DTS?
> >
> > > + default:
> > > + printf("USDHC controllers %d not
> > > supported \n", i + 1);
> > > + return -EINVAL;
> > > + }
> > > +
> > > + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
> > > + if (ret)
> > > + return ret;
> > > + }
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +int board_mmc_getcd(struct mmc *mmc)
> > > +{
> > > + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg
> > > *)mmc->priv;
> > > + int ret = 0;
> > > +
> > > + switch (cfg->esdhc_base) {
> > > + case USDHC3_BASE_ADDR:
> > > + ret = 1;
> > > + break;
> > > + case USDHC2_BASE_ADDR:
> > > + imx_iomux_v3_setup_pad(usdhc2_cd_pad);
> > > + gpio_request(USDHC2_CD_GPIO, "usdhc2 cd");
> > > + gpio_direction_input(USDHC2_CD_GPIO);
> > > +
> > > + /*
> > > + * Since it is the DAT3 pin, this pin is pulled
> > > to
> > > + * low voltage if no card
> > > + */
> > > + ret = gpio_get_value(USDHC2_CD_GPIO);
> > > +
> > > + imx_iomux_v3_setup_pad(usdhc2_dat3_pad);
> > > + return ret;
> > > + }
> > > +
> > > + return 1;
> > > +}
> > > +
> > > +void spl_board_init(void)
> > > +{
> > > + puts("Normal Boot\n");
> > > +}
> > > +
> > > +#ifdef CONFIG_SPL_LOAD_FIT
> > > +int board_fit_config_name_match(const char *name)
> > > +{
> > > + /* Just empty function now - can't decide what to choose
> > > */
> > > + debug("%s: %s\n", __func__, name);
> > > +
> > > + return 0;
> > > +}
> > > +#endif
> > > +
> > > +void board_init_f(ulong dummy)
> > > +{
> > > + int ret;
> > > +
> > > + /* Clear global data */
> > > + memset((void *)gd, 0, sizeof(gd_t));
> > > +
> > > + arch_cpu_init();
> > > +
> > > + init_uart_clk(1);
> > > +
> > > + board_early_init_f();
> > > +
> > > + timer_init();
> > > +
> > > + preloader_console_init();
> > > +
> > > + /* Clear the BSS. */
> > > + memset(__bss_start, 0, __bss_end - __bss_start);
> > > +
> > > + ret = spl_init();
> > > + if (ret) {
> > > + debug("spl_init() failed: %d\n", ret);
> > > + hang();
> > > + }
> > > +
> > > + enable_tzc380();
> > > +
> > > + /* DDR initialization */
> > > + spl_dram_init();
> > > +
> > > + board_init_r(NULL, 0);
> > > +}
> > > diff --git a/configs/imx8mm_evk_defconfig
> > > b/configs/imx8mm_evk_defconfig new file mode 100644
> > > index 0000000000..6110f23e38
> > > --- /dev/null
> > > +++ b/configs/imx8mm_evk_defconfig
> > > @@ -0,0 +1,41 @@
> > > +CONFIG_ARM=y
> > > +CONFIG_ARCH_IMX8M=y
> > > +CONFIG_SYS_TEXT_BASE=0x40200000
> > > +CONFIG_SPL_GPIO_SUPPORT=y
> > > +CONFIG_SYS_MALLOC_F_LEN=0x2000
> > > +CONFIG_TARGET_IMX8MM_EVK=y
> > > +CONFIG_SPL_MMC_SUPPORT=y
> > > +CONFIG_SPL_SERIAL_SUPPORT=y
> > > +CONFIG_SPL=y
> > > +CONFIG_FIT=y
> > > +CONFIG_FIT_EXTERNAL_OFFSET=0x3000
> > > +CONFIG_SPL_LOAD_FIT=y
> > > +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
> > >
> > +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m
> > /imximage.cfg,SPL_TEXT_BASE=0x7E1000"
> > > +CONFIG_DEFAULT_FDT_FILE="fsl-imx8mm-evk.dtb"
> > > +CONFIG_SPL_BOARD_INIT=y
> > > +CONFIG_SPL_I2C_SUPPORT=y
> > > +CONFIG_HUSH_PARSER=y
> > > +CONFIG_CMD_GPIO=y
> > > +CONFIG_CMD_I2C=y
> > > +CONFIG_CMD_CACHE=y
> > > +CONFIG_CMD_REGULATOR=y
> > > +CONFIG_CMD_EXT2=y
> > > +CONFIG_CMD_EXT4=y
> > > +CONFIG_CMD_EXT4_WRITE=y
> > > +CONFIG_CMD_FAT=y
> > > +CONFIG_OF_CONTROL=y
> > > +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mm-evk"
> > > +CONFIG_DM_GPIO=y
> > > +CONFIG_MXC_GPIO=y
> > > +CONFIG_DM_I2C=y
> > > +CONFIG_SYS_I2C_MXC=y
> > > +CONFIG_DM_MMC=y
> > > +CONFIG_DM_ETH=y
> >
> > Here you enable the DM_ETH, but the welcome u-boot info says:
> >
> > "Net: No ethernet found."
> >
> > > +CONFIG_PINCTRL=y
> > > +CONFIG_PINCTRL_IMX8M=y
> > > +CONFIG_DM_REGULATOR=y
> > > +CONFIG_DM_REGULATOR_FIXED=y
> > > +CONFIG_DM_REGULATOR_GPIO=y
> > > +CONFIG_MXC_UART=y
> > > +CONFIG_DM_THERMAL=y
> > > diff --git a/include/configs/imx8mm_evk.h
> > > b/include/configs/imx8mm_evk.h new file mode 100644
> > > index 0000000000..f944308757
> > > --- /dev/null
> > > +++ b/include/configs/imx8mm_evk.h
> > > @@ -0,0 +1,221 @@
> > > +/* SPDX-License-Identifier: GPL-2.0+ */
> > > +/*
> > > + * Copyright 2018 NXP
> > > + */
> > > +
> > > +#ifndef __IMX8MM_EVK_H
> > > +#define __IMX8MM_EVK_H
> > > +
> > > +#include <linux/sizes.h>
> > > +#include <asm/arch/imx-regs.h>
> > > +
> > > +#ifdef CONFIG_SECURE_BOOT
> > > +#define CONFIG_CSF_SIZE 0x2000 /* 8K
> > > region */ +#endif
> > > +
> > > +#define CONFIG_SPL_MAX_SIZE (148 * 1024)
> > > +#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
> > > +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
> > > +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
> > > +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
> > > +#define CONFIG_SYS_UBOOT_BASE \
> > > + (QSPI0_AMBA_BASE +
> > CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR *
> > > 512) +
> > > +#ifdef CONFIG_SPL_BUILD
> > > +/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
> > > +#define CONFIG_SPL_WATCHDOG_SUPPORT
> > > +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
> > > +#define CONFIG_SPL_POWER_SUPPORT
> > > +#define
> > > CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
> > > +#define CONFIG_SPL_STACK 0x91fff0 +#define
> > > CONFIG_SPL_LIBCOMMON_SUPPORT +#define
> > CONFIG_SPL_LIBGENERIC_SUPPORT
> > > +#define CONFIG_SPL_BSS_START_ADDR 0x00910000
> > > +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
> > > +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
> > > +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB
> > > */ +#define CONFIG_SYS_ICACHE_OFF
> > > +#define CONFIG_SYS_DCACHE_OFF
> > > +
> > > +#define CONFIG_MALLOC_F_ADDR 0x912000 /* malloc f
> > > used before GD_FLG_FULL_MALLOC_INIT set */ +
> > > +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a
> > error
> > > info not panic */ +
> > > +#undef CONFIG_DM_MMC
> > > +#undef CONFIG_DM_PMIC
> > > +#undef CONFIG_DM_PMIC_PFUZE100
> >
> > Why do you need to undef those config options?
> >
> > > +
> > > +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> > > +
> > > +#endif
> > > +
> > > +#define CONFIG_REMAKE_ELF
> > > +
> > > +#define CONFIG_BOARD_EARLY_INIT_F
> > > +#define CONFIG_BOARD_POSTCLK_INIT
> > > +#define CONFIG_BOARD_LATE_INIT
> > > +
> > > +/* Flat Device Tree Definitions */
> > > +#define CONFIG_OF_BOARD_SETUP
> > > +
> > > +#undef CONFIG_CMD_EXPORTENV
> > > +#undef CONFIG_CMD_IMPORTENV
> > > +#undef CONFIG_CMD_IMLS
> > > +
> > > +#undef CONFIG_CMD_CRC32
> > > +#undef CONFIG_BOOTM_NETBSD
> >
> > There seems to be some issue with inheritance, as you need to undef
> > those values manually.
> >
> > Why is it needed?
> >
> > > +
> > > +/* ENET Config */
> > > +/* ENET1 */
> > > +#if defined(CONFIG_CMD_NET)
> > > +#define CONFIG_CMD_PING
> > > +#define CONFIG_CMD_DHCP
> > > +#define CONFIG_CMD_MII
> > > +#define CONFIG_MII
> > > +#define CONFIG_ETHPRIME "FEC"
> > > +
> > > +#define CONFIG_FEC_MXC
> > > +#define CONFIG_FEC_XCV_TYPE RGMII
> > > +#define CONFIG_FEC_MXC_PHYADDR 0
> > > +#define FEC_QUIRK_ENET_MAC
> > > +
> > > +#define CONFIG_PHY_GIGE
> > > +#define IMX_FEC_BASE 0x30BE0000
> > > +
> > > +#define CONFIG_PHYLIB
> > > +#define CONFIG_PHY_ATHEROS
> > > +#endif
> > > +
> > > +/* Initial environment variables */
> > > +#define CONFIG_EXTRA_ENV_SETTINGS \
> > > + "script=boot.scr\0" \
> > > + "image=Image\0" \
> > > + "console=ttymxc1,115200
> > > earlycon=ec_imx6q,0x30890000,115200\0" \
> > > + "fdt_addr=0x43000000\0" \
> > > + "fdt_high=0xffffffffffffffff\0" \
> > > + "boot_fdt=try\0" \
> > > + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
> > > + "initrd_addr=0x43800000\0" \
> > > + "initrd_high=0xffffffffffffffff\0" \
> > > + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
> > > + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART)
> > > "\0" \
> > > + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
> > > + "mmcautodetect=yes\0" \
> > > + "mmcargs=setenv bootargs ${jh_clk} console=${console}
> > > root=${mmcroot}\0 " \
> > > + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart}
> > > ${loadaddr} ${script};\0" \
> > > + "bootscript=echo Running bootscript from mmc ...; " \
> > > + "source\0" \
> > > + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}
> > > ${image}\0" \
> > > + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr}
> > > ${fdt_file}\0" \
> > > + "mmcboot=echo Booting from mmc ...; " \
> > > + "run mmcargs; " \
> > > + "if test ${boot_fdt} = yes || test ${boot_fdt} =
> > > try; then " \
> > > + "if run loadfdt; then " \
> > > + "booti ${loadaddr} -
> > > ${fdt_addr}; " \
> > > + "else " \
> > > + "echo WARN: Cannot load the DT;
> > > " \
> > > + "fi; " \
> > > + "else " \
> > > + "echo wait for boot; " \
> > > + "fi;\0" \
> > > + "netargs=setenv bootargs ${jh_clk} console=${console} " \
> > > + "root=/dev/nfs " \
> > > + "ip=dhcp
> > > nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
> > > + "netboot=echo Booting from net ...; " \
> > > + "run netargs; " \
> > > + "if test ${ip_dyn} = yes; then " \
> > > + "setenv get_cmd dhcp; " \
> > > + "else " \
> > > + "setenv get_cmd tftp; " \
> > > + "fi; " \
> > > + "${get_cmd} ${loadaddr} ${image}; " \
> > > + "if test ${boot_fdt} = yes || test ${boot_fdt} =
> > > try; then " \
> > > + "if ${get_cmd} ${fdt_addr} ${fdt_file};
> > > then " \
> > > + "booti ${loadaddr} -
> > > ${fdt_addr}; " \
> > > + "else " \
> > > + "echo WARN: Cannot load the DT;
> > > " \
> > > + "fi; " \
> > > + "else " \
> > > + "booti; " \
> > > + "fi;\0"
> > > +
> > > +#define CONFIG_BOOTCOMMAND \
> > > + "mmc dev ${mmcdev}; if mmc rescan; then " \
> > > + "if run loadbootscript; then " \
> > > + "run bootscript; " \
> > > + "else " \
> > > + "if run loadimage; then " \
> > > + "run mmcboot; " \
> > > + "else run netboot; " \
> > > + "fi; " \
> > > + "fi; " \
> > > + "else booti ${loadaddr} - ${fdt_addr}; fi"
> > > +
> > > +/* Link Definitions */
> > > +#define CONFIG_LOADADDR 0x40480000
> > > +
> > > +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
> > > +
> > > +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
> > > +#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
> > > +#define CONFIG_SYS_INIT_SP_OFFSET \
> > > + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> > > +#define CONFIG_SYS_INIT_SP_ADDR \
> > > + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
> > > +
> > > +#define CONFIG_ENV_OVERWRITE
> > > +#if defined(CONFIG_ENV_IS_IN_MMC)
> > > +#define CONFIG_ENV_OFFSET (64 * SZ_64K)
> > > +#endif
> > > +#define CONFIG_ENV_SIZE 0x1000
> > > +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC2 */
> > > +#define
> > > CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2
> > > */ + +/* Size of malloc() pool */
> > > +#define CONFIG_SYS_MALLOC_LEN SZ_32M
> > > +
> > > +#define CONFIG_SYS_SDRAM_BASE 0x40000000
> > > +#define PHYS_SDRAM 0x40000000
> > > +#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB
> > > DDR */ +
> > > +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
> > > +#define CONFIG_SYS_MEMTEST_END
> > (CONFIG_SYS_MEMTEST_START +
> > > (PHYS_SDRAM_SIZE >> 1)) +
> > > +#define CONFIG_BAUDRATE 115200
> > > +
> > > +#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
> > > +
> > > +/* Monitor Command Prompt */
> > > +#undef CONFIG_SYS_PROMPT
> > > +#define CONFIG_SYS_PROMPT "u-boot=> "
> > > +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
> > > +#define CONFIG_SYS_CBSIZE 2048
> > > +#define CONFIG_SYS_MAXARGS 64
> > > +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
> > > +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
> > > +
> > > sizeof(CONFIG_SYS_PROMPT) + 16) +
> > > +#define CONFIG_IMX_BOOTAUX
> > > +
> > > +/* USDHC */
> > > +#define CONFIG_CMD_MMC
> > > +#define CONFIG_FSL_ESDHC
> > > +#define CONFIG_FSL_USDHC
> > > +
> > > +#define CONFIG_SYS_FSL_USDHC_NUM 2
> > > +#define CONFIG_SYS_FSL_ESDHC_ADDR 0
> > > +
> > > +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
> > > +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
> > > +
> > > +#define CONFIG_MXC_OCOTP
> > > +#define CONFIG_CMD_FUSE
> > > +
> > > +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus
> > > 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable
> > > I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /*
> > > enable I2C bus 3 */ +#define CONFIG_SYS_I2C_SPEED
> > > 100000
> >
> > Some of those values are (SYS_I2C_*, MXC_OCOTP, FSL_*) are already
> > supported by Kconfig. Please use Kconfig instead.
> >
> > > +
> > > +#define CONFIG_OF_SYSTEM_SETUP
> > > +
> > > +#endif
> >
> >
> > Best regards,
> >
> > Lukasz Majewski
> >
> > --
> >
> > DENX Software Engineering GmbH, Managing Director: Wolfgang
> > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell,
> > Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> > lukma at denx.de
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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^ permalink raw reply [flat|nested] 39+ messages in thread* [U-Boot] [PATCH 20/20] imx: add i.MX8MM EVK board support
2019-01-30 6:53 ` Lukasz Majewski
@ 2019-01-30 7:07 ` Peng Fan
2019-01-30 8:37 ` Lukasz Majewski
0 siblings, 1 reply; 39+ messages in thread
From: Peng Fan @ 2019-01-30 7:07 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: Lukasz Majewski [mailto:lukma at denx.de]
> Sent: 2019年1月30日 14:54
> To: Peng Fan <peng.fan@nxp.com>
> Cc: sbabic at denx.de; Fabio Estevam <fabio.estevam@nxp.com>;
> dl-uboot-imx <uboot-imx@nxp.com>; u-boot at lists.denx.de
> Subject: Re: [U-Boot] [PATCH 20/20] imx: add i.MX8MM EVK board support
>
> Hi Peng,
>
> > > -----Original Message-----
> > > From: Lukasz Majewski [mailto:lukma at denx.de]
> > > Sent: 2019年1月30日 7:19
> > > To: Peng Fan <peng.fan@nxp.com>
> > > Cc: sbabic at denx.de; Fabio Estevam <fabio.estevam@nxp.com>;
> > > dl-uboot-imx <uboot-imx@nxp.com>; u-boot at lists.denx.de
> > > Subject: Re: [U-Boot] [PATCH 20/20] imx: add i.MX8MM EVK board
> > > support
> > >
> > > Hi Peng,
> > >
> > > > Add i.MX8MM EVK board support.
> > > >
> > > > Add board and SoC dts
> > > > Add ddr training code
> > > > support SD/MMC/GPIO/PINCTRL/UART
> > > >
> > > > U-Boot SPL 2019.01-00148-g1179cffe66 (Jan 28 2019 - 17:37:34
> > > > +0800) Normal Boot
> > > > Trying to boot from MMC1
> > > >
> > > > U-Boot 2019.01-00148-g1179cffe66 (Jan 28 2019 - 17:37:34 +0800)
> > > >
> > > > CPU: Freescale i.MX8MMQ rev1.0 at 1200 MHz
> > > > Reset cause: POR
> > > > Model: NXP i.MX8MM EVK board
> > > > DRAM: 2 GiB
> > > > MMC: FSL_SDHC: 1, FSL_SDHC: 2
> > > > In: serial
> > > > Out: serial
> > > > Err: serial
> > > > DM
> > >
> > > You set/adjust latter in the code the fec network driver. Why it is
> > > not found?
> >
> > I dropped network support, could add it in V2.
>
> From the patch it seems like the ETH is fully supported, at lease from
> the source code point of view.
>
> >
> > >
> > > Could you also share the output of "dm tree" command?
> >
> > Sure.
> >
> > >
> > > I suppose/guess that this board shall support as much as possible of
> > > the DT/DM conversions?
> >
> > Ok.
>
> And I would like to emphasize the need of DDR training code (as a
> functions, not pair of offset and value).
>
> Are you able to provide such code in the next version of the patch?
There is already common code under drivers/ddr/imx8m
For the array in board file, It need ddr tool change, out of my knowledge.
Thanks,
Peng.
>
> >
> > Regards,
> > Peng.
> >
> > >
> > > > Hit any key to stop autoboot: 2
> > > >
> > > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > > ---
> > > > arch/arm/dts/fsl-imx8mm-evk.dts | 203 +++
> > > > arch/arm/dts/fsl-imx8mm.dtsi | 586 ++++++++
> > > > arch/arm/mach-imx/imx8m/Kconfig | 7 +
> > > > board/freescale/imx8mm_evk/Kconfig | 12 +
> > > > board/freescale/imx8mm_evk/MAINTAINERS | 6 +
> > > > board/freescale/imx8mm_evk/Makefile | 12 +
> > > > board/freescale/imx8mm_evk/imx8mm_evk.c | 144 ++
> > > > board/freescale/imx8mm_evk/lpddr4_timing.c | 1980
> > > > ++++++++++++++++++++++++++++
> > > > board/freescale/imx8mm_evk/spl.c | 187 +++
> > > > configs/imx8mm_evk_defconfig | 41 +
> > > > include/configs/imx8mm_evk.h | 221 ++++ 11 files
> > > > changed, 3399 insertions(+) create mode 100644
> > > > arch/arm/dts/fsl-imx8mm-evk.dts create mode 100644
> > > > arch/arm/dts/fsl-imx8mm.dtsi create mode 100644
> > > > board/freescale/imx8mm_evk/Kconfig create mode 100644
> > > > board/freescale/imx8mm_evk/MAINTAINERS create mode 100644
> > > > board/freescale/imx8mm_evk/Makefile create mode 100644
> > > > board/freescale/imx8mm_evk/imx8mm_evk.c create mode 100644
> > > > board/freescale/imx8mm_evk/lpddr4_timing.c create mode 100644
> > > > board/freescale/imx8mm_evk/spl.c create mode 100644
> > > > configs/imx8mm_evk_defconfig create mode 100644
> > > > include/configs/imx8mm_evk.h
> > > >
> > > > diff --git a/arch/arm/dts/fsl-imx8mm-evk.dts
> > > > b/arch/arm/dts/fsl-imx8mm-evk.dts new file mode 100644
> > > > index 0000000000..df409eca47
> > > > --- /dev/null
> > > > +++ b/arch/arm/dts/fsl-imx8mm-evk.dts
> > > > @@ -0,0 +1,203 @@
> > > > +// SPDX-License-Identifier: GPL-2.0+
> > > > +/*
> > > > + * Copyright 2019 NXP
> > > > + */
> > > > +
> > > > +/dts-v1/;
> > > > +
> > > > +#include "fsl-imx8mm.dtsi"
> > > > +
> > > > +/ {
> > > > + model = "NXP i.MX8MM EVK board";
> > > > + compatible = "fsl,imx8mm-evk", "fsl,imx8mm";
> > > > +
> > > > + chosen {
> > > > + stdout-path = &uart2;
> > > > + };
> > > > +
> > > > + regulators {
> > > > + compatible = "simple-bus";
> > > > + #address-cells = <1>;
> > > > + #size-cells = <0>;
> > > > +
> > > > + reg_usdhc2_vmmc: regulator-usdhc2 {
> > > > + compatible = "regulator-fixed";
> > > > + regulator-name = "VSD_3V3";
> > > > + regulator-min-microvolt = <3300000>;
> > > > + regulator-max-microvolt = <3300000>;
> > > > + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
> > > > + off-on-delay = <20000>;
> > > > + enable-active-high;
> > > > + };
> > > > + };
> > > > +};
> > > > +
> > > > +&iomuxc {
> > > > + pinctrl-names = "default";
> > > > +
> > > > + imx8mm-evk {
> > > > + pinctrl_fec1: fec1grp {
> > > > + fsl,pins = <
> > > > +
> > > > MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
> > > > +
> > > > MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
> > > > +
> > > > MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
> > > > +
> > > > MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
> > > > +
> > > > MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
> > > > +
> > > > MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
> > > > +
> > > > MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
> > > > +
> > > > MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
> > > > +
> > > > MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
> > > > +
> > > > MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
> > > > +
> > > > MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
> > > > +
> > > > MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
> > > > +
> > > > MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
> > > > +
> > > > MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
> > > > +
> > > > MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
> > > > + >;
> > > > + };
> > > > +
> > > > + pinctrl_gpio_led: gpioledgrp {
> > > > + fsl,pins = <
> > > > +
> > > > MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
> > > > + >;
> > > > + };
> > > > +
> > > > + pinctrl_uart2: uart2grp {
> > > > + fsl,pins = <
> > > > +
> > > > MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
> > > > +
> > > > MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
> > > > + >;
> > > > + };
> > > > +
> > > > + pinctrl_usdhc2_gpio: usdhc2grpgpio {
> > > > + fsl,pins = <
> > > > +
> > > > MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
> > > > +
> > > > MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
> > > > + >;
> > > > + };
> > > > +
> > > > + pinctrl_usdhc2: usdhc2grp {
> > > > + fsl,pins = <
> > > > +
> > > > MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
> > > > +
> > > > MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
> > > > +
> > > > MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
> > > > +
> > > > MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
> > > > +
> > > > MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
> > > > +
> > > > MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
> > > > +
> > > > MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
> > > > + >;
> > > > + };
> > > > +
> > > > + pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
> > > > + fsl,pins = <
> > > > +
> > > > MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
> > > > +
> > > > MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
> > > > +
> > > > MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
> > > > +
> > > > MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
> > > > +
> > > > MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
> > > > +
> > > > MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
> > > > +
> > > > MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
> > > > + >;
> > > > + };
> > > > +
> > > > + pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
> > > > + fsl,pins = <
> > > > +
> > > > MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
> > > > +
> > > > MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
> > > > +
> > > > MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
> > > > +
> > > > MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
> > > > +
> > > > MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
> > > > +
> > > > MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
> > > > +
> > > > MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
> > > > + >;
> > > > + };
> > > > +
> > > > + pinctrl_usdhc3: usdhc3grp {
> > > > + fsl,pins = <
> > > > +
> > > > MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
> > > > +
> > > > MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
> > > > +
> > > > MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
> > > > +
> > > > MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
> > > > +
> > > > MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
> > > > +
> > > > MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
> > > > +
> > > > MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
> > > > +
> > > > MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
> > > > +
> > > > MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
> > > > +
> > > > MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
> > > > +
> > > > MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
> > > > + >;
> > > > + };
> > > > +
> > > > + pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
> > > > + fsl,pins = <
> > > > +
> > > > MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
> > > > +
> > > > MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
> > > > +
> > > > MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
> > > > +
> > > > MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
> > > > +
> > > > MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
> > > > +
> > > > MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
> > > > +
> > > > MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
> > > > +
> > > > MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
> > > > +
> > > > MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
> > > > +
> > > > MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
> > > > +
> > > > MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
> > > > + >;
> > > > + };
> > > > +
> > > > + pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
> > > > + fsl,pins = <
> > > > +
> > > > MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
> > > > +
> > > > MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
> > > > +
> > > > MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
> > > > +
> > > > MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
> > > > +
> > > > MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
> > > > +
> > > > MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
> > > > +
> > > > MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
> > > > +
> > > > MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
> > > > +
> > > > MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
> > > > +
> > > > MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
> > > > +
> > > > MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
> > > > + >;
> > > > + };
> > > > +
> > > > + pinctrl_wdog: wdoggrp {
> > > > + fsl,pins = <
> > > > +
> > > > MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
> > > > + >;
> > > > + };
> > > > + };
> > > > +};
> > > > +
> > > > +&uart2 { /* console */
> > > > + pinctrl-names = "default";
> > > > + pinctrl-0 = <&pinctrl_uart2>;
> > > > + status = "okay";
> > > > +};
> > > > +
> > > > +&usdhc2 {
> > > > + pinctrl-names = "default", "state_100mhz",
> > > > "state_200mhz";
> > > > + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
> > > > + pinctrl-1 = <&pinctrl_usdhc2_100mhz>,
> > > > <&pinctrl_usdhc2_gpio>;
> > > > + pinctrl-2 = <&pinctrl_usdhc2_200mhz>,
> > > > <&pinctrl_usdhc2_gpio>;
> > > > + cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
> > > > + bus-width = <4>;
> > > > + vmmc-supply = <®_usdhc2_vmmc>;
> > > > + status = "okay";
> > > > +};
> > > > +
> > > > +&usdhc3 {
> > > > + pinctrl-names = "default", "state_100mhz",
> > > > "state_200mhz";
> > > > + pinctrl-0 = <&pinctrl_usdhc3>;
> > > > + pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
> > > > + pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
> > > > + bus-width = <8>;
> > > > + non-removable;
> > > > + status = "okay";
> > > > +};
> > > > +
> > > > +&wdog1 {
> > > > + pinctrl-names = "default";
> > > > + pinctrl-0 = <&pinctrl_wdog>;
> > > > + fsl,ext-reset-output;
> > > > + status = "okay";
> > > > +};
> > > > diff --git a/arch/arm/dts/fsl-imx8mm.dtsi
> > > > b/arch/arm/dts/fsl-imx8mm.dtsi new file mode 100644
> > > > index 0000000000..8a808f856d
> > > > --- /dev/null
> > > > +++ b/arch/arm/dts/fsl-imx8mm.dtsi
> > > > @@ -0,0 +1,586 @@
> > > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > > > +/*
> > > > + * Copyright 2017-2019 NXP
> > > > + */
> > > > +
> > > > +#include <dt-bindings/clock/imx8mm-clock.h>
> > > > +#include <dt-bindings/gpio/gpio.h>
> > > > +#include <dt-bindings/input/input.h>
> > > > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > > > +#include <dt-bindings/pinctrl/pins-imx8mm.h>
> > > > +#include <dt-bindings/thermal/thermal.h>
> > > > +
> > > > +/ {
> > > > + compatible = "fsl,imx8mm";
> > > > + interrupt-parent = <&gic>;
> > > > + #address-cells = <2>;
> > > > + #size-cells = <2>;
> > > > +
> > > > + aliases {
> > > > + i2c0 = &i2c1;
> > > > + i2c1 = &i2c2;
> > > > + i2c2 = &i2c3;
> > > > + i2c3 = &i2c4;
> > > > + serial0 = &uart1;
> > > > + serial1 = &uart2;
> > > > + serial2 = &uart3;
> > > > + serial3 = &uart4;
> > > > + spi0 = &ecspi1;
> > > > + spi1 = &ecspi2;
> > > > + spi2 = &ecspi3;
> > > > + mmc0 = &usdhc1;
> > > > + mmc1 = &usdhc2;
> > > > + mmc2 = &usdhc3;
> > > > + gpio0 = &gpio1;
> > > > + gpio1 = &gpio2;
> > > > + gpio2 = &gpio3;
> > > > + gpio3 = &gpio4;
> > > > + gpio4 = &gpio5;
> > > > + };
> > > > +
> > > > + cpus {
> > > > + #address-cells = <1>;
> > > > + #size-cells = <0>;
> > > > +
> > > > + A53_0: cpu at 0 {
> > > > + device_type = "cpu";
> > > > + compatible = "arm,cortex-a53";
> > > > + reg = <0x0>;
> > > > + enable-method = "psci";
> > > > + next-level-cache = <&A53_L2>;
> > > > + };
> > > > +
> > > > + A53_1: cpu at 1 {
> > > > + device_type = "cpu";
> > > > + compatible = "arm,cortex-a53";
> > > > + reg = <0x1>;
> > > > + enable-method = "psci";
> > > > + next-level-cache = <&A53_L2>;
> > > > + };
> > > > +
> > > > + A53_2: cpu at 2 {
> > > > + device_type = "cpu";
> > > > + compatible = "arm,cortex-a53";
> > > > + reg = <0x2>;
> > > > + enable-method = "psci";
> > > > + next-level-cache = <&A53_L2>;
> > > > + };
> > > > +
> > > > + A53_3: cpu at 3 {
> > > > + device_type = "cpu";
> > > > + compatible = "arm,cortex-a53";
> > > > + reg = <0x3>;
> > > > + enable-method = "psci";
> > > > + next-level-cache = <&A53_L2>;
> > > > + };
> > > > +
> > > > + A53_L2: l2-cache0 {
> > > > + compatible = "cache";
> > > > + };
> > > > + };
> > > > +
> > > > + memory at 40000000 {
> > > > + device_type = "memory";
> > > > + reg = <0x0 0x40000000 0 0x80000000>;
> > > > + };
> > > > +
> > > > + clocks {
> > > > + #address-cells = <1>;
> > > > + #size-cells = <0>;
> > > > +
> > > > + osc_32k: clock at 0 {
> > > > + compatible = "fixed-clock";
> > > > + reg = <0>;
> > > > + #clock-cells = <0>;
> > > > + clock-frequency = <32768>;
> > > > + clock-output-names = "osc_32k";
> > > > + };
> > > > +
> > > > + osc_24m: clock at 1 {
> > > > + compatible = "fixed-clock";
> > > > + reg = <1>;
> > > > + #clock-cells = <0>;
> > > > + clock-frequency = <24000000>;
> > > > + clock-output-names = "osc_24m";
> > > > + };
> > > > +
> > > > + clk_ext1: clock at 2 {
> > > > + compatible = "fixed-clock";
> > > > + reg = <3>;
> > > > + #clock-cells = <0>;
> > > > + clock-frequency = <133000000>;
> > > > + clock-output-names = "clk_ext1";
> > > > + };
> > > > +
> > > > + clk_ext2: clock at 3 {
> > > > + compatible = "fixed-clock";
> > > > + reg = <4>;
> > > > + #clock-cells = <0>;
> > > > + clock-frequency = <133000000>;
> > > > + clock-output-names = "clk_ext2";
> > > > + };
> > > > +
> > > > + clk_ext3: clock at 4 {
> > > > + compatible = "fixed-clock";
> > > > + reg = <5>;
> > > > + #clock-cells = <0>;
> > > > + clock-frequency = <133000000>;
> > > > + clock-output-names = "clk_ext3";
> > > > + };
> > > > +
> > > > + clk_ext4: clock at 5 {
> > > > + compatible = "fixed-clock";
> > > > + reg = <6>;
> > > > + #clock-cells = <0>;
> > > > + clock-frequency= <133000000>;
> > > > + clock-output-names = "clk_ext4";
> > > > + };
> > > > + };
> > > > +
> > > > + gic: interrupt-controller at 38800000 {
> > > > + compatible = "arm,gic-v3";
> > > > + reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */
> > > > + <0x0 0x38880000 0 0xC0000>; /* GICR
> > > > (RD_base + SGI_base) */
> > > > + #interrupt-cells = <3>;
> > > > + interrupt-controller;
> > > > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> > > > + };
> > > > +
> > > > + psci {
> > > > + compatible = "arm,psci-1.0";
> > > > + method = "smc";
> > > > + };
> > > > +
> > > > + pmu {
> > > > + compatible = "arm,armv8-pmuv3";
> > > > + interrupts = <GIC_PPI 7
> > > > + (GIC_CPU_MASK_SIMPLE(6) |
> > > > IRQ_TYPE_LEVEL_HIGH)>;
> > > > + interrupt-affinity = <&A53_0>, <&A53_1>,
> > > > <&A53_2>, <&A53_3>;
> > > > + };
> > > > +
> > > > + timer {
> > > > + compatible = "arm,armv8-timer";
> > > > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6)
> > > > | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
> > > > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6)
> > > > | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
> > > > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6)
> > > > | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
> > > > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6)
> > > > | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
> > > > + clock-frequency = <8000000>;
> > > > + arm,no-tick-in-suspend;
> > > > + };
> > > > +
> > > > + soc at 0 {
> > > > + compatible = "simple-bus";
> > > > + #address-cells = <2>;
> > > > + #size-cells = <2>;
> > > > + ranges;
> > > > +
> > > > + aips1: bus at 30000000 {
> > > > + compatible = "fsl,aips-bus",
> > > > "simple-bus";
> > > > + #address-cells = <2>;
> > > > + #size-cells = <2>;
> > > > + reg = <0x0 0x30000000 0x0 0x400000>;
> > > > + ranges;
> > > > +
> > > > + gpio1: gpio at 30200000 {
> > > > + compatible = "fsl,imx8mm-gpio",
> > > > "fsl,imx35-gpio";
> > > > + reg = <0x0 0x30200000 0x0
> > > > 0x10000>;
> > > > + interrupts = <GIC_SPI 64
> > > > IRQ_TYPE_LEVEL_HIGH>,
> > > > + <GIC_SPI 65
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + gpio-controller;
> > > > + #gpio-cells = <2>;
> > > > + interrupt-controller;
> > > > + #interrupt-cells = <2>;
> > > > + };
> > > > +
> > > > + gpio2: gpio at 30210000 {
> > > > + compatible = "fsl,imx8mm-gpio",
> > > > "fsl,imx35-gpio";
> > > > + reg = <0x0 0x30210000 0x0
> > > > 0x10000>;
> > > > + interrupts = <GIC_SPI 66
> > > > IRQ_TYPE_LEVEL_HIGH>,
> > > > + <GIC_SPI 67
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + gpio-controller;
> > > > + #gpio-cells = <2>;
> > > > + interrupt-controller;
> > > > + #interrupt-cells = <2>;
> > > > + };
> > > > +
> > > > + gpio3: gpio at 30220000 {
> > > > + compatible = "fsl,imx8mm-gpio",
> > > > "fsl,imx35-gpio";
> > > > + reg = <0x0 0x30220000 0x0
> > > > 0x10000>;
> > > > + interrupts = <GIC_SPI 68
> > > > IRQ_TYPE_LEVEL_HIGH>,
> > > > + <GIC_SPI 69
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + gpio-controller;
> > > > + #gpio-cells = <2>;
> > > > + interrupt-controller;
> > > > + #interrupt-cells = <2>;
> > > > + };
> > > > +
> > > > + gpio4: gpio at 30230000 {
> > > > + compatible = "fsl,imx8mm-gpio",
> > > > "fsl,imx35-gpio";
> > > > + reg = <0x0 0x30230000 0x0
> > > > 0x10000>;
> > > > + interrupts = <GIC_SPI 70
> > > > IRQ_TYPE_LEVEL_HIGH>,
> > > > + <GIC_SPI 71
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + gpio-controller;
> > > > + #gpio-cells = <2>;
> > > > + interrupt-controller;
> > > > + #interrupt-cells = <2>;
> > > > + };
> > > > +
> > > > + gpio5: gpio at 30240000 {
> > > > + compatible = "fsl,imx8mm-gpio",
> > > > "fsl,imx35-gpio";
> > > > + reg = <0x0 0x30240000 0x0
> > > > 0x10000>;
> > > > + interrupts = <GIC_SPI 72
> > > > IRQ_TYPE_LEVEL_HIGH>,
> > > > + <GIC_SPI 73
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + gpio-controller;
> > > > + #gpio-cells = <2>;
> > > > + interrupt-controller;
> > > > + #interrupt-cells = <2>;
> > > > + };
> > > > +
> > > > + wdog1: wdog at 30280000 {
> > > > + compatible = "fsl,imx21-wdt";
> > > > + reg = <0 0x30280000 0 0x10000>;
> > > > + interrupts = <GIC_SPI 78
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk
> > > > IMX8MM_CLK_WDOG1_ROOT>;
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + wdog2: wdog at 30290000 {
> > > > + compatible = "fsl,imx21-wdt";
> > > > + reg = <0 0x30290000 0 0x10000>;
> > > > + interrupts = <GIC_SPI 79
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk
> > > > IMX8MM_CLK_WDOG2_ROOT>;
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + wdog3: wdog at 302a0000 {
> > > > + compatible = "fsl,imx21-wdt";
> > > > + reg = <0 0x302a0000 0 0x10000>;
> > > > + interrupts = <GIC_SPI 10
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk
> > > > IMX8MM_CLK_WDOG3_ROOT>;
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + sdma2: dma-controller at 302c0000 {
> > > > + compatible = "fsl,imx8mq-sdma",
> > > > "fsl,imx7d-sdma";
> > > > + reg = <0x0 0x302c0000 0x0
> > > > 0x10000>;
> > > > + interrupts = <GIC_SPI 103
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk
> > > > IMX8MM_CLK_SDMA2_ROOT>,
> > > > + <&clk
> > > > IMX8MM_CLK_SDMA2_ROOT>;
> > > > + clock-names = "ipg", "ahb";
> > > > + #dma-cells = <3>;
> > > > + fsl,sdma-ram-script-name =
> > > > "imx/sdma/sdma-imx7d.bin";
> > > > + fsl,ratio-1-1;
> > > > + status = "okay";
> > > > + };
> > > > +
> > > > + sdma3: dma-controller at 302b0000 {
> > > > + compatible = "fsl,imx8mq-sdma",
> > > > "fsl,imx7d-sdma";
> > > > + reg = <0x0 0x302b0000 0x0
> > > > 0x10000>;
> > > > + interrupts = <GIC_SPI 34
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk
> > > > IMX8MM_CLK_SDMA3_ROOT>,
> > > > + <&clk IMX8MM_CLK_SDMA3_ROOT>;
> > > > + clock-names = "ipg", "ahb";
> > > > + #dma-cells = <3>;
> > > > + fsl,sdma-ram-script-name =
> > > > "imx/sdma/sdma-imx7d.bin";
> > > > + fsl,ratio-1-1;
> > > > + status = "okay";
> > > > + };
> > > > +
> > > > + iomuxc: pinctrl at 30330000 {
> > > > + compatible = "fsl,imx8mm-iomuxc";
> > > > + reg = <0x0 0x30330000 0x0
> > > > 0x10000>;
> > > > + };
> > > > +
> > > > + gpr: iomuxc-gpr at 30340000 {
> > > > + compatible =
> > > > "fsl,imx8mm-iomuxc-gpr", "syscon";
> > > > + reg = <0x0 0x30340000 0x0
> > > > 0x10000>;
> > > > + };
> > > > +
> > > > + ocotp: ocotp-ctrl at 30350000 {
> > > > + compatible = "fsl,imx8mq-ocotp",
> > > > "fsl,imx7d-ocotp", "syscon";
> > > > + reg = <0 0x30350000 0 0x10000>;
> > > > + clocks = <&clk
> > > > IMX8MM_CLK_OCOTP_ROOT>;
> > > > + /* For nvmem subnodes */
> > > > + #address-cells = <1>;
> > > > + #size-cells = <1>;
> > > > + };
> > > > +
> > > > + anatop: anatop at 30360000 {
> > > > + compatible = "fsl,imx8mm-anatop",
> > > > "syscon", "simple-bus";
> > > > + reg = <0x0 0x30360000 0x0
> > > > 0x10000>;
> > > > + };
> > > > +
> > > > + snvs: snvs at 30370000 {
> > > > + compatible =
> > > > "fsl,sec-v4.0-mon","syscon", "simple-mfd";
> > > > + reg = <0x0 0x30370000 0x0
> > > > 0x10000>; +
> > > > + snvs_rtc: snvs-rtc-lp{
> > > > + compatible =
> > > > "fsl,sec-v4.0-mon-rtc-lp";
> > > > + regmap =<&snvs>;
> > > > + offset = <0x34>;
> > > > + interrupts = <GIC_SPI
> > > > 19 IRQ_TYPE_LEVEL_HIGH>,
> > > > + <GIC_SPI
> > > > 20 IRQ_TYPE_LEVEL_HIGH>;
> > > > + };
> > > > +
> > > > + snvs_pwrkey: snvs-powerkey {
> > > > + compatible =
> > > > "fsl,sec-v4.0-pwrkey";
> > > > + regmap = <&snvs>;
> > > > + interrupts = <GIC_SPI 4
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + linux,keycode =
> > > > <KEY_POWER>;
> > > > + wakeup-source;
> > > > + };
> > > > + };
> > > > +
> > > > + clk: clock-controller at 30380000 {
> > > > + compatible = "fsl,imx8mm-ccm";
> > > > + reg = <0x0 0x30380000 0x0
> > > > 0x10000>;
> > > > + #clock-cells = <1>;
> > > > + clocks = <&osc_32k>, <&osc_24m>,
> > > > <&clk_ext1>, <&clk_ext2>,
> > > > + <&clk_ext3>,
> > > > <&clk_ext4>;
> > > > + clock-names = "osc_32k",
> > > > "osc_24m", "clk_ext1", "clk_ext2",
> > > > + "clk_ext3",
> > > > "clk_ext4";
> > > > + };
> > > > +
> > > > + src: src at 30390000 {
> > > > + compatible = "fsl,imx8mm-src",
> > > > "syscon";
> > > > + reg = <0x0 0x30390000 0x0
> > > > 0x10000>;
> > > > + interrupts = <GIC_SPI 89
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + #reset-cells = <1>;
> > > > + };
> > > > +
> > > > + gpc: gpc at 303a0000 {
> > > > + compatible = "fsl,imx8mm-gpc",
> > > > "syscon";
> > > > + reg = <0x0 0x303a0000 0x0
> > > > 0x10000>;
> > > > + interrupt-controller;
> > > > + interrupts = <GIC_SPI 87
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + #interrupt-cells = <3>;
> > > > + };
> > > > + };
> > > > +
> > > > + aips2: bus at 30400000 {
> > > > + compatible = "fsl,aips-bus",
> > > > "simple-bus";
> > > > + #address-cells = <2>;
> > > > + #size-cells = <2>;
> > > > + reg = <0x0 0x30400000 0x0 0x400000>;
> > > > + ranges;
> > > > +
> > > > + pwm1: pwm at 30660000 {
> > > > + compatible = "fsl,imx8mm-pwm",
> > > > "fsl,imx27-pwm";
> > > > + reg = <0x0 0x30660000 0x0
> > > > 0x10000>;
> > > > + interrupts = <GIC_SPI 81
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk
> > > > IMX8MM_CLK_PWM1_ROOT>,
> > > > + <&clk
> > > > IMX8MM_CLK_PWM1_ROOT>;
> > > > + clock-names = "ipg", "per";
> > > > + #pwm-cells = <2>;
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + pwm2: pwm at 30670000 {
> > > > + compatible = "fsl,imx8mm-pwm",
> > > > "fsl,imx27-pwm";
> > > > + reg = <0x0 0x30670000 0x0
> > > > 0x10000>;
> > > > + interrupts = <GIC_SPI 82
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk
> > > > IMX8MM_CLK_PWM2_ROOT>,
> > > > + <&clk
> > > > IMX8MM_CLK_PWM2_ROOT>;
> > > > + clock-names = "ipg", "per";
> > > > + #pwm-cells = <2>;
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + pwm3: pwm at 30680000 {
> > > > + compatible = "fsl,imx8mm-pwm",
> > > > "fsl,imx27-pwm";
> > > > + reg = <0x0 0x30680000 0x0
> > > > 0x10000>;
> > > > + interrupts = <GIC_SPI 83
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk
> > > > IMX8MM_CLK_PWM3_ROOT>,
> > > > + <&clk
> > > > IMX8MM_CLK_PWM3_ROOT>;
> > > > + clock-names = "ipg", "per";
> > > > + #pwm-cells = <2>;
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + pwm4: pwm at 30690000 {
> > > > + compatible = "fsl,imx8mm-pwm",
> > > > "fsl,imx27-pwm";
> > > > + reg = <0x0 0x30690000 0x0
> > > > 0x10000>;
> > > > + interrupts = <GIC_SPI 84
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk
> > > > IMX8MM_CLK_PWM4_ROOT>,
> > > > + <&clk
> > > > IMX8MM_CLK_PWM4_ROOT>;
> > > > + clock-names = "ipg", "per";
> > > > + #pwm-cells = <2>;
> > > > + status = "disabled";
> > > > + };
> > > > + };
> > > > +
> > > > + aips3: bus at 30800000 {
> > > > + compatible = "fsl,aips-bus",
> > > > "simple-bus";
> > > > + #address-cells = <2>;
> > > > + #size-cells = <2>;
> > > > + reg = <0x0 0x30800000 0x0 0x400000>;
> > > > + ranges;
> > > > +
> > > > + ecspi1: ecspi at 30820000 {
> > > > + #address-cells = <1>;
> > > > + #size-cells = <0>;
> > > > + compatible = "fsl,imx8mm-ecspi",
> > > > "fsl,imx51-ecspi";
> > > > + reg = <0x0 0x30820000 0x0
> > > > 0x10000>;
> > > > + interrupts = <GIC_SPI 31
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk
> > > > IMX8MM_CLK_ECSPI1_ROOT>,
> > > > + <&clk
> > > > IMX8MM_CLK_ECSPI1_ROOT>;
> > > > + clock-names = "ipg", "per";
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + ecspi2: ecspi at 30830000 {
> > > > + #address-cells = <1>;
> > > > + #size-cells = <0>;
> > > > + compatible = "fsl,imx8mm-ecspi",
> > > > "fsl,imx51-ecspi";
> > > > + reg = <0x0 0x30830000 0x0
> > > > 0x10000>;
> > > > + interrupts = <GIC_SPI 32
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk
> > > > IMX8MM_CLK_ECSPI2_ROOT>,
> > > > + <&clk
> > > > IMX8MM_CLK_ECSPI2_ROOT>;
> > > > + clock-names = "ipg", "per";
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + ecspi3: ecspi at 30840000 {
> > > > + #address-cells = <1>;
> > > > + #size-cells = <0>;
> > > > + compatible = "fsl,imx8mm-ecspi",
> > > > "fsl,imx51-ecspi";
> > > > + reg = <0x0 0x30840000 0x0
> > > > 0x10000>;
> > > > + interrupts = <GIC_SPI 33
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk
> > > > IMX8MM_CLK_ECSPI3_ROOT>,
> > > > + <&clk
> > > > IMX8MM_CLK_ECSPI3_ROOT>;
> > > > + clock-names = "ipg", "per";
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + uart1: serial at 30860000 {
> > > > + compatible = "fsl,imx8mm-uart",
> > > > + "fsl,imx6q-uart",
> > > > "fsl,imx21-uart";
> > > > + reg = <0x0 0x30860000 0x0
> > > > 0x10000>;
> > > > + interrupts = <GIC_SPI 26
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk
> > > > IMX8MM_CLK_UART1_ROOT>,
> > > > + <&clk
> > > > IMX8MM_CLK_UART1_ROOT>;
> > > > + clock-names = "ipg", "per";
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + uart3: serial at 30880000 {
> > > > + compatible = "fsl,imx8mm-uart",
> > > > + "fsl,imx6q-uart",
> > > > "fsl,imx21-uart";
> > > > + reg = <0x0 0x30880000 0x0
> > > > 0x10000>;
> > > > + interrupts = <GIC_SPI 28
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk
> > > > IMX8MM_CLK_UART3_ROOT>,
> > > > + <&clk
> > > > IMX8MM_CLK_UART3_ROOT>;
> > > > + clock-names = "ipg", "per";
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + uart2: serial at 30890000 {
> > > > + compatible = "fsl,imx8mm-uart",
> > > > + "fsl,imx6q-uart",
> > > > "fsl,imx21-uart";
> > > > + reg = <0x0 0x30890000 0x0
> > > > 0x10000>;
> > > > + interrupts = <GIC_SPI 27
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk
> > > > IMX8MM_CLK_UART2_ROOT>,
> > > > + <&clk
> > > > IMX8MM_CLK_UART2_ROOT>;
> > > > + clock-names = "ipg", "per";
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + i2c1: i2c at 30a20000 {
> > > > + #address-cells = <1>;
> > > > + #size-cells = <0>;
> > > > + compatible = "fsl,imx8mm-i2c",
> > > > "fsl,imx21-i2c";
> > > > + reg = <0x0 0x30a20000 0x0
> > > > 0x10000>;
> > > > + interrupts = <GIC_SPI 35
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk
> > > > IMX8MM_CLK_I2C1_ROOT>;
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + i2c2: i2c at 30a30000 {
> > > > + #address-cells = <1>;
> > > > + #size-cells = <0>;
> > > > + compatible = "fsl,imx8mm-i2c",
> > > > "fsl,imx21-i2c";
> > > > + reg = <0x0 0x30a30000 0x0
> > > > 0x10000>;
> > > > + interrupts = <GIC_SPI 36
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk
> > > > IMX8MM_CLK_I2C2_ROOT>;
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + i2c3: i2c at 30a40000 {
> > > > + #address-cells = <1>;
> > > > + #size-cells = <0>;
> > > > + compatible = "fsl,imx8mm-i2c",
> > > > "fsl,imx21-i2c";
> > > > + reg = <0x0 0x30a40000 0x0
> > > > 0x10000>;
> > > > + interrupts = <GIC_SPI 37
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk
> > > > IMX8MM_CLK_I2C3_ROOT>;
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + i2c4: i2c at 30a50000 {
> > > > + #address-cells = <1>;
> > > > + #size-cells = <0>;
> > > > + compatible = "fsl,imx8mm-i2c",
> > > > "fsl,imx21-i2c";
> > > > + reg = <0x0 0x30a50000 0x0
> > > > 0x10000>;
> > > > + interrupts = <GIC_SPI 38
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk
> > > > IMX8MM_CLK_I2C4_ROOT>;
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + uart4: serial at 30a60000 {
> > > > + compatible = "fsl,imx8mq-uart",
> > > > + "fsl,imx6q-uart",
> > > > "fsl,imx21-uart";
> > > > + reg = <0x0 0x30a60000 0x0
> > > > 0x10000>;
> > > > + interrupts = <GIC_SPI 29
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk
> > > > IMX8MM_CLK_UART4_ROOT>,
> > > > + <&clk
> > > > IMX8MM_CLK_UART4_ROOT>;
> > > > + clock-names = "ipg", "per";
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + usdhc1: mmc at 30b40000 {
> > > > + compatible = "fsl,imx8mq-usdhc",
> > > > "fsl,imx7d-usdhc";
> > > > + reg = <0x0 0x30b40000 0x0
> > > > 0x10000>;
> > > > + interrupts = <GIC_SPI 22
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk IMX8MM_CLK_DUMMY>,
> > > > + <&clk
> > > > IMX8MM_CLK_NAND_USDHC_BUS>,
> > > > + <&clk
> > > > IMX8MM_CLK_USDHC1_ROOT>;
> > > > + clock-names = "ipg", "ahb",
> > > > "per";
> > > > + assigned-clocks = <&clk
> > > > IMX8MM_CLK_USDHC1>;
> > > > + assigned-clock-rates =
> > > > <400000000>;
> > > > + fsl,tuning-start-tap = <20>;
> > > > + fsl,tuning-step= <2>;
> > > > + bus-width = <4>;
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + usdhc2: mmc at 30b50000 {
> > > > + compatible = "fsl,imx8mq-usdhc",
> > > > "fsl,imx7d-usdhc";
> > > > + reg = <0x0 0x30b50000 0x0
> > > > 0x10000>;
> > > > + interrupts = <GIC_SPI 23
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk IMX8MM_CLK_DUMMY>,
> > > > + <&clk
> > > > IMX8MM_CLK_NAND_USDHC_BUS>,
> > > > + <&clk
> > > > IMX8MM_CLK_USDHC2_ROOT>;
> > > > + clock-names = "ipg", "ahb",
> > > > "per";
> > > > + fsl,tuning-start-tap = <20>;
> > > > + fsl,tuning-step= <2>;
> > > > + bus-width = <4>;
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + usdhc3: mmc at 30b60000 {
> > > > + compatible = "fsl,imx8mq-usdhc",
> > > > "fsl,imx7d-usdhc";
> > > > + reg = <0x0 0x30b60000 0x0
> > > > 0x10000>;
> > > > + interrupts = <GIC_SPI 24
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk IMX8MM_CLK_DUMMY>,
> > > > + <&clk
> > > > IMX8MM_CLK_NAND_USDHC_BUS>,
> > > > + <&clk
> > > > IMX8MM_CLK_USDHC3_ROOT>;
> > > > + clock-names = "ipg", "ahb",
> > > > "per";
> > > > + assigned-clocks = <&clk
> > > > IMX8MM_CLK_USDHC3_ROOT>;
> > > > + assigned-clock-rates =
> > > > <400000000>;
> > > > + fsl,tuning-start-tap = <20>;
> > > > + fsl,tuning-step= <2>;
> > > > + bus-width = <4>;
> > > > + status = "disabled";
> > > > + };
> > > > + };
> > > > + };
> > > > +};
> > > > diff --git a/arch/arm/mach-imx/imx8m/Kconfig
> > > > b/arch/arm/mach-imx/imx8m/Kconfig index 35c978e863..f520075875
> > > 100644
> > > > --- a/arch/arm/mach-imx/imx8m/Kconfig
> > > > +++ b/arch/arm/mach-imx/imx8m/Kconfig
> > > > @@ -24,8 +24,15 @@ config TARGET_IMX8MQ_EVK
> > > > select IMX8MQ
> > > > select IMX8M_LPDDR4
> > > >
> > > > +config TARGET_IMX8MM_EVK
> > > > + bool "imx8mm LPDDR4 EVK board"
> > > > + select IMX8MM
> > > > + select SUPPORT_SPL
> > > > + select IMX8M_LPDDR4
> > >
> > > Here you shall put the select DM_{UART,USDHC, etc}
> > >
> > > > +
> > > > endchoice
> > > >
> > > > source "board/freescale/imx8mq_evk/Kconfig"
> > > > +source "board/freescale/imx8mm_evk/Kconfig"
> > > >
> > > > endif
> > > > diff --git a/board/freescale/imx8mm_evk/Kconfig
> > > > b/board/freescale/imx8mm_evk/Kconfig new file mode 100644
> > > > index 0000000000..299691a619
> > > > --- /dev/null
> > > > +++ b/board/freescale/imx8mm_evk/Kconfig
> > > > @@ -0,0 +1,12 @@
> > > > +if TARGET_IMX8MM_EVK
> > > > +
> > > > +config SYS_BOARD
> > > > + default "imx8mm_evk"
> > > > +
> > > > +config SYS_VENDOR
> > > > + default "freescale"
> > > > +
> > > > +config SYS_CONFIG_NAME
> > > > + default "imx8mm_evk"
> > > > +
> > > > +endif
> > > > diff --git a/board/freescale/imx8mm_evk/MAINTAINERS
> > > > b/board/freescale/imx8mm_evk/MAINTAINERS new file mode 100644
> > > > index 0000000000..b031bb0674
> > > > --- /dev/null
> > > > +++ b/board/freescale/imx8mm_evk/MAINTAINERS
> > > > @@ -0,0 +1,6 @@
> > > > +i.MX8MM EVK BOARD
> > > > +M: Peng Fan <peng.fan@nxp.com>
> > > > +S: Maintained
> > > > +F: board/freescale/imx8mm_evk/
> > > > +F: include/configs/imx8mm_evk.h
> > > > +F: configs/imx8mm_evk_defconfig
> > > > diff --git a/board/freescale/imx8mm_evk/Makefile
> > > > b/board/freescale/imx8mm_evk/Makefile new file mode 100644
> > > > index 0000000000..1db7b62caf
> > > > --- /dev/null
> > > > +++ b/board/freescale/imx8mm_evk/Makefile
> > > > @@ -0,0 +1,12 @@
> > > > +#
> > > > +# Copyright 2018 NXP
> > > > +#
> > > > +# SPDX-License-Identifier: GPL-2.0+
> > > > +#
> > > > +
> > > > +obj-y += imx8mm_evk.o
> > > > +
> > > > +ifdef CONFIG_SPL_BUILD
> > > > +obj-y += spl.o
> > > > +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
> > > > +endif
> > > > diff --git a/board/freescale/imx8mm_evk/imx8mm_evk.c
> > > > b/board/freescale/imx8mm_evk/imx8mm_evk.c new file mode 100644
> > > > index 0000000000..a681aca04d
> > > > --- /dev/null
> > > > +++ b/board/freescale/imx8mm_evk/imx8mm_evk.c
> > > > @@ -0,0 +1,144 @@
> > > > +// SPDX-License-Identifier: GPL-2.0+
> > > > +/*
> > > > + * Copyright 2018 NXP
> > > > + */
> > > > +
> > > > +#include <common.h>
> > > > +#include <malloc.h>
> > > > +#include <errno.h>
> > > > +#include <asm/io.h>
> > > > +#include <miiphy.h>
> > > > +#include <netdev.h>
> > > > +#include <asm/mach-imx/iomux-v3.h>
> > > > +#include <asm-generic/gpio.h>
> > > > +#include <fsl_esdhc.h>
> > > > +#include <mmc.h>
> > > > +#include <asm/arch/imx8mm_pins.h>
> > > > +#include <asm/arch/sys_proto.h>
> > > > +#include <asm/mach-imx/gpio.h>
> > > > +#include <asm/mach-imx/mxc_i2c.h>
> > > > +#include <asm/arch/clock.h>
> > > > +#include <spl.h>
> > > > +#include <asm/mach-imx/dma.h>
> > > > +
> > > > +DECLARE_GLOBAL_DATA_PTR;
> > > > +
> > > > +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
> > > > +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE |
> > > > PAD_CTL_PUE | PAD_CTL_PE) +
> > > > +static iomux_v3_cfg_t const uart_pads[] = {
> > > > + IMX8MM_PAD_UART2_RXD_UART2_RX |
> > > MUX_PAD_CTRL(UART_PAD_CTRL),
> > > > + IMX8MM_PAD_UART2_TXD_UART2_TX |
> > > MUX_PAD_CTRL(UART_PAD_CTRL),
> > > > +};
> > > > +
> > > > +static iomux_v3_cfg_t const wdog_pads[] = {
> > > > + IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B |
> > > > MUX_PAD_CTRL(WDOG_PAD_CTRL), +};
> > > > +
> > > > +int board_early_init_f(void)
> > > > +{
> > > > + struct wdog_regs *wdog = (struct wdog_regs
> > > > *)WDOG1_BASE_ADDR; +
> > > > + imx_iomux_v3_setup_multiple_pads(wdog_pads,
> > > > ARRAY_SIZE(wdog_pads)); +
> > > > + set_wdog_reset(wdog);
> > > > +
> > > > + imx_iomux_v3_setup_multiple_pads(uart_pads,
> > > > ARRAY_SIZE(uart_pads)); +
> > > > + return 0;
> > > > +}
> > > > +
> > > > +#ifdef CONFIG_BOARD_POSTCLK_INIT
> > > > +int board_postclk_init(void)
> > > > +{
> > > > + /* TODO */
> > > > + return 0;
> > > > +}
> > > > +#endif
> > > > +
> > > > +int dram_init(void)
> > > > +{
> > > > + /* rom_pointer[1] contains the size of TEE occupies */
> > > > + if (rom_pointer[1])
> > > > + gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
> > > > + else
> > > > + gd->ram_size = PHYS_SDRAM_SIZE;
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > +#ifdef CONFIG_OF_BOARD_SETUP
> > > > +int ft_board_setup(void *blob, bd_t *bd)
> > > ^^^ - fdt_board_setup ?
> > > > +{
> > > > + return 0;
> > > > +}
> > > > +#endif
> > > > +
> > > > +#ifdef CONFIG_FEC_MXC
> > > > +#define FEC_RST_PAD IMX_GPIO_NR(4, 22)
> > > > +static iomux_v3_cfg_t const fec1_rst_pads[] = {
> > > > + IMX8MM_PAD_SAI2_RXC_GPIO4_IO22 |
> > > MUX_PAD_CTRL(NO_PAD_CTRL),
> > >
> > > This shall be done with fsl_fec.c DM driver - there is support for
> > > adding reset pin (to dts).
> > >
> > > > +};
> > > > +
> > > > +static void setup_iomux_fec(void)
> > > > +{
> > > > + imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
> > > > +
> > > > ARRAY_SIZE(fec1_rst_pads)); +
> > > > + gpio_request(FEC_RST_PAD, "fec1_rst");
> > > > + gpio_direction_output(FEC_RST_PAD, 0);
> > > > + udelay(500);
> > > > + gpio_direction_output(FEC_RST_PAD, 1);
> > > > +}
> > >
> > > This shall be replaced with DM/DTS of the fsl_fec.c driver. Please
> > > also note that there are (at least on imx6q) some timing issues
> > > when we move the code to DM/DTS (some delay is needed).
> > >
> > > > +
> > > > +static int setup_fec(void)
> > > > +{
> > > > + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
> > > > + = (struct iomuxc_gpr_base_regs
> > > > *)IOMUXC_GPR_BASE_ADDR; +
> > > > + setup_iomux_fec();
> > > > +
> > > > + /* Use 125M anatop REF_CLK1 for ENET1, not from external
> > > > */
> > > > + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
> > > > +
> > > > IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT, 0);
> > > > + return set_clk_enet(ENET_125MHZ);
> > > > +}
> > > > +
> > > > +int board_phy_config(struct phy_device *phydev)
> > > > +{
> > > > + /* enable rgmii rxc skew and phy mode select to RGMII
> > > > copper */
> > > > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
> > > > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
> > > > +
> > > > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
> > > > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
> > > > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
> > > > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
> > > > +
> > > > + if (phydev->drv->config)
> > > > + phydev->drv->config(phydev);
> > > > + return 0;
> > >
> > > Which PHY do you use? E.g. KSZ... support passing those values via
> > > DTS.
> > > > +}
> > > > +#endif
> > > > +
> > > > +int board_init(void)
> > > > +{
> > > > +#ifdef CONFIG_FEC_MXC
> > > > + setup_fec();
> > > > +#endif
> > > > + return 0;
> > > > +}
> > > > +
> > > > +int board_mmc_get_env_dev(int devno)
> > > > +{
> > > > + return devno - 1;
> > > > +}
> > > > +
> > > > +int board_late_init(void)
> > > > +{
> > > > +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> > > > + env_set("board_name", "EVK");
> > > > + env_set("board_rev", "iMX8MM");
> > > > +#endif
> > > > + return 0;
> > > > +}
> > > > diff --git a/board/freescale/imx8mm_evk/lpddr4_timing.c
> > > > b/board/freescale/imx8mm_evk/lpddr4_timing.c new file mode 100644
> > > > index 0000000000..4bade5bf74
> > > > --- /dev/null
> > > > +++ b/board/freescale/imx8mm_evk/lpddr4_timing.c
> > > > @@ -0,0 +1,1980 @@
> > > > +// SPDX-License-Identifier: GPL-2.0+
> > > > +/*
> > > > + * Copyright 2018 NXP
> > >
> > > Author is missing.
> > >
> > > > + */
> > > > +
> > > > +#include <linux/kernel.h>
> > > > +#include <common.h>
> > > > +#include <asm/arch/ddr.h>
> > > > +#include <asm/arch/lpddr4_define.h>
> > > > +
> > > > +struct dram_cfg_param lpddr4_ddrc_cfg[] = {
> > > > + /* Start to config, default 3200mbps */
> > > > + { DDRC_DBG1(0), 0x00000001 },
> > > > + { DDRC_PWRCTL(0), 0x00000001 },
> > > > + { DDRC_MSTR(0), 0xa1080020 },
> > > > + { DDRC_RFSHTMG(0), 0x005b00d2 },
> > > > + { DDRC_INIT0(0), 0xC003061B },
> > > > + { DDRC_INIT1(0), 0x009D0000 },
> > > > + { DDRC_INIT3(0), 0x00D4002D },
> > > > + { DDRC_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 },
> > > > + { DDRC_INIT6(0), 0x0066004a },
> > > > + { DDRC_INIT7(0), 0x0006004a },
> > > > +
> > > > + { DDRC_DRAMTMG0(0), 0x1A201B22 },
> > > > + { DDRC_DRAMTMG1(0), 0x00060633 },
> > > > + { DDRC_DRAMTMG3(0), 0x00C0C000 },
> > > > + { DDRC_DRAMTMG4(0), 0x0F04080F },
> > > > + { DDRC_DRAMTMG5(0), 0x02040C0C },
> > > > + { DDRC_DRAMTMG6(0), 0x01010007 },
> > > > + { DDRC_DRAMTMG7(0), 0x00000401 },
> > > > + { DDRC_DRAMTMG12(0), 0x00020600 },
> > > > + { DDRC_DRAMTMG13(0), 0x0C100002 },
> > > > + { DDRC_DRAMTMG14(0), 0x000000E6 },
> > > > + { DDRC_DRAMTMG17(0), 0x00A00050 },
> > > > +
> > > > + { DDRC_ZQCTL0(0), 0x03200018 },
> > > > + { DDRC_ZQCTL1(0), 0x028061A8 },
> > > > + { DDRC_ZQCTL2(0), 0x00000000 },
> > > > +
> > > > + { DDRC_DFITMG0(0), 0x0497820A },
> > > > + { DDRC_DFITMG2(0), 0x0000170A },
> > > > + { DDRC_DRAMTMG2(0), 0x070E171a },
> > > > + { DDRC_DBICTL(0), 0x00000001 },
> > > > +
> > > > + { DDRC_DFITMG1(0), 0x00080303 },
> > > > + { DDRC_DFIUPD0(0), 0xE0400018 },
> > > > + { DDRC_DFIUPD1(0), 0x00DF00E4 },
> > > > + { DDRC_DFIUPD2(0), 0x80000000 },
> > > > + { DDRC_DFIMISC(0), 0x00000011 },
> > > > +
> > > > + { DDRC_DFIPHYMSTR(0), 0x00000000 },
> > > > + { DDRC_RANKCTL(0), 0x00000c99 },
> > > > +
> > > > + /* address mapping */
> > > > + { DDRC_ADDRMAP0(0), 0x0000001f },
> > > > + { DDRC_ADDRMAP1(0), 0x00080808 },
> > > > + { DDRC_ADDRMAP2(0), 0x00000000 },
> > > > + { DDRC_ADDRMAP3(0), 0x00000000 },
> > > > + { DDRC_ADDRMAP4(0), 0x00001f1f },
> > > > + { DDRC_ADDRMAP5(0), 0x07070707 },
> > > > + { DDRC_ADDRMAP6(0), 0x07070707 },
> > > > + { DDRC_ADDRMAP7(0), 0x00000f0f },
> > > > +
> > > > + /* performance setting */
> > > > + { DDRC_SCHED(0), 0x29001701 },
> > > > + { DDRC_SCHED1(0), 0x0000002c },
> > > > + { DDRC_PERFHPR1(0), 0x04000030 },
> > > > + { DDRC_PERFLPR1(0), 0x900093e7 },
> > > > + { DDRC_PERFWR1(0), 0x20005574 },
> > > > + { DDRC_PCCFG(0), 0x00000111 },
> > > > + { DDRC_PCFGW_0(0), 0x000072ff },
> > > > + { DDRC_PCFGQOS0_0(0), 0x02100e07 },
> > > > + { DDRC_PCFGQOS1_0(0), 0x00620096 },
> > > > + { DDRC_PCFGWQOS0_0(0), 0x01100e07 },
> > > > + { DDRC_PCFGWQOS1_0(0), 0x00c8012c },
> > > > +
> > > > + /* frequency P1&P2 */
> > > > + /* Frequency 1: 400mbps */
> > > > + { DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c },
> > > > + { DDRC_FREQ1_DRAMTMG1(0), 0x00030410 },
> > > > + { DDRC_FREQ1_DRAMTMG2(0), 0x0203090c },
> > > > + { DDRC_FREQ1_DRAMTMG3(0), 0x00505006 },
> > > > + { DDRC_FREQ1_DRAMTMG4(0), 0x05040305 },
> > > > + { DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504 },
> > > > + { DDRC_FREQ1_DRAMTMG6(0), 0x0a060004 },
> > > > + { DDRC_FREQ1_DRAMTMG7(0), 0x0000090e },
> > > > + { DDRC_FREQ1_DRAMTMG14(0), 0x00000032 },
> > > > + { DDRC_FREQ1_DRAMTMG15(0), 0x00000000 },
> > > > + { DDRC_FREQ1_DRAMTMG17(0), 0x0036001b },
> > > > + { DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1 },
> > > > + { DDRC_FREQ1_DFITMG0(0), 0x03818200 },
> > > > + { DDRC_FREQ1_DFITMG2(0), 0x00000000 },
> > > > + { DDRC_FREQ1_RFSHTMG(0), 0x000C001c },
> > > > + { DDRC_FREQ1_INIT3(0), 0x00840000 },
> > > > + { DDRC_FREQ1_INIT4(0), 0x00310000 },
> > > > + { DDRC_FREQ1_INIT6(0), 0x0066004a },
> > > > + { DDRC_FREQ1_INIT7(0), 0x0006004a },
> > > > +
> > > > + /* Frequency 2: 100mbps */
> > > > + { DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c },
> > > > + { DDRC_FREQ2_DRAMTMG1(0), 0x00030410 },
> > > > + { DDRC_FREQ2_DRAMTMG2(0), 0x0203090c },
> > > > + { DDRC_FREQ2_DRAMTMG3(0), 0x00505006 },
> > > > + { DDRC_FREQ2_DRAMTMG4(0), 0x05040305 },
> > > > + { DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504 },
> > > > + { DDRC_FREQ2_DRAMTMG6(0), 0x0a060004 },
> > > > + { DDRC_FREQ2_DRAMTMG7(0), 0x0000090e },
> > > > + { DDRC_FREQ2_DRAMTMG14(0), 0x00000032 },
> > > > + { DDRC_FREQ2_DRAMTMG17(0), 0x0036001b },
> > > > + { DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1 },
> > > > + { DDRC_FREQ2_DFITMG0(0), 0x03818200 },
> > > > + { DDRC_FREQ2_DFITMG2(0), 0x00000000 },
> > > > + { DDRC_FREQ2_RFSHTMG(0), 0x0003800c },
> > > > + { DDRC_FREQ2_RFSHTMG(0), 0x00030007 },
> > > > + { DDRC_FREQ2_INIT3(0), 0x00840000 },
> > > > + { DDRC_FREQ2_INIT4(0), 0x00310008 },
> > > > + { DDRC_FREQ2_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 },
> > > > + { DDRC_FREQ2_INIT6(0), 0x0066004a },
> > > > + { DDRC_FREQ2_INIT7(0), 0x0006004a },
> > > > +
> > > > + /* boot start point */
> > > > + { DDRC_MSTR2(0), 0x2 }, //DDRC_MSTR2
> > > > +};
> > > > +
> > > > +/* PHY Initialize Configuration */
> > > > +struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
> > > > + { 0x1005f, 0x1ff },
> > > > + { 0x1015f, 0x1ff },
> > > > + { 0x1105f, 0x1ff },
> > > > + { 0x1115f, 0x1ff },
> > > > + { 0x1205f, 0x1ff },
> > > > + { 0x1215f, 0x1ff },
> > > > + { 0x1305f, 0x1ff },
> > > > + { 0x1315f, 0x1ff },
> > > > +
> > > > + { 0x11005f, 0x1ff },
> > > > + { 0x11015f, 0x1ff },
> > > > + { 0x11105f, 0x1ff },
> > > > + { 0x11115f, 0x1ff },
> > > > + { 0x11205f, 0x1ff },
> > > > + { 0x11215f, 0x1ff },
> > > > + { 0x11305f, 0x1ff },
> > > > + { 0x11315f, 0x1ff },
> > > > +
> > > > + { 0x21005f, 0x1ff },
> > > > + { 0x21015f, 0x1ff },
> > > > + { 0x21105f, 0x1ff },
> > > > + { 0x21115f, 0x1ff },
> > > > + { 0x21205f, 0x1ff },
> > > > + { 0x21215f, 0x1ff },
> > > > + { 0x21305f, 0x1ff },
> > > > + { 0x21315f, 0x1ff },
> > > > +
> > > > + { 0x55, 0x1ff },
> > > > + { 0x1055, 0x1ff },
> > > > + { 0x2055, 0x1ff },
> > > > + { 0x3055, 0x1ff },
> > > > + { 0x4055, 0x1ff },
> > > > + { 0x5055, 0x1ff },
> > > > + { 0x6055, 0x1ff },
> > > > + { 0x7055, 0x1ff },
> > > > + { 0x8055, 0x1ff },
> > > > + { 0x9055, 0x1ff },
> > > > +
> > > > + { 0x200c5, 0x19 },
> > > > + { 0x1200c5, 0x7 },
> > > > + { 0x2200c5, 0x7 },
> > > > +
> > > > + { 0x2002e, 0x2 },
> > > > + { 0x12002e, 0x2 },
> > > > + { 0x22002e, 0x2 },
> > > > +
> > > > + { 0x90204, 0x0 },
> > > > + { 0x190204, 0x0 },
> > > > + { 0x290204, 0x0 },
> > > > +
> > > > + { 0x20024, 0xab },
> > > > + { 0x2003a, 0x0 },
> > > > +
> > > > + { 0x120024, 0xab },
> > > > + { 0x2003a, 0x0 },
> > > > +
> > > > + { 0x220024, 0xab },
> > > > + { 0x2003a, 0x0 },
> > > > +
> > > > + { 0x20056, 0x3 },
> > > > + { 0x120056, 0xa },
> > > > + { 0x220056, 0xa },
> > > > +
> > > > + { 0x1004d, 0xe00 },
> > > > + { 0x1014d, 0xe00 },
> > > > + { 0x1104d, 0xe00 },
> > > > + { 0x1114d, 0xe00 },
> > > > + { 0x1204d, 0xe00 },
> > > > + { 0x1214d, 0xe00 },
> > > > + { 0x1304d, 0xe00 },
> > > > + { 0x1314d, 0xe00 },
> > > > +
> > > > + { 0x11004d, 0xe00 },
> > > > + { 0x11014d, 0xe00 },
> > > > + { 0x11104d, 0xe00 },
> > > > + { 0x11114d, 0xe00 },
> > > > + { 0x11204d, 0xe00 },
> > > > + { 0x11214d, 0xe00 },
> > > > + { 0x11304d, 0xe00 },
> > > > + { 0x11314d, 0xe00 },
> > > > +
> > > > + { 0x21004d, 0xe00 },
> > > > + { 0x21014d, 0xe00 },
> > > > + { 0x21104d, 0xe00 },
> > > > + { 0x21114d, 0xe00 },
> > > > + { 0x21204d, 0xe00 },
> > > > + { 0x21214d, 0xe00 },
> > > > + { 0x21304d, 0xe00 },
> > > > + { 0x21314d, 0xe00 },
> > > > +
> > > > + { 0x10049, 0xfbe },
> > > > + { 0x10149, 0xfbe },
> > > > + { 0x11049, 0xfbe },
> > > > + { 0x11149, 0xfbe },
> > > > + { 0x12049, 0xfbe },
> > > > + { 0x12149, 0xfbe },
> > > > + { 0x13049, 0xfbe },
> > > > + { 0x13149, 0xfbe },
> > > > +
> > > > + { 0x110049, 0xfbe },
> > > > + { 0x110149, 0xfbe },
> > > > + { 0x111049, 0xfbe },
> > > > + { 0x111149, 0xfbe },
> > > > + { 0x112049, 0xfbe },
> > > > + { 0x112149, 0xfbe },
> > > > + { 0x113049, 0xfbe },
> > > > + { 0x113149, 0xfbe },
> > > > +
> > > > + { 0x210049, 0xfbe },
> > > > + { 0x210149, 0xfbe },
> > > > + { 0x211049, 0xfbe },
> > > > + { 0x211149, 0xfbe },
> > > > + { 0x212049, 0xfbe },
> > > > + { 0x212149, 0xfbe },
> > > > + { 0x213049, 0xfbe },
> > > > + { 0x213149, 0xfbe },
> > > > +
> > > > + { 0x43, 0x63 },
> > > > + { 0x1043, 0x63 },
> > > > + { 0x2043, 0x63 },
> > > > + { 0x3043, 0x63 },
> > > > + { 0x4043, 0x63 },
> > > > + { 0x5043, 0x63 },
> > > > + { 0x6043, 0x63 },
> > > > + { 0x7043, 0x63 },
> > > > + { 0x8043, 0x63 },
> > > > + { 0x9043, 0x63 },
> > > > +
> > > > + { 0x20018, 0x3 },
> > > > + { 0x20075, 0x4 },
> > > > + { 0x20050, 0x0 },
> > > > + { 0x20008, 0x2ee },
> > > > + { 0x120008, 0x64 },
> > > > + { 0x220008, 0x19 },
> > > > + { 0x20088, 0x9 },
> > > > +
> > > > + { 0x200b2, 0x1d4 },
> > > > + { 0x10043, 0x5a1 },
> > > > + { 0x10143, 0x5a1 },
> > > > + { 0x11043, 0x5a1 },
> > > > + { 0x11143, 0x5a1 },
> > > > + { 0x12043, 0x5a1 },
> > > > + { 0x12143, 0x5a1 },
> > > > + { 0x13043, 0x5a1 },
> > > > + { 0x13143, 0x5a1 },
> > > > +
> > > > + { 0x1200b2, 0xdc },
> > > > + { 0x110043, 0x5a1 },
> > > > + { 0x110143, 0x5a1 },
> > > > + { 0x111043, 0x5a1 },
> > > > + { 0x111143, 0x5a1 },
> > > > + { 0x112043, 0x5a1 },
> > > > + { 0x112143, 0x5a1 },
> > > > + { 0x113043, 0x5a1 },
> > > > + { 0x113143, 0x5a1 },
> > > > +
> > > > + { 0x2200b2, 0xdc },
> > > > + { 0x210043, 0x5a1 },
> > > > + { 0x210143, 0x5a1 },
> > > > + { 0x211043, 0x5a1 },
> > > > + { 0x211143, 0x5a1 },
> > > > + { 0x212043, 0x5a1 },
> > > > + { 0x212143, 0x5a1 },
> > > > + { 0x213043, 0x5a1 },
> > > > + { 0x213143, 0x5a1 },
> > > > +
> > > > + { 0x200fa, 0x1 },
> > > > + { 0x1200fa, 0x1 },
> > > > + { 0x2200fa, 0x1 },
> > > > +
> > > > + { 0x20019, 0x1 },
> > > > + { 0x120019, 0x1 },
> > > > + { 0x220019, 0x1 },
> > > > +
> > > > + { 0x200f0, 0x660 },
> > > > + { 0x200f1, 0x0 },
> > > > + { 0x200f2, 0x4444 },
> > > > + { 0x200f3, 0x8888 },
> > > > + { 0x200f4, 0x5665 },
> > > > + { 0x200f5, 0x0 },
> > > > + { 0x200f6, 0x0 },
> > > > + { 0x200f7, 0xf000 },
> > > > +
> > > > + { 0x20025, 0x0 },
> > > > + { 0x2002d, LPDDR4_PHY_DMIPinPresent },
> > > > + { 0x12002d, LPDDR4_PHY_DMIPinPresent },
> > > > + { 0x22002d, LPDDR4_PHY_DMIPinPresent },
> > > > + { 0x200c7, 0x21 },
> > > > + { 0x200ca, 0x24 },
> > > > + { 0x1200c7, 0x21 },
> > > > + { 0x1200ca, 0x24 },
> > > > + { 0x2200c7, 0x21 },
> > > > + { 0x2200ca, 0x24 },
> > >
> > > Why do you add tuple - offset and value? Shouldn't we have the
> > > DDR training functions here?
> > >
> > > It is possible to train IMX6Q and Vybrid's DDR3 (as fair as I know).
> > > Would it be also possible to add the DDR4 training code for IMX8?
> > >
> > > > +};
> > > > +
> > > > +/* ddr phy trained csr */
> > > > +struct dram_cfg_param lpddr4_ddrphy_trained_csr[] = {
> > > > + { 0x200b2, 0x0 },
> > > > + { 0x1200b2, 0x0 },
> > > > + { 0x2200b2, 0x0 },
> > > > + { 0x200cb, 0x0 },
> > > > + { 0x10043, 0x0 },
> > > > + { 0x110043, 0x0 },
> > > > + { 0x210043, 0x0 },
> > > > + { 0x10143, 0x0 },
> > > > + { 0x110143, 0x0 },
> > > > + { 0x210143, 0x0 },
> > > > + { 0x11043, 0x0 },
> > > > + { 0x111043, 0x0 },
> > > > + { 0x211043, 0x0 },
> > > > + { 0x11143, 0x0 },
> > > > + { 0x111143, 0x0 },
> > > > + { 0x211143, 0x0 },
> > > > + { 0x12043, 0x0 },
> > > > + { 0x112043, 0x0 },
> > > > + { 0x212043, 0x0 },
> > > > + { 0x12143, 0x0 },
> > > > + { 0x112143, 0x0 },
> > > > + { 0x212143, 0x0 },
> > > > + { 0x13043, 0x0 },
> > > > + { 0x113043, 0x0 },
> > > > + { 0x213043, 0x0 },
> > > > + { 0x13143, 0x0 },
> > > > + { 0x113143, 0x0 },
> > > > + { 0x213143, 0x0 },
> > > > + { 0x80, 0x0 },
> > > > + { 0x100080, 0x0 },
> > > > + { 0x200080, 0x0 },
> > > > + { 0x1080, 0x0 },
> > > > + { 0x101080, 0x0 },
> > > > + { 0x201080, 0x0 },
> > > > + { 0x2080, 0x0 },
> > > > + { 0x102080, 0x0 },
> > > > + { 0x202080, 0x0 },
> > > > + { 0x3080, 0x0 },
> > > > + { 0x103080, 0x0 },
> > > > + { 0x203080, 0x0 },
> > > > + { 0x4080, 0x0 },
> > > > + { 0x104080, 0x0 },
> > > > + { 0x204080, 0x0 },
> > > > + { 0x5080, 0x0 },
> > > > + { 0x105080, 0x0 },
> > > > + { 0x205080, 0x0 },
> > > > + { 0x6080, 0x0 },
> > > > + { 0x106080, 0x0 },
> > > > + { 0x206080, 0x0 },
> > > > + { 0x7080, 0x0 },
> > > > + { 0x107080, 0x0 },
> > > > + { 0x207080, 0x0 },
> > > > + { 0x8080, 0x0 },
> > > > + { 0x108080, 0x0 },
> > > > + { 0x208080, 0x0 },
> > > > + { 0x9080, 0x0 },
> > > > + { 0x109080, 0x0 },
> > > > + { 0x209080, 0x0 },
> > > > + { 0x10080, 0x0 },
> > > > + { 0x110080, 0x0 },
> > > > + { 0x210080, 0x0 },
> > > > + { 0x10180, 0x0 },
> > > > + { 0x110180, 0x0 },
> > > > + { 0x210180, 0x0 },
> > > > + { 0x11080, 0x0 },
> > > > + { 0x111080, 0x0 },
> > > > + { 0x211080, 0x0 },
> > > > + { 0x11180, 0x0 },
> > > > + { 0x111180, 0x0 },
> > > > + { 0x211180, 0x0 },
> > > > + { 0x12080, 0x0 },
> > > > + { 0x112080, 0x0 },
> > > > + { 0x212080, 0x0 },
> > > > + { 0x12180, 0x0 },
> > > > + { 0x112180, 0x0 },
> > > > + { 0x212180, 0x0 },
> > > > + { 0x13080, 0x0 },
> > > > + { 0x113080, 0x0 },
> > > > + { 0x213080, 0x0 },
> > > > + { 0x13180, 0x0 },
> > > > + { 0x113180, 0x0 },
> > > > + { 0x213180, 0x0 },
> > > > + { 0x10081, 0x0 },
> > > > + { 0x110081, 0x0 },
> > > > + { 0x210081, 0x0 },
> > > > + { 0x10181, 0x0 },
> > > > + { 0x110181, 0x0 },
> > > > + { 0x210181, 0x0 },
> > > > + { 0x11081, 0x0 },
> > > > + { 0x111081, 0x0 },
> > > > + { 0x211081, 0x0 },
> > > > + { 0x11181, 0x0 },
> > > > + { 0x111181, 0x0 },
> > > > + { 0x211181, 0x0 },
> > > > + { 0x12081, 0x0 },
> > > > + { 0x112081, 0x0 },
> > > > + { 0x212081, 0x0 },
> > > > + { 0x12181, 0x0 },
> > > > + { 0x112181, 0x0 },
> > > > + { 0x212181, 0x0 },
> > > > + { 0x13081, 0x0 },
> > > > + { 0x113081, 0x0 },
> > > > + { 0x213081, 0x0 },
> > > > + { 0x13181, 0x0 },
> > > > + { 0x113181, 0x0 },
> > > > + { 0x213181, 0x0 },
> > > > + { 0x100d0, 0x0 },
> > > > + { 0x1100d0, 0x0 },
> > > > + { 0x2100d0, 0x0 },
> > > > + { 0x101d0, 0x0 },
> > > > + { 0x1101d0, 0x0 },
> > > > + { 0x2101d0, 0x0 },
> > > > + { 0x110d0, 0x0 },
> > > > + { 0x1110d0, 0x0 },
> > > > + { 0x2110d0, 0x0 },
> > > > + { 0x111d0, 0x0 },
> > > > + { 0x1111d0, 0x0 },
> > > > + { 0x2111d0, 0x0 },
> > > > + { 0x120d0, 0x0 },
> > > > + { 0x1120d0, 0x0 },
> > > > + { 0x2120d0, 0x0 },
> > > > + { 0x121d0, 0x0 },
> > > > + { 0x1121d0, 0x0 },
> > > > + { 0x2121d0, 0x0 },
> > > > + { 0x130d0, 0x0 },
> > > > + { 0x1130d0, 0x0 },
> > > > + { 0x2130d0, 0x0 },
> > > > + { 0x131d0, 0x0 },
> > > > + { 0x1131d0, 0x0 },
> > > > + { 0x2131d0, 0x0 },
> > > > + { 0x100d1, 0x0 },
> > > > + { 0x1100d1, 0x0 },
> > > > + { 0x2100d1, 0x0 },
> > > > + { 0x101d1, 0x0 },
> > > > + { 0x1101d1, 0x0 },
> > > > + { 0x2101d1, 0x0 },
> > > > + { 0x110d1, 0x0 },
> > > > + { 0x1110d1, 0x0 },
> > > > + { 0x2110d1, 0x0 },
> > > > + { 0x111d1, 0x0 },
> > > > + { 0x1111d1, 0x0 },
> > > > + { 0x2111d1, 0x0 },
> > > > + { 0x120d1, 0x0 },
> > > > + { 0x1120d1, 0x0 },
> > > > + { 0x2120d1, 0x0 },
> > > > + { 0x121d1, 0x0 },
> > > > + { 0x1121d1, 0x0 },
> > > > + { 0x2121d1, 0x0 },
> > > > + { 0x130d1, 0x0 },
> > > > + { 0x1130d1, 0x0 },
> > > > + { 0x2130d1, 0x0 },
> > > > + { 0x131d1, 0x0 },
> > > > + { 0x1131d1, 0x0 },
> > > > + { 0x2131d1, 0x0 },
> > > > + { 0x10068, 0x0 },
> > > > + { 0x10168, 0x0 },
> > > > + { 0x10268, 0x0 },
> > > > + { 0x10368, 0x0 },
> > > > + { 0x10468, 0x0 },
> > > > + { 0x10568, 0x0 },
> > > > + { 0x10668, 0x0 },
> > > > + { 0x10768, 0x0 },
> > > > + { 0x10868, 0x0 },
> > > > + { 0x11068, 0x0 },
> > > > + { 0x11168, 0x0 },
> > > > + { 0x11268, 0x0 },
> > > > + { 0x11368, 0x0 },
> > > > + { 0x11468, 0x0 },
> > > > + { 0x11568, 0x0 },
> > > > + { 0x11668, 0x0 },
> > > > + { 0x11768, 0x0 },
> > > > + { 0x11868, 0x0 },
> > > > + { 0x12068, 0x0 },
> > > > + { 0x12168, 0x0 },
> > > > + { 0x12268, 0x0 },
> > > > + { 0x12368, 0x0 },
> > > > + { 0x12468, 0x0 },
> > > > + { 0x12568, 0x0 },
> > > > + { 0x12668, 0x0 },
> > > > + { 0x12768, 0x0 },
> > > > + { 0x12868, 0x0 },
> > > > + { 0x13068, 0x0 },
> > > > + { 0x13168, 0x0 },
> > > > + { 0x13268, 0x0 },
> > > > + { 0x13368, 0x0 },
> > > > + { 0x13468, 0x0 },
> > > > + { 0x13568, 0x0 },
> > > > + { 0x13668, 0x0 },
> > > > + { 0x13768, 0x0 },
> > > > + { 0x13868, 0x0 },
> > > > + { 0x10069, 0x0 },
> > > > + { 0x10169, 0x0 },
> > > > + { 0x10269, 0x0 },
> > > > + { 0x10369, 0x0 },
> > > > + { 0x10469, 0x0 },
> > > > + { 0x10569, 0x0 },
> > > > + { 0x10669, 0x0 },
> > > > + { 0x10769, 0x0 },
> > > > + { 0x10869, 0x0 },
> > > > + { 0x11069, 0x0 },
> > > > + { 0x11169, 0x0 },
> > > > + { 0x11269, 0x0 },
> > > > + { 0x11369, 0x0 },
> > > > + { 0x11469, 0x0 },
> > > > + { 0x11569, 0x0 },
> > > > + { 0x11669, 0x0 },
> > > > + { 0x11769, 0x0 },
> > > > + { 0x11869, 0x0 },
> > > > + { 0x12069, 0x0 },
> > > > + { 0x12169, 0x0 },
> > > > + { 0x12269, 0x0 },
> > > > + { 0x12369, 0x0 },
> > > > + { 0x12469, 0x0 },
> > > > + { 0x12569, 0x0 },
> > > > + { 0x12669, 0x0 },
> > > > + { 0x12769, 0x0 },
> > > > + { 0x12869, 0x0 },
> > > > + { 0x13069, 0x0 },
> > > > + { 0x13169, 0x0 },
> > > > + { 0x13269, 0x0 },
> > > > + { 0x13369, 0x0 },
> > > > + { 0x13469, 0x0 },
> > > > + { 0x13569, 0x0 },
> > > > + { 0x13669, 0x0 },
> > > > + { 0x13769, 0x0 },
> > > > + { 0x13869, 0x0 },
> > > > + { 0x1008c, 0x0 },
> > > > + { 0x11008c, 0x0 },
> > > > + { 0x21008c, 0x0 },
> > > > + { 0x1018c, 0x0 },
> > > > + { 0x11018c, 0x0 },
> > > > + { 0x21018c, 0x0 },
> > > > + { 0x1108c, 0x0 },
> > > > + { 0x11108c, 0x0 },
> > > > + { 0x21108c, 0x0 },
> > > > + { 0x1118c, 0x0 },
> > > > + { 0x11118c, 0x0 },
> > > > + { 0x21118c, 0x0 },
> > > > + { 0x1208c, 0x0 },
> > > > + { 0x11208c, 0x0 },
> > > > + { 0x21208c, 0x0 },
> > > > + { 0x1218c, 0x0 },
> > > > + { 0x11218c, 0x0 },
> > > > + { 0x21218c, 0x0 },
> > > > + { 0x1308c, 0x0 },
> > > > + { 0x11308c, 0x0 },
> > > > + { 0x21308c, 0x0 },
> > > > + { 0x1318c, 0x0 },
> > > > + { 0x11318c, 0x0 },
> > > > + { 0x21318c, 0x0 },
> > > > + { 0x1008d, 0x0 },
> > > > + { 0x11008d, 0x0 },
> > > > + { 0x21008d, 0x0 },
> > > > + { 0x1018d, 0x0 },
> > > > + { 0x11018d, 0x0 },
> > > > + { 0x21018d, 0x0 },
> > > > + { 0x1108d, 0x0 },
> > > > + { 0x11108d, 0x0 },
> > > > + { 0x21108d, 0x0 },
> > > > + { 0x1118d, 0x0 },
> > > > + { 0x11118d, 0x0 },
> > > > + { 0x21118d, 0x0 },
> > > > + { 0x1208d, 0x0 },
> > > > + { 0x11208d, 0x0 },
> > > > + { 0x21208d, 0x0 },
> > > > + { 0x1218d, 0x0 },
> > > > + { 0x11218d, 0x0 },
> > > > + { 0x21218d, 0x0 },
> > > > + { 0x1308d, 0x0 },
> > > > + { 0x11308d, 0x0 },
> > > > + { 0x21308d, 0x0 },
> > > > + { 0x1318d, 0x0 },
> > > > + { 0x11318d, 0x0 },
> > > > + { 0x21318d, 0x0 },
> > > > + { 0x100c0, 0x0 },
> > > > + { 0x1100c0, 0x0 },
> > > > + { 0x2100c0, 0x0 },
> > > > + { 0x101c0, 0x0 },
> > > > + { 0x1101c0, 0x0 },
> > > > + { 0x2101c0, 0x0 },
> > > > + { 0x102c0, 0x0 },
> > > > + { 0x1102c0, 0x0 },
> > > > + { 0x2102c0, 0x0 },
> > > > + { 0x103c0, 0x0 },
> > > > + { 0x1103c0, 0x0 },
> > > > + { 0x2103c0, 0x0 },
> > > > + { 0x104c0, 0x0 },
> > > > + { 0x1104c0, 0x0 },
> > > > + { 0x2104c0, 0x0 },
> > > > + { 0x105c0, 0x0 },
> > > > + { 0x1105c0, 0x0 },
> > > > + { 0x2105c0, 0x0 },
> > > > + { 0x106c0, 0x0 },
> > > > + { 0x1106c0, 0x0 },
> > > > + { 0x2106c0, 0x0 },
> > > > + { 0x107c0, 0x0 },
> > > > + { 0x1107c0, 0x0 },
> > > > + { 0x2107c0, 0x0 },
> > > > + { 0x108c0, 0x0 },
> > > > + { 0x1108c0, 0x0 },
> > > > + { 0x2108c0, 0x0 },
> > > > + { 0x110c0, 0x0 },
> > > > + { 0x1110c0, 0x0 },
> > > > + { 0x2110c0, 0x0 },
> > > > + { 0x111c0, 0x0 },
> > > > + { 0x1111c0, 0x0 },
> > > > + { 0x2111c0, 0x0 },
> > > > + { 0x112c0, 0x0 },
> > > > + { 0x1112c0, 0x0 },
> > > > + { 0x2112c0, 0x0 },
> > > > + { 0x113c0, 0x0 },
> > > > + { 0x1113c0, 0x0 },
> > > > + { 0x2113c0, 0x0 },
> > > > + { 0x114c0, 0x0 },
> > > > + { 0x1114c0, 0x0 },
> > > > + { 0x2114c0, 0x0 },
> > > > + { 0x115c0, 0x0 },
> > > > + { 0x1115c0, 0x0 },
> > > > + { 0x2115c0, 0x0 },
> > > > + { 0x116c0, 0x0 },
> > > > + { 0x1116c0, 0x0 },
> > > > + { 0x2116c0, 0x0 },
> > > > + { 0x117c0, 0x0 },
> > > > + { 0x1117c0, 0x0 },
> > > > + { 0x2117c0, 0x0 },
> > > > + { 0x118c0, 0x0 },
> > > > + { 0x1118c0, 0x0 },
> > > > + { 0x2118c0, 0x0 },
> > > > + { 0x120c0, 0x0 },
> > > > + { 0x1120c0, 0x0 },
> > > > + { 0x2120c0, 0x0 },
> > > > + { 0x121c0, 0x0 },
> > > > + { 0x1121c0, 0x0 },
> > > > + { 0x2121c0, 0x0 },
> > > > + { 0x122c0, 0x0 },
> > > > + { 0x1122c0, 0x0 },
> > > > + { 0x2122c0, 0x0 },
> > > > + { 0x123c0, 0x0 },
> > > > + { 0x1123c0, 0x0 },
> > > > + { 0x2123c0, 0x0 },
> > > > + { 0x124c0, 0x0 },
> > > > + { 0x1124c0, 0x0 },
> > > > + { 0x2124c0, 0x0 },
> > > > + { 0x125c0, 0x0 },
> > > > + { 0x1125c0, 0x0 },
> > > > + { 0x2125c0, 0x0 },
> > > > + { 0x126c0, 0x0 },
> > > > + { 0x1126c0, 0x0 },
> > > > + { 0x2126c0, 0x0 },
> > > > + { 0x127c0, 0x0 },
> > > > + { 0x1127c0, 0x0 },
> > > > + { 0x2127c0, 0x0 },
> > > > + { 0x128c0, 0x0 },
> > > > + { 0x1128c0, 0x0 },
> > > > + { 0x2128c0, 0x0 },
> > > > + { 0x130c0, 0x0 },
> > > > + { 0x1130c0, 0x0 },
> > > > + { 0x2130c0, 0x0 },
> > > > + { 0x131c0, 0x0 },
> > > > + { 0x1131c0, 0x0 },
> > > > + { 0x2131c0, 0x0 },
> > > > + { 0x132c0, 0x0 },
> > > > + { 0x1132c0, 0x0 },
> > > > + { 0x2132c0, 0x0 },
> > > > + { 0x133c0, 0x0 },
> > > > + { 0x1133c0, 0x0 },
> > > > + { 0x2133c0, 0x0 },
> > > > + { 0x134c0, 0x0 },
> > > > + { 0x1134c0, 0x0 },
> > > > + { 0x2134c0, 0x0 },
> > > > + { 0x135c0, 0x0 },
> > > > + { 0x1135c0, 0x0 },
> > > > + { 0x2135c0, 0x0 },
> > > > + { 0x136c0, 0x0 },
> > > > + { 0x1136c0, 0x0 },
> > > > + { 0x2136c0, 0x0 },
> > > > + { 0x137c0, 0x0 },
> > > > + { 0x1137c0, 0x0 },
> > > > + { 0x2137c0, 0x0 },
> > > > + { 0x138c0, 0x0 },
> > > > + { 0x1138c0, 0x0 },
> > > > + { 0x2138c0, 0x0 },
> > > > + { 0x100c1, 0x0 },
> > > > + { 0x1100c1, 0x0 },
> > > > + { 0x2100c1, 0x0 },
> > > > + { 0x101c1, 0x0 },
> > > > + { 0x1101c1, 0x0 },
> > > > + { 0x2101c1, 0x0 },
> > > > + { 0x102c1, 0x0 },
> > > > + { 0x1102c1, 0x0 },
> > > > + { 0x2102c1, 0x0 },
> > > > + { 0x103c1, 0x0 },
> > > > + { 0x1103c1, 0x0 },
> > > > + { 0x2103c1, 0x0 },
> > > > + { 0x104c1, 0x0 },
> > > > + { 0x1104c1, 0x0 },
> > > > + { 0x2104c1, 0x0 },
> > > > + { 0x105c1, 0x0 },
> > > > + { 0x1105c1, 0x0 },
> > > > + { 0x2105c1, 0x0 },
> > > > + { 0x106c1, 0x0 },
> > > > + { 0x1106c1, 0x0 },
> > > > + { 0x2106c1, 0x0 },
> > > > + { 0x107c1, 0x0 },
> > > > + { 0x1107c1, 0x0 },
> > > > + { 0x2107c1, 0x0 },
> > > > + { 0x108c1, 0x0 },
> > > > + { 0x1108c1, 0x0 },
> > > > + { 0x2108c1, 0x0 },
> > > > + { 0x110c1, 0x0 },
> > > > + { 0x1110c1, 0x0 },
> > > > + { 0x2110c1, 0x0 },
> > > > + { 0x111c1, 0x0 },
> > > > + { 0x1111c1, 0x0 },
> > > > + { 0x2111c1, 0x0 },
> > > > + { 0x112c1, 0x0 },
> > > > + { 0x1112c1, 0x0 },
> > > > + { 0x2112c1, 0x0 },
> > > > + { 0x113c1, 0x0 },
> > > > + { 0x1113c1, 0x0 },
> > > > + { 0x2113c1, 0x0 },
> > > > + { 0x114c1, 0x0 },
> > > > + { 0x1114c1, 0x0 },
> > > > + { 0x2114c1, 0x0 },
> > > > + { 0x115c1, 0x0 },
> > > > + { 0x1115c1, 0x0 },
> > > > + { 0x2115c1, 0x0 },
> > > > + { 0x116c1, 0x0 },
> > > > + { 0x1116c1, 0x0 },
> > > > + { 0x2116c1, 0x0 },
> > > > + { 0x117c1, 0x0 },
> > > > + { 0x1117c1, 0x0 },
> > > > + { 0x2117c1, 0x0 },
> > > > + { 0x118c1, 0x0 },
> > > > + { 0x1118c1, 0x0 },
> > > > + { 0x2118c1, 0x0 },
> > > > + { 0x120c1, 0x0 },
> > > > + { 0x1120c1, 0x0 },
> > > > + { 0x2120c1, 0x0 },
> > > > + { 0x121c1, 0x0 },
> > > > + { 0x1121c1, 0x0 },
> > > > + { 0x2121c1, 0x0 },
> > > > + { 0x122c1, 0x0 },
> > > > + { 0x1122c1, 0x0 },
> > > > + { 0x2122c1, 0x0 },
> > > > + { 0x123c1, 0x0 },
> > > > + { 0x1123c1, 0x0 },
> > > > + { 0x2123c1, 0x0 },
> > > > + { 0x124c1, 0x0 },
> > > > + { 0x1124c1, 0x0 },
> > > > + { 0x2124c1, 0x0 },
> > > > + { 0x125c1, 0x0 },
> > > > + { 0x1125c1, 0x0 },
> > > > + { 0x2125c1, 0x0 },
> > > > + { 0x126c1, 0x0 },
> > > > + { 0x1126c1, 0x0 },
> > > > + { 0x2126c1, 0x0 },
> > > > + { 0x127c1, 0x0 },
> > > > + { 0x1127c1, 0x0 },
> > > > + { 0x2127c1, 0x0 },
> > > > + { 0x128c1, 0x0 },
> > > > + { 0x1128c1, 0x0 },
> > > > + { 0x2128c1, 0x0 },
> > > > + { 0x130c1, 0x0 },
> > > > + { 0x1130c1, 0x0 },
> > > > + { 0x2130c1, 0x0 },
> > > > + { 0x131c1, 0x0 },
> > > > + { 0x1131c1, 0x0 },
> > > > + { 0x2131c1, 0x0 },
> > > > + { 0x132c1, 0x0 },
> > > > + { 0x1132c1, 0x0 },
> > > > + { 0x2132c1, 0x0 },
> > > > + { 0x133c1, 0x0 },
> > > > + { 0x1133c1, 0x0 },
> > > > + { 0x2133c1, 0x0 },
> > > > + { 0x134c1, 0x0 },
> > > > + { 0x1134c1, 0x0 },
> > > > + { 0x2134c1, 0x0 },
> > > > + { 0x135c1, 0x0 },
> > > > + { 0x1135c1, 0x0 },
> > > > + { 0x2135c1, 0x0 },
> > > > + { 0x136c1, 0x0 },
> > > > + { 0x1136c1, 0x0 },
> > > > + { 0x2136c1, 0x0 },
> > > > + { 0x137c1, 0x0 },
> > > > + { 0x1137c1, 0x0 },
> > > > + { 0x2137c1, 0x0 },
> > > > + { 0x138c1, 0x0 },
> > > > + { 0x1138c1, 0x0 },
> > > > + { 0x2138c1, 0x0 },
> > > > + { 0x10020, 0x0 },
> > > > + { 0x110020, 0x0 },
> > > > + { 0x210020, 0x0 },
> > > > + { 0x11020, 0x0 },
> > > > + { 0x111020, 0x0 },
> > > > + { 0x211020, 0x0 },
> > > > + { 0x12020, 0x0 },
> > > > + { 0x112020, 0x0 },
> > > > + { 0x212020, 0x0 },
> > > > + { 0x13020, 0x0 },
> > > > + { 0x113020, 0x0 },
> > > > + { 0x213020, 0x0 },
> > > > + { 0x20072, 0x0 },
> > > > + { 0x20073, 0x0 },
> > > > + { 0x20074, 0x0 },
> > > > + { 0x100aa, 0x0 },
> > > > + { 0x110aa, 0x0 },
> > > > + { 0x120aa, 0x0 },
> > > > + { 0x130aa, 0x0 },
> > > > + { 0x20010, 0x0 },
> > > > + { 0x120010, 0x0 },
> > > > + { 0x220010, 0x0 },
> > > > + { 0x20011, 0x0 },
> > > > + { 0x120011, 0x0 },
> > > > + { 0x220011, 0x0 },
> > > > + { 0x100ae, 0x0 },
> > > > + { 0x1100ae, 0x0 },
> > > > + { 0x2100ae, 0x0 },
> > > > + { 0x100af, 0x0 },
> > > > + { 0x1100af, 0x0 },
> > > > + { 0x2100af, 0x0 },
> > > > + { 0x110ae, 0x0 },
> > > > + { 0x1110ae, 0x0 },
> > > > + { 0x2110ae, 0x0 },
> > > > + { 0x110af, 0x0 },
> > > > + { 0x1110af, 0x0 },
> > > > + { 0x2110af, 0x0 },
> > > > + { 0x120ae, 0x0 },
> > > > + { 0x1120ae, 0x0 },
> > > > + { 0x2120ae, 0x0 },
> > > > + { 0x120af, 0x0 },
> > > > + { 0x1120af, 0x0 },
> > > > + { 0x2120af, 0x0 },
> > > > + { 0x130ae, 0x0 },
> > > > + { 0x1130ae, 0x0 },
> > > > + { 0x2130ae, 0x0 },
> > > > + { 0x130af, 0x0 },
> > > > + { 0x1130af, 0x0 },
> > > > + { 0x2130af, 0x0 },
> > > > + { 0x20020, 0x0 },
> > > > + { 0x120020, 0x0 },
> > > > + { 0x220020, 0x0 },
> > > > + { 0x100a0, 0x0 },
> > > > + { 0x100a1, 0x0 },
> > > > + { 0x100a2, 0x0 },
> > > > + { 0x100a3, 0x0 },
> > > > + { 0x100a4, 0x0 },
> > > > + { 0x100a5, 0x0 },
> > > > + { 0x100a6, 0x0 },
> > > > + { 0x100a7, 0x0 },
> > > > + { 0x110a0, 0x0 },
> > > > + { 0x110a1, 0x0 },
> > > > + { 0x110a2, 0x0 },
> > > > + { 0x110a3, 0x0 },
> > > > + { 0x110a4, 0x0 },
> > > > + { 0x110a5, 0x0 },
> > > > + { 0x110a6, 0x0 },
> > > > + { 0x110a7, 0x0 },
> > > > + { 0x120a0, 0x0 },
> > > > + { 0x120a1, 0x0 },
> > > > + { 0x120a2, 0x0 },
> > > > + { 0x120a3, 0x0 },
> > > > + { 0x120a4, 0x0 },
> > > > + { 0x120a5, 0x0 },
> > > > + { 0x120a6, 0x0 },
> > > > + { 0x120a7, 0x0 },
> > > > + { 0x130a0, 0x0 },
> > > > + { 0x130a1, 0x0 },
> > > > + { 0x130a2, 0x0 },
> > > > + { 0x130a3, 0x0 },
> > > > + { 0x130a4, 0x0 },
> > > > + { 0x130a5, 0x0 },
> > > > + { 0x130a6, 0x0 },
> > > > + { 0x130a7, 0x0 },
> > > > + { 0x2007c, 0x0 },
> > > > + { 0x12007c, 0x0 },
> > > > + { 0x22007c, 0x0 },
> > > > + { 0x2007d, 0x0 },
> > > > + { 0x12007d, 0x0 },
> > > > + { 0x22007d, 0x0 },
> > > > + { 0x400fd, 0x0 },
> > > > + { 0x400c0, 0x0 },
> > > > + { 0x90201, 0x0 },
> > > > + { 0x190201, 0x0 },
> > > > + { 0x290201, 0x0 },
> > > > + { 0x90202, 0x0 },
> > > > + { 0x190202, 0x0 },
> > > > + { 0x290202, 0x0 },
> > > > + { 0x90203, 0x0 },
> > > > + { 0x190203, 0x0 },
> > > > + { 0x290203, 0x0 },
> > > > + { 0x90204, 0x0 },
> > > > + { 0x190204, 0x0 },
> > > > + { 0x290204, 0x0 },
> > > > + { 0x90205, 0x0 },
> > > > + { 0x190205, 0x0 },
> > > > + { 0x290205, 0x0 },
> > > > + { 0x90206, 0x0 },
> > > > + { 0x190206, 0x0 },
> > > > + { 0x290206, 0x0 },
> > > > + { 0x90207, 0x0 },
> > > > + { 0x190207, 0x0 },
> > > > + { 0x290207, 0x0 },
> > > > + { 0x90208, 0x0 },
> > > > + { 0x190208, 0x0 },
> > > > + { 0x290208, 0x0 },
> > > > + { 0x10062, 0x0 },
> > > > + { 0x10162, 0x0 },
> > > > + { 0x10262, 0x0 },
> > > > + { 0x10362, 0x0 },
> > > > + { 0x10462, 0x0 },
> > > > + { 0x10562, 0x0 },
> > > > + { 0x10662, 0x0 },
> > > > + { 0x10762, 0x0 },
> > > > + { 0x10862, 0x0 },
> > > > + { 0x11062, 0x0 },
> > > > + { 0x11162, 0x0 },
> > > > + { 0x11262, 0x0 },
> > > > + { 0x11362, 0x0 },
> > > > + { 0x11462, 0x0 },
> > > > + { 0x11562, 0x0 },
> > > > + { 0x11662, 0x0 },
> > > > + { 0x11762, 0x0 },
> > > > + { 0x11862, 0x0 },
> > > > + { 0x12062, 0x0 },
> > > > + { 0x12162, 0x0 },
> > > > + { 0x12262, 0x0 },
> > > > + { 0x12362, 0x0 },
> > > > + { 0x12462, 0x0 },
> > > > + { 0x12562, 0x0 },
> > > > + { 0x12662, 0x0 },
> > > > + { 0x12762, 0x0 },
> > > > + { 0x12862, 0x0 },
> > > > + { 0x13062, 0x0 },
> > > > + { 0x13162, 0x0 },
> > > > + { 0x13262, 0x0 },
> > > > + { 0x13362, 0x0 },
> > > > + { 0x13462, 0x0 },
> > > > + { 0x13562, 0x0 },
> > > > + { 0x13662, 0x0 },
> > > > + { 0x13762, 0x0 },
> > > > + { 0x13862, 0x0 },
> > > > + { 0x20077, 0x0 },
> > > > + { 0x10001, 0x0 },
> > > > + { 0x11001, 0x0 },
> > > > + { 0x12001, 0x0 },
> > > > + { 0x13001, 0x0 },
> > > > + { 0x10040, 0x0 },
> > > > + { 0x10140, 0x0 },
> > > > + { 0x10240, 0x0 },
> > > > + { 0x10340, 0x0 },
> > > > + { 0x10440, 0x0 },
> > > > + { 0x10540, 0x0 },
> > > > + { 0x10640, 0x0 },
> > > > + { 0x10740, 0x0 },
> > > > + { 0x10840, 0x0 },
> > > > + { 0x10030, 0x0 },
> > > > + { 0x10130, 0x0 },
> > > > + { 0x10230, 0x0 },
> > > > + { 0x10330, 0x0 },
> > > > + { 0x10430, 0x0 },
> > > > + { 0x10530, 0x0 },
> > > > + { 0x10630, 0x0 },
> > > > + { 0x10730, 0x0 },
> > > > + { 0x10830, 0x0 },
> > > > + { 0x11040, 0x0 },
> > > > + { 0x11140, 0x0 },
> > > > + { 0x11240, 0x0 },
> > > > + { 0x11340, 0x0 },
> > > > + { 0x11440, 0x0 },
> > > > + { 0x11540, 0x0 },
> > > > + { 0x11640, 0x0 },
> > > > + { 0x11740, 0x0 },
> > > > + { 0x11840, 0x0 },
> > > > + { 0x11030, 0x0 },
> > > > + { 0x11130, 0x0 },
> > > > + { 0x11230, 0x0 },
> > > > + { 0x11330, 0x0 },
> > > > + { 0x11430, 0x0 },
> > > > + { 0x11530, 0x0 },
> > > > + { 0x11630, 0x0 },
> > > > + { 0x11730, 0x0 },
> > > > + { 0x11830, 0x0 },
> > > > + { 0x12040, 0x0 },
> > > > + { 0x12140, 0x0 },
> > > > + { 0x12240, 0x0 },
> > > > + { 0x12340, 0x0 },
> > > > + { 0x12440, 0x0 },
> > > > + { 0x12540, 0x0 },
> > > > + { 0x12640, 0x0 },
> > > > + { 0x12740, 0x0 },
> > > > + { 0x12840, 0x0 },
> > > > + { 0x12030, 0x0 },
> > > > + { 0x12130, 0x0 },
> > > > + { 0x12230, 0x0 },
> > > > + { 0x12330, 0x0 },
> > > > + { 0x12430, 0x0 },
> > > > + { 0x12530, 0x0 },
> > > > + { 0x12630, 0x0 },
> > > > + { 0x12730, 0x0 },
> > > > + { 0x12830, 0x0 },
> > > > + { 0x13040, 0x0 },
> > > > + { 0x13140, 0x0 },
> > > > + { 0x13240, 0x0 },
> > > > + { 0x13340, 0x0 },
> > > > + { 0x13440, 0x0 },
> > > > + { 0x13540, 0x0 },
> > > > + { 0x13640, 0x0 },
> > > > + { 0x13740, 0x0 },
> > > > + { 0x13840, 0x0 },
> > > > + { 0x13030, 0x0 },
> > > > + { 0x13130, 0x0 },
> > > > + { 0x13230, 0x0 },
> > > > + { 0x13330, 0x0 },
> > > > + { 0x13430, 0x0 },
> > > > + { 0x13530, 0x0 },
> > > > + { 0x13630, 0x0 },
> > > > + { 0x13730, 0x0 },
> > > > + { 0x13830, 0x0 },
> > > > +};
> > >
> > > The same as above. Please look into imx6q DDR3 training code.
> > >
> > > > +
> > > > +/* P0 message block paremeter for training firmware */
> > > > +struct dram_cfg_param lpddr4_fsp0_cfg[] = {
> > > > + { 0xd0000, 0x0 },
> > > > + { 0x54000, 0x0 },
> > > > + { 0x54001, 0x0 },
> > > > + { 0x54002, 0x0 },
> > > > + { 0x54003, 0xbb8 },
> > > > + { 0x54004, 0x2 },
> > > > + { 0x54005, ((LPDDR4_PHY_RON << 8) |
> > > > LPDDR4_PHY_RTT) },//PHY Ron/Rtt
> > > > + { 0x54006, LPDDR4_PHY_VREF_VALUE },
> > > > + { 0x54007, 0x0 },
> > > > + { 0x54008, 0x131f },
> > > > + { 0x54009, 0xc8 },
> > > > + { 0x5400a, 0x0 },
> > > > + { 0x5400b, 0x2 },
> > > > + { 0x5400c, 0x0 },
> > > > + { 0x5400d, 0x0 },
> > > > + { 0x5400e, 0x0 },
> > > > + { 0x5400f, 0x0 },
> > > > + { 0x54010, 0x0 },
> > > > + { 0x54011, 0x0 },
> > > > + { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
> > > > + { 0x54013, 0x0 },
> > > > + { 0x54014, 0x0 },
> > > > + { 0x54015, 0x0 },
> > > > + { 0x54016, 0x0 },
> > > > + { 0x54017, 0x0 },
> > > > + { 0x54018, 0x0 },
> > > > + { 0x54019, 0x2dd4 },
> > > > + { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
> > > > + { 0x5401b, 0x4d66 },
> > > > + { 0x5401c, 0x4d08 },
> > > > + { 0x5401d, 0x0 },
> > > > + { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
> > > > + { 0x5401f, 0x2dd4 },
> > > > + { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
> > > > + { 0x54021, 0x4d66 },
> > > > + { 0x54022, 0x4d08 },
> > > > + { 0x54023, 0x0 },
> > > > + { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
> > > > + { 0x54025, 0x0 },
> > > > + { 0x54026, 0x0 },
> > > > + { 0x54027, 0x0 },
> > > > + { 0x54028, 0x0 },
> > > > + { 0x54029, 0x0 },
> > > > + { 0x5402a, 0x0 },
> > > > + { 0x5402b, 0x1000 },
> > > > + { 0x5402c, LPDDR4_CS },
> > > > + { 0x5402d, 0x0 },
> > > > + { 0x5402e, 0x0 },
> > > > + { 0x5402f, 0x0 },
> > > > + { 0x54030, 0x0 },
> > > > + { 0x54031, 0x0 },
> > > > + { 0x54032, 0xd400 },
> > > > + { 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
> > > > + { 0x54034, 0x6600 },
> > > > + { 0x54035, 0x84d },
> > > > + { 0x54036, 0x4d },
> > > > + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
> > > > + { 0x54038, 0xd400 },
> > > > + { 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
> > > > + { 0x5403a, 0x6600 },
> > > > + { 0x5403b, 0x84d },
> > > > + { 0x5403c, 0x4d },
> > > > + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
> > > > + { 0x5403e, 0x0 },
> > > > + { 0x5403f, 0x0 },
> > > > + { 0x54040, 0x0 },
> > > > + { 0x54041, 0x0 },
> > > > + { 0x54042, 0x0 },
> > > > + { 0x54043, 0x0 },
> > > > + { 0x54044, 0x0 },
> > > > + { 0xd0000, 0x1 },
> > > > +};
> > > > +
> > > > +/* P1 message block paremeter for training firmware */
> > > > +struct dram_cfg_param lpddr4_fsp1_cfg[] = {
> > > > + { 0xd0000, 0x0 },
> > > > + { 0x54000, 0x0 },
> > > > + { 0x54001, 0x0 },
> > > > + { 0x54002, 0x101 },
> > > > + { 0x54003, 0x190 },
> > > > + { 0x54004, 0x2 },
> > > > + { 0x54005, ((LPDDR4_PHY_RON << 8) |
> > > > LPDDR4_PHY_RTT) },//PHY Ron/Rtt
> > > > + { 0x54006, LPDDR4_PHY_VREF_VALUE },
> > > > + { 0x54007, 0x0 },
> > > > + { 0x54008, 0x121f },
> > > > + { 0x54009, 0xc8 },
> > > > + { 0x5400a, 0x0 },
> > > > + { 0x5400b, 0x2 },
> > > > + { 0x5400c, 0x0 },
> > > > + { 0x5400d, 0x0 },
> > > > + { 0x5400e, 0x0 },
> > > > + { 0x5400f, 0x0 },
> > > > + { 0x54010, 0x0 },
> > > > + { 0x54011, 0x0 },
> > > > + { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
> > > > + { 0x54013, 0x0 },
> > > > + { 0x54014, 0x0 },
> > > > + { 0x54015, 0x0 },
> > > > + { 0x54016, 0x0 },
> > > > + { 0x54017, 0x0 },
> > > > + { 0x54018, 0x0 },
> > > > + { 0x54019, 0x84 },
> > > > + { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
> > > > + { 0x5401b, 0x4d66 },
> > > > + { 0x5401c, 0x4d08 },
> > > > + { 0x5401d, 0x0 },
> > > > + { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
> > > > + { 0x5401f, 0x84 },
> > > > + { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
> > > > + { 0x54021, 0x4d66 },
> > > > + { 0x54022, 0x4d08 },
> > > > + { 0x54023, 0x0 },
> > > > + { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
> > > > + { 0x54025, 0x0 },
> > > > + { 0x54026, 0x0 },
> > > > + { 0x54027, 0x0 },
> > > > + { 0x54028, 0x0 },
> > > > + { 0x54029, 0x0 },
> > > > + { 0x5402a, 0x0 },
> > > > + { 0x5402b, 0x1000 },
> > > > + { 0x5402c, LPDDR4_CS },
> > > > + { 0x5402d, 0x0 },
> > > > + { 0x5402e, 0x0 },
> > > > + { 0x5402f, 0x0 },
> > > > + { 0x54030, 0x0 },
> > > > + { 0x54031, 0x0 },
> > > > + { 0x54032, 0x8400 },
> > > > + { 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
> > > > + { 0x54034, 0x6600 },
> > > > + { 0x54035, 0x84d },
> > > > + { 0x54036, 0x4d },
> > > > + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
> > > > + { 0x54038, 0x8400 },
> > > > + { 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
> > > > + { 0x5403a, 0x6600 },
> > > > + { 0x5403b, 0x84d },
> > > > + { 0x5403c, 0x4d },
> > > > + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
> > > > + { 0x5403e, 0x0 },
> > > > + { 0x5403f, 0x0 },
> > > > + { 0x54040, 0x0 },
> > > > + { 0x54041, 0x0 },
> > > > + { 0x54042, 0x0 },
> > > > + { 0x54043, 0x0 },
> > > > + { 0x54044, 0x0 },
> > > > + { 0xd0000, 0x1 },
> > > > +};
> > > > +
> > > > +/* P1 message block paremeter for training firmware */
> > > > +struct dram_cfg_param lpddr4_fsp2_cfg[] = {
> > > > + { 0xd0000, 0x0 },
> > > > + { 0x54000, 0x0 },
> > > > + { 0x54001, 0x0 },
> > > > + { 0x54002, 0x102 },
> > > > + { 0x54003, 0x64 },
> > > > + { 0x54004, 0x2 },
> > > > + { 0x54005, ((LPDDR4_PHY_RON << 8) |
> > > > LPDDR4_PHY_RTT) },//PHY Ron/Rtt
> > > > + { 0x54006, LPDDR4_PHY_VREF_VALUE },
> > > > + { 0x54007, 0x0 },
> > > > + { 0x54008, 0x121f },
> > > > + { 0x54009, 0xc8 },
> > > > + { 0x5400a, 0x0 },
> > > > + { 0x5400b, 0x2 },
> > > > + { 0x5400c, 0x0 },
> > > > + { 0x5400d, 0x0 },
> > > > + { 0x5400e, 0x0 },
> > > > + { 0x5400f, 0x0 },
> > > > + { 0x54010, 0x0 },
> > > > + { 0x54011, 0x0 },
> > > > + { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
> > > > + { 0x54013, 0x0 },
> > > > + { 0x54014, 0x0 },
> > > > + { 0x54015, 0x0 },
> > > > + { 0x54016, 0x0 },
> > > > + { 0x54017, 0x0 },
> > > > + { 0x54018, 0x0 },
> > > > + { 0x54019, 0x84 },
> > > > + { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
> > > > + { 0x5401b, 0x4d66 },
> > > > + { 0x5401c, 0x4d08 },
> > > > + { 0x5401d, 0x0 },
> > > > + { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
> > > > + { 0x5401f, 0x84 },
> > > > + { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
> > > > + { 0x54021, 0x4d66 },
> > > > + { 0x54022, 0x4d08 },
> > > > + { 0x54023, 0x0 },
> > > > + { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
> > > > + { 0x54025, 0x0 },
> > > > + { 0x54026, 0x0 },
> > > > + { 0x54027, 0x0 },
> > > > + { 0x54028, 0x0 },
> > > > + { 0x54029, 0x0 },
> > > > + { 0x5402a, 0x0 },
> > > > + { 0x5402b, 0x1000 },
> > > > + { 0x5402c, LPDDR4_CS },
> > > > + { 0x5402d, 0x0 },
> > > > + { 0x5402e, 0x0 },
> > > > + { 0x5402f, 0x0 },
> > > > + { 0x54030, 0x0 },
> > > > + { 0x54031, 0x0 },
> > > > + { 0x54032, 0x8400 },
> > > > + { 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
> > > > + { 0x54034, 0x6600 },
> > > > + { 0x54035, 0x84d },
> > > > + { 0x54036, 0x4d },
> > > > + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
> > > > + { 0x54038, 0x8400 },
> > > > + { 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
> > > > + { 0x5403a, 0x6600 },
> > > > + { 0x5403b, 0x84d },
> > > > + { 0x5403c, 0x4d },
> > > > + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
> > > > + { 0x5403e, 0x0 },
> > > > + { 0x5403f, 0x0 },
> > > > + { 0x54040, 0x0 },
> > > > + { 0x54041, 0x0 },
> > > > + { 0x54042, 0x0 },
> > > > + { 0x54043, 0x0 },
> > > > + { 0x54044, 0x0 },
> > > > + { 0xd0000, 0x1 },
> > > > +};
> > > > +
> > > > +/* P0 2D message block paremeter for training firmware */
> > > > +struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
> > > > + { 0xd0000, 0x0 },
> > > > + { 0x54000, 0x0 },
> > > > + { 0x54001, 0x0 },
> > > > + { 0x54002, 0x0 },
> > > > + { 0x54003, 0xbb8 },
> > > > + { 0x54004, 0x2 },
> > > > + { 0x54005, ((LPDDR4_PHY_RON << 8) |
> > > > LPDDR4_PHY_RTT) },//PHY Ron/Rtt
> > > > + { 0x54006, LPDDR4_PHY_VREF_VALUE },
> > > > + { 0x54007, 0x0 },
> > > > + { 0x54008, 0x61 },
> > > > + { 0x54009, 0xc8 },
> > > > + { 0x5400a, 0x0 },
> > > > + { 0x5400b, 0x2 },
> > > > + { 0x5400c, 0x0 },
> > > > + { 0x5400d, 0x0 },
> > > > + { 0x5400e, 0x0 },
> > > > + { 0x5400f, 0x100 },
> > > > + { 0x54010, 0x1f7f },
> > > > + { 0x54011, 0x0 },
> > > > + { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
> > > > + { 0x54013, 0x0 },
> > > > + { 0x54014, 0x0 },
> > > > + { 0x54015, 0x0 },
> > > > + { 0x54016, 0x0 },
> > > > + { 0x54017, 0x0 },
> > > > + { 0x54018, 0x0 },
> > > > + { 0x54019, 0x2dd4 },
> > > > + { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
> > > > + { 0x5401b, 0x4d66 },
> > > > + { 0x5401c, 0x4d08 },
> > > > + { 0x5401d, 0x0 },
> > > > + { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
> > > > + { 0x5401f, 0x2dd4 },
> > > > + { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
> > > > + { 0x54021, 0x4d66 },
> > > > + { 0x54022, 0x4d08 },
> > > > + { 0x54023, 0x0 },
> > > > + { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
> > > > + { 0x54025, 0x0 },
> > > > + { 0x54026, 0x0 },
> > > > + { 0x54027, 0x0 },
> > > > + { 0x54028, 0x0 },
> > > > + { 0x54029, 0x0 },
> > > > + { 0x5402a, 0x0 },
> > > > + { 0x5402b, 0x1000 },
> > > > + { 0x5402c, LPDDR4_CS },
> > > > + { 0x5402d, 0x0 },
> > > > + { 0x5402e, 0x0 },
> > > > + { 0x5402f, 0x0 },
> > > > + { 0x54030, 0x0 },
> > > > + { 0x54031, 0x0 },
> > > > + { 0x54032, 0xd400 },
> > > > + { 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
> > > > + { 0x54034, 0x6600 },
> > > > + { 0x54035, 0x84d },
> > > > + { 0x54036, 0x4d },
> > > > + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
> > > > + { 0x54038, 0xd400 },
> > > > + { 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
> > > > + { 0x5403a, 0x6600 },
> > > > + { 0x5403b, 0x84d },
> > > > + { 0x5403c, 0x4d },
> > > > + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
> > > > + { 0x5403e, 0x0 },
> > > > + { 0x5403f, 0x0 },
> > > > + { 0x54040, 0x0 },
> > > > + { 0x54041, 0x0 },
> > > > + { 0x54042, 0x0 },
> > > > + { 0x54043, 0x0 },
> > > > + { 0x54044, 0x0 },
> > > > + { 0xd0000, 0x1 },
> > > > +};
> > > > +
> > > > +/* DRAM PHY init engine image */
> > > > +struct dram_cfg_param lpddr4_phy_pie[] = {
> > > > + { 0xd0000, 0x0 },
> > > > + { 0x90000, 0x10 },
> > > > + { 0x90001, 0x400 },
> > > > + { 0x90002, 0x10e },
> > > > + { 0x90003, 0x0 },
> > > > + { 0x90004, 0x0 },
> > > > + { 0x90005, 0x8 },
> > > > + { 0x90029, 0xb },
> > > > + { 0x9002a, 0x480 },
> > > > + { 0x9002b, 0x109 },
> > > > + { 0x9002c, 0x8 },
> > > > + { 0x9002d, 0x448 },
> > > > + { 0x9002e, 0x139 },
> > > > + { 0x9002f, 0x8 },
> > > > + { 0x90030, 0x478 },
> > > > + { 0x90031, 0x109 },
> > > > + { 0x90032, 0x0 },
> > > > + { 0x90033, 0xe8 },
> > > > + { 0x90034, 0x109 },
> > > > + { 0x90035, 0x2 },
> > > > + { 0x90036, 0x10 },
> > > > + { 0x90037, 0x139 },
> > > > + { 0x90038, 0xf },
> > > > + { 0x90039, 0x7c0 },
> > > > + { 0x9003a, 0x139 },
> > > > + { 0x9003b, 0x44 },
> > > > + { 0x9003c, 0x630 },
> > > > + { 0x9003d, 0x159 },
> > > > + { 0x9003e, 0x14f },
> > > > + { 0x9003f, 0x630 },
> > > > + { 0x90040, 0x159 },
> > > > + { 0x90041, 0x47 },
> > > > + { 0x90042, 0x630 },
> > > > + { 0x90043, 0x149 },
> > > > + { 0x90044, 0x4f },
> > > > + { 0x90045, 0x630 },
> > > > + { 0x90046, 0x179 },
> > > > + { 0x90047, 0x8 },
> > > > + { 0x90048, 0xe0 },
> > > > + { 0x90049, 0x109 },
> > > > + { 0x9004a, 0x0 },
> > > > + { 0x9004b, 0x7c8 },
> > > > + { 0x9004c, 0x109 },
> > > > + { 0x9004d, 0x0 },
> > > > + { 0x9004e, 0x1 },
> > > > + { 0x9004f, 0x8 },
> > > > + { 0x90050, 0x0 },
> > > > + { 0x90051, 0x45a },
> > > > + { 0x90052, 0x9 },
> > > > + { 0x90053, 0x0 },
> > > > + { 0x90054, 0x448 },
> > > > + { 0x90055, 0x109 },
> > > > + { 0x90056, 0x40 },
> > > > + { 0x90057, 0x630 },
> > > > + { 0x90058, 0x179 },
> > > > + { 0x90059, 0x1 },
> > > > + { 0x9005a, 0x618 },
> > > > + { 0x9005b, 0x109 },
> > > > + { 0x9005c, 0x40c0 },
> > > > + { 0x9005d, 0x630 },
> > > > + { 0x9005e, 0x149 },
> > > > + { 0x9005f, 0x8 },
> > > > + { 0x90060, 0x4 },
> > > > + { 0x90061, 0x48 },
> > > > + { 0x90062, 0x4040 },
> > > > + { 0x90063, 0x630 },
> > > > + { 0x90064, 0x149 },
> > > > + { 0x90065, 0x0 },
> > > > + { 0x90066, 0x4 },
> > > > + { 0x90067, 0x48 },
> > > > + { 0x90068, 0x40 },
> > > > + { 0x90069, 0x630 },
> > > > + { 0x9006a, 0x149 },
> > > > + { 0x9006b, 0x10 },
> > > > + { 0x9006c, 0x4 },
> > > > + { 0x9006d, 0x18 },
> > > > + { 0x9006e, 0x0 },
> > > > + { 0x9006f, 0x4 },
> > > > + { 0x90070, 0x78 },
> > > > + { 0x90071, 0x549 },
> > > > + { 0x90072, 0x630 },
> > > > + { 0x90073, 0x159 },
> > > > + { 0x90074, 0xd49 },
> > > > + { 0x90075, 0x630 },
> > > > + { 0x90076, 0x159 },
> > > > + { 0x90077, 0x94a },
> > > > + { 0x90078, 0x630 },
> > > > + { 0x90079, 0x159 },
> > > > + { 0x9007a, 0x441 },
> > > > + { 0x9007b, 0x630 },
> > > > + { 0x9007c, 0x149 },
> > > > + { 0x9007d, 0x42 },
> > > > + { 0x9007e, 0x630 },
> > > > + { 0x9007f, 0x149 },
> > > > + { 0x90080, 0x1 },
> > > > + { 0x90081, 0x630 },
> > > > + { 0x90082, 0x149 },
> > > > + { 0x90083, 0x0 },
> > > > + { 0x90084, 0xe0 },
> > > > + { 0x90085, 0x109 },
> > > > + { 0x90086, 0xa },
> > > > + { 0x90087, 0x10 },
> > > > + { 0x90088, 0x109 },
> > > > + { 0x90089, 0x9 },
> > > > + { 0x9008a, 0x3c0 },
> > > > + { 0x9008b, 0x149 },
> > > > + { 0x9008c, 0x9 },
> > > > + { 0x9008d, 0x3c0 },
> > > > + { 0x9008e, 0x159 },
> > > > + { 0x9008f, 0x18 },
> > > > + { 0x90090, 0x10 },
> > > > + { 0x90091, 0x109 },
> > > > + { 0x90092, 0x0 },
> > > > + { 0x90093, 0x3c0 },
> > > > + { 0x90094, 0x109 },
> > > > + { 0x90095, 0x18 },
> > > > + { 0x90096, 0x4 },
> > > > + { 0x90097, 0x48 },
> > > > + { 0x90098, 0x18 },
> > > > + { 0x90099, 0x4 },
> > > > + { 0x9009a, 0x58 },
> > > > + { 0x9009b, 0xa },
> > > > + { 0x9009c, 0x10 },
> > > > + { 0x9009d, 0x109 },
> > > > + { 0x9009e, 0x2 },
> > > > + { 0x9009f, 0x10 },
> > > > + { 0x900a0, 0x109 },
> > > > + { 0x900a1, 0x5 },
> > > > + { 0x900a2, 0x7c0 },
> > > > + { 0x900a3, 0x109 },
> > > > + { 0x900a4, 0x10 },
> > > > + { 0x900a5, 0x10 },
> > > > + { 0x900a6, 0x109 },
> > > > + { 0x40000, 0x811 },
> > > > + { 0x40020, 0x880 },
> > > > + { 0x40040, 0x0 },
> > > > + { 0x40060, 0x0 },
> > > > + { 0x40001, 0x4008 },
> > > > + { 0x40021, 0x83 },
> > > > + { 0x40041, 0x4f },
> > > > + { 0x40061, 0x0 },
> > > > + { 0x40002, 0x4040 },
> > > > + { 0x40022, 0x83 },
> > > > + { 0x40042, 0x51 },
> > > > + { 0x40062, 0x0 },
> > > > + { 0x40003, 0x811 },
> > > > + { 0x40023, 0x880 },
> > > > + { 0x40043, 0x0 },
> > > > + { 0x40063, 0x0 },
> > > > + { 0x40004, 0x720 },
> > > > + { 0x40024, 0xf },
> > > > + { 0x40044, 0x1740 },
> > > > + { 0x40064, 0x0 },
> > > > + { 0x40005, 0x16 },
> > > > + { 0x40025, 0x83 },
> > > > + { 0x40045, 0x4b },
> > > > + { 0x40065, 0x0 },
> > > > + { 0x40006, 0x716 },
> > > > + { 0x40026, 0xf },
> > > > + { 0x40046, 0x2001 },
> > > > + { 0x40066, 0x0 },
> > > > + { 0x40007, 0x716 },
> > > > + { 0x40027, 0xf },
> > > > + { 0x40047, 0x2800 },
> > > > + { 0x40067, 0x0 },
> > > > + { 0x40008, 0x716 },
> > > > + { 0x40028, 0xf },
> > > > + { 0x40048, 0xf00 },
> > > > + { 0x40068, 0x0 },
> > > > + { 0x40009, 0x720 },
> > > > + { 0x40029, 0xf },
> > > > + { 0x40049, 0x1400 },
> > > > + { 0x40069, 0x0 },
> > > > + { 0x4000a, 0xe08 },
> > > > + { 0x4002a, 0xc15 },
> > > > + { 0x4004a, 0x0 },
> > > > + { 0x4006a, 0x0 },
> > > > + { 0x4000b, 0x623 },
> > > > + { 0x4002b, 0x15 },
> > > > + { 0x4004b, 0x0 },
> > > > + { 0x4006b, 0x0 },
> > > > + { 0x4000c, 0x4028 },
> > > > + { 0x4002c, 0x80 },
> > > > + { 0x4004c, 0x0 },
> > > > + { 0x4006c, 0x0 },
> > > > + { 0x4000d, 0xe08 },
> > > > + { 0x4002d, 0xc1a },
> > > > + { 0x4004d, 0x0 },
> > > > + { 0x4006d, 0x0 },
> > > > + { 0x4000e, 0x623 },
> > > > + { 0x4002e, 0x1a },
> > > > + { 0x4004e, 0x0 },
> > > > + { 0x4006e, 0x0 },
> > > > + { 0x4000f, 0x4040 },
> > > > + { 0x4002f, 0x80 },
> > > > + { 0x4004f, 0x0 },
> > > > + { 0x4006f, 0x0 },
> > > > + { 0x40010, 0x2604 },
> > > > + { 0x40030, 0x15 },
> > > > + { 0x40050, 0x0 },
> > > > + { 0x40070, 0x0 },
> > > > + { 0x40011, 0x708 },
> > > > + { 0x40031, 0x5 },
> > > > + { 0x40051, 0x0 },
> > > > + { 0x40071, 0x2002 },
> > > > + { 0x40012, 0x8 },
> > > > + { 0x40032, 0x80 },
> > > > + { 0x40052, 0x0 },
> > > > + { 0x40072, 0x0 },
> > > > + { 0x40013, 0x2604 },
> > > > + { 0x40033, 0x1a },
> > > > + { 0x40053, 0x0 },
> > > > + { 0x40073, 0x0 },
> > > > + { 0x40014, 0x708 },
> > > > + { 0x40034, 0xa },
> > > > + { 0x40054, 0x0 },
> > > > + { 0x40074, 0x2002 },
> > > > + { 0x40015, 0x4040 },
> > > > + { 0x40035, 0x80 },
> > > > + { 0x40055, 0x0 },
> > > > + { 0x40075, 0x0 },
> > > > + { 0x40016, 0x60a },
> > > > + { 0x40036, 0x15 },
> > > > + { 0x40056, 0x1200 },
> > > > + { 0x40076, 0x0 },
> > > > + { 0x40017, 0x61a },
> > > > + { 0x40037, 0x15 },
> > > > + { 0x40057, 0x1300 },
> > > > + { 0x40077, 0x0 },
> > > > + { 0x40018, 0x60a },
> > > > + { 0x40038, 0x1a },
> > > > + { 0x40058, 0x1200 },
> > > > + { 0x40078, 0x0 },
> > > > + { 0x40019, 0x642 },
> > > > + { 0x40039, 0x1a },
> > > > + { 0x40059, 0x1300 },
> > > > + { 0x40079, 0x0 },
> > > > + { 0x4001a, 0x4808 },
> > > > + { 0x4003a, 0x880 },
> > > > + { 0x4005a, 0x0 },
> > > > + { 0x4007a, 0x0 },
> > > > + { 0x900a7, 0x0 },
> > > > + { 0x900a8, 0x790 },
> > > > + { 0x900a9, 0x11a },
> > > > + { 0x900aa, 0x8 },
> > > > + { 0x900ab, 0x7aa },
> > > > + { 0x900ac, 0x2a },
> > > > + { 0x900ad, 0x10 },
> > > > + { 0x900ae, 0x7b2 },
> > > > + { 0x900af, 0x2a },
> > > > + { 0x900b0, 0x0 },
> > > > + { 0x900b1, 0x7c8 },
> > > > + { 0x900b2, 0x109 },
> > > > + { 0x900b3, 0x10 },
> > > > + { 0x900b4, 0x2a8 },
> > > > + { 0x900b5, 0x129 },
> > > > + { 0x900b6, 0x8 },
> > > > + { 0x900b7, 0x370 },
> > > > + { 0x900b8, 0x129 },
> > > > + { 0x900b9, 0xa },
> > > > + { 0x900ba, 0x3c8 },
> > > > + { 0x900bb, 0x1a9 },
> > > > + { 0x900bc, 0xc },
> > > > + { 0x900bd, 0x408 },
> > > > + { 0x900be, 0x199 },
> > > > + { 0x900bf, 0x14 },
> > > > + { 0x900c0, 0x790 },
> > > > + { 0x900c1, 0x11a },
> > > > + { 0x900c2, 0x8 },
> > > > + { 0x900c3, 0x4 },
> > > > + { 0x900c4, 0x18 },
> > > > + { 0x900c5, 0xe },
> > > > + { 0x900c6, 0x408 },
> > > > + { 0x900c7, 0x199 },
> > > > + { 0x900c8, 0x8 },
> > > > + { 0x900c9, 0x8568 },
> > > > + { 0x900ca, 0x108 },
> > > > + { 0x900cb, 0x18 },
> > > > + { 0x900cc, 0x790 },
> > > > + { 0x900cd, 0x16a },
> > > > + { 0x900ce, 0x8 },
> > > > + { 0x900cf, 0x1d8 },
> > > > + { 0x900d0, 0x169 },
> > > > + { 0x900d1, 0x10 },
> > > > + { 0x900d2, 0x8558 },
> > > > + { 0x900d3, 0x168 },
> > > > + { 0x900d4, 0x70 },
> > > > + { 0x900d5, 0x788 },
> > > > + { 0x900d6, 0x16a },
> > > > + { 0x900d7, 0x1ff8 },
> > > > + { 0x900d8, 0x85a8 },
> > > > + { 0x900d9, 0x1e8 },
> > > > + { 0x900da, 0x50 },
> > > > + { 0x900db, 0x798 },
> > > > + { 0x900dc, 0x16a },
> > > > + { 0x900dd, 0x60 },
> > > > + { 0x900de, 0x7a0 },
> > > > + { 0x900df, 0x16a },
> > > > + { 0x900e0, 0x8 },
> > > > + { 0x900e1, 0x8310 },
> > > > + { 0x900e2, 0x168 },
> > > > + { 0x900e3, 0x8 },
> > > > + { 0x900e4, 0xa310 },
> > > > + { 0x900e5, 0x168 },
> > > > + { 0x900e6, 0xa },
> > > > + { 0x900e7, 0x408 },
> > > > + { 0x900e8, 0x169 },
> > > > + { 0x900e9, 0x6e },
> > > > + { 0x900ea, 0x0 },
> > > > + { 0x900eb, 0x68 },
> > > > + { 0x900ec, 0x0 },
> > > > + { 0x900ed, 0x408 },
> > > > + { 0x900ee, 0x169 },
> > > > + { 0x900ef, 0x0 },
> > > > + { 0x900f0, 0x8310 },
> > > > + { 0x900f1, 0x168 },
> > > > + { 0x900f2, 0x0 },
> > > > + { 0x900f3, 0xa310 },
> > > > + { 0x900f4, 0x168 },
> > > > + { 0x900f5, 0x1ff8 },
> > > > + { 0x900f6, 0x85a8 },
> > > > + { 0x900f7, 0x1e8 },
> > > > + { 0x900f8, 0x68 },
> > > > + { 0x900f9, 0x798 },
> > > > + { 0x900fa, 0x16a },
> > > > + { 0x900fb, 0x78 },
> > > > + { 0x900fc, 0x7a0 },
> > > > + { 0x900fd, 0x16a },
> > > > + { 0x900fe, 0x68 },
> > > > + { 0x900ff, 0x790 },
> > > > + { 0x90100, 0x16a },
> > > > + { 0x90101, 0x8 },
> > > > + { 0x90102, 0x8b10 },
> > > > + { 0x90103, 0x168 },
> > > > + { 0x90104, 0x8 },
> > > > + { 0x90105, 0xab10 },
> > > > + { 0x90106, 0x168 },
> > > > + { 0x90107, 0xa },
> > > > + { 0x90108, 0x408 },
> > > > + { 0x90109, 0x169 },
> > > > + { 0x9010a, 0x58 },
> > > > + { 0x9010b, 0x0 },
> > > > + { 0x9010c, 0x68 },
> > > > + { 0x9010d, 0x0 },
> > > > + { 0x9010e, 0x408 },
> > > > + { 0x9010f, 0x169 },
> > > > + { 0x90110, 0x0 },
> > > > + { 0x90111, 0x8b10 },
> > > > + { 0x90112, 0x168 },
> > > > + { 0x90113, 0x0 },
> > > > + { 0x90114, 0xab10 },
> > > > + { 0x90115, 0x168 },
> > > > + { 0x90116, 0x0 },
> > > > + { 0x90117, 0x1d8 },
> > > > + { 0x90118, 0x169 },
> > > > + { 0x90119, 0x80 },
> > > > + { 0x9011a, 0x790 },
> > > > + { 0x9011b, 0x16a },
> > > > + { 0x9011c, 0x18 },
> > > > + { 0x9011d, 0x7aa },
> > > > + { 0x9011e, 0x6a },
> > > > + { 0x9011f, 0xa },
> > > > + { 0x90120, 0x0 },
> > > > + { 0x90121, 0x1e9 },
> > > > + { 0x90122, 0x8 },
> > > > + { 0x90123, 0x8080 },
> > > > + { 0x90124, 0x108 },
> > > > + { 0x90125, 0xf },
> > > > + { 0x90126, 0x408 },
> > > > + { 0x90127, 0x169 },
> > > > + { 0x90128, 0xc },
> > > > + { 0x90129, 0x0 },
> > > > + { 0x9012a, 0x68 },
> > > > + { 0x9012b, 0x9 },
> > > > + { 0x9012c, 0x0 },
> > > > + { 0x9012d, 0x1a9 },
> > > > + { 0x9012e, 0x0 },
> > > > + { 0x9012f, 0x408 },
> > > > + { 0x90130, 0x169 },
> > > > + { 0x90131, 0x0 },
> > > > + { 0x90132, 0x8080 },
> > > > + { 0x90133, 0x108 },
> > > > + { 0x90134, 0x8 },
> > > > + { 0x90135, 0x7aa },
> > > > + { 0x90136, 0x6a },
> > > > + { 0x90137, 0x0 },
> > > > + { 0x90138, 0x8568 },
> > > > + { 0x90139, 0x108 },
> > > > + { 0x9013a, 0xb7 },
> > > > + { 0x9013b, 0x790 },
> > > > + { 0x9013c, 0x16a },
> > > > + { 0x9013d, 0x1f },
> > > > + { 0x9013e, 0x0 },
> > > > + { 0x9013f, 0x68 },
> > > > + { 0x90140, 0x8 },
> > > > + { 0x90141, 0x8558 },
> > > > + { 0x90142, 0x168 },
> > > > + { 0x90143, 0xf },
> > > > + { 0x90144, 0x408 },
> > > > + { 0x90145, 0x169 },
> > > > + { 0x90146, 0xc },
> > > > + { 0x90147, 0x0 },
> > > > + { 0x90148, 0x68 },
> > > > + { 0x90149, 0x0 },
> > > > + { 0x9014a, 0x408 },
> > > > + { 0x9014b, 0x169 },
> > > > + { 0x9014c, 0x0 },
> > > > + { 0x9014d, 0x8558 },
> > > > + { 0x9014e, 0x168 },
> > > > + { 0x9014f, 0x8 },
> > > > + { 0x90150, 0x3c8 },
> > > > + { 0x90151, 0x1a9 },
> > > > + { 0x90152, 0x3 },
> > > > + { 0x90153, 0x370 },
> > > > + { 0x90154, 0x129 },
> > > > + { 0x90155, 0x20 },
> > > > + { 0x90156, 0x2aa },
> > > > + { 0x90157, 0x9 },
> > > > + { 0x90158, 0x0 },
> > > > + { 0x90159, 0x400 },
> > > > + { 0x9015a, 0x10e },
> > > > + { 0x9015b, 0x8 },
> > > > + { 0x9015c, 0xe8 },
> > > > + { 0x9015d, 0x109 },
> > > > + { 0x9015e, 0x0 },
> > > > + { 0x9015f, 0x8140 },
> > > > + { 0x90160, 0x10c },
> > > > + { 0x90161, 0x10 },
> > > > + { 0x90162, 0x8138 },
> > > > + { 0x90163, 0x10c },
> > > > + { 0x90164, 0x8 },
> > > > + { 0x90165, 0x7c8 },
> > > > + { 0x90166, 0x101 },
> > > > + { 0x90167, 0x8 },
> > > > + { 0x90168, 0x0 },
> > > > + { 0x90169, 0x8 },
> > > > + { 0x9016a, 0x8 },
> > > > + { 0x9016b, 0x448 },
> > > > + { 0x9016c, 0x109 },
> > > > + { 0x9016d, 0xf },
> > > > + { 0x9016e, 0x7c0 },
> > > > + { 0x9016f, 0x109 },
> > > > + { 0x90170, 0x0 },
> > > > + { 0x90171, 0xe8 },
> > > > + { 0x90172, 0x109 },
> > > > + { 0x90173, 0x47 },
> > > > + { 0x90174, 0x630 },
> > > > + { 0x90175, 0x109 },
> > > > + { 0x90176, 0x8 },
> > > > + { 0x90177, 0x618 },
> > > > + { 0x90178, 0x109 },
> > > > + { 0x90179, 0x8 },
> > > > + { 0x9017a, 0xe0 },
> > > > + { 0x9017b, 0x109 },
> > > > + { 0x9017c, 0x0 },
> > > > + { 0x9017d, 0x7c8 },
> > > > + { 0x9017e, 0x109 },
> > > > + { 0x9017f, 0x8 },
> > > > + { 0x90180, 0x8140 },
> > > > + { 0x90181, 0x10c },
> > > > + { 0x90182, 0x0 },
> > > > + { 0x90183, 0x1 },
> > > > + { 0x90184, 0x8 },
> > > > + { 0x90185, 0x8 },
> > > > + { 0x90186, 0x4 },
> > > > + { 0x90187, 0x8 },
> > > > + { 0x90188, 0x8 },
> > > > + { 0x90189, 0x7c8 },
> > > > + { 0x9018a, 0x101 },
> > > > + { 0x90006, 0x0 },
> > > > + { 0x90007, 0x0 },
> > > > + { 0x90008, 0x8 },
> > > > + { 0x90009, 0x0 },
> > > > + { 0x9000a, 0x0 },
> > > > + { 0x9000b, 0x0 },
> > > > + { 0xd00e7, 0x400 },
> > > > + { 0x90017, 0x0 },
> > > > + { 0x9001f, 0x2a },
> > > > + { 0x90026, 0x6a },
> > > > + { 0x400d0, 0x0 },
> > > > + { 0x400d1, 0x101 },
> > > > + { 0x400d2, 0x105 },
> > > > + { 0x400d3, 0x107 },
> > > > + { 0x400d4, 0x10f },
> > > > + { 0x400d5, 0x202 },
> > > > + { 0x400d6, 0x20a },
> > > > + { 0x400d7, 0x20b },
> > > > + { 0x2003a, 0x2 },
> > > > + { 0x2000b, 0x5d },
> > > > + { 0x2000c, 0xbb },
> > > > + { 0x2000d, 0x753 },
> > > > + { 0x2000e, 0x2c },
> > > > + { 0x12000b, 0xc },
> > > > + { 0x12000c, 0x19 },
> > > > + { 0x12000d, 0xfa },
> > > > + { 0x12000e, 0x10 },
> > > > + { 0x22000b, 0x3 },
> > > > + { 0x22000c, 0x6 },
> > > > + { 0x22000d, 0x3e },
> > > > + { 0x22000e, 0x10 },
> > > > + { 0x9000c, 0x0 },
> > > > + { 0x9000d, 0x173 },
> > > > + { 0x9000e, 0x60 },
> > > > + { 0x9000f, 0x6110 },
> > > > + { 0x90010, 0x2152 },
> > > > + { 0x90011, 0xdfbd },
> > > > + { 0x90012, 0x60 },
> > > > + { 0x90013, 0x6152 },
> > > > + { 0x20010, 0x5a },
> > > > + { 0x20011, 0x3 },
> > > > + { 0x40080, 0xe0 },
> > > > + { 0x40081, 0x12 },
> > > > + { 0x40082, 0xe0 },
> > > > + { 0x40083, 0x12 },
> > > > + { 0x40084, 0xe0 },
> > > > + { 0x40085, 0x12 },
> > > > + { 0x140080, 0xe0 },
> > > > + { 0x140081, 0x12 },
> > > > + { 0x140082, 0xe0 },
> > > > + { 0x140083, 0x12 },
> > > > + { 0x140084, 0xe0 },
> > > > + { 0x140085, 0x12 },
> > > > + { 0x240080, 0xe0 },
> > > > + { 0x240081, 0x12 },
> > > > + { 0x240082, 0xe0 },
> > > > + { 0x240083, 0x12 },
> > > > + { 0x240084, 0xe0 },
> > > > + { 0x240085, 0x12 },
> > > > + { 0x400fd, 0xf },
> > > > + { 0x10011, 0x1 },
> > > > + { 0x10012, 0x1 },
> > > > + { 0x10013, 0x180 },
> > > > + { 0x10018, 0x1 },
> > > > + { 0x10002, 0x6209 },
> > > > + { 0x100b2, 0x1 },
> > > > + { 0x101b4, 0x1 },
> > > > + { 0x102b4, 0x1 },
> > > > + { 0x103b4, 0x1 },
> > > > + { 0x104b4, 0x1 },
> > > > + { 0x105b4, 0x1 },
> > > > + { 0x106b4, 0x1 },
> > > > + { 0x107b4, 0x1 },
> > > > + { 0x108b4, 0x1 },
> > > > + { 0x11011, 0x1 },
> > > > + { 0x11012, 0x1 },
> > > > + { 0x11013, 0x180 },
> > > > + { 0x11018, 0x1 },
> > > > + { 0x11002, 0x6209 },
> > > > + { 0x110b2, 0x1 },
> > > > + { 0x111b4, 0x1 },
> > > > + { 0x112b4, 0x1 },
> > > > + { 0x113b4, 0x1 },
> > > > + { 0x114b4, 0x1 },
> > > > + { 0x115b4, 0x1 },
> > > > + { 0x116b4, 0x1 },
> > > > + { 0x117b4, 0x1 },
> > > > + { 0x118b4, 0x1 },
> > > > + { 0x12011, 0x1 },
> > > > + { 0x12012, 0x1 },
> > > > + { 0x12013, 0x180 },
> > > > + { 0x12018, 0x1 },
> > > > + { 0x12002, 0x6209 },
> > > > + { 0x120b2, 0x1 },
> > > > + { 0x121b4, 0x1 },
> > > > + { 0x122b4, 0x1 },
> > > > + { 0x123b4, 0x1 },
> > > > + { 0x124b4, 0x1 },
> > > > + { 0x125b4, 0x1 },
> > > > + { 0x126b4, 0x1 },
> > > > + { 0x127b4, 0x1 },
> > > > + { 0x128b4, 0x1 },
> > > > + { 0x13011, 0x1 },
> > > > + { 0x13012, 0x1 },
> > > > + { 0x13013, 0x180 },
> > > > + { 0x13018, 0x1 },
> > > > + { 0x13002, 0x6209 },
> > > > + { 0x130b2, 0x1 },
> > > > + { 0x131b4, 0x1 },
> > > > + { 0x132b4, 0x1 },
> > > > + { 0x133b4, 0x1 },
> > > > + { 0x134b4, 0x1 },
> > > > + { 0x135b4, 0x1 },
> > > > + { 0x136b4, 0x1 },
> > > > + { 0x137b4, 0x1 },
> > > > + { 0x138b4, 0x1 },
> > > > + { 0x2003a, 0x2 },
> > > > + { 0xc0080, 0x2 },
> > > > + { 0xd0000, 0x1 },
> > > > +};
> > >
> > > The same as above.
> > >
> > > > +
> > > > +struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
> > > > + {
> > > > + /* P0 3000mts 1D */
> > > > + .drate = 3000,
> > > > + .fw_type = FW_1D_IMAGE,
> > > > + .fsp_cfg = lpddr4_fsp0_cfg,
> > > > + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg),
> > > > + },
> > > > + {
> > > > + /* P0 3000mts 2D */
> > > > + .drate = 3000,
> > > > + .fw_type = FW_2D_IMAGE,
> > > > + .fsp_cfg = lpddr4_fsp0_2d_cfg,
> > > > + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg),
> > > > + },
> > > > + {
> > > > + /* P1 400mts 1D */
> > > > + .drate = 400,
> > > > + .fw_type = FW_1D_IMAGE,
> > > > + .fsp_cfg = lpddr4_fsp1_cfg,
> > > > + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg),
> > > > + },
> > > > + {
> > > > + /* P1 100mts 1D */
> > > > + .drate = 100,
> > > > + .fw_type = FW_1D_IMAGE,
> > > > + .fsp_cfg = lpddr4_fsp2_cfg,
> > > > + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg),
> > > > + },
> > > > +};
> > > > +
> > > > +/* lpddr4 timing config params on EVK board */
> > > > +struct dram_timing_info dram_timing = {
> > > > + .ddrc_cfg = lpddr4_ddrc_cfg,
> > > > + .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
> > > > + .ddrphy_cfg = lpddr4_ddrphy_cfg,
> > > > + .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg),
> > > > + .fsp_msg = lpddr4_dram_fsp_msg,
> > > > + .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg),
> > > > + .ddrphy_trained_csr = lpddr4_ddrphy_trained_csr,
> > > > + .ddrphy_trained_csr_num =
> > > > ARRAY_SIZE(lpddr4_ddrphy_trained_csr),
> > > > + .ddrphy_pie = lpddr4_phy_pie,
> > > > + .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
> > >
> > > It would be best to get the above values calculated dynamically for
> > > this SoC.
> > >
> > > > +};
> > > > diff --git a/board/freescale/imx8mm_evk/spl.c
> > > > b/board/freescale/imx8mm_evk/spl.c new file mode 100644
> > > > index 0000000000..cf1dfc2c2a
> > > > --- /dev/null
> > > > +++ b/board/freescale/imx8mm_evk/spl.c
> > > > @@ -0,0 +1,187 @@
> > > > +// SPDX-License-Identifier: GPL-2.0+
> > > > +/*
> > > > + * Copyright 2019 NXP
> > > > + */
> > > > +
> > > > +#include <common.h>
> > > > +#include <spl.h>
> > > > +#include <asm/io.h>
> > > > +#include <errno.h>
> > > > +#include <asm/io.h>
> > > > +#include <asm/mach-imx/iomux-v3.h>
> > > > +#include <asm/arch/imx8mm_pins.h>
> > > > +#include <asm/arch/sys_proto.h>
> > > > +#include <power/pmic.h>
> > > > +#include <asm/arch/clock.h>
> > > > +#include <asm/mach-imx/gpio.h>
> > > > +#include <asm/mach-imx/mxc_i2c.h>
> > > > +#include <fsl_esdhc.h>
> > > > +#include <mmc.h>
> > > > +#include <asm/arch/ddr.h>
> > > > +
> > > > +DECLARE_GLOBAL_DATA_PTR;
> > > > +
> > > > +void spl_dram_init(void)
> > > > +{
> > > > + ddr_init(&dram_timing);
> > > > +}
> > > > +
> > > > +#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 18)
> > > > +#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
> > > > +
> > > > +#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS |
> > > PAD_CTL_PUE | \
> > > > + PAD_CTL_PE | PAD_CTL_FSEL2)
> > > > +#define USDHC_GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE1)
> > > > +
> > > > +static iomux_v3_cfg_t const usdhc3_pads[] = {
> > > > + IMX8MM_PAD_NAND_WE_B_USDHC3_CLK |
> > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > + IMX8MM_PAD_NAND_WP_B_USDHC3_CMD |
> > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > + IMX8MM_PAD_NAND_DATA04_USDHC3_DATA0 |
> > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > + IMX8MM_PAD_NAND_DATA05_USDHC3_DATA1 |
> > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > + IMX8MM_PAD_NAND_DATA06_USDHC3_DATA2 |
> > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > + IMX8MM_PAD_NAND_DATA07_USDHC3_DATA3 |
> > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > + IMX8MM_PAD_NAND_RE_B_USDHC3_DATA4 |
> > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > + IMX8MM_PAD_NAND_CE2_B_USDHC3_DATA5 |
> > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > + IMX8MM_PAD_NAND_CE3_B_USDHC3_DATA6 |
> > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > + IMX8MM_PAD_NAND_CLE_USDHC3_DATA7 |
> > > > MUX_PAD_CTRL(USDHC_PAD_CTRL), +};
> > > > +
> > > > +static iomux_v3_cfg_t const usdhc2_pads[] = {
> > > > + IMX8MM_PAD_SD2_CLK_USDHC2_CLK |
> > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > + IMX8MM_PAD_SD2_CMD_USDHC2_CMD |
> > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > + IMX8MM_PAD_SD2_DATA0_USDHC2_DATA0 |
> > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > + IMX8MM_PAD_SD2_DATA1_USDHC2_DATA1 |
> > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > + IMX8MM_PAD_SD2_DATA2_USDHC2_DATA2 |
> > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > + IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 |
> > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > + IMX8MM_PAD_SD2_RESET_B_GPIO2_IO19 |
> > > > MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), +};
> > > > +
> > > > +/*
> > > > + * The evk board uses DAT3 to detect CD card plugin,
> > > > + * in u-boot we mux the pin to GPIO when doing board_mmc_getcd.
> > > > + */
> > > > +static iomux_v3_cfg_t const usdhc2_cd_pad =
> > > > + IMX8MM_PAD_SD2_DATA3_GPIO2_IO18 |
> > > > MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL); +
> > > > +static iomux_v3_cfg_t const usdhc2_dat3_pad =
> > > > + IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 |
> > > > + MUX_PAD_CTRL(USDHC_PAD_CTRL);
> > > > +
> > > > +static struct fsl_esdhc_cfg usdhc_cfg[2] = {
> > > > + {USDHC2_BASE_ADDR, 0, 1},
> > > > + {USDHC3_BASE_ADDR, 0, 1},
> > > > +};
> > > > +
> > > > +int board_mmc_init(bd_t *bis)
> > > > +{
> > > > + int i, ret;
> > > > + /*
> > > > + * According to the board_mmc_init() the following map is
> > > > done:
> > > > + * (U-Boot device node) (Physical Port)
> > > > + * mmc0 USDHC1
> > > > + * mmc1 USDHC2
> > > > + */
> > > > + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
> > > > + switch (i) {
> > > > + case 0:
> > > > + usdhc_cfg[0].sdhc_clk =
> > > > mxc_get_clock(MXC_ESDHC2_CLK);
> > > > +
> > > > imx_iomux_v3_setup_multiple_pads(usdhc2_pads, +
> > > > ARRAY_SIZE(usdhc2_pads));
> > > > + gpio_request(USDHC2_PWR_GPIO,
> > > > "usdhc2_reset");
> > > > + gpio_direction_output(USDHC2_PWR_GPIO,
> > > > 0);
> > > > + udelay(500);
> > > > + gpio_direction_output(USDHC2_PWR_GPIO,
> > > > 1);
> > > > + break;
> > > > + case 1:
> > > > + usdhc_cfg[1].sdhc_clk =
> > > > mxc_get_clock(MXC_ESDHC3_CLK);
> > > > +
> > > > imx_iomux_v3_setup_multiple_pads(usdhc3_pads, +
> > > > ARRAY_SIZE(usdhc3_pads));
> > > > + break;
> > >
> > > It would be best if you could enable DM/DTS in SPL too from the
> > > outset (and share the SPL size).
> > >
> > > Do you have any timeline for converting SPL to DM/DTS?
> > >
> > > > + default:
> > > > + printf("USDHC controllers %d not
> > > > supported \n", i + 1);
> > > > + return -EINVAL;
> > > > + }
> > > > +
> > > > + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
> > > > + if (ret)
> > > > + return ret;
> > > > + }
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > +int board_mmc_getcd(struct mmc *mmc)
> > > > +{
> > > > + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg
> > > > *)mmc->priv;
> > > > + int ret = 0;
> > > > +
> > > > + switch (cfg->esdhc_base) {
> > > > + case USDHC3_BASE_ADDR:
> > > > + ret = 1;
> > > > + break;
> > > > + case USDHC2_BASE_ADDR:
> > > > + imx_iomux_v3_setup_pad(usdhc2_cd_pad);
> > > > + gpio_request(USDHC2_CD_GPIO, "usdhc2 cd");
> > > > + gpio_direction_input(USDHC2_CD_GPIO);
> > > > +
> > > > + /*
> > > > + * Since it is the DAT3 pin, this pin is pulled
> > > > to
> > > > + * low voltage if no card
> > > > + */
> > > > + ret = gpio_get_value(USDHC2_CD_GPIO);
> > > > +
> > > > + imx_iomux_v3_setup_pad(usdhc2_dat3_pad);
> > > > + return ret;
> > > > + }
> > > > +
> > > > + return 1;
> > > > +}
> > > > +
> > > > +void spl_board_init(void)
> > > > +{
> > > > + puts("Normal Boot\n");
> > > > +}
> > > > +
> > > > +#ifdef CONFIG_SPL_LOAD_FIT
> > > > +int board_fit_config_name_match(const char *name)
> > > > +{
> > > > + /* Just empty function now - can't decide what to choose
> > > > */
> > > > + debug("%s: %s\n", __func__, name);
> > > > +
> > > > + return 0;
> > > > +}
> > > > +#endif
> > > > +
> > > > +void board_init_f(ulong dummy)
> > > > +{
> > > > + int ret;
> > > > +
> > > > + /* Clear global data */
> > > > + memset((void *)gd, 0, sizeof(gd_t));
> > > > +
> > > > + arch_cpu_init();
> > > > +
> > > > + init_uart_clk(1);
> > > > +
> > > > + board_early_init_f();
> > > > +
> > > > + timer_init();
> > > > +
> > > > + preloader_console_init();
> > > > +
> > > > + /* Clear the BSS. */
> > > > + memset(__bss_start, 0, __bss_end - __bss_start);
> > > > +
> > > > + ret = spl_init();
> > > > + if (ret) {
> > > > + debug("spl_init() failed: %d\n", ret);
> > > > + hang();
> > > > + }
> > > > +
> > > > + enable_tzc380();
> > > > +
> > > > + /* DDR initialization */
> > > > + spl_dram_init();
> > > > +
> > > > + board_init_r(NULL, 0);
> > > > +}
> > > > diff --git a/configs/imx8mm_evk_defconfig
> > > > b/configs/imx8mm_evk_defconfig new file mode 100644
> > > > index 0000000000..6110f23e38
> > > > --- /dev/null
> > > > +++ b/configs/imx8mm_evk_defconfig
> > > > @@ -0,0 +1,41 @@
> > > > +CONFIG_ARM=y
> > > > +CONFIG_ARCH_IMX8M=y
> > > > +CONFIG_SYS_TEXT_BASE=0x40200000
> > > > +CONFIG_SPL_GPIO_SUPPORT=y
> > > > +CONFIG_SYS_MALLOC_F_LEN=0x2000
> > > > +CONFIG_TARGET_IMX8MM_EVK=y
> > > > +CONFIG_SPL_MMC_SUPPORT=y
> > > > +CONFIG_SPL_SERIAL_SUPPORT=y
> > > > +CONFIG_SPL=y
> > > > +CONFIG_FIT=y
> > > > +CONFIG_FIT_EXTERNAL_OFFSET=0x3000
> > > > +CONFIG_SPL_LOAD_FIT=y
> > > >
> +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
> > > >
> > >
> +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m
> > > /imximage.cfg,SPL_TEXT_BASE=0x7E1000"
> > > > +CONFIG_DEFAULT_FDT_FILE="fsl-imx8mm-evk.dtb"
> > > > +CONFIG_SPL_BOARD_INIT=y
> > > > +CONFIG_SPL_I2C_SUPPORT=y
> > > > +CONFIG_HUSH_PARSER=y
> > > > +CONFIG_CMD_GPIO=y
> > > > +CONFIG_CMD_I2C=y
> > > > +CONFIG_CMD_CACHE=y
> > > > +CONFIG_CMD_REGULATOR=y
> > > > +CONFIG_CMD_EXT2=y
> > > > +CONFIG_CMD_EXT4=y
> > > > +CONFIG_CMD_EXT4_WRITE=y
> > > > +CONFIG_CMD_FAT=y
> > > > +CONFIG_OF_CONTROL=y
> > > > +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mm-evk"
> > > > +CONFIG_DM_GPIO=y
> > > > +CONFIG_MXC_GPIO=y
> > > > +CONFIG_DM_I2C=y
> > > > +CONFIG_SYS_I2C_MXC=y
> > > > +CONFIG_DM_MMC=y
> > > > +CONFIG_DM_ETH=y
> > >
> > > Here you enable the DM_ETH, but the welcome u-boot info says:
> > >
> > > "Net: No ethernet found."
> > >
> > > > +CONFIG_PINCTRL=y
> > > > +CONFIG_PINCTRL_IMX8M=y
> > > > +CONFIG_DM_REGULATOR=y
> > > > +CONFIG_DM_REGULATOR_FIXED=y
> > > > +CONFIG_DM_REGULATOR_GPIO=y
> > > > +CONFIG_MXC_UART=y
> > > > +CONFIG_DM_THERMAL=y
> > > > diff --git a/include/configs/imx8mm_evk.h
> > > > b/include/configs/imx8mm_evk.h new file mode 100644
> > > > index 0000000000..f944308757
> > > > --- /dev/null
> > > > +++ b/include/configs/imx8mm_evk.h
> > > > @@ -0,0 +1,221 @@
> > > > +/* SPDX-License-Identifier: GPL-2.0+ */
> > > > +/*
> > > > + * Copyright 2018 NXP
> > > > + */
> > > > +
> > > > +#ifndef __IMX8MM_EVK_H
> > > > +#define __IMX8MM_EVK_H
> > > > +
> > > > +#include <linux/sizes.h>
> > > > +#include <asm/arch/imx-regs.h>
> > > > +
> > > > +#ifdef CONFIG_SECURE_BOOT
> > > > +#define CONFIG_CSF_SIZE 0x2000 /* 8K
> > > > region */ +#endif
> > > > +
> > > > +#define CONFIG_SPL_MAX_SIZE (148 * 1024)
> > > > +#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
> > > > +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
> > > > +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
> 0x300
> > > > +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
> > > > +#define CONFIG_SYS_UBOOT_BASE \
> > > > + (QSPI0_AMBA_BASE +
> > > CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR *
> > > > 512) +
> > > > +#ifdef CONFIG_SPL_BUILD
> > > > +/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
> > > > +#define CONFIG_SPL_WATCHDOG_SUPPORT
> > > > +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
> > > > +#define CONFIG_SPL_POWER_SUPPORT
> > > > +#define
> > > > CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
> > > > +#define CONFIG_SPL_STACK 0x91fff0 +#define
> > > > CONFIG_SPL_LIBCOMMON_SUPPORT +#define
> > > CONFIG_SPL_LIBGENERIC_SUPPORT
> > > > +#define CONFIG_SPL_BSS_START_ADDR 0x00910000
> > > > +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
> > > > +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
> > > > +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB
> > > > */ +#define CONFIG_SYS_ICACHE_OFF
> > > > +#define CONFIG_SYS_DCACHE_OFF
> > > > +
> > > > +#define CONFIG_MALLOC_F_ADDR 0x912000 /* malloc f
> > > > used before GD_FLG_FULL_MALLOC_INIT set */ +
> > > > +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image
> gives a
> > > error
> > > > info not panic */ +
> > > > +#undef CONFIG_DM_MMC
> > > > +#undef CONFIG_DM_PMIC
> > > > +#undef CONFIG_DM_PMIC_PFUZE100
> > >
> > > Why do you need to undef those config options?
> > >
> > > > +
> > > > +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> > > > +
> > > > +#endif
> > > > +
> > > > +#define CONFIG_REMAKE_ELF
> > > > +
> > > > +#define CONFIG_BOARD_EARLY_INIT_F
> > > > +#define CONFIG_BOARD_POSTCLK_INIT
> > > > +#define CONFIG_BOARD_LATE_INIT
> > > > +
> > > > +/* Flat Device Tree Definitions */
> > > > +#define CONFIG_OF_BOARD_SETUP
> > > > +
> > > > +#undef CONFIG_CMD_EXPORTENV
> > > > +#undef CONFIG_CMD_IMPORTENV
> > > > +#undef CONFIG_CMD_IMLS
> > > > +
> > > > +#undef CONFIG_CMD_CRC32
> > > > +#undef CONFIG_BOOTM_NETBSD
> > >
> > > There seems to be some issue with inheritance, as you need to undef
> > > those values manually.
> > >
> > > Why is it needed?
> > >
> > > > +
> > > > +/* ENET Config */
> > > > +/* ENET1 */
> > > > +#if defined(CONFIG_CMD_NET)
> > > > +#define CONFIG_CMD_PING
> > > > +#define CONFIG_CMD_DHCP
> > > > +#define CONFIG_CMD_MII
> > > > +#define CONFIG_MII
> > > > +#define CONFIG_ETHPRIME "FEC"
> > > > +
> > > > +#define CONFIG_FEC_MXC
> > > > +#define CONFIG_FEC_XCV_TYPE RGMII
> > > > +#define CONFIG_FEC_MXC_PHYADDR 0
> > > > +#define FEC_QUIRK_ENET_MAC
> > > > +
> > > > +#define CONFIG_PHY_GIGE
> > > > +#define IMX_FEC_BASE 0x30BE0000
> > > > +
> > > > +#define CONFIG_PHYLIB
> > > > +#define CONFIG_PHY_ATHEROS
> > > > +#endif
> > > > +
> > > > +/* Initial environment variables */
> > > > +#define CONFIG_EXTRA_ENV_SETTINGS \
> > > > + "script=boot.scr\0" \
> > > > + "image=Image\0" \
> > > > + "console=ttymxc1,115200
> > > > earlycon=ec_imx6q,0x30890000,115200\0" \
> > > > + "fdt_addr=0x43000000\0" \
> > > > + "fdt_high=0xffffffffffffffff\0" \
> > > > + "boot_fdt=try\0" \
> > > > + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
> > > > + "initrd_addr=0x43800000\0" \
> > > > + "initrd_high=0xffffffffffffffff\0" \
> > > > + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
> > > > + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART)
> > > > "\0" \
> > > > + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
> > > > + "mmcautodetect=yes\0" \
> > > > + "mmcargs=setenv bootargs ${jh_clk} console=${console}
> > > > root=${mmcroot}\0 " \
> > > > + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart}
> > > > ${loadaddr} ${script};\0" \
> > > > + "bootscript=echo Running bootscript from mmc ...; " \
> > > > + "source\0" \
> > > > + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}
> > > > ${image}\0" \
> > > > + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr}
> > > > ${fdt_file}\0" \
> > > > + "mmcboot=echo Booting from mmc ...; " \
> > > > + "run mmcargs; " \
> > > > + "if test ${boot_fdt} = yes || test ${boot_fdt} =
> > > > try; then " \
> > > > + "if run loadfdt; then " \
> > > > + "booti ${loadaddr} -
> > > > ${fdt_addr}; " \
> > > > + "else " \
> > > > + "echo WARN: Cannot load the DT;
> > > > " \
> > > > + "fi; " \
> > > > + "else " \
> > > > + "echo wait for boot; " \
> > > > + "fi;\0" \
> > > > + "netargs=setenv bootargs ${jh_clk} console=${console} " \
> > > > + "root=/dev/nfs " \
> > > > + "ip=dhcp
> > > > nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
> > > > + "netboot=echo Booting from net ...; " \
> > > > + "run netargs; " \
> > > > + "if test ${ip_dyn} = yes; then " \
> > > > + "setenv get_cmd dhcp; " \
> > > > + "else " \
> > > > + "setenv get_cmd tftp; " \
> > > > + "fi; " \
> > > > + "${get_cmd} ${loadaddr} ${image}; " \
> > > > + "if test ${boot_fdt} = yes || test ${boot_fdt} =
> > > > try; then " \
> > > > + "if ${get_cmd} ${fdt_addr} ${fdt_file};
> > > > then " \
> > > > + "booti ${loadaddr} -
> > > > ${fdt_addr}; " \
> > > > + "else " \
> > > > + "echo WARN: Cannot load the DT;
> > > > " \
> > > > + "fi; " \
> > > > + "else " \
> > > > + "booti; " \
> > > > + "fi;\0"
> > > > +
> > > > +#define CONFIG_BOOTCOMMAND \
> > > > + "mmc dev ${mmcdev}; if mmc rescan; then " \
> > > > + "if run loadbootscript; then " \
> > > > + "run bootscript; " \
> > > > + "else " \
> > > > + "if run loadimage; then " \
> > > > + "run mmcboot; " \
> > > > + "else run netboot; " \
> > > > + "fi; " \
> > > > + "fi; " \
> > > > + "else booti ${loadaddr} - ${fdt_addr}; fi"
> > > > +
> > > > +/* Link Definitions */
> > > > +#define CONFIG_LOADADDR 0x40480000
> > > > +
> > > > +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
> > > > +
> > > > +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
> > > > +#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
> > > > +#define CONFIG_SYS_INIT_SP_OFFSET \
> > > > + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> > > > +#define CONFIG_SYS_INIT_SP_ADDR \
> > > > + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
> > > > +
> > > > +#define CONFIG_ENV_OVERWRITE
> > > > +#if defined(CONFIG_ENV_IS_IN_MMC)
> > > > +#define CONFIG_ENV_OFFSET (64 * SZ_64K)
> > > > +#endif
> > > > +#define CONFIG_ENV_SIZE 0x1000
> > > > +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC2 */
> > > > +#define
> > > > CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2
> > > > */ + +/* Size of malloc() pool */
> > > > +#define CONFIG_SYS_MALLOC_LEN SZ_32M
> > > > +
> > > > +#define CONFIG_SYS_SDRAM_BASE 0x40000000
> > > > +#define PHYS_SDRAM 0x40000000
> > > > +#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB
> > > > DDR */ +
> > > > +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
> > > > +#define CONFIG_SYS_MEMTEST_END
> > > (CONFIG_SYS_MEMTEST_START +
> > > > (PHYS_SDRAM_SIZE >> 1)) +
> > > > +#define CONFIG_BAUDRATE 115200
> > > > +
> > > > +#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
> > > > +
> > > > +/* Monitor Command Prompt */
> > > > +#undef CONFIG_SYS_PROMPT
> > > > +#define CONFIG_SYS_PROMPT "u-boot=> "
> > > > +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
> > > > +#define CONFIG_SYS_CBSIZE 2048
> > > > +#define CONFIG_SYS_MAXARGS 64
> > > > +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
> > > > +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
> > > > +
> > > > sizeof(CONFIG_SYS_PROMPT) + 16) +
> > > > +#define CONFIG_IMX_BOOTAUX
> > > > +
> > > > +/* USDHC */
> > > > +#define CONFIG_CMD_MMC
> > > > +#define CONFIG_FSL_ESDHC
> > > > +#define CONFIG_FSL_USDHC
> > > > +
> > > > +#define CONFIG_SYS_FSL_USDHC_NUM 2
> > > > +#define CONFIG_SYS_FSL_ESDHC_ADDR 0
> > > > +
> > > > +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
> > > > +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
> > > > +
> > > > +#define CONFIG_MXC_OCOTP
> > > > +#define CONFIG_CMD_FUSE
> > > > +
> > > > +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus
> > > > 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable
> > > > I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /*
> > > > enable I2C bus 3 */ +#define CONFIG_SYS_I2C_SPEED
> > > > 100000
> > >
> > > Some of those values are (SYS_I2C_*, MXC_OCOTP, FSL_*) are already
> > > supported by Kconfig. Please use Kconfig instead.
> > >
> > > > +
> > > > +#define CONFIG_OF_SYSTEM_SETUP
> > > > +
> > > > +#endif
> > >
> > >
> > > Best regards,
> > >
> > > Lukasz Majewski
> > >
> > > --
> > >
> > > DENX Software Engineering GmbH, Managing Director: Wolfgang
> > > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell,
> > > Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> > > lukma at denx.de
>
>
>
>
> Best regards,
>
> Lukasz Majewski
>
> --
>
> DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> lukma at denx.de
^ permalink raw reply [flat|nested] 39+ messages in thread* [U-Boot] [PATCH 20/20] imx: add i.MX8MM EVK board support
2019-01-30 7:07 ` Peng Fan
@ 2019-01-30 8:37 ` Lukasz Majewski
2019-01-30 8:50 ` Peng Fan
0 siblings, 1 reply; 39+ messages in thread
From: Lukasz Majewski @ 2019-01-30 8:37 UTC (permalink / raw)
To: u-boot
On Wed, 30 Jan 2019 07:07:10 +0000
Peng Fan <peng.fan@nxp.com> wrote:
> > -----Original Message-----
> > From: Lukasz Majewski [mailto:lukma at denx.de]
> > Sent: 2019年1月30日 14:54
> > To: Peng Fan <peng.fan@nxp.com>
> > Cc: sbabic at denx.de; Fabio Estevam <fabio.estevam@nxp.com>;
> > dl-uboot-imx <uboot-imx@nxp.com>; u-boot at lists.denx.de
> > Subject: Re: [U-Boot] [PATCH 20/20] imx: add i.MX8MM EVK board
> > support
> >
> > Hi Peng,
> >
> > > > -----Original Message-----
> > > > From: Lukasz Majewski [mailto:lukma at denx.de]
> > > > Sent: 2019年1月30日 7:19
> > > > To: Peng Fan <peng.fan@nxp.com>
> > > > Cc: sbabic at denx.de; Fabio Estevam <fabio.estevam@nxp.com>;
> > > > dl-uboot-imx <uboot-imx@nxp.com>; u-boot at lists.denx.de
> > > > Subject: Re: [U-Boot] [PATCH 20/20] imx: add i.MX8MM EVK board
> > > > support
> > > >
> > > > Hi Peng,
> > > >
> > > > > Add i.MX8MM EVK board support.
> > > > >
> > > > > Add board and SoC dts
> > > > > Add ddr training code
> > > > > support SD/MMC/GPIO/PINCTRL/UART
> > > > >
> > > > > U-Boot SPL 2019.01-00148-g1179cffe66 (Jan 28 2019 - 17:37:34
> > > > > +0800) Normal Boot
> > > > > Trying to boot from MMC1
> > > > >
> > > > > U-Boot 2019.01-00148-g1179cffe66 (Jan 28 2019 - 17:37:34
> > > > > +0800)
> > > > >
> > > > > CPU: Freescale i.MX8MMQ rev1.0 at 1200 MHz
> > > > > Reset cause: POR
> > > > > Model: NXP i.MX8MM EVK board
> > > > > DRAM: 2 GiB
> > > > > MMC: FSL_SDHC: 1, FSL_SDHC: 2
> > > > > In: serial
> > > > > Out: serial
> > > > > Err: serial
> > > > > DM
> > > >
> > > > You set/adjust latter in the code the fec network driver. Why
> > > > it is not found?
> > >
> > > I dropped network support, could add it in V2.
> >
> > From the patch it seems like the ETH is fully supported, at lease
> > from the source code point of view.
> >
> > >
> > > >
> > > > Could you also share the output of "dm tree" command?
> > >
> > > Sure.
> > >
> > > >
> > > > I suppose/guess that this board shall support as much as
> > > > possible of the DT/DM conversions?
> > >
> > > Ok.
> >
> > And I would like to emphasize the need of DDR training code (as a
> > functions, not pair of offset and value).
> >
> > Are you able to provide such code in the next version of the
> > patch?
>
> There is already common code under drivers/ddr/imx8m
Yes. Indeed there code is there.
> For the array in board file, It need ddr tool change, out of my
> knowledge.
If the code is there - why not use it for this board? In that way we
would kill two birds with one stone - the code would be tested on
"blessed" NXP's development board.
>
> Thanks,
> Peng.
>
> >
> > >
> > > Regards,
> > > Peng.
> > >
> > > >
> > > > > Hit any key to stop autoboot: 2
> > > > >
> > > > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > > > ---
> > > > > arch/arm/dts/fsl-imx8mm-evk.dts | 203 +++
> > > > > arch/arm/dts/fsl-imx8mm.dtsi | 586 ++++++++
> > > > > arch/arm/mach-imx/imx8m/Kconfig | 7 +
> > > > > board/freescale/imx8mm_evk/Kconfig | 12 +
> > > > > board/freescale/imx8mm_evk/MAINTAINERS | 6 +
> > > > > board/freescale/imx8mm_evk/Makefile | 12 +
> > > > > board/freescale/imx8mm_evk/imx8mm_evk.c | 144 ++
> > > > > board/freescale/imx8mm_evk/lpddr4_timing.c | 1980
> > > > > ++++++++++++++++++++++++++++
> > > > > board/freescale/imx8mm_evk/spl.c | 187 +++
> > > > > configs/imx8mm_evk_defconfig | 41 +
> > > > > include/configs/imx8mm_evk.h | 221 ++++ 11
> > > > > files changed, 3399 insertions(+) create mode 100644
> > > > > arch/arm/dts/fsl-imx8mm-evk.dts create mode 100644
> > > > > arch/arm/dts/fsl-imx8mm.dtsi create mode 100644
> > > > > board/freescale/imx8mm_evk/Kconfig create mode 100644
> > > > > board/freescale/imx8mm_evk/MAINTAINERS create mode 100644
> > > > > board/freescale/imx8mm_evk/Makefile create mode 100644
> > > > > board/freescale/imx8mm_evk/imx8mm_evk.c create mode 100644
> > > > > board/freescale/imx8mm_evk/lpddr4_timing.c create mode 100644
> > > > > board/freescale/imx8mm_evk/spl.c create mode 100644
> > > > > configs/imx8mm_evk_defconfig create mode 100644
> > > > > include/configs/imx8mm_evk.h
> > > > >
> > > > > diff --git a/arch/arm/dts/fsl-imx8mm-evk.dts
> > > > > b/arch/arm/dts/fsl-imx8mm-evk.dts new file mode 100644
> > > > > index 0000000000..df409eca47
> > > > > --- /dev/null
> > > > > +++ b/arch/arm/dts/fsl-imx8mm-evk.dts
> > > > > @@ -0,0 +1,203 @@
> > > > > +// SPDX-License-Identifier: GPL-2.0+
> > > > > +/*
> > > > > + * Copyright 2019 NXP
> > > > > + */
> > > > > +
> > > > > +/dts-v1/;
> > > > > +
> > > > > +#include "fsl-imx8mm.dtsi"
> > > > > +
> > > > > +/ {
> > > > > + model = "NXP i.MX8MM EVK board";
> > > > > + compatible = "fsl,imx8mm-evk", "fsl,imx8mm";
> > > > > +
> > > > > + chosen {
> > > > > + stdout-path = &uart2;
> > > > > + };
> > > > > +
> > > > > + regulators {
> > > > > + compatible = "simple-bus";
> > > > > + #address-cells = <1>;
> > > > > + #size-cells = <0>;
> > > > > +
> > > > > + reg_usdhc2_vmmc: regulator-usdhc2 {
> > > > > + compatible = "regulator-fixed";
> > > > > + regulator-name = "VSD_3V3";
> > > > > + regulator-min-microvolt = <3300000>;
> > > > > + regulator-max-microvolt = <3300000>;
> > > > > + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
> > > > > + off-on-delay = <20000>;
> > > > > + enable-active-high;
> > > > > + };
> > > > > + };
> > > > > +};
> > > > > +
> > > > > +&iomuxc {
> > > > > + pinctrl-names = "default";
> > > > > +
> > > > > + imx8mm-evk {
> > > > > + pinctrl_fec1: fec1grp {
> > > > > + fsl,pins = <
> > > > > +
> > > > > MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
> > > > > +
> > > > > MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
> > > > > +
> > > > > MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
> > > > > +
> > > > > MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
> > > > > +
> > > > > MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
> > > > > +
> > > > > MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
> > > > > +
> > > > > MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
> > > > > +
> > > > > MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
> > > > > +
> > > > > MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
> > > > > +
> > > > > MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
> > > > > +
> > > > > MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
> > > > > +
> > > > > MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
> > > > > +
> > > > > MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
> > > > > +
> > > > > MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
> > > > > +
> > > > > MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
> > > > > + >;
> > > > > + };
> > > > > +
> > > > > + pinctrl_gpio_led: gpioledgrp {
> > > > > + fsl,pins = <
> > > > > +
> > > > > MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
> > > > > + >;
> > > > > + };
> > > > > +
> > > > > + pinctrl_uart2: uart2grp {
> > > > > + fsl,pins = <
> > > > > +
> > > > > MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
> > > > > +
> > > > > MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
> > > > > + >;
> > > > > + };
> > > > > +
> > > > > + pinctrl_usdhc2_gpio: usdhc2grpgpio {
> > > > > + fsl,pins = <
> > > > > +
> > > > > MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
> > > > > +
> > > > > MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
> > > > > + >;
> > > > > + };
> > > > > +
> > > > > + pinctrl_usdhc2: usdhc2grp {
> > > > > + fsl,pins = <
> > > > > +
> > > > > MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
> > > > > +
> > > > > MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
> > > > > +
> > > > > MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
> > > > > +
> > > > > MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
> > > > > +
> > > > > MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
> > > > > +
> > > > > MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
> > > > > +
> > > > > MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
> > > > > + >;
> > > > > + };
> > > > > +
> > > > > + pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
> > > > > + fsl,pins = <
> > > > > +
> > > > > MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
> > > > > +
> > > > > MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
> > > > > +
> > > > > MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
> > > > > +
> > > > > MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
> > > > > +
> > > > > MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
> > > > > +
> > > > > MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
> > > > > +
> > > > > MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
> > > > > + >;
> > > > > + };
> > > > > +
> > > > > + pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
> > > > > + fsl,pins = <
> > > > > +
> > > > > MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
> > > > > +
> > > > > MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
> > > > > +
> > > > > MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
> > > > > +
> > > > > MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
> > > > > +
> > > > > MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
> > > > > +
> > > > > MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
> > > > > +
> > > > > MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
> > > > > + >;
> > > > > + };
> > > > > +
> > > > > + pinctrl_usdhc3: usdhc3grp {
> > > > > + fsl,pins = <
> > > > > +
> > > > > MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
> > > > > +
> > > > > MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
> > > > > +
> > > > > MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
> > > > > +
> > > > > MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
> > > > > +
> > > > > MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
> > > > > +
> > > > > MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
> > > > > +
> > > > > MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
> > > > > +
> > > > > MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
> > > > > +
> > > > > MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
> > > > > +
> > > > > MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
> > > > > +
> > > > > MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
> > > > > + >;
> > > > > + };
> > > > > +
> > > > > + pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
> > > > > + fsl,pins = <
> > > > > +
> > > > > MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
> > > > > +
> > > > > MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
> > > > > +
> > > > > MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
> > > > > +
> > > > > MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
> > > > > +
> > > > > MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
> > > > > +
> > > > > MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
> > > > > +
> > > > > MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
> > > > > +
> > > > > MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
> > > > > +
> > > > > MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
> > > > > +
> > > > > MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
> > > > > +
> > > > > MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
> > > > > + >;
> > > > > + };
> > > > > +
> > > > > + pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
> > > > > + fsl,pins = <
> > > > > +
> > > > > MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
> > > > > +
> > > > > MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
> > > > > +
> > > > > MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
> > > > > +
> > > > > MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
> > > > > +
> > > > > MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
> > > > > +
> > > > > MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
> > > > > +
> > > > > MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
> > > > > +
> > > > > MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
> > > > > +
> > > > > MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
> > > > > +
> > > > > MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
> > > > > +
> > > > > MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
> > > > > + >;
> > > > > + };
> > > > > +
> > > > > + pinctrl_wdog: wdoggrp {
> > > > > + fsl,pins = <
> > > > > +
> > > > > MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
> > > > > + >;
> > > > > + };
> > > > > + };
> > > > > +};
> > > > > +
> > > > > +&uart2 { /* console */
> > > > > + pinctrl-names = "default";
> > > > > + pinctrl-0 = <&pinctrl_uart2>;
> > > > > + status = "okay";
> > > > > +};
> > > > > +
> > > > > +&usdhc2 {
> > > > > + pinctrl-names = "default", "state_100mhz",
> > > > > "state_200mhz";
> > > > > + pinctrl-0 = <&pinctrl_usdhc2>,
> > > > > <&pinctrl_usdhc2_gpio>;
> > > > > + pinctrl-1 = <&pinctrl_usdhc2_100mhz>,
> > > > > <&pinctrl_usdhc2_gpio>;
> > > > > + pinctrl-2 = <&pinctrl_usdhc2_200mhz>,
> > > > > <&pinctrl_usdhc2_gpio>;
> > > > > + cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
> > > > > + bus-width = <4>;
> > > > > + vmmc-supply = <®_usdhc2_vmmc>;
> > > > > + status = "okay";
> > > > > +};
> > > > > +
> > > > > +&usdhc3 {
> > > > > + pinctrl-names = "default", "state_100mhz",
> > > > > "state_200mhz";
> > > > > + pinctrl-0 = <&pinctrl_usdhc3>;
> > > > > + pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
> > > > > + pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
> > > > > + bus-width = <8>;
> > > > > + non-removable;
> > > > > + status = "okay";
> > > > > +};
> > > > > +
> > > > > +&wdog1 {
> > > > > + pinctrl-names = "default";
> > > > > + pinctrl-0 = <&pinctrl_wdog>;
> > > > > + fsl,ext-reset-output;
> > > > > + status = "okay";
> > > > > +};
> > > > > diff --git a/arch/arm/dts/fsl-imx8mm.dtsi
> > > > > b/arch/arm/dts/fsl-imx8mm.dtsi new file mode 100644
> > > > > index 0000000000..8a808f856d
> > > > > --- /dev/null
> > > > > +++ b/arch/arm/dts/fsl-imx8mm.dtsi
> > > > > @@ -0,0 +1,586 @@
> > > > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > > > > +/*
> > > > > + * Copyright 2017-2019 NXP
> > > > > + */
> > > > > +
> > > > > +#include <dt-bindings/clock/imx8mm-clock.h>
> > > > > +#include <dt-bindings/gpio/gpio.h>
> > > > > +#include <dt-bindings/input/input.h>
> > > > > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > > > > +#include <dt-bindings/pinctrl/pins-imx8mm.h>
> > > > > +#include <dt-bindings/thermal/thermal.h>
> > > > > +
> > > > > +/ {
> > > > > + compatible = "fsl,imx8mm";
> > > > > + interrupt-parent = <&gic>;
> > > > > + #address-cells = <2>;
> > > > > + #size-cells = <2>;
> > > > > +
> > > > > + aliases {
> > > > > + i2c0 = &i2c1;
> > > > > + i2c1 = &i2c2;
> > > > > + i2c2 = &i2c3;
> > > > > + i2c3 = &i2c4;
> > > > > + serial0 = &uart1;
> > > > > + serial1 = &uart2;
> > > > > + serial2 = &uart3;
> > > > > + serial3 = &uart4;
> > > > > + spi0 = &ecspi1;
> > > > > + spi1 = &ecspi2;
> > > > > + spi2 = &ecspi3;
> > > > > + mmc0 = &usdhc1;
> > > > > + mmc1 = &usdhc2;
> > > > > + mmc2 = &usdhc3;
> > > > > + gpio0 = &gpio1;
> > > > > + gpio1 = &gpio2;
> > > > > + gpio2 = &gpio3;
> > > > > + gpio3 = &gpio4;
> > > > > + gpio4 = &gpio5;
> > > > > + };
> > > > > +
> > > > > + cpus {
> > > > > + #address-cells = <1>;
> > > > > + #size-cells = <0>;
> > > > > +
> > > > > + A53_0: cpu at 0 {
> > > > > + device_type = "cpu";
> > > > > + compatible = "arm,cortex-a53";
> > > > > + reg = <0x0>;
> > > > > + enable-method = "psci";
> > > > > + next-level-cache = <&A53_L2>;
> > > > > + };
> > > > > +
> > > > > + A53_1: cpu at 1 {
> > > > > + device_type = "cpu";
> > > > > + compatible = "arm,cortex-a53";
> > > > > + reg = <0x1>;
> > > > > + enable-method = "psci";
> > > > > + next-level-cache = <&A53_L2>;
> > > > > + };
> > > > > +
> > > > > + A53_2: cpu at 2 {
> > > > > + device_type = "cpu";
> > > > > + compatible = "arm,cortex-a53";
> > > > > + reg = <0x2>;
> > > > > + enable-method = "psci";
> > > > > + next-level-cache = <&A53_L2>;
> > > > > + };
> > > > > +
> > > > > + A53_3: cpu at 3 {
> > > > > + device_type = "cpu";
> > > > > + compatible = "arm,cortex-a53";
> > > > > + reg = <0x3>;
> > > > > + enable-method = "psci";
> > > > > + next-level-cache = <&A53_L2>;
> > > > > + };
> > > > > +
> > > > > + A53_L2: l2-cache0 {
> > > > > + compatible = "cache";
> > > > > + };
> > > > > + };
> > > > > +
> > > > > + memory at 40000000 {
> > > > > + device_type = "memory";
> > > > > + reg = <0x0 0x40000000 0 0x80000000>;
> > > > > + };
> > > > > +
> > > > > + clocks {
> > > > > + #address-cells = <1>;
> > > > > + #size-cells = <0>;
> > > > > +
> > > > > + osc_32k: clock at 0 {
> > > > > + compatible = "fixed-clock";
> > > > > + reg = <0>;
> > > > > + #clock-cells = <0>;
> > > > > + clock-frequency = <32768>;
> > > > > + clock-output-names = "osc_32k";
> > > > > + };
> > > > > +
> > > > > + osc_24m: clock at 1 {
> > > > > + compatible = "fixed-clock";
> > > > > + reg = <1>;
> > > > > + #clock-cells = <0>;
> > > > > + clock-frequency = <24000000>;
> > > > > + clock-output-names = "osc_24m";
> > > > > + };
> > > > > +
> > > > > + clk_ext1: clock at 2 {
> > > > > + compatible = "fixed-clock";
> > > > > + reg = <3>;
> > > > > + #clock-cells = <0>;
> > > > > + clock-frequency = <133000000>;
> > > > > + clock-output-names = "clk_ext1";
> > > > > + };
> > > > > +
> > > > > + clk_ext2: clock at 3 {
> > > > > + compatible = "fixed-clock";
> > > > > + reg = <4>;
> > > > > + #clock-cells = <0>;
> > > > > + clock-frequency = <133000000>;
> > > > > + clock-output-names = "clk_ext2";
> > > > > + };
> > > > > +
> > > > > + clk_ext3: clock at 4 {
> > > > > + compatible = "fixed-clock";
> > > > > + reg = <5>;
> > > > > + #clock-cells = <0>;
> > > > > + clock-frequency = <133000000>;
> > > > > + clock-output-names = "clk_ext3";
> > > > > + };
> > > > > +
> > > > > + clk_ext4: clock at 5 {
> > > > > + compatible = "fixed-clock";
> > > > > + reg = <6>;
> > > > > + #clock-cells = <0>;
> > > > > + clock-frequency= <133000000>;
> > > > > + clock-output-names = "clk_ext4";
> > > > > + };
> > > > > + };
> > > > > +
> > > > > + gic: interrupt-controller at 38800000 {
> > > > > + compatible = "arm,gic-v3";
> > > > > + reg = <0x0 0x38800000 0 0x10000>, /* GIC
> > > > > Dist */
> > > > > + <0x0 0x38880000 0 0xC0000>; /* GICR
> > > > > (RD_base + SGI_base) */
> > > > > + #interrupt-cells = <3>;
> > > > > + interrupt-controller;
> > > > > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> > > > > + };
> > > > > +
> > > > > + psci {
> > > > > + compatible = "arm,psci-1.0";
> > > > > + method = "smc";
> > > > > + };
> > > > > +
> > > > > + pmu {
> > > > > + compatible = "arm,armv8-pmuv3";
> > > > > + interrupts = <GIC_PPI 7
> > > > > + (GIC_CPU_MASK_SIMPLE(6) |
> > > > > IRQ_TYPE_LEVEL_HIGH)>;
> > > > > + interrupt-affinity = <&A53_0>, <&A53_1>,
> > > > > <&A53_2>, <&A53_3>;
> > > > > + };
> > > > > +
> > > > > + timer {
> > > > > + compatible = "arm,armv8-timer";
> > > > > + interrupts = <GIC_PPI 13
> > > > > (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical
> > > > > Secure */
> > > > > + <GIC_PPI 14
> > > > > (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical
> > > > > Non-Secure */
> > > > > + <GIC_PPI 11
> > > > > (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
> > > > > + <GIC_PPI 10
> > > > > (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor
> > > > > */
> > > > > + clock-frequency = <8000000>;
> > > > > + arm,no-tick-in-suspend;
> > > > > + };
> > > > > +
> > > > > + soc at 0 {
> > > > > + compatible = "simple-bus";
> > > > > + #address-cells = <2>;
> > > > > + #size-cells = <2>;
> > > > > + ranges;
> > > > > +
> > > > > + aips1: bus at 30000000 {
> > > > > + compatible = "fsl,aips-bus",
> > > > > "simple-bus";
> > > > > + #address-cells = <2>;
> > > > > + #size-cells = <2>;
> > > > > + reg = <0x0 0x30000000 0x0 0x400000>;
> > > > > + ranges;
> > > > > +
> > > > > + gpio1: gpio at 30200000 {
> > > > > + compatible =
> > > > > "fsl,imx8mm-gpio", "fsl,imx35-gpio";
> > > > > + reg = <0x0 0x30200000 0x0
> > > > > 0x10000>;
> > > > > + interrupts = <GIC_SPI 64
> > > > > IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 65
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > + gpio-controller;
> > > > > + #gpio-cells = <2>;
> > > > > + interrupt-controller;
> > > > > + #interrupt-cells = <2>;
> > > > > + };
> > > > > +
> > > > > + gpio2: gpio at 30210000 {
> > > > > + compatible =
> > > > > "fsl,imx8mm-gpio", "fsl,imx35-gpio";
> > > > > + reg = <0x0 0x30210000 0x0
> > > > > 0x10000>;
> > > > > + interrupts = <GIC_SPI 66
> > > > > IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 67
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > + gpio-controller;
> > > > > + #gpio-cells = <2>;
> > > > > + interrupt-controller;
> > > > > + #interrupt-cells = <2>;
> > > > > + };
> > > > > +
> > > > > + gpio3: gpio at 30220000 {
> > > > > + compatible =
> > > > > "fsl,imx8mm-gpio", "fsl,imx35-gpio";
> > > > > + reg = <0x0 0x30220000 0x0
> > > > > 0x10000>;
> > > > > + interrupts = <GIC_SPI 68
> > > > > IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 69
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > + gpio-controller;
> > > > > + #gpio-cells = <2>;
> > > > > + interrupt-controller;
> > > > > + #interrupt-cells = <2>;
> > > > > + };
> > > > > +
> > > > > + gpio4: gpio at 30230000 {
> > > > > + compatible =
> > > > > "fsl,imx8mm-gpio", "fsl,imx35-gpio";
> > > > > + reg = <0x0 0x30230000 0x0
> > > > > 0x10000>;
> > > > > + interrupts = <GIC_SPI 70
> > > > > IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 71
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > + gpio-controller;
> > > > > + #gpio-cells = <2>;
> > > > > + interrupt-controller;
> > > > > + #interrupt-cells = <2>;
> > > > > + };
> > > > > +
> > > > > + gpio5: gpio at 30240000 {
> > > > > + compatible =
> > > > > "fsl,imx8mm-gpio", "fsl,imx35-gpio";
> > > > > + reg = <0x0 0x30240000 0x0
> > > > > 0x10000>;
> > > > > + interrupts = <GIC_SPI 72
> > > > > IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 73
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > + gpio-controller;
> > > > > + #gpio-cells = <2>;
> > > > > + interrupt-controller;
> > > > > + #interrupt-cells = <2>;
> > > > > + };
> > > > > +
> > > > > + wdog1: wdog at 30280000 {
> > > > > + compatible = "fsl,imx21-wdt";
> > > > > + reg = <0 0x30280000 0
> > > > > 0x10000>;
> > > > > + interrupts = <GIC_SPI 78
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > + clocks = <&clk
> > > > > IMX8MM_CLK_WDOG1_ROOT>;
> > > > > + status = "disabled";
> > > > > + };
> > > > > +
> > > > > + wdog2: wdog at 30290000 {
> > > > > + compatible = "fsl,imx21-wdt";
> > > > > + reg = <0 0x30290000 0
> > > > > 0x10000>;
> > > > > + interrupts = <GIC_SPI 79
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > + clocks = <&clk
> > > > > IMX8MM_CLK_WDOG2_ROOT>;
> > > > > + status = "disabled";
> > > > > + };
> > > > > +
> > > > > + wdog3: wdog at 302a0000 {
> > > > > + compatible = "fsl,imx21-wdt";
> > > > > + reg = <0 0x302a0000 0
> > > > > 0x10000>;
> > > > > + interrupts = <GIC_SPI 10
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > + clocks = <&clk
> > > > > IMX8MM_CLK_WDOG3_ROOT>;
> > > > > + status = "disabled";
> > > > > + };
> > > > > +
> > > > > + sdma2: dma-controller at 302c0000 {
> > > > > + compatible =
> > > > > "fsl,imx8mq-sdma", "fsl,imx7d-sdma";
> > > > > + reg = <0x0 0x302c0000 0x0
> > > > > 0x10000>;
> > > > > + interrupts = <GIC_SPI 103
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > + clocks = <&clk
> > > > > IMX8MM_CLK_SDMA2_ROOT>,
> > > > > + <&clk
> > > > > IMX8MM_CLK_SDMA2_ROOT>;
> > > > > + clock-names = "ipg", "ahb";
> > > > > + #dma-cells = <3>;
> > > > > + fsl,sdma-ram-script-name =
> > > > > "imx/sdma/sdma-imx7d.bin";
> > > > > + fsl,ratio-1-1;
> > > > > + status = "okay";
> > > > > + };
> > > > > +
> > > > > + sdma3: dma-controller at 302b0000 {
> > > > > + compatible =
> > > > > "fsl,imx8mq-sdma", "fsl,imx7d-sdma";
> > > > > + reg = <0x0 0x302b0000 0x0
> > > > > 0x10000>;
> > > > > + interrupts = <GIC_SPI 34
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > + clocks = <&clk
> > > > > IMX8MM_CLK_SDMA3_ROOT>,
> > > > > + <&clk
> > > > > IMX8MM_CLK_SDMA3_ROOT>;
> > > > > + clock-names = "ipg", "ahb";
> > > > > + #dma-cells = <3>;
> > > > > + fsl,sdma-ram-script-name =
> > > > > "imx/sdma/sdma-imx7d.bin";
> > > > > + fsl,ratio-1-1;
> > > > > + status = "okay";
> > > > > + };
> > > > > +
> > > > > + iomuxc: pinctrl at 30330000 {
> > > > > + compatible =
> > > > > "fsl,imx8mm-iomuxc";
> > > > > + reg = <0x0 0x30330000 0x0
> > > > > 0x10000>;
> > > > > + };
> > > > > +
> > > > > + gpr: iomuxc-gpr at 30340000 {
> > > > > + compatible =
> > > > > "fsl,imx8mm-iomuxc-gpr", "syscon";
> > > > > + reg = <0x0 0x30340000 0x0
> > > > > 0x10000>;
> > > > > + };
> > > > > +
> > > > > + ocotp: ocotp-ctrl at 30350000 {
> > > > > + compatible =
> > > > > "fsl,imx8mq-ocotp", "fsl,imx7d-ocotp", "syscon";
> > > > > + reg = <0 0x30350000 0
> > > > > 0x10000>;
> > > > > + clocks = <&clk
> > > > > IMX8MM_CLK_OCOTP_ROOT>;
> > > > > + /* For nvmem subnodes */
> > > > > + #address-cells = <1>;
> > > > > + #size-cells = <1>;
> > > > > + };
> > > > > +
> > > > > + anatop: anatop at 30360000 {
> > > > > + compatible =
> > > > > "fsl,imx8mm-anatop", "syscon", "simple-bus";
> > > > > + reg = <0x0 0x30360000 0x0
> > > > > 0x10000>;
> > > > > + };
> > > > > +
> > > > > + snvs: snvs at 30370000 {
> > > > > + compatible =
> > > > > "fsl,sec-v4.0-mon","syscon", "simple-mfd";
> > > > > + reg = <0x0 0x30370000 0x0
> > > > > 0x10000>; +
> > > > > + snvs_rtc: snvs-rtc-lp{
> > > > > + compatible =
> > > > > "fsl,sec-v4.0-mon-rtc-lp";
> > > > > + regmap =<&snvs>;
> > > > > + offset = <0x34>;
> > > > > + interrupts = <GIC_SPI
> > > > > 19 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI
> > > > > 20 IRQ_TYPE_LEVEL_HIGH>;
> > > > > + };
> > > > > +
> > > > > + snvs_pwrkey: snvs-powerkey {
> > > > > + compatible =
> > > > > "fsl,sec-v4.0-pwrkey";
> > > > > + regmap = <&snvs>;
> > > > > + interrupts =
> > > > > <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
> > > > > + linux,keycode =
> > > > > <KEY_POWER>;
> > > > > + wakeup-source;
> > > > > + };
> > > > > + };
> > > > > +
> > > > > + clk: clock-controller at 30380000 {
> > > > > + compatible =
> > > > > "fsl,imx8mm-ccm";
> > > > > + reg = <0x0 0x30380000 0x0
> > > > > 0x10000>;
> > > > > + #clock-cells = <1>;
> > > > > + clocks = <&osc_32k>,
> > > > > <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
> > > > > + <&clk_ext3>,
> > > > > <&clk_ext4>;
> > > > > + clock-names = "osc_32k",
> > > > > "osc_24m", "clk_ext1", "clk_ext2",
> > > > > + "clk_ext3",
> > > > > "clk_ext4";
> > > > > + };
> > > > > +
> > > > > + src: src at 30390000 {
> > > > > + compatible =
> > > > > "fsl,imx8mm-src", "syscon";
> > > > > + reg = <0x0 0x30390000 0x0
> > > > > 0x10000>;
> > > > > + interrupts = <GIC_SPI 89
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > + #reset-cells = <1>;
> > > > > + };
> > > > > +
> > > > > + gpc: gpc at 303a0000 {
> > > > > + compatible =
> > > > > "fsl,imx8mm-gpc", "syscon";
> > > > > + reg = <0x0 0x303a0000 0x0
> > > > > 0x10000>;
> > > > > + interrupt-controller;
> > > > > + interrupts = <GIC_SPI 87
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > + #interrupt-cells = <3>;
> > > > > + };
> > > > > + };
> > > > > +
> > > > > + aips2: bus at 30400000 {
> > > > > + compatible = "fsl,aips-bus",
> > > > > "simple-bus";
> > > > > + #address-cells = <2>;
> > > > > + #size-cells = <2>;
> > > > > + reg = <0x0 0x30400000 0x0 0x400000>;
> > > > > + ranges;
> > > > > +
> > > > > + pwm1: pwm at 30660000 {
> > > > > + compatible =
> > > > > "fsl,imx8mm-pwm", "fsl,imx27-pwm";
> > > > > + reg = <0x0 0x30660000 0x0
> > > > > 0x10000>;
> > > > > + interrupts = <GIC_SPI 81
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > + clocks = <&clk
> > > > > IMX8MM_CLK_PWM1_ROOT>,
> > > > > + <&clk
> > > > > IMX8MM_CLK_PWM1_ROOT>;
> > > > > + clock-names = "ipg", "per";
> > > > > + #pwm-cells = <2>;
> > > > > + status = "disabled";
> > > > > + };
> > > > > +
> > > > > + pwm2: pwm at 30670000 {
> > > > > + compatible =
> > > > > "fsl,imx8mm-pwm", "fsl,imx27-pwm";
> > > > > + reg = <0x0 0x30670000 0x0
> > > > > 0x10000>;
> > > > > + interrupts = <GIC_SPI 82
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > + clocks = <&clk
> > > > > IMX8MM_CLK_PWM2_ROOT>,
> > > > > + <&clk
> > > > > IMX8MM_CLK_PWM2_ROOT>;
> > > > > + clock-names = "ipg", "per";
> > > > > + #pwm-cells = <2>;
> > > > > + status = "disabled";
> > > > > + };
> > > > > +
> > > > > + pwm3: pwm at 30680000 {
> > > > > + compatible =
> > > > > "fsl,imx8mm-pwm", "fsl,imx27-pwm";
> > > > > + reg = <0x0 0x30680000 0x0
> > > > > 0x10000>;
> > > > > + interrupts = <GIC_SPI 83
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > + clocks = <&clk
> > > > > IMX8MM_CLK_PWM3_ROOT>,
> > > > > + <&clk
> > > > > IMX8MM_CLK_PWM3_ROOT>;
> > > > > + clock-names = "ipg", "per";
> > > > > + #pwm-cells = <2>;
> > > > > + status = "disabled";
> > > > > + };
> > > > > +
> > > > > + pwm4: pwm at 30690000 {
> > > > > + compatible =
> > > > > "fsl,imx8mm-pwm", "fsl,imx27-pwm";
> > > > > + reg = <0x0 0x30690000 0x0
> > > > > 0x10000>;
> > > > > + interrupts = <GIC_SPI 84
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > + clocks = <&clk
> > > > > IMX8MM_CLK_PWM4_ROOT>,
> > > > > + <&clk
> > > > > IMX8MM_CLK_PWM4_ROOT>;
> > > > > + clock-names = "ipg", "per";
> > > > > + #pwm-cells = <2>;
> > > > > + status = "disabled";
> > > > > + };
> > > > > + };
> > > > > +
> > > > > + aips3: bus at 30800000 {
> > > > > + compatible = "fsl,aips-bus",
> > > > > "simple-bus";
> > > > > + #address-cells = <2>;
> > > > > + #size-cells = <2>;
> > > > > + reg = <0x0 0x30800000 0x0 0x400000>;
> > > > > + ranges;
> > > > > +
> > > > > + ecspi1: ecspi at 30820000 {
> > > > > + #address-cells = <1>;
> > > > > + #size-cells = <0>;
> > > > > + compatible =
> > > > > "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
> > > > > + reg = <0x0 0x30820000 0x0
> > > > > 0x10000>;
> > > > > + interrupts = <GIC_SPI 31
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > + clocks = <&clk
> > > > > IMX8MM_CLK_ECSPI1_ROOT>,
> > > > > + <&clk
> > > > > IMX8MM_CLK_ECSPI1_ROOT>;
> > > > > + clock-names = "ipg", "per";
> > > > > + status = "disabled";
> > > > > + };
> > > > > +
> > > > > + ecspi2: ecspi at 30830000 {
> > > > > + #address-cells = <1>;
> > > > > + #size-cells = <0>;
> > > > > + compatible =
> > > > > "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
> > > > > + reg = <0x0 0x30830000 0x0
> > > > > 0x10000>;
> > > > > + interrupts = <GIC_SPI 32
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > + clocks = <&clk
> > > > > IMX8MM_CLK_ECSPI2_ROOT>,
> > > > > + <&clk
> > > > > IMX8MM_CLK_ECSPI2_ROOT>;
> > > > > + clock-names = "ipg", "per";
> > > > > + status = "disabled";
> > > > > + };
> > > > > +
> > > > > + ecspi3: ecspi at 30840000 {
> > > > > + #address-cells = <1>;
> > > > > + #size-cells = <0>;
> > > > > + compatible =
> > > > > "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
> > > > > + reg = <0x0 0x30840000 0x0
> > > > > 0x10000>;
> > > > > + interrupts = <GIC_SPI 33
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > + clocks = <&clk
> > > > > IMX8MM_CLK_ECSPI3_ROOT>,
> > > > > + <&clk
> > > > > IMX8MM_CLK_ECSPI3_ROOT>;
> > > > > + clock-names = "ipg", "per";
> > > > > + status = "disabled";
> > > > > + };
> > > > > +
> > > > > + uart1: serial at 30860000 {
> > > > > + compatible =
> > > > > "fsl,imx8mm-uart",
> > > > > +
> > > > > "fsl,imx6q-uart", "fsl,imx21-uart";
> > > > > + reg = <0x0 0x30860000 0x0
> > > > > 0x10000>;
> > > > > + interrupts = <GIC_SPI 26
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > + clocks = <&clk
> > > > > IMX8MM_CLK_UART1_ROOT>,
> > > > > + <&clk
> > > > > IMX8MM_CLK_UART1_ROOT>;
> > > > > + clock-names = "ipg", "per";
> > > > > + status = "disabled";
> > > > > + };
> > > > > +
> > > > > + uart3: serial at 30880000 {
> > > > > + compatible =
> > > > > "fsl,imx8mm-uart",
> > > > > +
> > > > > "fsl,imx6q-uart", "fsl,imx21-uart";
> > > > > + reg = <0x0 0x30880000 0x0
> > > > > 0x10000>;
> > > > > + interrupts = <GIC_SPI 28
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > + clocks = <&clk
> > > > > IMX8MM_CLK_UART3_ROOT>,
> > > > > + <&clk
> > > > > IMX8MM_CLK_UART3_ROOT>;
> > > > > + clock-names = "ipg", "per";
> > > > > + status = "disabled";
> > > > > + };
> > > > > +
> > > > > + uart2: serial at 30890000 {
> > > > > + compatible =
> > > > > "fsl,imx8mm-uart",
> > > > > +
> > > > > "fsl,imx6q-uart", "fsl,imx21-uart";
> > > > > + reg = <0x0 0x30890000 0x0
> > > > > 0x10000>;
> > > > > + interrupts = <GIC_SPI 27
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > + clocks = <&clk
> > > > > IMX8MM_CLK_UART2_ROOT>,
> > > > > + <&clk
> > > > > IMX8MM_CLK_UART2_ROOT>;
> > > > > + clock-names = "ipg", "per";
> > > > > + status = "disabled";
> > > > > + };
> > > > > +
> > > > > + i2c1: i2c at 30a20000 {
> > > > > + #address-cells = <1>;
> > > > > + #size-cells = <0>;
> > > > > + compatible =
> > > > > "fsl,imx8mm-i2c", "fsl,imx21-i2c";
> > > > > + reg = <0x0 0x30a20000 0x0
> > > > > 0x10000>;
> > > > > + interrupts = <GIC_SPI 35
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > + clocks = <&clk
> > > > > IMX8MM_CLK_I2C1_ROOT>;
> > > > > + status = "disabled";
> > > > > + };
> > > > > +
> > > > > + i2c2: i2c at 30a30000 {
> > > > > + #address-cells = <1>;
> > > > > + #size-cells = <0>;
> > > > > + compatible =
> > > > > "fsl,imx8mm-i2c", "fsl,imx21-i2c";
> > > > > + reg = <0x0 0x30a30000 0x0
> > > > > 0x10000>;
> > > > > + interrupts = <GIC_SPI 36
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > + clocks = <&clk
> > > > > IMX8MM_CLK_I2C2_ROOT>;
> > > > > + status = "disabled";
> > > > > + };
> > > > > +
> > > > > + i2c3: i2c at 30a40000 {
> > > > > + #address-cells = <1>;
> > > > > + #size-cells = <0>;
> > > > > + compatible =
> > > > > "fsl,imx8mm-i2c", "fsl,imx21-i2c";
> > > > > + reg = <0x0 0x30a40000 0x0
> > > > > 0x10000>;
> > > > > + interrupts = <GIC_SPI 37
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > + clocks = <&clk
> > > > > IMX8MM_CLK_I2C3_ROOT>;
> > > > > + status = "disabled";
> > > > > + };
> > > > > +
> > > > > + i2c4: i2c at 30a50000 {
> > > > > + #address-cells = <1>;
> > > > > + #size-cells = <0>;
> > > > > + compatible =
> > > > > "fsl,imx8mm-i2c", "fsl,imx21-i2c";
> > > > > + reg = <0x0 0x30a50000 0x0
> > > > > 0x10000>;
> > > > > + interrupts = <GIC_SPI 38
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > + clocks = <&clk
> > > > > IMX8MM_CLK_I2C4_ROOT>;
> > > > > + status = "disabled";
> > > > > + };
> > > > > +
> > > > > + uart4: serial at 30a60000 {
> > > > > + compatible =
> > > > > "fsl,imx8mq-uart",
> > > > > +
> > > > > "fsl,imx6q-uart", "fsl,imx21-uart";
> > > > > + reg = <0x0 0x30a60000 0x0
> > > > > 0x10000>;
> > > > > + interrupts = <GIC_SPI 29
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > + clocks = <&clk
> > > > > IMX8MM_CLK_UART4_ROOT>,
> > > > > + <&clk
> > > > > IMX8MM_CLK_UART4_ROOT>;
> > > > > + clock-names = "ipg", "per";
> > > > > + status = "disabled";
> > > > > + };
> > > > > +
> > > > > + usdhc1: mmc at 30b40000 {
> > > > > + compatible =
> > > > > "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc";
> > > > > + reg = <0x0 0x30b40000 0x0
> > > > > 0x10000>;
> > > > > + interrupts = <GIC_SPI 22
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > + clocks = <&clk
> > > > > IMX8MM_CLK_DUMMY>,
> > > > > + <&clk
> > > > > IMX8MM_CLK_NAND_USDHC_BUS>,
> > > > > + <&clk
> > > > > IMX8MM_CLK_USDHC1_ROOT>;
> > > > > + clock-names = "ipg", "ahb",
> > > > > "per";
> > > > > + assigned-clocks = <&clk
> > > > > IMX8MM_CLK_USDHC1>;
> > > > > + assigned-clock-rates =
> > > > > <400000000>;
> > > > > + fsl,tuning-start-tap = <20>;
> > > > > + fsl,tuning-step= <2>;
> > > > > + bus-width = <4>;
> > > > > + status = "disabled";
> > > > > + };
> > > > > +
> > > > > + usdhc2: mmc at 30b50000 {
> > > > > + compatible =
> > > > > "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc";
> > > > > + reg = <0x0 0x30b50000 0x0
> > > > > 0x10000>;
> > > > > + interrupts = <GIC_SPI 23
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > + clocks = <&clk
> > > > > IMX8MM_CLK_DUMMY>,
> > > > > + <&clk
> > > > > IMX8MM_CLK_NAND_USDHC_BUS>,
> > > > > + <&clk
> > > > > IMX8MM_CLK_USDHC2_ROOT>;
> > > > > + clock-names = "ipg", "ahb",
> > > > > "per";
> > > > > + fsl,tuning-start-tap = <20>;
> > > > > + fsl,tuning-step= <2>;
> > > > > + bus-width = <4>;
> > > > > + status = "disabled";
> > > > > + };
> > > > > +
> > > > > + usdhc3: mmc at 30b60000 {
> > > > > + compatible =
> > > > > "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc";
> > > > > + reg = <0x0 0x30b60000 0x0
> > > > > 0x10000>;
> > > > > + interrupts = <GIC_SPI 24
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > + clocks = <&clk
> > > > > IMX8MM_CLK_DUMMY>,
> > > > > + <&clk
> > > > > IMX8MM_CLK_NAND_USDHC_BUS>,
> > > > > + <&clk
> > > > > IMX8MM_CLK_USDHC3_ROOT>;
> > > > > + clock-names = "ipg", "ahb",
> > > > > "per";
> > > > > + assigned-clocks = <&clk
> > > > > IMX8MM_CLK_USDHC3_ROOT>;
> > > > > + assigned-clock-rates =
> > > > > <400000000>;
> > > > > + fsl,tuning-start-tap = <20>;
> > > > > + fsl,tuning-step= <2>;
> > > > > + bus-width = <4>;
> > > > > + status = "disabled";
> > > > > + };
> > > > > + };
> > > > > + };
> > > > > +};
> > > > > diff --git a/arch/arm/mach-imx/imx8m/Kconfig
> > > > > b/arch/arm/mach-imx/imx8m/Kconfig index
> > > > > 35c978e863..f520075875
> > > > 100644
> > > > > --- a/arch/arm/mach-imx/imx8m/Kconfig
> > > > > +++ b/arch/arm/mach-imx/imx8m/Kconfig
> > > > > @@ -24,8 +24,15 @@ config TARGET_IMX8MQ_EVK
> > > > > select IMX8MQ
> > > > > select IMX8M_LPDDR4
> > > > >
> > > > > +config TARGET_IMX8MM_EVK
> > > > > + bool "imx8mm LPDDR4 EVK board"
> > > > > + select IMX8MM
> > > > > + select SUPPORT_SPL
> > > > > + select IMX8M_LPDDR4
> > > >
> > > > Here you shall put the select DM_{UART,USDHC, etc}
> > > >
> > > > > +
> > > > > endchoice
> > > > >
> > > > > source "board/freescale/imx8mq_evk/Kconfig"
> > > > > +source "board/freescale/imx8mm_evk/Kconfig"
> > > > >
> > > > > endif
> > > > > diff --git a/board/freescale/imx8mm_evk/Kconfig
> > > > > b/board/freescale/imx8mm_evk/Kconfig new file mode 100644
> > > > > index 0000000000..299691a619
> > > > > --- /dev/null
> > > > > +++ b/board/freescale/imx8mm_evk/Kconfig
> > > > > @@ -0,0 +1,12 @@
> > > > > +if TARGET_IMX8MM_EVK
> > > > > +
> > > > > +config SYS_BOARD
> > > > > + default "imx8mm_evk"
> > > > > +
> > > > > +config SYS_VENDOR
> > > > > + default "freescale"
> > > > > +
> > > > > +config SYS_CONFIG_NAME
> > > > > + default "imx8mm_evk"
> > > > > +
> > > > > +endif
> > > > > diff --git a/board/freescale/imx8mm_evk/MAINTAINERS
> > > > > b/board/freescale/imx8mm_evk/MAINTAINERS new file mode 100644
> > > > > index 0000000000..b031bb0674
> > > > > --- /dev/null
> > > > > +++ b/board/freescale/imx8mm_evk/MAINTAINERS
> > > > > @@ -0,0 +1,6 @@
> > > > > +i.MX8MM EVK BOARD
> > > > > +M: Peng Fan <peng.fan@nxp.com>
> > > > > +S: Maintained
> > > > > +F: board/freescale/imx8mm_evk/
> > > > > +F: include/configs/imx8mm_evk.h
> > > > > +F: configs/imx8mm_evk_defconfig
> > > > > diff --git a/board/freescale/imx8mm_evk/Makefile
> > > > > b/board/freescale/imx8mm_evk/Makefile new file mode 100644
> > > > > index 0000000000..1db7b62caf
> > > > > --- /dev/null
> > > > > +++ b/board/freescale/imx8mm_evk/Makefile
> > > > > @@ -0,0 +1,12 @@
> > > > > +#
> > > > > +# Copyright 2018 NXP
> > > > > +#
> > > > > +# SPDX-License-Identifier: GPL-2.0+
> > > > > +#
> > > > > +
> > > > > +obj-y += imx8mm_evk.o
> > > > > +
> > > > > +ifdef CONFIG_SPL_BUILD
> > > > > +obj-y += spl.o
> > > > > +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
> > > > > +endif
> > > > > diff --git a/board/freescale/imx8mm_evk/imx8mm_evk.c
> > > > > b/board/freescale/imx8mm_evk/imx8mm_evk.c new file mode 100644
> > > > > index 0000000000..a681aca04d
> > > > > --- /dev/null
> > > > > +++ b/board/freescale/imx8mm_evk/imx8mm_evk.c
> > > > > @@ -0,0 +1,144 @@
> > > > > +// SPDX-License-Identifier: GPL-2.0+
> > > > > +/*
> > > > > + * Copyright 2018 NXP
> > > > > + */
> > > > > +
> > > > > +#include <common.h>
> > > > > +#include <malloc.h>
> > > > > +#include <errno.h>
> > > > > +#include <asm/io.h>
> > > > > +#include <miiphy.h>
> > > > > +#include <netdev.h>
> > > > > +#include <asm/mach-imx/iomux-v3.h>
> > > > > +#include <asm-generic/gpio.h>
> > > > > +#include <fsl_esdhc.h>
> > > > > +#include <mmc.h>
> > > > > +#include <asm/arch/imx8mm_pins.h>
> > > > > +#include <asm/arch/sys_proto.h>
> > > > > +#include <asm/mach-imx/gpio.h>
> > > > > +#include <asm/mach-imx/mxc_i2c.h>
> > > > > +#include <asm/arch/clock.h>
> > > > > +#include <spl.h>
> > > > > +#include <asm/mach-imx/dma.h>
> > > > > +
> > > > > +DECLARE_GLOBAL_DATA_PTR;
> > > > > +
> > > > > +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
> > > > > +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE |
> > > > > PAD_CTL_PUE | PAD_CTL_PE) +
> > > > > +static iomux_v3_cfg_t const uart_pads[] = {
> > > > > + IMX8MM_PAD_UART2_RXD_UART2_RX |
> > > > MUX_PAD_CTRL(UART_PAD_CTRL),
> > > > > + IMX8MM_PAD_UART2_TXD_UART2_TX |
> > > > MUX_PAD_CTRL(UART_PAD_CTRL),
> > > > > +};
> > > > > +
> > > > > +static iomux_v3_cfg_t const wdog_pads[] = {
> > > > > + IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B |
> > > > > MUX_PAD_CTRL(WDOG_PAD_CTRL), +};
> > > > > +
> > > > > +int board_early_init_f(void)
> > > > > +{
> > > > > + struct wdog_regs *wdog = (struct wdog_regs
> > > > > *)WDOG1_BASE_ADDR; +
> > > > > + imx_iomux_v3_setup_multiple_pads(wdog_pads,
> > > > > ARRAY_SIZE(wdog_pads)); +
> > > > > + set_wdog_reset(wdog);
> > > > > +
> > > > > + imx_iomux_v3_setup_multiple_pads(uart_pads,
> > > > > ARRAY_SIZE(uart_pads)); +
> > > > > + return 0;
> > > > > +}
> > > > > +
> > > > > +#ifdef CONFIG_BOARD_POSTCLK_INIT
> > > > > +int board_postclk_init(void)
> > > > > +{
> > > > > + /* TODO */
> > > > > + return 0;
> > > > > +}
> > > > > +#endif
> > > > > +
> > > > > +int dram_init(void)
> > > > > +{
> > > > > + /* rom_pointer[1] contains the size of TEE occupies
> > > > > */
> > > > > + if (rom_pointer[1])
> > > > > + gd->ram_size = PHYS_SDRAM_SIZE -
> > > > > rom_pointer[1];
> > > > > + else
> > > > > + gd->ram_size = PHYS_SDRAM_SIZE;
> > > > > +
> > > > > + return 0;
> > > > > +}
> > > > > +
> > > > > +#ifdef CONFIG_OF_BOARD_SETUP
> > > > > +int ft_board_setup(void *blob, bd_t *bd)
> > > > ^^^ - fdt_board_setup ?
> > > > > +{
> > > > > + return 0;
> > > > > +}
> > > > > +#endif
> > > > > +
> > > > > +#ifdef CONFIG_FEC_MXC
> > > > > +#define FEC_RST_PAD IMX_GPIO_NR(4, 22)
> > > > > +static iomux_v3_cfg_t const fec1_rst_pads[] = {
> > > > > + IMX8MM_PAD_SAI2_RXC_GPIO4_IO22 |
> > > > MUX_PAD_CTRL(NO_PAD_CTRL),
> > > >
> > > > This shall be done with fsl_fec.c DM driver - there is support
> > > > for adding reset pin (to dts).
> > > >
> > > > > +};
> > > > > +
> > > > > +static void setup_iomux_fec(void)
> > > > > +{
> > > > > + imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
> > > > > +
> > > > > ARRAY_SIZE(fec1_rst_pads)); +
> > > > > + gpio_request(FEC_RST_PAD, "fec1_rst");
> > > > > + gpio_direction_output(FEC_RST_PAD, 0);
> > > > > + udelay(500);
> > > > > + gpio_direction_output(FEC_RST_PAD, 1);
> > > > > +}
> > > >
> > > > This shall be replaced with DM/DTS of the fsl_fec.c driver.
> > > > Please also note that there are (at least on imx6q) some timing
> > > > issues when we move the code to DM/DTS (some delay is needed).
> > > >
> > > > > +
> > > > > +static int setup_fec(void)
> > > > > +{
> > > > > + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
> > > > > + = (struct iomuxc_gpr_base_regs
> > > > > *)IOMUXC_GPR_BASE_ADDR; +
> > > > > + setup_iomux_fec();
> > > > > +
> > > > > + /* Use 125M anatop REF_CLK1 for ENET1, not from
> > > > > external */
> > > > > + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
> > > > > +
> > > > > IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT, 0);
> > > > > + return set_clk_enet(ENET_125MHZ);
> > > > > +}
> > > > > +
> > > > > +int board_phy_config(struct phy_device *phydev)
> > > > > +{
> > > > > + /* enable rgmii rxc skew and phy mode select to RGMII
> > > > > copper */
> > > > > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
> > > > > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
> > > > > +
> > > > > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
> > > > > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
> > > > > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
> > > > > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
> > > > > +
> > > > > + if (phydev->drv->config)
> > > > > + phydev->drv->config(phydev);
> > > > > + return 0;
> > > >
> > > > Which PHY do you use? E.g. KSZ... support passing those values
> > > > via DTS.
> > > > > +}
> > > > > +#endif
> > > > > +
> > > > > +int board_init(void)
> > > > > +{
> > > > > +#ifdef CONFIG_FEC_MXC
> > > > > + setup_fec();
> > > > > +#endif
> > > > > + return 0;
> > > > > +}
> > > > > +
> > > > > +int board_mmc_get_env_dev(int devno)
> > > > > +{
> > > > > + return devno - 1;
> > > > > +}
> > > > > +
> > > > > +int board_late_init(void)
> > > > > +{
> > > > > +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> > > > > + env_set("board_name", "EVK");
> > > > > + env_set("board_rev", "iMX8MM");
> > > > > +#endif
> > > > > + return 0;
> > > > > +}
> > > > > diff --git a/board/freescale/imx8mm_evk/lpddr4_timing.c
> > > > > b/board/freescale/imx8mm_evk/lpddr4_timing.c new file mode
> > > > > 100644 index 0000000000..4bade5bf74
> > > > > --- /dev/null
> > > > > +++ b/board/freescale/imx8mm_evk/lpddr4_timing.c
> > > > > @@ -0,0 +1,1980 @@
> > > > > +// SPDX-License-Identifier: GPL-2.0+
> > > > > +/*
> > > > > + * Copyright 2018 NXP
> > > >
> > > > Author is missing.
> > > >
> > > > > + */
> > > > > +
> > > > > +#include <linux/kernel.h>
> > > > > +#include <common.h>
> > > > > +#include <asm/arch/ddr.h>
> > > > > +#include <asm/arch/lpddr4_define.h>
> > > > > +
> > > > > +struct dram_cfg_param lpddr4_ddrc_cfg[] = {
> > > > > + /* Start to config, default 3200mbps */
> > > > > + { DDRC_DBG1(0), 0x00000001 },
> > > > > + { DDRC_PWRCTL(0), 0x00000001 },
> > > > > + { DDRC_MSTR(0), 0xa1080020 },
> > > > > + { DDRC_RFSHTMG(0), 0x005b00d2 },
> > > > > + { DDRC_INIT0(0), 0xC003061B },
> > > > > + { DDRC_INIT1(0), 0x009D0000 },
> > > > > + { DDRC_INIT3(0), 0x00D4002D },
> > > > > + { DDRC_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 },
> > > > > + { DDRC_INIT6(0), 0x0066004a },
> > > > > + { DDRC_INIT7(0), 0x0006004a },
> > > > > +
> > > > > + { DDRC_DRAMTMG0(0), 0x1A201B22 },
> > > > > + { DDRC_DRAMTMG1(0), 0x00060633 },
> > > > > + { DDRC_DRAMTMG3(0), 0x00C0C000 },
> > > > > + { DDRC_DRAMTMG4(0), 0x0F04080F },
> > > > > + { DDRC_DRAMTMG5(0), 0x02040C0C },
> > > > > + { DDRC_DRAMTMG6(0), 0x01010007 },
> > > > > + { DDRC_DRAMTMG7(0), 0x00000401 },
> > > > > + { DDRC_DRAMTMG12(0), 0x00020600 },
> > > > > + { DDRC_DRAMTMG13(0), 0x0C100002 },
> > > > > + { DDRC_DRAMTMG14(0), 0x000000E6 },
> > > > > + { DDRC_DRAMTMG17(0), 0x00A00050 },
> > > > > +
> > > > > + { DDRC_ZQCTL0(0), 0x03200018 },
> > > > > + { DDRC_ZQCTL1(0), 0x028061A8 },
> > > > > + { DDRC_ZQCTL2(0), 0x00000000 },
> > > > > +
> > > > > + { DDRC_DFITMG0(0), 0x0497820A },
> > > > > + { DDRC_DFITMG2(0), 0x0000170A },
> > > > > + { DDRC_DRAMTMG2(0), 0x070E171a },
> > > > > + { DDRC_DBICTL(0), 0x00000001 },
> > > > > +
> > > > > + { DDRC_DFITMG1(0), 0x00080303 },
> > > > > + { DDRC_DFIUPD0(0), 0xE0400018 },
> > > > > + { DDRC_DFIUPD1(0), 0x00DF00E4 },
> > > > > + { DDRC_DFIUPD2(0), 0x80000000 },
> > > > > + { DDRC_DFIMISC(0), 0x00000011 },
> > > > > +
> > > > > + { DDRC_DFIPHYMSTR(0), 0x00000000 },
> > > > > + { DDRC_RANKCTL(0), 0x00000c99 },
> > > > > +
> > > > > + /* address mapping */
> > > > > + { DDRC_ADDRMAP0(0), 0x0000001f },
> > > > > + { DDRC_ADDRMAP1(0), 0x00080808 },
> > > > > + { DDRC_ADDRMAP2(0), 0x00000000 },
> > > > > + { DDRC_ADDRMAP3(0), 0x00000000 },
> > > > > + { DDRC_ADDRMAP4(0), 0x00001f1f },
> > > > > + { DDRC_ADDRMAP5(0), 0x07070707 },
> > > > > + { DDRC_ADDRMAP6(0), 0x07070707 },
> > > > > + { DDRC_ADDRMAP7(0), 0x00000f0f },
> > > > > +
> > > > > + /* performance setting */
> > > > > + { DDRC_SCHED(0), 0x29001701 },
> > > > > + { DDRC_SCHED1(0), 0x0000002c },
> > > > > + { DDRC_PERFHPR1(0), 0x04000030 },
> > > > > + { DDRC_PERFLPR1(0), 0x900093e7 },
> > > > > + { DDRC_PERFWR1(0), 0x20005574 },
> > > > > + { DDRC_PCCFG(0), 0x00000111 },
> > > > > + { DDRC_PCFGW_0(0), 0x000072ff },
> > > > > + { DDRC_PCFGQOS0_0(0), 0x02100e07 },
> > > > > + { DDRC_PCFGQOS1_0(0), 0x00620096 },
> > > > > + { DDRC_PCFGWQOS0_0(0), 0x01100e07 },
> > > > > + { DDRC_PCFGWQOS1_0(0), 0x00c8012c },
> > > > > +
> > > > > + /* frequency P1&P2 */
> > > > > + /* Frequency 1: 400mbps */
> > > > > + { DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c },
> > > > > + { DDRC_FREQ1_DRAMTMG1(0), 0x00030410 },
> > > > > + { DDRC_FREQ1_DRAMTMG2(0), 0x0203090c },
> > > > > + { DDRC_FREQ1_DRAMTMG3(0), 0x00505006 },
> > > > > + { DDRC_FREQ1_DRAMTMG4(0), 0x05040305 },
> > > > > + { DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504 },
> > > > > + { DDRC_FREQ1_DRAMTMG6(0), 0x0a060004 },
> > > > > + { DDRC_FREQ1_DRAMTMG7(0), 0x0000090e },
> > > > > + { DDRC_FREQ1_DRAMTMG14(0), 0x00000032 },
> > > > > + { DDRC_FREQ1_DRAMTMG15(0), 0x00000000 },
> > > > > + { DDRC_FREQ1_DRAMTMG17(0), 0x0036001b },
> > > > > + { DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1 },
> > > > > + { DDRC_FREQ1_DFITMG0(0), 0x03818200 },
> > > > > + { DDRC_FREQ1_DFITMG2(0), 0x00000000 },
> > > > > + { DDRC_FREQ1_RFSHTMG(0), 0x000C001c },
> > > > > + { DDRC_FREQ1_INIT3(0), 0x00840000 },
> > > > > + { DDRC_FREQ1_INIT4(0), 0x00310000 },
> > > > > + { DDRC_FREQ1_INIT6(0), 0x0066004a },
> > > > > + { DDRC_FREQ1_INIT7(0), 0x0006004a },
> > > > > +
> > > > > + /* Frequency 2: 100mbps */
> > > > > + { DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c },
> > > > > + { DDRC_FREQ2_DRAMTMG1(0), 0x00030410 },
> > > > > + { DDRC_FREQ2_DRAMTMG2(0), 0x0203090c },
> > > > > + { DDRC_FREQ2_DRAMTMG3(0), 0x00505006 },
> > > > > + { DDRC_FREQ2_DRAMTMG4(0), 0x05040305 },
> > > > > + { DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504 },
> > > > > + { DDRC_FREQ2_DRAMTMG6(0), 0x0a060004 },
> > > > > + { DDRC_FREQ2_DRAMTMG7(0), 0x0000090e },
> > > > > + { DDRC_FREQ2_DRAMTMG14(0), 0x00000032 },
> > > > > + { DDRC_FREQ2_DRAMTMG17(0), 0x0036001b },
> > > > > + { DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1 },
> > > > > + { DDRC_FREQ2_DFITMG0(0), 0x03818200 },
> > > > > + { DDRC_FREQ2_DFITMG2(0), 0x00000000 },
> > > > > + { DDRC_FREQ2_RFSHTMG(0), 0x0003800c },
> > > > > + { DDRC_FREQ2_RFSHTMG(0), 0x00030007 },
> > > > > + { DDRC_FREQ2_INIT3(0), 0x00840000 },
> > > > > + { DDRC_FREQ2_INIT4(0), 0x00310008 },
> > > > > + { DDRC_FREQ2_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 },
> > > > > + { DDRC_FREQ2_INIT6(0), 0x0066004a },
> > > > > + { DDRC_FREQ2_INIT7(0), 0x0006004a },
> > > > > +
> > > > > + /* boot start point */
> > > > > + { DDRC_MSTR2(0), 0x2 }, //DDRC_MSTR2
> > > > > +};
> > > > > +
> > > > > +/* PHY Initialize Configuration */
> > > > > +struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
> > > > > + { 0x1005f, 0x1ff },
> > > > > + { 0x1015f, 0x1ff },
> > > > > + { 0x1105f, 0x1ff },
> > > > > + { 0x1115f, 0x1ff },
> > > > > + { 0x1205f, 0x1ff },
> > > > > + { 0x1215f, 0x1ff },
> > > > > + { 0x1305f, 0x1ff },
> > > > > + { 0x1315f, 0x1ff },
> > > > > +
> > > > > + { 0x11005f, 0x1ff },
> > > > > + { 0x11015f, 0x1ff },
> > > > > + { 0x11105f, 0x1ff },
> > > > > + { 0x11115f, 0x1ff },
> > > > > + { 0x11205f, 0x1ff },
> > > > > + { 0x11215f, 0x1ff },
> > > > > + { 0x11305f, 0x1ff },
> > > > > + { 0x11315f, 0x1ff },
> > > > > +
> > > > > + { 0x21005f, 0x1ff },
> > > > > + { 0x21015f, 0x1ff },
> > > > > + { 0x21105f, 0x1ff },
> > > > > + { 0x21115f, 0x1ff },
> > > > > + { 0x21205f, 0x1ff },
> > > > > + { 0x21215f, 0x1ff },
> > > > > + { 0x21305f, 0x1ff },
> > > > > + { 0x21315f, 0x1ff },
> > > > > +
> > > > > + { 0x55, 0x1ff },
> > > > > + { 0x1055, 0x1ff },
> > > > > + { 0x2055, 0x1ff },
> > > > > + { 0x3055, 0x1ff },
> > > > > + { 0x4055, 0x1ff },
> > > > > + { 0x5055, 0x1ff },
> > > > > + { 0x6055, 0x1ff },
> > > > > + { 0x7055, 0x1ff },
> > > > > + { 0x8055, 0x1ff },
> > > > > + { 0x9055, 0x1ff },
> > > > > +
> > > > > + { 0x200c5, 0x19 },
> > > > > + { 0x1200c5, 0x7 },
> > > > > + { 0x2200c5, 0x7 },
> > > > > +
> > > > > + { 0x2002e, 0x2 },
> > > > > + { 0x12002e, 0x2 },
> > > > > + { 0x22002e, 0x2 },
> > > > > +
> > > > > + { 0x90204, 0x0 },
> > > > > + { 0x190204, 0x0 },
> > > > > + { 0x290204, 0x0 },
> > > > > +
> > > > > + { 0x20024, 0xab },
> > > > > + { 0x2003a, 0x0 },
> > > > > +
> > > > > + { 0x120024, 0xab },
> > > > > + { 0x2003a, 0x0 },
> > > > > +
> > > > > + { 0x220024, 0xab },
> > > > > + { 0x2003a, 0x0 },
> > > > > +
> > > > > + { 0x20056, 0x3 },
> > > > > + { 0x120056, 0xa },
> > > > > + { 0x220056, 0xa },
> > > > > +
> > > > > + { 0x1004d, 0xe00 },
> > > > > + { 0x1014d, 0xe00 },
> > > > > + { 0x1104d, 0xe00 },
> > > > > + { 0x1114d, 0xe00 },
> > > > > + { 0x1204d, 0xe00 },
> > > > > + { 0x1214d, 0xe00 },
> > > > > + { 0x1304d, 0xe00 },
> > > > > + { 0x1314d, 0xe00 },
> > > > > +
> > > > > + { 0x11004d, 0xe00 },
> > > > > + { 0x11014d, 0xe00 },
> > > > > + { 0x11104d, 0xe00 },
> > > > > + { 0x11114d, 0xe00 },
> > > > > + { 0x11204d, 0xe00 },
> > > > > + { 0x11214d, 0xe00 },
> > > > > + { 0x11304d, 0xe00 },
> > > > > + { 0x11314d, 0xe00 },
> > > > > +
> > > > > + { 0x21004d, 0xe00 },
> > > > > + { 0x21014d, 0xe00 },
> > > > > + { 0x21104d, 0xe00 },
> > > > > + { 0x21114d, 0xe00 },
> > > > > + { 0x21204d, 0xe00 },
> > > > > + { 0x21214d, 0xe00 },
> > > > > + { 0x21304d, 0xe00 },
> > > > > + { 0x21314d, 0xe00 },
> > > > > +
> > > > > + { 0x10049, 0xfbe },
> > > > > + { 0x10149, 0xfbe },
> > > > > + { 0x11049, 0xfbe },
> > > > > + { 0x11149, 0xfbe },
> > > > > + { 0x12049, 0xfbe },
> > > > > + { 0x12149, 0xfbe },
> > > > > + { 0x13049, 0xfbe },
> > > > > + { 0x13149, 0xfbe },
> > > > > +
> > > > > + { 0x110049, 0xfbe },
> > > > > + { 0x110149, 0xfbe },
> > > > > + { 0x111049, 0xfbe },
> > > > > + { 0x111149, 0xfbe },
> > > > > + { 0x112049, 0xfbe },
> > > > > + { 0x112149, 0xfbe },
> > > > > + { 0x113049, 0xfbe },
> > > > > + { 0x113149, 0xfbe },
> > > > > +
> > > > > + { 0x210049, 0xfbe },
> > > > > + { 0x210149, 0xfbe },
> > > > > + { 0x211049, 0xfbe },
> > > > > + { 0x211149, 0xfbe },
> > > > > + { 0x212049, 0xfbe },
> > > > > + { 0x212149, 0xfbe },
> > > > > + { 0x213049, 0xfbe },
> > > > > + { 0x213149, 0xfbe },
> > > > > +
> > > > > + { 0x43, 0x63 },
> > > > > + { 0x1043, 0x63 },
> > > > > + { 0x2043, 0x63 },
> > > > > + { 0x3043, 0x63 },
> > > > > + { 0x4043, 0x63 },
> > > > > + { 0x5043, 0x63 },
> > > > > + { 0x6043, 0x63 },
> > > > > + { 0x7043, 0x63 },
> > > > > + { 0x8043, 0x63 },
> > > > > + { 0x9043, 0x63 },
> > > > > +
> > > > > + { 0x20018, 0x3 },
> > > > > + { 0x20075, 0x4 },
> > > > > + { 0x20050, 0x0 },
> > > > > + { 0x20008, 0x2ee },
> > > > > + { 0x120008, 0x64 },
> > > > > + { 0x220008, 0x19 },
> > > > > + { 0x20088, 0x9 },
> > > > > +
> > > > > + { 0x200b2, 0x1d4 },
> > > > > + { 0x10043, 0x5a1 },
> > > > > + { 0x10143, 0x5a1 },
> > > > > + { 0x11043, 0x5a1 },
> > > > > + { 0x11143, 0x5a1 },
> > > > > + { 0x12043, 0x5a1 },
> > > > > + { 0x12143, 0x5a1 },
> > > > > + { 0x13043, 0x5a1 },
> > > > > + { 0x13143, 0x5a1 },
> > > > > +
> > > > > + { 0x1200b2, 0xdc },
> > > > > + { 0x110043, 0x5a1 },
> > > > > + { 0x110143, 0x5a1 },
> > > > > + { 0x111043, 0x5a1 },
> > > > > + { 0x111143, 0x5a1 },
> > > > > + { 0x112043, 0x5a1 },
> > > > > + { 0x112143, 0x5a1 },
> > > > > + { 0x113043, 0x5a1 },
> > > > > + { 0x113143, 0x5a1 },
> > > > > +
> > > > > + { 0x2200b2, 0xdc },
> > > > > + { 0x210043, 0x5a1 },
> > > > > + { 0x210143, 0x5a1 },
> > > > > + { 0x211043, 0x5a1 },
> > > > > + { 0x211143, 0x5a1 },
> > > > > + { 0x212043, 0x5a1 },
> > > > > + { 0x212143, 0x5a1 },
> > > > > + { 0x213043, 0x5a1 },
> > > > > + { 0x213143, 0x5a1 },
> > > > > +
> > > > > + { 0x200fa, 0x1 },
> > > > > + { 0x1200fa, 0x1 },
> > > > > + { 0x2200fa, 0x1 },
> > > > > +
> > > > > + { 0x20019, 0x1 },
> > > > > + { 0x120019, 0x1 },
> > > > > + { 0x220019, 0x1 },
> > > > > +
> > > > > + { 0x200f0, 0x660 },
> > > > > + { 0x200f1, 0x0 },
> > > > > + { 0x200f2, 0x4444 },
> > > > > + { 0x200f3, 0x8888 },
> > > > > + { 0x200f4, 0x5665 },
> > > > > + { 0x200f5, 0x0 },
> > > > > + { 0x200f6, 0x0 },
> > > > > + { 0x200f7, 0xf000 },
> > > > > +
> > > > > + { 0x20025, 0x0 },
> > > > > + { 0x2002d, LPDDR4_PHY_DMIPinPresent },
> > > > > + { 0x12002d, LPDDR4_PHY_DMIPinPresent },
> > > > > + { 0x22002d, LPDDR4_PHY_DMIPinPresent },
> > > > > + { 0x200c7, 0x21 },
> > > > > + { 0x200ca, 0x24 },
> > > > > + { 0x1200c7, 0x21 },
> > > > > + { 0x1200ca, 0x24 },
> > > > > + { 0x2200c7, 0x21 },
> > > > > + { 0x2200ca, 0x24 },
> > > >
> > > > Why do you add tuple - offset and value? Shouldn't we have the
> > > > DDR training functions here?
> > > >
> > > > It is possible to train IMX6Q and Vybrid's DDR3 (as fair as I
> > > > know). Would it be also possible to add the DDR4 training code
> > > > for IMX8?
> > > > > +};
> > > > > +
> > > > > +/* ddr phy trained csr */
> > > > > +struct dram_cfg_param lpddr4_ddrphy_trained_csr[] = {
> > > > > + { 0x200b2, 0x0 },
> > > > > + { 0x1200b2, 0x0 },
> > > > > + { 0x2200b2, 0x0 },
> > > > > + { 0x200cb, 0x0 },
> > > > > + { 0x10043, 0x0 },
> > > > > + { 0x110043, 0x0 },
> > > > > + { 0x210043, 0x0 },
> > > > > + { 0x10143, 0x0 },
> > > > > + { 0x110143, 0x0 },
> > > > > + { 0x210143, 0x0 },
> > > > > + { 0x11043, 0x0 },
> > > > > + { 0x111043, 0x0 },
> > > > > + { 0x211043, 0x0 },
> > > > > + { 0x11143, 0x0 },
> > > > > + { 0x111143, 0x0 },
> > > > > + { 0x211143, 0x0 },
> > > > > + { 0x12043, 0x0 },
> > > > > + { 0x112043, 0x0 },
> > > > > + { 0x212043, 0x0 },
> > > > > + { 0x12143, 0x0 },
> > > > > + { 0x112143, 0x0 },
> > > > > + { 0x212143, 0x0 },
> > > > > + { 0x13043, 0x0 },
> > > > > + { 0x113043, 0x0 },
> > > > > + { 0x213043, 0x0 },
> > > > > + { 0x13143, 0x0 },
> > > > > + { 0x113143, 0x0 },
> > > > > + { 0x213143, 0x0 },
> > > > > + { 0x80, 0x0 },
> > > > > + { 0x100080, 0x0 },
> > > > > + { 0x200080, 0x0 },
> > > > > + { 0x1080, 0x0 },
> > > > > + { 0x101080, 0x0 },
> > > > > + { 0x201080, 0x0 },
> > > > > + { 0x2080, 0x0 },
> > > > > + { 0x102080, 0x0 },
> > > > > + { 0x202080, 0x0 },
> > > > > + { 0x3080, 0x0 },
> > > > > + { 0x103080, 0x0 },
> > > > > + { 0x203080, 0x0 },
> > > > > + { 0x4080, 0x0 },
> > > > > + { 0x104080, 0x0 },
> > > > > + { 0x204080, 0x0 },
> > > > > + { 0x5080, 0x0 },
> > > > > + { 0x105080, 0x0 },
> > > > > + { 0x205080, 0x0 },
> > > > > + { 0x6080, 0x0 },
> > > > > + { 0x106080, 0x0 },
> > > > > + { 0x206080, 0x0 },
> > > > > + { 0x7080, 0x0 },
> > > > > + { 0x107080, 0x0 },
> > > > > + { 0x207080, 0x0 },
> > > > > + { 0x8080, 0x0 },
> > > > > + { 0x108080, 0x0 },
> > > > > + { 0x208080, 0x0 },
> > > > > + { 0x9080, 0x0 },
> > > > > + { 0x109080, 0x0 },
> > > > > + { 0x209080, 0x0 },
> > > > > + { 0x10080, 0x0 },
> > > > > + { 0x110080, 0x0 },
> > > > > + { 0x210080, 0x0 },
> > > > > + { 0x10180, 0x0 },
> > > > > + { 0x110180, 0x0 },
> > > > > + { 0x210180, 0x0 },
> > > > > + { 0x11080, 0x0 },
> > > > > + { 0x111080, 0x0 },
> > > > > + { 0x211080, 0x0 },
> > > > > + { 0x11180, 0x0 },
> > > > > + { 0x111180, 0x0 },
> > > > > + { 0x211180, 0x0 },
> > > > > + { 0x12080, 0x0 },
> > > > > + { 0x112080, 0x0 },
> > > > > + { 0x212080, 0x0 },
> > > > > + { 0x12180, 0x0 },
> > > > > + { 0x112180, 0x0 },
> > > > > + { 0x212180, 0x0 },
> > > > > + { 0x13080, 0x0 },
> > > > > + { 0x113080, 0x0 },
> > > > > + { 0x213080, 0x0 },
> > > > > + { 0x13180, 0x0 },
> > > > > + { 0x113180, 0x0 },
> > > > > + { 0x213180, 0x0 },
> > > > > + { 0x10081, 0x0 },
> > > > > + { 0x110081, 0x0 },
> > > > > + { 0x210081, 0x0 },
> > > > > + { 0x10181, 0x0 },
> > > > > + { 0x110181, 0x0 },
> > > > > + { 0x210181, 0x0 },
> > > > > + { 0x11081, 0x0 },
> > > > > + { 0x111081, 0x0 },
> > > > > + { 0x211081, 0x0 },
> > > > > + { 0x11181, 0x0 },
> > > > > + { 0x111181, 0x0 },
> > > > > + { 0x211181, 0x0 },
> > > > > + { 0x12081, 0x0 },
> > > > > + { 0x112081, 0x0 },
> > > > > + { 0x212081, 0x0 },
> > > > > + { 0x12181, 0x0 },
> > > > > + { 0x112181, 0x0 },
> > > > > + { 0x212181, 0x0 },
> > > > > + { 0x13081, 0x0 },
> > > > > + { 0x113081, 0x0 },
> > > > > + { 0x213081, 0x0 },
> > > > > + { 0x13181, 0x0 },
> > > > > + { 0x113181, 0x0 },
> > > > > + { 0x213181, 0x0 },
> > > > > + { 0x100d0, 0x0 },
> > > > > + { 0x1100d0, 0x0 },
> > > > > + { 0x2100d0, 0x0 },
> > > > > + { 0x101d0, 0x0 },
> > > > > + { 0x1101d0, 0x0 },
> > > > > + { 0x2101d0, 0x0 },
> > > > > + { 0x110d0, 0x0 },
> > > > > + { 0x1110d0, 0x0 },
> > > > > + { 0x2110d0, 0x0 },
> > > > > + { 0x111d0, 0x0 },
> > > > > + { 0x1111d0, 0x0 },
> > > > > + { 0x2111d0, 0x0 },
> > > > > + { 0x120d0, 0x0 },
> > > > > + { 0x1120d0, 0x0 },
> > > > > + { 0x2120d0, 0x0 },
> > > > > + { 0x121d0, 0x0 },
> > > > > + { 0x1121d0, 0x0 },
> > > > > + { 0x2121d0, 0x0 },
> > > > > + { 0x130d0, 0x0 },
> > > > > + { 0x1130d0, 0x0 },
> > > > > + { 0x2130d0, 0x0 },
> > > > > + { 0x131d0, 0x0 },
> > > > > + { 0x1131d0, 0x0 },
> > > > > + { 0x2131d0, 0x0 },
> > > > > + { 0x100d1, 0x0 },
> > > > > + { 0x1100d1, 0x0 },
> > > > > + { 0x2100d1, 0x0 },
> > > > > + { 0x101d1, 0x0 },
> > > > > + { 0x1101d1, 0x0 },
> > > > > + { 0x2101d1, 0x0 },
> > > > > + { 0x110d1, 0x0 },
> > > > > + { 0x1110d1, 0x0 },
> > > > > + { 0x2110d1, 0x0 },
> > > > > + { 0x111d1, 0x0 },
> > > > > + { 0x1111d1, 0x0 },
> > > > > + { 0x2111d1, 0x0 },
> > > > > + { 0x120d1, 0x0 },
> > > > > + { 0x1120d1, 0x0 },
> > > > > + { 0x2120d1, 0x0 },
> > > > > + { 0x121d1, 0x0 },
> > > > > + { 0x1121d1, 0x0 },
> > > > > + { 0x2121d1, 0x0 },
> > > > > + { 0x130d1, 0x0 },
> > > > > + { 0x1130d1, 0x0 },
> > > > > + { 0x2130d1, 0x0 },
> > > > > + { 0x131d1, 0x0 },
> > > > > + { 0x1131d1, 0x0 },
> > > > > + { 0x2131d1, 0x0 },
> > > > > + { 0x10068, 0x0 },
> > > > > + { 0x10168, 0x0 },
> > > > > + { 0x10268, 0x0 },
> > > > > + { 0x10368, 0x0 },
> > > > > + { 0x10468, 0x0 },
> > > > > + { 0x10568, 0x0 },
> > > > > + { 0x10668, 0x0 },
> > > > > + { 0x10768, 0x0 },
> > > > > + { 0x10868, 0x0 },
> > > > > + { 0x11068, 0x0 },
> > > > > + { 0x11168, 0x0 },
> > > > > + { 0x11268, 0x0 },
> > > > > + { 0x11368, 0x0 },
> > > > > + { 0x11468, 0x0 },
> > > > > + { 0x11568, 0x0 },
> > > > > + { 0x11668, 0x0 },
> > > > > + { 0x11768, 0x0 },
> > > > > + { 0x11868, 0x0 },
> > > > > + { 0x12068, 0x0 },
> > > > > + { 0x12168, 0x0 },
> > > > > + { 0x12268, 0x0 },
> > > > > + { 0x12368, 0x0 },
> > > > > + { 0x12468, 0x0 },
> > > > > + { 0x12568, 0x0 },
> > > > > + { 0x12668, 0x0 },
> > > > > + { 0x12768, 0x0 },
> > > > > + { 0x12868, 0x0 },
> > > > > + { 0x13068, 0x0 },
> > > > > + { 0x13168, 0x0 },
> > > > > + { 0x13268, 0x0 },
> > > > > + { 0x13368, 0x0 },
> > > > > + { 0x13468, 0x0 },
> > > > > + { 0x13568, 0x0 },
> > > > > + { 0x13668, 0x0 },
> > > > > + { 0x13768, 0x0 },
> > > > > + { 0x13868, 0x0 },
> > > > > + { 0x10069, 0x0 },
> > > > > + { 0x10169, 0x0 },
> > > > > + { 0x10269, 0x0 },
> > > > > + { 0x10369, 0x0 },
> > > > > + { 0x10469, 0x0 },
> > > > > + { 0x10569, 0x0 },
> > > > > + { 0x10669, 0x0 },
> > > > > + { 0x10769, 0x0 },
> > > > > + { 0x10869, 0x0 },
> > > > > + { 0x11069, 0x0 },
> > > > > + { 0x11169, 0x0 },
> > > > > + { 0x11269, 0x0 },
> > > > > + { 0x11369, 0x0 },
> > > > > + { 0x11469, 0x0 },
> > > > > + { 0x11569, 0x0 },
> > > > > + { 0x11669, 0x0 },
> > > > > + { 0x11769, 0x0 },
> > > > > + { 0x11869, 0x0 },
> > > > > + { 0x12069, 0x0 },
> > > > > + { 0x12169, 0x0 },
> > > > > + { 0x12269, 0x0 },
> > > > > + { 0x12369, 0x0 },
> > > > > + { 0x12469, 0x0 },
> > > > > + { 0x12569, 0x0 },
> > > > > + { 0x12669, 0x0 },
> > > > > + { 0x12769, 0x0 },
> > > > > + { 0x12869, 0x0 },
> > > > > + { 0x13069, 0x0 },
> > > > > + { 0x13169, 0x0 },
> > > > > + { 0x13269, 0x0 },
> > > > > + { 0x13369, 0x0 },
> > > > > + { 0x13469, 0x0 },
> > > > > + { 0x13569, 0x0 },
> > > > > + { 0x13669, 0x0 },
> > > > > + { 0x13769, 0x0 },
> > > > > + { 0x13869, 0x0 },
> > > > > + { 0x1008c, 0x0 },
> > > > > + { 0x11008c, 0x0 },
> > > > > + { 0x21008c, 0x0 },
> > > > > + { 0x1018c, 0x0 },
> > > > > + { 0x11018c, 0x0 },
> > > > > + { 0x21018c, 0x0 },
> > > > > + { 0x1108c, 0x0 },
> > > > > + { 0x11108c, 0x0 },
> > > > > + { 0x21108c, 0x0 },
> > > > > + { 0x1118c, 0x0 },
> > > > > + { 0x11118c, 0x0 },
> > > > > + { 0x21118c, 0x0 },
> > > > > + { 0x1208c, 0x0 },
> > > > > + { 0x11208c, 0x0 },
> > > > > + { 0x21208c, 0x0 },
> > > > > + { 0x1218c, 0x0 },
> > > > > + { 0x11218c, 0x0 },
> > > > > + { 0x21218c, 0x0 },
> > > > > + { 0x1308c, 0x0 },
> > > > > + { 0x11308c, 0x0 },
> > > > > + { 0x21308c, 0x0 },
> > > > > + { 0x1318c, 0x0 },
> > > > > + { 0x11318c, 0x0 },
> > > > > + { 0x21318c, 0x0 },
> > > > > + { 0x1008d, 0x0 },
> > > > > + { 0x11008d, 0x0 },
> > > > > + { 0x21008d, 0x0 },
> > > > > + { 0x1018d, 0x0 },
> > > > > + { 0x11018d, 0x0 },
> > > > > + { 0x21018d, 0x0 },
> > > > > + { 0x1108d, 0x0 },
> > > > > + { 0x11108d, 0x0 },
> > > > > + { 0x21108d, 0x0 },
> > > > > + { 0x1118d, 0x0 },
> > > > > + { 0x11118d, 0x0 },
> > > > > + { 0x21118d, 0x0 },
> > > > > + { 0x1208d, 0x0 },
> > > > > + { 0x11208d, 0x0 },
> > > > > + { 0x21208d, 0x0 },
> > > > > + { 0x1218d, 0x0 },
> > > > > + { 0x11218d, 0x0 },
> > > > > + { 0x21218d, 0x0 },
> > > > > + { 0x1308d, 0x0 },
> > > > > + { 0x11308d, 0x0 },
> > > > > + { 0x21308d, 0x0 },
> > > > > + { 0x1318d, 0x0 },
> > > > > + { 0x11318d, 0x0 },
> > > > > + { 0x21318d, 0x0 },
> > > > > + { 0x100c0, 0x0 },
> > > > > + { 0x1100c0, 0x0 },
> > > > > + { 0x2100c0, 0x0 },
> > > > > + { 0x101c0, 0x0 },
> > > > > + { 0x1101c0, 0x0 },
> > > > > + { 0x2101c0, 0x0 },
> > > > > + { 0x102c0, 0x0 },
> > > > > + { 0x1102c0, 0x0 },
> > > > > + { 0x2102c0, 0x0 },
> > > > > + { 0x103c0, 0x0 },
> > > > > + { 0x1103c0, 0x0 },
> > > > > + { 0x2103c0, 0x0 },
> > > > > + { 0x104c0, 0x0 },
> > > > > + { 0x1104c0, 0x0 },
> > > > > + { 0x2104c0, 0x0 },
> > > > > + { 0x105c0, 0x0 },
> > > > > + { 0x1105c0, 0x0 },
> > > > > + { 0x2105c0, 0x0 },
> > > > > + { 0x106c0, 0x0 },
> > > > > + { 0x1106c0, 0x0 },
> > > > > + { 0x2106c0, 0x0 },
> > > > > + { 0x107c0, 0x0 },
> > > > > + { 0x1107c0, 0x0 },
> > > > > + { 0x2107c0, 0x0 },
> > > > > + { 0x108c0, 0x0 },
> > > > > + { 0x1108c0, 0x0 },
> > > > > + { 0x2108c0, 0x0 },
> > > > > + { 0x110c0, 0x0 },
> > > > > + { 0x1110c0, 0x0 },
> > > > > + { 0x2110c0, 0x0 },
> > > > > + { 0x111c0, 0x0 },
> > > > > + { 0x1111c0, 0x0 },
> > > > > + { 0x2111c0, 0x0 },
> > > > > + { 0x112c0, 0x0 },
> > > > > + { 0x1112c0, 0x0 },
> > > > > + { 0x2112c0, 0x0 },
> > > > > + { 0x113c0, 0x0 },
> > > > > + { 0x1113c0, 0x0 },
> > > > > + { 0x2113c0, 0x0 },
> > > > > + { 0x114c0, 0x0 },
> > > > > + { 0x1114c0, 0x0 },
> > > > > + { 0x2114c0, 0x0 },
> > > > > + { 0x115c0, 0x0 },
> > > > > + { 0x1115c0, 0x0 },
> > > > > + { 0x2115c0, 0x0 },
> > > > > + { 0x116c0, 0x0 },
> > > > > + { 0x1116c0, 0x0 },
> > > > > + { 0x2116c0, 0x0 },
> > > > > + { 0x117c0, 0x0 },
> > > > > + { 0x1117c0, 0x0 },
> > > > > + { 0x2117c0, 0x0 },
> > > > > + { 0x118c0, 0x0 },
> > > > > + { 0x1118c0, 0x0 },
> > > > > + { 0x2118c0, 0x0 },
> > > > > + { 0x120c0, 0x0 },
> > > > > + { 0x1120c0, 0x0 },
> > > > > + { 0x2120c0, 0x0 },
> > > > > + { 0x121c0, 0x0 },
> > > > > + { 0x1121c0, 0x0 },
> > > > > + { 0x2121c0, 0x0 },
> > > > > + { 0x122c0, 0x0 },
> > > > > + { 0x1122c0, 0x0 },
> > > > > + { 0x2122c0, 0x0 },
> > > > > + { 0x123c0, 0x0 },
> > > > > + { 0x1123c0, 0x0 },
> > > > > + { 0x2123c0, 0x0 },
> > > > > + { 0x124c0, 0x0 },
> > > > > + { 0x1124c0, 0x0 },
> > > > > + { 0x2124c0, 0x0 },
> > > > > + { 0x125c0, 0x0 },
> > > > > + { 0x1125c0, 0x0 },
> > > > > + { 0x2125c0, 0x0 },
> > > > > + { 0x126c0, 0x0 },
> > > > > + { 0x1126c0, 0x0 },
> > > > > + { 0x2126c0, 0x0 },
> > > > > + { 0x127c0, 0x0 },
> > > > > + { 0x1127c0, 0x0 },
> > > > > + { 0x2127c0, 0x0 },
> > > > > + { 0x128c0, 0x0 },
> > > > > + { 0x1128c0, 0x0 },
> > > > > + { 0x2128c0, 0x0 },
> > > > > + { 0x130c0, 0x0 },
> > > > > + { 0x1130c0, 0x0 },
> > > > > + { 0x2130c0, 0x0 },
> > > > > + { 0x131c0, 0x0 },
> > > > > + { 0x1131c0, 0x0 },
> > > > > + { 0x2131c0, 0x0 },
> > > > > + { 0x132c0, 0x0 },
> > > > > + { 0x1132c0, 0x0 },
> > > > > + { 0x2132c0, 0x0 },
> > > > > + { 0x133c0, 0x0 },
> > > > > + { 0x1133c0, 0x0 },
> > > > > + { 0x2133c0, 0x0 },
> > > > > + { 0x134c0, 0x0 },
> > > > > + { 0x1134c0, 0x0 },
> > > > > + { 0x2134c0, 0x0 },
> > > > > + { 0x135c0, 0x0 },
> > > > > + { 0x1135c0, 0x0 },
> > > > > + { 0x2135c0, 0x0 },
> > > > > + { 0x136c0, 0x0 },
> > > > > + { 0x1136c0, 0x0 },
> > > > > + { 0x2136c0, 0x0 },
> > > > > + { 0x137c0, 0x0 },
> > > > > + { 0x1137c0, 0x0 },
> > > > > + { 0x2137c0, 0x0 },
> > > > > + { 0x138c0, 0x0 },
> > > > > + { 0x1138c0, 0x0 },
> > > > > + { 0x2138c0, 0x0 },
> > > > > + { 0x100c1, 0x0 },
> > > > > + { 0x1100c1, 0x0 },
> > > > > + { 0x2100c1, 0x0 },
> > > > > + { 0x101c1, 0x0 },
> > > > > + { 0x1101c1, 0x0 },
> > > > > + { 0x2101c1, 0x0 },
> > > > > + { 0x102c1, 0x0 },
> > > > > + { 0x1102c1, 0x0 },
> > > > > + { 0x2102c1, 0x0 },
> > > > > + { 0x103c1, 0x0 },
> > > > > + { 0x1103c1, 0x0 },
> > > > > + { 0x2103c1, 0x0 },
> > > > > + { 0x104c1, 0x0 },
> > > > > + { 0x1104c1, 0x0 },
> > > > > + { 0x2104c1, 0x0 },
> > > > > + { 0x105c1, 0x0 },
> > > > > + { 0x1105c1, 0x0 },
> > > > > + { 0x2105c1, 0x0 },
> > > > > + { 0x106c1, 0x0 },
> > > > > + { 0x1106c1, 0x0 },
> > > > > + { 0x2106c1, 0x0 },
> > > > > + { 0x107c1, 0x0 },
> > > > > + { 0x1107c1, 0x0 },
> > > > > + { 0x2107c1, 0x0 },
> > > > > + { 0x108c1, 0x0 },
> > > > > + { 0x1108c1, 0x0 },
> > > > > + { 0x2108c1, 0x0 },
> > > > > + { 0x110c1, 0x0 },
> > > > > + { 0x1110c1, 0x0 },
> > > > > + { 0x2110c1, 0x0 },
> > > > > + { 0x111c1, 0x0 },
> > > > > + { 0x1111c1, 0x0 },
> > > > > + { 0x2111c1, 0x0 },
> > > > > + { 0x112c1, 0x0 },
> > > > > + { 0x1112c1, 0x0 },
> > > > > + { 0x2112c1, 0x0 },
> > > > > + { 0x113c1, 0x0 },
> > > > > + { 0x1113c1, 0x0 },
> > > > > + { 0x2113c1, 0x0 },
> > > > > + { 0x114c1, 0x0 },
> > > > > + { 0x1114c1, 0x0 },
> > > > > + { 0x2114c1, 0x0 },
> > > > > + { 0x115c1, 0x0 },
> > > > > + { 0x1115c1, 0x0 },
> > > > > + { 0x2115c1, 0x0 },
> > > > > + { 0x116c1, 0x0 },
> > > > > + { 0x1116c1, 0x0 },
> > > > > + { 0x2116c1, 0x0 },
> > > > > + { 0x117c1, 0x0 },
> > > > > + { 0x1117c1, 0x0 },
> > > > > + { 0x2117c1, 0x0 },
> > > > > + { 0x118c1, 0x0 },
> > > > > + { 0x1118c1, 0x0 },
> > > > > + { 0x2118c1, 0x0 },
> > > > > + { 0x120c1, 0x0 },
> > > > > + { 0x1120c1, 0x0 },
> > > > > + { 0x2120c1, 0x0 },
> > > > > + { 0x121c1, 0x0 },
> > > > > + { 0x1121c1, 0x0 },
> > > > > + { 0x2121c1, 0x0 },
> > > > > + { 0x122c1, 0x0 },
> > > > > + { 0x1122c1, 0x0 },
> > > > > + { 0x2122c1, 0x0 },
> > > > > + { 0x123c1, 0x0 },
> > > > > + { 0x1123c1, 0x0 },
> > > > > + { 0x2123c1, 0x0 },
> > > > > + { 0x124c1, 0x0 },
> > > > > + { 0x1124c1, 0x0 },
> > > > > + { 0x2124c1, 0x0 },
> > > > > + { 0x125c1, 0x0 },
> > > > > + { 0x1125c1, 0x0 },
> > > > > + { 0x2125c1, 0x0 },
> > > > > + { 0x126c1, 0x0 },
> > > > > + { 0x1126c1, 0x0 },
> > > > > + { 0x2126c1, 0x0 },
> > > > > + { 0x127c1, 0x0 },
> > > > > + { 0x1127c1, 0x0 },
> > > > > + { 0x2127c1, 0x0 },
> > > > > + { 0x128c1, 0x0 },
> > > > > + { 0x1128c1, 0x0 },
> > > > > + { 0x2128c1, 0x0 },
> > > > > + { 0x130c1, 0x0 },
> > > > > + { 0x1130c1, 0x0 },
> > > > > + { 0x2130c1, 0x0 },
> > > > > + { 0x131c1, 0x0 },
> > > > > + { 0x1131c1, 0x0 },
> > > > > + { 0x2131c1, 0x0 },
> > > > > + { 0x132c1, 0x0 },
> > > > > + { 0x1132c1, 0x0 },
> > > > > + { 0x2132c1, 0x0 },
> > > > > + { 0x133c1, 0x0 },
> > > > > + { 0x1133c1, 0x0 },
> > > > > + { 0x2133c1, 0x0 },
> > > > > + { 0x134c1, 0x0 },
> > > > > + { 0x1134c1, 0x0 },
> > > > > + { 0x2134c1, 0x0 },
> > > > > + { 0x135c1, 0x0 },
> > > > > + { 0x1135c1, 0x0 },
> > > > > + { 0x2135c1, 0x0 },
> > > > > + { 0x136c1, 0x0 },
> > > > > + { 0x1136c1, 0x0 },
> > > > > + { 0x2136c1, 0x0 },
> > > > > + { 0x137c1, 0x0 },
> > > > > + { 0x1137c1, 0x0 },
> > > > > + { 0x2137c1, 0x0 },
> > > > > + { 0x138c1, 0x0 },
> > > > > + { 0x1138c1, 0x0 },
> > > > > + { 0x2138c1, 0x0 },
> > > > > + { 0x10020, 0x0 },
> > > > > + { 0x110020, 0x0 },
> > > > > + { 0x210020, 0x0 },
> > > > > + { 0x11020, 0x0 },
> > > > > + { 0x111020, 0x0 },
> > > > > + { 0x211020, 0x0 },
> > > > > + { 0x12020, 0x0 },
> > > > > + { 0x112020, 0x0 },
> > > > > + { 0x212020, 0x0 },
> > > > > + { 0x13020, 0x0 },
> > > > > + { 0x113020, 0x0 },
> > > > > + { 0x213020, 0x0 },
> > > > > + { 0x20072, 0x0 },
> > > > > + { 0x20073, 0x0 },
> > > > > + { 0x20074, 0x0 },
> > > > > + { 0x100aa, 0x0 },
> > > > > + { 0x110aa, 0x0 },
> > > > > + { 0x120aa, 0x0 },
> > > > > + { 0x130aa, 0x0 },
> > > > > + { 0x20010, 0x0 },
> > > > > + { 0x120010, 0x0 },
> > > > > + { 0x220010, 0x0 },
> > > > > + { 0x20011, 0x0 },
> > > > > + { 0x120011, 0x0 },
> > > > > + { 0x220011, 0x0 },
> > > > > + { 0x100ae, 0x0 },
> > > > > + { 0x1100ae, 0x0 },
> > > > > + { 0x2100ae, 0x0 },
> > > > > + { 0x100af, 0x0 },
> > > > > + { 0x1100af, 0x0 },
> > > > > + { 0x2100af, 0x0 },
> > > > > + { 0x110ae, 0x0 },
> > > > > + { 0x1110ae, 0x0 },
> > > > > + { 0x2110ae, 0x0 },
> > > > > + { 0x110af, 0x0 },
> > > > > + { 0x1110af, 0x0 },
> > > > > + { 0x2110af, 0x0 },
> > > > > + { 0x120ae, 0x0 },
> > > > > + { 0x1120ae, 0x0 },
> > > > > + { 0x2120ae, 0x0 },
> > > > > + { 0x120af, 0x0 },
> > > > > + { 0x1120af, 0x0 },
> > > > > + { 0x2120af, 0x0 },
> > > > > + { 0x130ae, 0x0 },
> > > > > + { 0x1130ae, 0x0 },
> > > > > + { 0x2130ae, 0x0 },
> > > > > + { 0x130af, 0x0 },
> > > > > + { 0x1130af, 0x0 },
> > > > > + { 0x2130af, 0x0 },
> > > > > + { 0x20020, 0x0 },
> > > > > + { 0x120020, 0x0 },
> > > > > + { 0x220020, 0x0 },
> > > > > + { 0x100a0, 0x0 },
> > > > > + { 0x100a1, 0x0 },
> > > > > + { 0x100a2, 0x0 },
> > > > > + { 0x100a3, 0x0 },
> > > > > + { 0x100a4, 0x0 },
> > > > > + { 0x100a5, 0x0 },
> > > > > + { 0x100a6, 0x0 },
> > > > > + { 0x100a7, 0x0 },
> > > > > + { 0x110a0, 0x0 },
> > > > > + { 0x110a1, 0x0 },
> > > > > + { 0x110a2, 0x0 },
> > > > > + { 0x110a3, 0x0 },
> > > > > + { 0x110a4, 0x0 },
> > > > > + { 0x110a5, 0x0 },
> > > > > + { 0x110a6, 0x0 },
> > > > > + { 0x110a7, 0x0 },
> > > > > + { 0x120a0, 0x0 },
> > > > > + { 0x120a1, 0x0 },
> > > > > + { 0x120a2, 0x0 },
> > > > > + { 0x120a3, 0x0 },
> > > > > + { 0x120a4, 0x0 },
> > > > > + { 0x120a5, 0x0 },
> > > > > + { 0x120a6, 0x0 },
> > > > > + { 0x120a7, 0x0 },
> > > > > + { 0x130a0, 0x0 },
> > > > > + { 0x130a1, 0x0 },
> > > > > + { 0x130a2, 0x0 },
> > > > > + { 0x130a3, 0x0 },
> > > > > + { 0x130a4, 0x0 },
> > > > > + { 0x130a5, 0x0 },
> > > > > + { 0x130a6, 0x0 },
> > > > > + { 0x130a7, 0x0 },
> > > > > + { 0x2007c, 0x0 },
> > > > > + { 0x12007c, 0x0 },
> > > > > + { 0x22007c, 0x0 },
> > > > > + { 0x2007d, 0x0 },
> > > > > + { 0x12007d, 0x0 },
> > > > > + { 0x22007d, 0x0 },
> > > > > + { 0x400fd, 0x0 },
> > > > > + { 0x400c0, 0x0 },
> > > > > + { 0x90201, 0x0 },
> > > > > + { 0x190201, 0x0 },
> > > > > + { 0x290201, 0x0 },
> > > > > + { 0x90202, 0x0 },
> > > > > + { 0x190202, 0x0 },
> > > > > + { 0x290202, 0x0 },
> > > > > + { 0x90203, 0x0 },
> > > > > + { 0x190203, 0x0 },
> > > > > + { 0x290203, 0x0 },
> > > > > + { 0x90204, 0x0 },
> > > > > + { 0x190204, 0x0 },
> > > > > + { 0x290204, 0x0 },
> > > > > + { 0x90205, 0x0 },
> > > > > + { 0x190205, 0x0 },
> > > > > + { 0x290205, 0x0 },
> > > > > + { 0x90206, 0x0 },
> > > > > + { 0x190206, 0x0 },
> > > > > + { 0x290206, 0x0 },
> > > > > + { 0x90207, 0x0 },
> > > > > + { 0x190207, 0x0 },
> > > > > + { 0x290207, 0x0 },
> > > > > + { 0x90208, 0x0 },
> > > > > + { 0x190208, 0x0 },
> > > > > + { 0x290208, 0x0 },
> > > > > + { 0x10062, 0x0 },
> > > > > + { 0x10162, 0x0 },
> > > > > + { 0x10262, 0x0 },
> > > > > + { 0x10362, 0x0 },
> > > > > + { 0x10462, 0x0 },
> > > > > + { 0x10562, 0x0 },
> > > > > + { 0x10662, 0x0 },
> > > > > + { 0x10762, 0x0 },
> > > > > + { 0x10862, 0x0 },
> > > > > + { 0x11062, 0x0 },
> > > > > + { 0x11162, 0x0 },
> > > > > + { 0x11262, 0x0 },
> > > > > + { 0x11362, 0x0 },
> > > > > + { 0x11462, 0x0 },
> > > > > + { 0x11562, 0x0 },
> > > > > + { 0x11662, 0x0 },
> > > > > + { 0x11762, 0x0 },
> > > > > + { 0x11862, 0x0 },
> > > > > + { 0x12062, 0x0 },
> > > > > + { 0x12162, 0x0 },
> > > > > + { 0x12262, 0x0 },
> > > > > + { 0x12362, 0x0 },
> > > > > + { 0x12462, 0x0 },
> > > > > + { 0x12562, 0x0 },
> > > > > + { 0x12662, 0x0 },
> > > > > + { 0x12762, 0x0 },
> > > > > + { 0x12862, 0x0 },
> > > > > + { 0x13062, 0x0 },
> > > > > + { 0x13162, 0x0 },
> > > > > + { 0x13262, 0x0 },
> > > > > + { 0x13362, 0x0 },
> > > > > + { 0x13462, 0x0 },
> > > > > + { 0x13562, 0x0 },
> > > > > + { 0x13662, 0x0 },
> > > > > + { 0x13762, 0x0 },
> > > > > + { 0x13862, 0x0 },
> > > > > + { 0x20077, 0x0 },
> > > > > + { 0x10001, 0x0 },
> > > > > + { 0x11001, 0x0 },
> > > > > + { 0x12001, 0x0 },
> > > > > + { 0x13001, 0x0 },
> > > > > + { 0x10040, 0x0 },
> > > > > + { 0x10140, 0x0 },
> > > > > + { 0x10240, 0x0 },
> > > > > + { 0x10340, 0x0 },
> > > > > + { 0x10440, 0x0 },
> > > > > + { 0x10540, 0x0 },
> > > > > + { 0x10640, 0x0 },
> > > > > + { 0x10740, 0x0 },
> > > > > + { 0x10840, 0x0 },
> > > > > + { 0x10030, 0x0 },
> > > > > + { 0x10130, 0x0 },
> > > > > + { 0x10230, 0x0 },
> > > > > + { 0x10330, 0x0 },
> > > > > + { 0x10430, 0x0 },
> > > > > + { 0x10530, 0x0 },
> > > > > + { 0x10630, 0x0 },
> > > > > + { 0x10730, 0x0 },
> > > > > + { 0x10830, 0x0 },
> > > > > + { 0x11040, 0x0 },
> > > > > + { 0x11140, 0x0 },
> > > > > + { 0x11240, 0x0 },
> > > > > + { 0x11340, 0x0 },
> > > > > + { 0x11440, 0x0 },
> > > > > + { 0x11540, 0x0 },
> > > > > + { 0x11640, 0x0 },
> > > > > + { 0x11740, 0x0 },
> > > > > + { 0x11840, 0x0 },
> > > > > + { 0x11030, 0x0 },
> > > > > + { 0x11130, 0x0 },
> > > > > + { 0x11230, 0x0 },
> > > > > + { 0x11330, 0x0 },
> > > > > + { 0x11430, 0x0 },
> > > > > + { 0x11530, 0x0 },
> > > > > + { 0x11630, 0x0 },
> > > > > + { 0x11730, 0x0 },
> > > > > + { 0x11830, 0x0 },
> > > > > + { 0x12040, 0x0 },
> > > > > + { 0x12140, 0x0 },
> > > > > + { 0x12240, 0x0 },
> > > > > + { 0x12340, 0x0 },
> > > > > + { 0x12440, 0x0 },
> > > > > + { 0x12540, 0x0 },
> > > > > + { 0x12640, 0x0 },
> > > > > + { 0x12740, 0x0 },
> > > > > + { 0x12840, 0x0 },
> > > > > + { 0x12030, 0x0 },
> > > > > + { 0x12130, 0x0 },
> > > > > + { 0x12230, 0x0 },
> > > > > + { 0x12330, 0x0 },
> > > > > + { 0x12430, 0x0 },
> > > > > + { 0x12530, 0x0 },
> > > > > + { 0x12630, 0x0 },
> > > > > + { 0x12730, 0x0 },
> > > > > + { 0x12830, 0x0 },
> > > > > + { 0x13040, 0x0 },
> > > > > + { 0x13140, 0x0 },
> > > > > + { 0x13240, 0x0 },
> > > > > + { 0x13340, 0x0 },
> > > > > + { 0x13440, 0x0 },
> > > > > + { 0x13540, 0x0 },
> > > > > + { 0x13640, 0x0 },
> > > > > + { 0x13740, 0x0 },
> > > > > + { 0x13840, 0x0 },
> > > > > + { 0x13030, 0x0 },
> > > > > + { 0x13130, 0x0 },
> > > > > + { 0x13230, 0x0 },
> > > > > + { 0x13330, 0x0 },
> > > > > + { 0x13430, 0x0 },
> > > > > + { 0x13530, 0x0 },
> > > > > + { 0x13630, 0x0 },
> > > > > + { 0x13730, 0x0 },
> > > > > + { 0x13830, 0x0 },
> > > > > +};
> > > >
> > > > The same as above. Please look into imx6q DDR3 training code.
> > > >
> > > > > +
> > > > > +/* P0 message block paremeter for training firmware */
> > > > > +struct dram_cfg_param lpddr4_fsp0_cfg[] = {
> > > > > + { 0xd0000, 0x0 },
> > > > > + { 0x54000, 0x0 },
> > > > > + { 0x54001, 0x0 },
> > > > > + { 0x54002, 0x0 },
> > > > > + { 0x54003, 0xbb8 },
> > > > > + { 0x54004, 0x2 },
> > > > > + { 0x54005, ((LPDDR4_PHY_RON << 8) |
> > > > > LPDDR4_PHY_RTT) },//PHY Ron/Rtt
> > > > > + { 0x54006, LPDDR4_PHY_VREF_VALUE },
> > > > > + { 0x54007, 0x0 },
> > > > > + { 0x54008, 0x131f },
> > > > > + { 0x54009, 0xc8 },
> > > > > + { 0x5400a, 0x0 },
> > > > > + { 0x5400b, 0x2 },
> > > > > + { 0x5400c, 0x0 },
> > > > > + { 0x5400d, 0x0 },
> > > > > + { 0x5400e, 0x0 },
> > > > > + { 0x5400f, 0x0 },
> > > > > + { 0x54010, 0x0 },
> > > > > + { 0x54011, 0x0 },
> > > > > + { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
> > > > > + { 0x54013, 0x0 },
> > > > > + { 0x54014, 0x0 },
> > > > > + { 0x54015, 0x0 },
> > > > > + { 0x54016, 0x0 },
> > > > > + { 0x54017, 0x0 },
> > > > > + { 0x54018, 0x0 },
> > > > > + { 0x54019, 0x2dd4 },
> > > > > + { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
> > > > > + { 0x5401b, 0x4d66 },
> > > > > + { 0x5401c, 0x4d08 },
> > > > > + { 0x5401d, 0x0 },
> > > > > + { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
> > > > > + { 0x5401f, 0x2dd4 },
> > > > > + { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
> > > > > + { 0x54021, 0x4d66 },
> > > > > + { 0x54022, 0x4d08 },
> > > > > + { 0x54023, 0x0 },
> > > > > + { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
> > > > > + { 0x54025, 0x0 },
> > > > > + { 0x54026, 0x0 },
> > > > > + { 0x54027, 0x0 },
> > > > > + { 0x54028, 0x0 },
> > > > > + { 0x54029, 0x0 },
> > > > > + { 0x5402a, 0x0 },
> > > > > + { 0x5402b, 0x1000 },
> > > > > + { 0x5402c, LPDDR4_CS },
> > > > > + { 0x5402d, 0x0 },
> > > > > + { 0x5402e, 0x0 },
> > > > > + { 0x5402f, 0x0 },
> > > > > + { 0x54030, 0x0 },
> > > > > + { 0x54031, 0x0 },
> > > > > + { 0x54032, 0xd400 },
> > > > > + { 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
> > > > > + { 0x54034, 0x6600 },
> > > > > + { 0x54035, 0x84d },
> > > > > + { 0x54036, 0x4d },
> > > > > + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
> > > > > + { 0x54038, 0xd400 },
> > > > > + { 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
> > > > > + { 0x5403a, 0x6600 },
> > > > > + { 0x5403b, 0x84d },
> > > > > + { 0x5403c, 0x4d },
> > > > > + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
> > > > > + { 0x5403e, 0x0 },
> > > > > + { 0x5403f, 0x0 },
> > > > > + { 0x54040, 0x0 },
> > > > > + { 0x54041, 0x0 },
> > > > > + { 0x54042, 0x0 },
> > > > > + { 0x54043, 0x0 },
> > > > > + { 0x54044, 0x0 },
> > > > > + { 0xd0000, 0x1 },
> > > > > +};
> > > > > +
> > > > > +/* P1 message block paremeter for training firmware */
> > > > > +struct dram_cfg_param lpddr4_fsp1_cfg[] = {
> > > > > + { 0xd0000, 0x0 },
> > > > > + { 0x54000, 0x0 },
> > > > > + { 0x54001, 0x0 },
> > > > > + { 0x54002, 0x101 },
> > > > > + { 0x54003, 0x190 },
> > > > > + { 0x54004, 0x2 },
> > > > > + { 0x54005, ((LPDDR4_PHY_RON << 8) |
> > > > > LPDDR4_PHY_RTT) },//PHY Ron/Rtt
> > > > > + { 0x54006, LPDDR4_PHY_VREF_VALUE },
> > > > > + { 0x54007, 0x0 },
> > > > > + { 0x54008, 0x121f },
> > > > > + { 0x54009, 0xc8 },
> > > > > + { 0x5400a, 0x0 },
> > > > > + { 0x5400b, 0x2 },
> > > > > + { 0x5400c, 0x0 },
> > > > > + { 0x5400d, 0x0 },
> > > > > + { 0x5400e, 0x0 },
> > > > > + { 0x5400f, 0x0 },
> > > > > + { 0x54010, 0x0 },
> > > > > + { 0x54011, 0x0 },
> > > > > + { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
> > > > > + { 0x54013, 0x0 },
> > > > > + { 0x54014, 0x0 },
> > > > > + { 0x54015, 0x0 },
> > > > > + { 0x54016, 0x0 },
> > > > > + { 0x54017, 0x0 },
> > > > > + { 0x54018, 0x0 },
> > > > > + { 0x54019, 0x84 },
> > > > > + { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
> > > > > + { 0x5401b, 0x4d66 },
> > > > > + { 0x5401c, 0x4d08 },
> > > > > + { 0x5401d, 0x0 },
> > > > > + { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
> > > > > + { 0x5401f, 0x84 },
> > > > > + { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
> > > > > + { 0x54021, 0x4d66 },
> > > > > + { 0x54022, 0x4d08 },
> > > > > + { 0x54023, 0x0 },
> > > > > + { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
> > > > > + { 0x54025, 0x0 },
> > > > > + { 0x54026, 0x0 },
> > > > > + { 0x54027, 0x0 },
> > > > > + { 0x54028, 0x0 },
> > > > > + { 0x54029, 0x0 },
> > > > > + { 0x5402a, 0x0 },
> > > > > + { 0x5402b, 0x1000 },
> > > > > + { 0x5402c, LPDDR4_CS },
> > > > > + { 0x5402d, 0x0 },
> > > > > + { 0x5402e, 0x0 },
> > > > > + { 0x5402f, 0x0 },
> > > > > + { 0x54030, 0x0 },
> > > > > + { 0x54031, 0x0 },
> > > > > + { 0x54032, 0x8400 },
> > > > > + { 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
> > > > > + { 0x54034, 0x6600 },
> > > > > + { 0x54035, 0x84d },
> > > > > + { 0x54036, 0x4d },
> > > > > + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
> > > > > + { 0x54038, 0x8400 },
> > > > > + { 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
> > > > > + { 0x5403a, 0x6600 },
> > > > > + { 0x5403b, 0x84d },
> > > > > + { 0x5403c, 0x4d },
> > > > > + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
> > > > > + { 0x5403e, 0x0 },
> > > > > + { 0x5403f, 0x0 },
> > > > > + { 0x54040, 0x0 },
> > > > > + { 0x54041, 0x0 },
> > > > > + { 0x54042, 0x0 },
> > > > > + { 0x54043, 0x0 },
> > > > > + { 0x54044, 0x0 },
> > > > > + { 0xd0000, 0x1 },
> > > > > +};
> > > > > +
> > > > > +/* P1 message block paremeter for training firmware */
> > > > > +struct dram_cfg_param lpddr4_fsp2_cfg[] = {
> > > > > + { 0xd0000, 0x0 },
> > > > > + { 0x54000, 0x0 },
> > > > > + { 0x54001, 0x0 },
> > > > > + { 0x54002, 0x102 },
> > > > > + { 0x54003, 0x64 },
> > > > > + { 0x54004, 0x2 },
> > > > > + { 0x54005, ((LPDDR4_PHY_RON << 8) |
> > > > > LPDDR4_PHY_RTT) },//PHY Ron/Rtt
> > > > > + { 0x54006, LPDDR4_PHY_VREF_VALUE },
> > > > > + { 0x54007, 0x0 },
> > > > > + { 0x54008, 0x121f },
> > > > > + { 0x54009, 0xc8 },
> > > > > + { 0x5400a, 0x0 },
> > > > > + { 0x5400b, 0x2 },
> > > > > + { 0x5400c, 0x0 },
> > > > > + { 0x5400d, 0x0 },
> > > > > + { 0x5400e, 0x0 },
> > > > > + { 0x5400f, 0x0 },
> > > > > + { 0x54010, 0x0 },
> > > > > + { 0x54011, 0x0 },
> > > > > + { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
> > > > > + { 0x54013, 0x0 },
> > > > > + { 0x54014, 0x0 },
> > > > > + { 0x54015, 0x0 },
> > > > > + { 0x54016, 0x0 },
> > > > > + { 0x54017, 0x0 },
> > > > > + { 0x54018, 0x0 },
> > > > > + { 0x54019, 0x84 },
> > > > > + { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
> > > > > + { 0x5401b, 0x4d66 },
> > > > > + { 0x5401c, 0x4d08 },
> > > > > + { 0x5401d, 0x0 },
> > > > > + { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
> > > > > + { 0x5401f, 0x84 },
> > > > > + { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
> > > > > + { 0x54021, 0x4d66 },
> > > > > + { 0x54022, 0x4d08 },
> > > > > + { 0x54023, 0x0 },
> > > > > + { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
> > > > > + { 0x54025, 0x0 },
> > > > > + { 0x54026, 0x0 },
> > > > > + { 0x54027, 0x0 },
> > > > > + { 0x54028, 0x0 },
> > > > > + { 0x54029, 0x0 },
> > > > > + { 0x5402a, 0x0 },
> > > > > + { 0x5402b, 0x1000 },
> > > > > + { 0x5402c, LPDDR4_CS },
> > > > > + { 0x5402d, 0x0 },
> > > > > + { 0x5402e, 0x0 },
> > > > > + { 0x5402f, 0x0 },
> > > > > + { 0x54030, 0x0 },
> > > > > + { 0x54031, 0x0 },
> > > > > + { 0x54032, 0x8400 },
> > > > > + { 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
> > > > > + { 0x54034, 0x6600 },
> > > > > + { 0x54035, 0x84d },
> > > > > + { 0x54036, 0x4d },
> > > > > + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
> > > > > + { 0x54038, 0x8400 },
> > > > > + { 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
> > > > > + { 0x5403a, 0x6600 },
> > > > > + { 0x5403b, 0x84d },
> > > > > + { 0x5403c, 0x4d },
> > > > > + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
> > > > > + { 0x5403e, 0x0 },
> > > > > + { 0x5403f, 0x0 },
> > > > > + { 0x54040, 0x0 },
> > > > > + { 0x54041, 0x0 },
> > > > > + { 0x54042, 0x0 },
> > > > > + { 0x54043, 0x0 },
> > > > > + { 0x54044, 0x0 },
> > > > > + { 0xd0000, 0x1 },
> > > > > +};
> > > > > +
> > > > > +/* P0 2D message block paremeter for training firmware */
> > > > > +struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
> > > > > + { 0xd0000, 0x0 },
> > > > > + { 0x54000, 0x0 },
> > > > > + { 0x54001, 0x0 },
> > > > > + { 0x54002, 0x0 },
> > > > > + { 0x54003, 0xbb8 },
> > > > > + { 0x54004, 0x2 },
> > > > > + { 0x54005, ((LPDDR4_PHY_RON << 8) |
> > > > > LPDDR4_PHY_RTT) },//PHY Ron/Rtt
> > > > > + { 0x54006, LPDDR4_PHY_VREF_VALUE },
> > > > > + { 0x54007, 0x0 },
> > > > > + { 0x54008, 0x61 },
> > > > > + { 0x54009, 0xc8 },
> > > > > + { 0x5400a, 0x0 },
> > > > > + { 0x5400b, 0x2 },
> > > > > + { 0x5400c, 0x0 },
> > > > > + { 0x5400d, 0x0 },
> > > > > + { 0x5400e, 0x0 },
> > > > > + { 0x5400f, 0x100 },
> > > > > + { 0x54010, 0x1f7f },
> > > > > + { 0x54011, 0x0 },
> > > > > + { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
> > > > > + { 0x54013, 0x0 },
> > > > > + { 0x54014, 0x0 },
> > > > > + { 0x54015, 0x0 },
> > > > > + { 0x54016, 0x0 },
> > > > > + { 0x54017, 0x0 },
> > > > > + { 0x54018, 0x0 },
> > > > > + { 0x54019, 0x2dd4 },
> > > > > + { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
> > > > > + { 0x5401b, 0x4d66 },
> > > > > + { 0x5401c, 0x4d08 },
> > > > > + { 0x5401d, 0x0 },
> > > > > + { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
> > > > > + { 0x5401f, 0x2dd4 },
> > > > > + { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
> > > > > + { 0x54021, 0x4d66 },
> > > > > + { 0x54022, 0x4d08 },
> > > > > + { 0x54023, 0x0 },
> > > > > + { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
> > > > > + { 0x54025, 0x0 },
> > > > > + { 0x54026, 0x0 },
> > > > > + { 0x54027, 0x0 },
> > > > > + { 0x54028, 0x0 },
> > > > > + { 0x54029, 0x0 },
> > > > > + { 0x5402a, 0x0 },
> > > > > + { 0x5402b, 0x1000 },
> > > > > + { 0x5402c, LPDDR4_CS },
> > > > > + { 0x5402d, 0x0 },
> > > > > + { 0x5402e, 0x0 },
> > > > > + { 0x5402f, 0x0 },
> > > > > + { 0x54030, 0x0 },
> > > > > + { 0x54031, 0x0 },
> > > > > + { 0x54032, 0xd400 },
> > > > > + { 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
> > > > > + { 0x54034, 0x6600 },
> > > > > + { 0x54035, 0x84d },
> > > > > + { 0x54036, 0x4d },
> > > > > + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
> > > > > + { 0x54038, 0xd400 },
> > > > > + { 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
> > > > > + { 0x5403a, 0x6600 },
> > > > > + { 0x5403b, 0x84d },
> > > > > + { 0x5403c, 0x4d },
> > > > > + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
> > > > > + { 0x5403e, 0x0 },
> > > > > + { 0x5403f, 0x0 },
> > > > > + { 0x54040, 0x0 },
> > > > > + { 0x54041, 0x0 },
> > > > > + { 0x54042, 0x0 },
> > > > > + { 0x54043, 0x0 },
> > > > > + { 0x54044, 0x0 },
> > > > > + { 0xd0000, 0x1 },
> > > > > +};
> > > > > +
> > > > > +/* DRAM PHY init engine image */
> > > > > +struct dram_cfg_param lpddr4_phy_pie[] = {
> > > > > + { 0xd0000, 0x0 },
> > > > > + { 0x90000, 0x10 },
> > > > > + { 0x90001, 0x400 },
> > > > > + { 0x90002, 0x10e },
> > > > > + { 0x90003, 0x0 },
> > > > > + { 0x90004, 0x0 },
> > > > > + { 0x90005, 0x8 },
> > > > > + { 0x90029, 0xb },
> > > > > + { 0x9002a, 0x480 },
> > > > > + { 0x9002b, 0x109 },
> > > > > + { 0x9002c, 0x8 },
> > > > > + { 0x9002d, 0x448 },
> > > > > + { 0x9002e, 0x139 },
> > > > > + { 0x9002f, 0x8 },
> > > > > + { 0x90030, 0x478 },
> > > > > + { 0x90031, 0x109 },
> > > > > + { 0x90032, 0x0 },
> > > > > + { 0x90033, 0xe8 },
> > > > > + { 0x90034, 0x109 },
> > > > > + { 0x90035, 0x2 },
> > > > > + { 0x90036, 0x10 },
> > > > > + { 0x90037, 0x139 },
> > > > > + { 0x90038, 0xf },
> > > > > + { 0x90039, 0x7c0 },
> > > > > + { 0x9003a, 0x139 },
> > > > > + { 0x9003b, 0x44 },
> > > > > + { 0x9003c, 0x630 },
> > > > > + { 0x9003d, 0x159 },
> > > > > + { 0x9003e, 0x14f },
> > > > > + { 0x9003f, 0x630 },
> > > > > + { 0x90040, 0x159 },
> > > > > + { 0x90041, 0x47 },
> > > > > + { 0x90042, 0x630 },
> > > > > + { 0x90043, 0x149 },
> > > > > + { 0x90044, 0x4f },
> > > > > + { 0x90045, 0x630 },
> > > > > + { 0x90046, 0x179 },
> > > > > + { 0x90047, 0x8 },
> > > > > + { 0x90048, 0xe0 },
> > > > > + { 0x90049, 0x109 },
> > > > > + { 0x9004a, 0x0 },
> > > > > + { 0x9004b, 0x7c8 },
> > > > > + { 0x9004c, 0x109 },
> > > > > + { 0x9004d, 0x0 },
> > > > > + { 0x9004e, 0x1 },
> > > > > + { 0x9004f, 0x8 },
> > > > > + { 0x90050, 0x0 },
> > > > > + { 0x90051, 0x45a },
> > > > > + { 0x90052, 0x9 },
> > > > > + { 0x90053, 0x0 },
> > > > > + { 0x90054, 0x448 },
> > > > > + { 0x90055, 0x109 },
> > > > > + { 0x90056, 0x40 },
> > > > > + { 0x90057, 0x630 },
> > > > > + { 0x90058, 0x179 },
> > > > > + { 0x90059, 0x1 },
> > > > > + { 0x9005a, 0x618 },
> > > > > + { 0x9005b, 0x109 },
> > > > > + { 0x9005c, 0x40c0 },
> > > > > + { 0x9005d, 0x630 },
> > > > > + { 0x9005e, 0x149 },
> > > > > + { 0x9005f, 0x8 },
> > > > > + { 0x90060, 0x4 },
> > > > > + { 0x90061, 0x48 },
> > > > > + { 0x90062, 0x4040 },
> > > > > + { 0x90063, 0x630 },
> > > > > + { 0x90064, 0x149 },
> > > > > + { 0x90065, 0x0 },
> > > > > + { 0x90066, 0x4 },
> > > > > + { 0x90067, 0x48 },
> > > > > + { 0x90068, 0x40 },
> > > > > + { 0x90069, 0x630 },
> > > > > + { 0x9006a, 0x149 },
> > > > > + { 0x9006b, 0x10 },
> > > > > + { 0x9006c, 0x4 },
> > > > > + { 0x9006d, 0x18 },
> > > > > + { 0x9006e, 0x0 },
> > > > > + { 0x9006f, 0x4 },
> > > > > + { 0x90070, 0x78 },
> > > > > + { 0x90071, 0x549 },
> > > > > + { 0x90072, 0x630 },
> > > > > + { 0x90073, 0x159 },
> > > > > + { 0x90074, 0xd49 },
> > > > > + { 0x90075, 0x630 },
> > > > > + { 0x90076, 0x159 },
> > > > > + { 0x90077, 0x94a },
> > > > > + { 0x90078, 0x630 },
> > > > > + { 0x90079, 0x159 },
> > > > > + { 0x9007a, 0x441 },
> > > > > + { 0x9007b, 0x630 },
> > > > > + { 0x9007c, 0x149 },
> > > > > + { 0x9007d, 0x42 },
> > > > > + { 0x9007e, 0x630 },
> > > > > + { 0x9007f, 0x149 },
> > > > > + { 0x90080, 0x1 },
> > > > > + { 0x90081, 0x630 },
> > > > > + { 0x90082, 0x149 },
> > > > > + { 0x90083, 0x0 },
> > > > > + { 0x90084, 0xe0 },
> > > > > + { 0x90085, 0x109 },
> > > > > + { 0x90086, 0xa },
> > > > > + { 0x90087, 0x10 },
> > > > > + { 0x90088, 0x109 },
> > > > > + { 0x90089, 0x9 },
> > > > > + { 0x9008a, 0x3c0 },
> > > > > + { 0x9008b, 0x149 },
> > > > > + { 0x9008c, 0x9 },
> > > > > + { 0x9008d, 0x3c0 },
> > > > > + { 0x9008e, 0x159 },
> > > > > + { 0x9008f, 0x18 },
> > > > > + { 0x90090, 0x10 },
> > > > > + { 0x90091, 0x109 },
> > > > > + { 0x90092, 0x0 },
> > > > > + { 0x90093, 0x3c0 },
> > > > > + { 0x90094, 0x109 },
> > > > > + { 0x90095, 0x18 },
> > > > > + { 0x90096, 0x4 },
> > > > > + { 0x90097, 0x48 },
> > > > > + { 0x90098, 0x18 },
> > > > > + { 0x90099, 0x4 },
> > > > > + { 0x9009a, 0x58 },
> > > > > + { 0x9009b, 0xa },
> > > > > + { 0x9009c, 0x10 },
> > > > > + { 0x9009d, 0x109 },
> > > > > + { 0x9009e, 0x2 },
> > > > > + { 0x9009f, 0x10 },
> > > > > + { 0x900a0, 0x109 },
> > > > > + { 0x900a1, 0x5 },
> > > > > + { 0x900a2, 0x7c0 },
> > > > > + { 0x900a3, 0x109 },
> > > > > + { 0x900a4, 0x10 },
> > > > > + { 0x900a5, 0x10 },
> > > > > + { 0x900a6, 0x109 },
> > > > > + { 0x40000, 0x811 },
> > > > > + { 0x40020, 0x880 },
> > > > > + { 0x40040, 0x0 },
> > > > > + { 0x40060, 0x0 },
> > > > > + { 0x40001, 0x4008 },
> > > > > + { 0x40021, 0x83 },
> > > > > + { 0x40041, 0x4f },
> > > > > + { 0x40061, 0x0 },
> > > > > + { 0x40002, 0x4040 },
> > > > > + { 0x40022, 0x83 },
> > > > > + { 0x40042, 0x51 },
> > > > > + { 0x40062, 0x0 },
> > > > > + { 0x40003, 0x811 },
> > > > > + { 0x40023, 0x880 },
> > > > > + { 0x40043, 0x0 },
> > > > > + { 0x40063, 0x0 },
> > > > > + { 0x40004, 0x720 },
> > > > > + { 0x40024, 0xf },
> > > > > + { 0x40044, 0x1740 },
> > > > > + { 0x40064, 0x0 },
> > > > > + { 0x40005, 0x16 },
> > > > > + { 0x40025, 0x83 },
> > > > > + { 0x40045, 0x4b },
> > > > > + { 0x40065, 0x0 },
> > > > > + { 0x40006, 0x716 },
> > > > > + { 0x40026, 0xf },
> > > > > + { 0x40046, 0x2001 },
> > > > > + { 0x40066, 0x0 },
> > > > > + { 0x40007, 0x716 },
> > > > > + { 0x40027, 0xf },
> > > > > + { 0x40047, 0x2800 },
> > > > > + { 0x40067, 0x0 },
> > > > > + { 0x40008, 0x716 },
> > > > > + { 0x40028, 0xf },
> > > > > + { 0x40048, 0xf00 },
> > > > > + { 0x40068, 0x0 },
> > > > > + { 0x40009, 0x720 },
> > > > > + { 0x40029, 0xf },
> > > > > + { 0x40049, 0x1400 },
> > > > > + { 0x40069, 0x0 },
> > > > > + { 0x4000a, 0xe08 },
> > > > > + { 0x4002a, 0xc15 },
> > > > > + { 0x4004a, 0x0 },
> > > > > + { 0x4006a, 0x0 },
> > > > > + { 0x4000b, 0x623 },
> > > > > + { 0x4002b, 0x15 },
> > > > > + { 0x4004b, 0x0 },
> > > > > + { 0x4006b, 0x0 },
> > > > > + { 0x4000c, 0x4028 },
> > > > > + { 0x4002c, 0x80 },
> > > > > + { 0x4004c, 0x0 },
> > > > > + { 0x4006c, 0x0 },
> > > > > + { 0x4000d, 0xe08 },
> > > > > + { 0x4002d, 0xc1a },
> > > > > + { 0x4004d, 0x0 },
> > > > > + { 0x4006d, 0x0 },
> > > > > + { 0x4000e, 0x623 },
> > > > > + { 0x4002e, 0x1a },
> > > > > + { 0x4004e, 0x0 },
> > > > > + { 0x4006e, 0x0 },
> > > > > + { 0x4000f, 0x4040 },
> > > > > + { 0x4002f, 0x80 },
> > > > > + { 0x4004f, 0x0 },
> > > > > + { 0x4006f, 0x0 },
> > > > > + { 0x40010, 0x2604 },
> > > > > + { 0x40030, 0x15 },
> > > > > + { 0x40050, 0x0 },
> > > > > + { 0x40070, 0x0 },
> > > > > + { 0x40011, 0x708 },
> > > > > + { 0x40031, 0x5 },
> > > > > + { 0x40051, 0x0 },
> > > > > + { 0x40071, 0x2002 },
> > > > > + { 0x40012, 0x8 },
> > > > > + { 0x40032, 0x80 },
> > > > > + { 0x40052, 0x0 },
> > > > > + { 0x40072, 0x0 },
> > > > > + { 0x40013, 0x2604 },
> > > > > + { 0x40033, 0x1a },
> > > > > + { 0x40053, 0x0 },
> > > > > + { 0x40073, 0x0 },
> > > > > + { 0x40014, 0x708 },
> > > > > + { 0x40034, 0xa },
> > > > > + { 0x40054, 0x0 },
> > > > > + { 0x40074, 0x2002 },
> > > > > + { 0x40015, 0x4040 },
> > > > > + { 0x40035, 0x80 },
> > > > > + { 0x40055, 0x0 },
> > > > > + { 0x40075, 0x0 },
> > > > > + { 0x40016, 0x60a },
> > > > > + { 0x40036, 0x15 },
> > > > > + { 0x40056, 0x1200 },
> > > > > + { 0x40076, 0x0 },
> > > > > + { 0x40017, 0x61a },
> > > > > + { 0x40037, 0x15 },
> > > > > + { 0x40057, 0x1300 },
> > > > > + { 0x40077, 0x0 },
> > > > > + { 0x40018, 0x60a },
> > > > > + { 0x40038, 0x1a },
> > > > > + { 0x40058, 0x1200 },
> > > > > + { 0x40078, 0x0 },
> > > > > + { 0x40019, 0x642 },
> > > > > + { 0x40039, 0x1a },
> > > > > + { 0x40059, 0x1300 },
> > > > > + { 0x40079, 0x0 },
> > > > > + { 0x4001a, 0x4808 },
> > > > > + { 0x4003a, 0x880 },
> > > > > + { 0x4005a, 0x0 },
> > > > > + { 0x4007a, 0x0 },
> > > > > + { 0x900a7, 0x0 },
> > > > > + { 0x900a8, 0x790 },
> > > > > + { 0x900a9, 0x11a },
> > > > > + { 0x900aa, 0x8 },
> > > > > + { 0x900ab, 0x7aa },
> > > > > + { 0x900ac, 0x2a },
> > > > > + { 0x900ad, 0x10 },
> > > > > + { 0x900ae, 0x7b2 },
> > > > > + { 0x900af, 0x2a },
> > > > > + { 0x900b0, 0x0 },
> > > > > + { 0x900b1, 0x7c8 },
> > > > > + { 0x900b2, 0x109 },
> > > > > + { 0x900b3, 0x10 },
> > > > > + { 0x900b4, 0x2a8 },
> > > > > + { 0x900b5, 0x129 },
> > > > > + { 0x900b6, 0x8 },
> > > > > + { 0x900b7, 0x370 },
> > > > > + { 0x900b8, 0x129 },
> > > > > + { 0x900b9, 0xa },
> > > > > + { 0x900ba, 0x3c8 },
> > > > > + { 0x900bb, 0x1a9 },
> > > > > + { 0x900bc, 0xc },
> > > > > + { 0x900bd, 0x408 },
> > > > > + { 0x900be, 0x199 },
> > > > > + { 0x900bf, 0x14 },
> > > > > + { 0x900c0, 0x790 },
> > > > > + { 0x900c1, 0x11a },
> > > > > + { 0x900c2, 0x8 },
> > > > > + { 0x900c3, 0x4 },
> > > > > + { 0x900c4, 0x18 },
> > > > > + { 0x900c5, 0xe },
> > > > > + { 0x900c6, 0x408 },
> > > > > + { 0x900c7, 0x199 },
> > > > > + { 0x900c8, 0x8 },
> > > > > + { 0x900c9, 0x8568 },
> > > > > + { 0x900ca, 0x108 },
> > > > > + { 0x900cb, 0x18 },
> > > > > + { 0x900cc, 0x790 },
> > > > > + { 0x900cd, 0x16a },
> > > > > + { 0x900ce, 0x8 },
> > > > > + { 0x900cf, 0x1d8 },
> > > > > + { 0x900d0, 0x169 },
> > > > > + { 0x900d1, 0x10 },
> > > > > + { 0x900d2, 0x8558 },
> > > > > + { 0x900d3, 0x168 },
> > > > > + { 0x900d4, 0x70 },
> > > > > + { 0x900d5, 0x788 },
> > > > > + { 0x900d6, 0x16a },
> > > > > + { 0x900d7, 0x1ff8 },
> > > > > + { 0x900d8, 0x85a8 },
> > > > > + { 0x900d9, 0x1e8 },
> > > > > + { 0x900da, 0x50 },
> > > > > + { 0x900db, 0x798 },
> > > > > + { 0x900dc, 0x16a },
> > > > > + { 0x900dd, 0x60 },
> > > > > + { 0x900de, 0x7a0 },
> > > > > + { 0x900df, 0x16a },
> > > > > + { 0x900e0, 0x8 },
> > > > > + { 0x900e1, 0x8310 },
> > > > > + { 0x900e2, 0x168 },
> > > > > + { 0x900e3, 0x8 },
> > > > > + { 0x900e4, 0xa310 },
> > > > > + { 0x900e5, 0x168 },
> > > > > + { 0x900e6, 0xa },
> > > > > + { 0x900e7, 0x408 },
> > > > > + { 0x900e8, 0x169 },
> > > > > + { 0x900e9, 0x6e },
> > > > > + { 0x900ea, 0x0 },
> > > > > + { 0x900eb, 0x68 },
> > > > > + { 0x900ec, 0x0 },
> > > > > + { 0x900ed, 0x408 },
> > > > > + { 0x900ee, 0x169 },
> > > > > + { 0x900ef, 0x0 },
> > > > > + { 0x900f0, 0x8310 },
> > > > > + { 0x900f1, 0x168 },
> > > > > + { 0x900f2, 0x0 },
> > > > > + { 0x900f3, 0xa310 },
> > > > > + { 0x900f4, 0x168 },
> > > > > + { 0x900f5, 0x1ff8 },
> > > > > + { 0x900f6, 0x85a8 },
> > > > > + { 0x900f7, 0x1e8 },
> > > > > + { 0x900f8, 0x68 },
> > > > > + { 0x900f9, 0x798 },
> > > > > + { 0x900fa, 0x16a },
> > > > > + { 0x900fb, 0x78 },
> > > > > + { 0x900fc, 0x7a0 },
> > > > > + { 0x900fd, 0x16a },
> > > > > + { 0x900fe, 0x68 },
> > > > > + { 0x900ff, 0x790 },
> > > > > + { 0x90100, 0x16a },
> > > > > + { 0x90101, 0x8 },
> > > > > + { 0x90102, 0x8b10 },
> > > > > + { 0x90103, 0x168 },
> > > > > + { 0x90104, 0x8 },
> > > > > + { 0x90105, 0xab10 },
> > > > > + { 0x90106, 0x168 },
> > > > > + { 0x90107, 0xa },
> > > > > + { 0x90108, 0x408 },
> > > > > + { 0x90109, 0x169 },
> > > > > + { 0x9010a, 0x58 },
> > > > > + { 0x9010b, 0x0 },
> > > > > + { 0x9010c, 0x68 },
> > > > > + { 0x9010d, 0x0 },
> > > > > + { 0x9010e, 0x408 },
> > > > > + { 0x9010f, 0x169 },
> > > > > + { 0x90110, 0x0 },
> > > > > + { 0x90111, 0x8b10 },
> > > > > + { 0x90112, 0x168 },
> > > > > + { 0x90113, 0x0 },
> > > > > + { 0x90114, 0xab10 },
> > > > > + { 0x90115, 0x168 },
> > > > > + { 0x90116, 0x0 },
> > > > > + { 0x90117, 0x1d8 },
> > > > > + { 0x90118, 0x169 },
> > > > > + { 0x90119, 0x80 },
> > > > > + { 0x9011a, 0x790 },
> > > > > + { 0x9011b, 0x16a },
> > > > > + { 0x9011c, 0x18 },
> > > > > + { 0x9011d, 0x7aa },
> > > > > + { 0x9011e, 0x6a },
> > > > > + { 0x9011f, 0xa },
> > > > > + { 0x90120, 0x0 },
> > > > > + { 0x90121, 0x1e9 },
> > > > > + { 0x90122, 0x8 },
> > > > > + { 0x90123, 0x8080 },
> > > > > + { 0x90124, 0x108 },
> > > > > + { 0x90125, 0xf },
> > > > > + { 0x90126, 0x408 },
> > > > > + { 0x90127, 0x169 },
> > > > > + { 0x90128, 0xc },
> > > > > + { 0x90129, 0x0 },
> > > > > + { 0x9012a, 0x68 },
> > > > > + { 0x9012b, 0x9 },
> > > > > + { 0x9012c, 0x0 },
> > > > > + { 0x9012d, 0x1a9 },
> > > > > + { 0x9012e, 0x0 },
> > > > > + { 0x9012f, 0x408 },
> > > > > + { 0x90130, 0x169 },
> > > > > + { 0x90131, 0x0 },
> > > > > + { 0x90132, 0x8080 },
> > > > > + { 0x90133, 0x108 },
> > > > > + { 0x90134, 0x8 },
> > > > > + { 0x90135, 0x7aa },
> > > > > + { 0x90136, 0x6a },
> > > > > + { 0x90137, 0x0 },
> > > > > + { 0x90138, 0x8568 },
> > > > > + { 0x90139, 0x108 },
> > > > > + { 0x9013a, 0xb7 },
> > > > > + { 0x9013b, 0x790 },
> > > > > + { 0x9013c, 0x16a },
> > > > > + { 0x9013d, 0x1f },
> > > > > + { 0x9013e, 0x0 },
> > > > > + { 0x9013f, 0x68 },
> > > > > + { 0x90140, 0x8 },
> > > > > + { 0x90141, 0x8558 },
> > > > > + { 0x90142, 0x168 },
> > > > > + { 0x90143, 0xf },
> > > > > + { 0x90144, 0x408 },
> > > > > + { 0x90145, 0x169 },
> > > > > + { 0x90146, 0xc },
> > > > > + { 0x90147, 0x0 },
> > > > > + { 0x90148, 0x68 },
> > > > > + { 0x90149, 0x0 },
> > > > > + { 0x9014a, 0x408 },
> > > > > + { 0x9014b, 0x169 },
> > > > > + { 0x9014c, 0x0 },
> > > > > + { 0x9014d, 0x8558 },
> > > > > + { 0x9014e, 0x168 },
> > > > > + { 0x9014f, 0x8 },
> > > > > + { 0x90150, 0x3c8 },
> > > > > + { 0x90151, 0x1a9 },
> > > > > + { 0x90152, 0x3 },
> > > > > + { 0x90153, 0x370 },
> > > > > + { 0x90154, 0x129 },
> > > > > + { 0x90155, 0x20 },
> > > > > + { 0x90156, 0x2aa },
> > > > > + { 0x90157, 0x9 },
> > > > > + { 0x90158, 0x0 },
> > > > > + { 0x90159, 0x400 },
> > > > > + { 0x9015a, 0x10e },
> > > > > + { 0x9015b, 0x8 },
> > > > > + { 0x9015c, 0xe8 },
> > > > > + { 0x9015d, 0x109 },
> > > > > + { 0x9015e, 0x0 },
> > > > > + { 0x9015f, 0x8140 },
> > > > > + { 0x90160, 0x10c },
> > > > > + { 0x90161, 0x10 },
> > > > > + { 0x90162, 0x8138 },
> > > > > + { 0x90163, 0x10c },
> > > > > + { 0x90164, 0x8 },
> > > > > + { 0x90165, 0x7c8 },
> > > > > + { 0x90166, 0x101 },
> > > > > + { 0x90167, 0x8 },
> > > > > + { 0x90168, 0x0 },
> > > > > + { 0x90169, 0x8 },
> > > > > + { 0x9016a, 0x8 },
> > > > > + { 0x9016b, 0x448 },
> > > > > + { 0x9016c, 0x109 },
> > > > > + { 0x9016d, 0xf },
> > > > > + { 0x9016e, 0x7c0 },
> > > > > + { 0x9016f, 0x109 },
> > > > > + { 0x90170, 0x0 },
> > > > > + { 0x90171, 0xe8 },
> > > > > + { 0x90172, 0x109 },
> > > > > + { 0x90173, 0x47 },
> > > > > + { 0x90174, 0x630 },
> > > > > + { 0x90175, 0x109 },
> > > > > + { 0x90176, 0x8 },
> > > > > + { 0x90177, 0x618 },
> > > > > + { 0x90178, 0x109 },
> > > > > + { 0x90179, 0x8 },
> > > > > + { 0x9017a, 0xe0 },
> > > > > + { 0x9017b, 0x109 },
> > > > > + { 0x9017c, 0x0 },
> > > > > + { 0x9017d, 0x7c8 },
> > > > > + { 0x9017e, 0x109 },
> > > > > + { 0x9017f, 0x8 },
> > > > > + { 0x90180, 0x8140 },
> > > > > + { 0x90181, 0x10c },
> > > > > + { 0x90182, 0x0 },
> > > > > + { 0x90183, 0x1 },
> > > > > + { 0x90184, 0x8 },
> > > > > + { 0x90185, 0x8 },
> > > > > + { 0x90186, 0x4 },
> > > > > + { 0x90187, 0x8 },
> > > > > + { 0x90188, 0x8 },
> > > > > + { 0x90189, 0x7c8 },
> > > > > + { 0x9018a, 0x101 },
> > > > > + { 0x90006, 0x0 },
> > > > > + { 0x90007, 0x0 },
> > > > > + { 0x90008, 0x8 },
> > > > > + { 0x90009, 0x0 },
> > > > > + { 0x9000a, 0x0 },
> > > > > + { 0x9000b, 0x0 },
> > > > > + { 0xd00e7, 0x400 },
> > > > > + { 0x90017, 0x0 },
> > > > > + { 0x9001f, 0x2a },
> > > > > + { 0x90026, 0x6a },
> > > > > + { 0x400d0, 0x0 },
> > > > > + { 0x400d1, 0x101 },
> > > > > + { 0x400d2, 0x105 },
> > > > > + { 0x400d3, 0x107 },
> > > > > + { 0x400d4, 0x10f },
> > > > > + { 0x400d5, 0x202 },
> > > > > + { 0x400d6, 0x20a },
> > > > > + { 0x400d7, 0x20b },
> > > > > + { 0x2003a, 0x2 },
> > > > > + { 0x2000b, 0x5d },
> > > > > + { 0x2000c, 0xbb },
> > > > > + { 0x2000d, 0x753 },
> > > > > + { 0x2000e, 0x2c },
> > > > > + { 0x12000b, 0xc },
> > > > > + { 0x12000c, 0x19 },
> > > > > + { 0x12000d, 0xfa },
> > > > > + { 0x12000e, 0x10 },
> > > > > + { 0x22000b, 0x3 },
> > > > > + { 0x22000c, 0x6 },
> > > > > + { 0x22000d, 0x3e },
> > > > > + { 0x22000e, 0x10 },
> > > > > + { 0x9000c, 0x0 },
> > > > > + { 0x9000d, 0x173 },
> > > > > + { 0x9000e, 0x60 },
> > > > > + { 0x9000f, 0x6110 },
> > > > > + { 0x90010, 0x2152 },
> > > > > + { 0x90011, 0xdfbd },
> > > > > + { 0x90012, 0x60 },
> > > > > + { 0x90013, 0x6152 },
> > > > > + { 0x20010, 0x5a },
> > > > > + { 0x20011, 0x3 },
> > > > > + { 0x40080, 0xe0 },
> > > > > + { 0x40081, 0x12 },
> > > > > + { 0x40082, 0xe0 },
> > > > > + { 0x40083, 0x12 },
> > > > > + { 0x40084, 0xe0 },
> > > > > + { 0x40085, 0x12 },
> > > > > + { 0x140080, 0xe0 },
> > > > > + { 0x140081, 0x12 },
> > > > > + { 0x140082, 0xe0 },
> > > > > + { 0x140083, 0x12 },
> > > > > + { 0x140084, 0xe0 },
> > > > > + { 0x140085, 0x12 },
> > > > > + { 0x240080, 0xe0 },
> > > > > + { 0x240081, 0x12 },
> > > > > + { 0x240082, 0xe0 },
> > > > > + { 0x240083, 0x12 },
> > > > > + { 0x240084, 0xe0 },
> > > > > + { 0x240085, 0x12 },
> > > > > + { 0x400fd, 0xf },
> > > > > + { 0x10011, 0x1 },
> > > > > + { 0x10012, 0x1 },
> > > > > + { 0x10013, 0x180 },
> > > > > + { 0x10018, 0x1 },
> > > > > + { 0x10002, 0x6209 },
> > > > > + { 0x100b2, 0x1 },
> > > > > + { 0x101b4, 0x1 },
> > > > > + { 0x102b4, 0x1 },
> > > > > + { 0x103b4, 0x1 },
> > > > > + { 0x104b4, 0x1 },
> > > > > + { 0x105b4, 0x1 },
> > > > > + { 0x106b4, 0x1 },
> > > > > + { 0x107b4, 0x1 },
> > > > > + { 0x108b4, 0x1 },
> > > > > + { 0x11011, 0x1 },
> > > > > + { 0x11012, 0x1 },
> > > > > + { 0x11013, 0x180 },
> > > > > + { 0x11018, 0x1 },
> > > > > + { 0x11002, 0x6209 },
> > > > > + { 0x110b2, 0x1 },
> > > > > + { 0x111b4, 0x1 },
> > > > > + { 0x112b4, 0x1 },
> > > > > + { 0x113b4, 0x1 },
> > > > > + { 0x114b4, 0x1 },
> > > > > + { 0x115b4, 0x1 },
> > > > > + { 0x116b4, 0x1 },
> > > > > + { 0x117b4, 0x1 },
> > > > > + { 0x118b4, 0x1 },
> > > > > + { 0x12011, 0x1 },
> > > > > + { 0x12012, 0x1 },
> > > > > + { 0x12013, 0x180 },
> > > > > + { 0x12018, 0x1 },
> > > > > + { 0x12002, 0x6209 },
> > > > > + { 0x120b2, 0x1 },
> > > > > + { 0x121b4, 0x1 },
> > > > > + { 0x122b4, 0x1 },
> > > > > + { 0x123b4, 0x1 },
> > > > > + { 0x124b4, 0x1 },
> > > > > + { 0x125b4, 0x1 },
> > > > > + { 0x126b4, 0x1 },
> > > > > + { 0x127b4, 0x1 },
> > > > > + { 0x128b4, 0x1 },
> > > > > + { 0x13011, 0x1 },
> > > > > + { 0x13012, 0x1 },
> > > > > + { 0x13013, 0x180 },
> > > > > + { 0x13018, 0x1 },
> > > > > + { 0x13002, 0x6209 },
> > > > > + { 0x130b2, 0x1 },
> > > > > + { 0x131b4, 0x1 },
> > > > > + { 0x132b4, 0x1 },
> > > > > + { 0x133b4, 0x1 },
> > > > > + { 0x134b4, 0x1 },
> > > > > + { 0x135b4, 0x1 },
> > > > > + { 0x136b4, 0x1 },
> > > > > + { 0x137b4, 0x1 },
> > > > > + { 0x138b4, 0x1 },
> > > > > + { 0x2003a, 0x2 },
> > > > > + { 0xc0080, 0x2 },
> > > > > + { 0xd0000, 0x1 },
> > > > > +};
> > > >
> > > > The same as above.
> > > >
> > > > > +
> > > > > +struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
> > > > > + {
> > > > > + /* P0 3000mts 1D */
> > > > > + .drate = 3000,
> > > > > + .fw_type = FW_1D_IMAGE,
> > > > > + .fsp_cfg = lpddr4_fsp0_cfg,
> > > > > + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg),
> > > > > + },
> > > > > + {
> > > > > + /* P0 3000mts 2D */
> > > > > + .drate = 3000,
> > > > > + .fw_type = FW_2D_IMAGE,
> > > > > + .fsp_cfg = lpddr4_fsp0_2d_cfg,
> > > > > + .fsp_cfg_num =
> > > > > ARRAY_SIZE(lpddr4_fsp0_2d_cfg),
> > > > > + },
> > > > > + {
> > > > > + /* P1 400mts 1D */
> > > > > + .drate = 400,
> > > > > + .fw_type = FW_1D_IMAGE,
> > > > > + .fsp_cfg = lpddr4_fsp1_cfg,
> > > > > + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg),
> > > > > + },
> > > > > + {
> > > > > + /* P1 100mts 1D */
> > > > > + .drate = 100,
> > > > > + .fw_type = FW_1D_IMAGE,
> > > > > + .fsp_cfg = lpddr4_fsp2_cfg,
> > > > > + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg),
> > > > > + },
> > > > > +};
> > > > > +
> > > > > +/* lpddr4 timing config params on EVK board */
> > > > > +struct dram_timing_info dram_timing = {
> > > > > + .ddrc_cfg = lpddr4_ddrc_cfg,
> > > > > + .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
> > > > > + .ddrphy_cfg = lpddr4_ddrphy_cfg,
> > > > > + .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg),
> > > > > + .fsp_msg = lpddr4_dram_fsp_msg,
> > > > > + .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg),
> > > > > + .ddrphy_trained_csr = lpddr4_ddrphy_trained_csr,
> > > > > + .ddrphy_trained_csr_num =
> > > > > ARRAY_SIZE(lpddr4_ddrphy_trained_csr),
> > > > > + .ddrphy_pie = lpddr4_phy_pie,
> > > > > + .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
> > > >
> > > > It would be best to get the above values calculated dynamically
> > > > for this SoC.
> > > >
> > > > > +};
> > > > > diff --git a/board/freescale/imx8mm_evk/spl.c
> > > > > b/board/freescale/imx8mm_evk/spl.c new file mode 100644
> > > > > index 0000000000..cf1dfc2c2a
> > > > > --- /dev/null
> > > > > +++ b/board/freescale/imx8mm_evk/spl.c
> > > > > @@ -0,0 +1,187 @@
> > > > > +// SPDX-License-Identifier: GPL-2.0+
> > > > > +/*
> > > > > + * Copyright 2019 NXP
> > > > > + */
> > > > > +
> > > > > +#include <common.h>
> > > > > +#include <spl.h>
> > > > > +#include <asm/io.h>
> > > > > +#include <errno.h>
> > > > > +#include <asm/io.h>
> > > > > +#include <asm/mach-imx/iomux-v3.h>
> > > > > +#include <asm/arch/imx8mm_pins.h>
> > > > > +#include <asm/arch/sys_proto.h>
> > > > > +#include <power/pmic.h>
> > > > > +#include <asm/arch/clock.h>
> > > > > +#include <asm/mach-imx/gpio.h>
> > > > > +#include <asm/mach-imx/mxc_i2c.h>
> > > > > +#include <fsl_esdhc.h>
> > > > > +#include <mmc.h>
> > > > > +#include <asm/arch/ddr.h>
> > > > > +
> > > > > +DECLARE_GLOBAL_DATA_PTR;
> > > > > +
> > > > > +void spl_dram_init(void)
> > > > > +{
> > > > > + ddr_init(&dram_timing);
> > > > > +}
> > > > > +
> > > > > +#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 18)
> > > > > +#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
> > > > > +
> > > > > +#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS |
> > > > PAD_CTL_PUE | \
> > > > > + PAD_CTL_PE | PAD_CTL_FSEL2)
> > > > > +#define USDHC_GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE1)
> > > > > +
> > > > > +static iomux_v3_cfg_t const usdhc3_pads[] = {
> > > > > + IMX8MM_PAD_NAND_WE_B_USDHC3_CLK |
> > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > + IMX8MM_PAD_NAND_WP_B_USDHC3_CMD |
> > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > + IMX8MM_PAD_NAND_DATA04_USDHC3_DATA0 |
> > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > + IMX8MM_PAD_NAND_DATA05_USDHC3_DATA1 |
> > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > + IMX8MM_PAD_NAND_DATA06_USDHC3_DATA2 |
> > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > + IMX8MM_PAD_NAND_DATA07_USDHC3_DATA3 |
> > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > + IMX8MM_PAD_NAND_RE_B_USDHC3_DATA4 |
> > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > + IMX8MM_PAD_NAND_CE2_B_USDHC3_DATA5 |
> > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > + IMX8MM_PAD_NAND_CE3_B_USDHC3_DATA6 |
> > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > + IMX8MM_PAD_NAND_CLE_USDHC3_DATA7 |
> > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL), +};
> > > > > +
> > > > > +static iomux_v3_cfg_t const usdhc2_pads[] = {
> > > > > + IMX8MM_PAD_SD2_CLK_USDHC2_CLK |
> > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > + IMX8MM_PAD_SD2_CMD_USDHC2_CMD |
> > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > + IMX8MM_PAD_SD2_DATA0_USDHC2_DATA0 |
> > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > + IMX8MM_PAD_SD2_DATA1_USDHC2_DATA1 |
> > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > + IMX8MM_PAD_SD2_DATA2_USDHC2_DATA2 |
> > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > + IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 |
> > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > + IMX8MM_PAD_SD2_RESET_B_GPIO2_IO19 |
> > > > > MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), +};
> > > > > +
> > > > > +/*
> > > > > + * The evk board uses DAT3 to detect CD card plugin,
> > > > > + * in u-boot we mux the pin to GPIO when doing
> > > > > board_mmc_getcd.
> > > > > + */
> > > > > +static iomux_v3_cfg_t const usdhc2_cd_pad =
> > > > > + IMX8MM_PAD_SD2_DATA3_GPIO2_IO18 |
> > > > > MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL); +
> > > > > +static iomux_v3_cfg_t const usdhc2_dat3_pad =
> > > > > + IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 |
> > > > > + MUX_PAD_CTRL(USDHC_PAD_CTRL);
> > > > > +
> > > > > +static struct fsl_esdhc_cfg usdhc_cfg[2] = {
> > > > > + {USDHC2_BASE_ADDR, 0, 1},
> > > > > + {USDHC3_BASE_ADDR, 0, 1},
> > > > > +};
> > > > > +
> > > > > +int board_mmc_init(bd_t *bis)
> > > > > +{
> > > > > + int i, ret;
> > > > > + /*
> > > > > + * According to the board_mmc_init() the following
> > > > > map is done:
> > > > > + * (U-Boot device node) (Physical Port)
> > > > > + * mmc0 USDHC1
> > > > > + * mmc1 USDHC2
> > > > > + */
> > > > > + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
> > > > > + switch (i) {
> > > > > + case 0:
> > > > > + usdhc_cfg[0].sdhc_clk =
> > > > > mxc_get_clock(MXC_ESDHC2_CLK);
> > > > > +
> > > > > imx_iomux_v3_setup_multiple_pads(usdhc2_pads, +
> > > > > ARRAY_SIZE(usdhc2_pads));
> > > > > + gpio_request(USDHC2_PWR_GPIO,
> > > > > "usdhc2_reset");
> > > > > +
> > > > > gpio_direction_output(USDHC2_PWR_GPIO, 0);
> > > > > + udelay(500);
> > > > > +
> > > > > gpio_direction_output(USDHC2_PWR_GPIO, 1);
> > > > > + break;
> > > > > + case 1:
> > > > > + usdhc_cfg[1].sdhc_clk =
> > > > > mxc_get_clock(MXC_ESDHC3_CLK);
> > > > > +
> > > > > imx_iomux_v3_setup_multiple_pads(usdhc3_pads, +
> > > > > ARRAY_SIZE(usdhc3_pads));
> > > > > + break;
> > > >
> > > > It would be best if you could enable DM/DTS in SPL too from the
> > > > outset (and share the SPL size).
> > > >
> > > > Do you have any timeline for converting SPL to DM/DTS?
> > > >
> > > > > + default:
> > > > > + printf("USDHC controllers %d not
> > > > > supported \n", i + 1);
> > > > > + return -EINVAL;
> > > > > + }
> > > > > +
> > > > > + ret = fsl_esdhc_initialize(bis,
> > > > > &usdhc_cfg[i]);
> > > > > + if (ret)
> > > > > + return ret;
> > > > > + }
> > > > > +
> > > > > + return 0;
> > > > > +}
> > > > > +
> > > > > +int board_mmc_getcd(struct mmc *mmc)
> > > > > +{
> > > > > + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg
> > > > > *)mmc->priv;
> > > > > + int ret = 0;
> > > > > +
> > > > > + switch (cfg->esdhc_base) {
> > > > > + case USDHC3_BASE_ADDR:
> > > > > + ret = 1;
> > > > > + break;
> > > > > + case USDHC2_BASE_ADDR:
> > > > > + imx_iomux_v3_setup_pad(usdhc2_cd_pad);
> > > > > + gpio_request(USDHC2_CD_GPIO, "usdhc2 cd");
> > > > > + gpio_direction_input(USDHC2_CD_GPIO);
> > > > > +
> > > > > + /*
> > > > > + * Since it is the DAT3 pin, this pin is
> > > > > pulled to
> > > > > + * low voltage if no card
> > > > > + */
> > > > > + ret = gpio_get_value(USDHC2_CD_GPIO);
> > > > > +
> > > > > + imx_iomux_v3_setup_pad(usdhc2_dat3_pad);
> > > > > + return ret;
> > > > > + }
> > > > > +
> > > > > + return 1;
> > > > > +}
> > > > > +
> > > > > +void spl_board_init(void)
> > > > > +{
> > > > > + puts("Normal Boot\n");
> > > > > +}
> > > > > +
> > > > > +#ifdef CONFIG_SPL_LOAD_FIT
> > > > > +int board_fit_config_name_match(const char *name)
> > > > > +{
> > > > > + /* Just empty function now - can't decide what to
> > > > > choose */
> > > > > + debug("%s: %s\n", __func__, name);
> > > > > +
> > > > > + return 0;
> > > > > +}
> > > > > +#endif
> > > > > +
> > > > > +void board_init_f(ulong dummy)
> > > > > +{
> > > > > + int ret;
> > > > > +
> > > > > + /* Clear global data */
> > > > > + memset((void *)gd, 0, sizeof(gd_t));
> > > > > +
> > > > > + arch_cpu_init();
> > > > > +
> > > > > + init_uart_clk(1);
> > > > > +
> > > > > + board_early_init_f();
> > > > > +
> > > > > + timer_init();
> > > > > +
> > > > > + preloader_console_init();
> > > > > +
> > > > > + /* Clear the BSS. */
> > > > > + memset(__bss_start, 0, __bss_end - __bss_start);
> > > > > +
> > > > > + ret = spl_init();
> > > > > + if (ret) {
> > > > > + debug("spl_init() failed: %d\n", ret);
> > > > > + hang();
> > > > > + }
> > > > > +
> > > > > + enable_tzc380();
> > > > > +
> > > > > + /* DDR initialization */
> > > > > + spl_dram_init();
> > > > > +
> > > > > + board_init_r(NULL, 0);
> > > > > +}
> > > > > diff --git a/configs/imx8mm_evk_defconfig
> > > > > b/configs/imx8mm_evk_defconfig new file mode 100644
> > > > > index 0000000000..6110f23e38
> > > > > --- /dev/null
> > > > > +++ b/configs/imx8mm_evk_defconfig
> > > > > @@ -0,0 +1,41 @@
> > > > > +CONFIG_ARM=y
> > > > > +CONFIG_ARCH_IMX8M=y
> > > > > +CONFIG_SYS_TEXT_BASE=0x40200000
> > > > > +CONFIG_SPL_GPIO_SUPPORT=y
> > > > > +CONFIG_SYS_MALLOC_F_LEN=0x2000
> > > > > +CONFIG_TARGET_IMX8MM_EVK=y
> > > > > +CONFIG_SPL_MMC_SUPPORT=y
> > > > > +CONFIG_SPL_SERIAL_SUPPORT=y
> > > > > +CONFIG_SPL=y
> > > > > +CONFIG_FIT=y
> > > > > +CONFIG_FIT_EXTERNAL_OFFSET=0x3000
> > > > > +CONFIG_SPL_LOAD_FIT=y
> > > > >
> > +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
> > > > >
> > > >
> > +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m
> > > > /imximage.cfg,SPL_TEXT_BASE=0x7E1000"
> > > > > +CONFIG_DEFAULT_FDT_FILE="fsl-imx8mm-evk.dtb"
> > > > > +CONFIG_SPL_BOARD_INIT=y
> > > > > +CONFIG_SPL_I2C_SUPPORT=y
> > > > > +CONFIG_HUSH_PARSER=y
> > > > > +CONFIG_CMD_GPIO=y
> > > > > +CONFIG_CMD_I2C=y
> > > > > +CONFIG_CMD_CACHE=y
> > > > > +CONFIG_CMD_REGULATOR=y
> > > > > +CONFIG_CMD_EXT2=y
> > > > > +CONFIG_CMD_EXT4=y
> > > > > +CONFIG_CMD_EXT4_WRITE=y
> > > > > +CONFIG_CMD_FAT=y
> > > > > +CONFIG_OF_CONTROL=y
> > > > > +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mm-evk"
> > > > > +CONFIG_DM_GPIO=y
> > > > > +CONFIG_MXC_GPIO=y
> > > > > +CONFIG_DM_I2C=y
> > > > > +CONFIG_SYS_I2C_MXC=y
> > > > > +CONFIG_DM_MMC=y
> > > > > +CONFIG_DM_ETH=y
> > > >
> > > > Here you enable the DM_ETH, but the welcome u-boot info says:
> > > >
> > > > "Net: No ethernet found."
> > > >
> > > > > +CONFIG_PINCTRL=y
> > > > > +CONFIG_PINCTRL_IMX8M=y
> > > > > +CONFIG_DM_REGULATOR=y
> > > > > +CONFIG_DM_REGULATOR_FIXED=y
> > > > > +CONFIG_DM_REGULATOR_GPIO=y
> > > > > +CONFIG_MXC_UART=y
> > > > > +CONFIG_DM_THERMAL=y
> > > > > diff --git a/include/configs/imx8mm_evk.h
> > > > > b/include/configs/imx8mm_evk.h new file mode 100644
> > > > > index 0000000000..f944308757
> > > > > --- /dev/null
> > > > > +++ b/include/configs/imx8mm_evk.h
> > > > > @@ -0,0 +1,221 @@
> > > > > +/* SPDX-License-Identifier: GPL-2.0+ */
> > > > > +/*
> > > > > + * Copyright 2018 NXP
> > > > > + */
> > > > > +
> > > > > +#ifndef __IMX8MM_EVK_H
> > > > > +#define __IMX8MM_EVK_H
> > > > > +
> > > > > +#include <linux/sizes.h>
> > > > > +#include <asm/arch/imx-regs.h>
> > > > > +
> > > > > +#ifdef CONFIG_SECURE_BOOT
> > > > > +#define CONFIG_CSF_SIZE 0x2000 /* 8K
> > > > > region */ +#endif
> > > > > +
> > > > > +#define CONFIG_SPL_MAX_SIZE (148 * 1024)
> > > > > +#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
> > > > > +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
> > > > > +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
> > 0x300
> > > > > +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
> > > > > +#define CONFIG_SYS_UBOOT_BASE \
> > > > > + (QSPI0_AMBA_BASE +
> > > > CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR *
> > > > > 512) +
> > > > > +#ifdef CONFIG_SPL_BUILD
> > > > > +/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
> > > > > +#define CONFIG_SPL_WATCHDOG_SUPPORT
> > > > > +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
> > > > > +#define CONFIG_SPL_POWER_SUPPORT
> > > > > +#define
> > > > > CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
> > > > > +#define CONFIG_SPL_STACK 0x91fff0 +#define
> > > > > CONFIG_SPL_LIBCOMMON_SUPPORT +#define
> > > > CONFIG_SPL_LIBGENERIC_SUPPORT
> > > > > +#define CONFIG_SPL_BSS_START_ADDR 0x00910000
> > > > > +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB
> > > > > */ +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
> > > > > +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512
> > > > > KB */ +#define CONFIG_SYS_ICACHE_OFF
> > > > > +#define CONFIG_SYS_DCACHE_OFF
> > > > > +
> > > > > +#define CONFIG_MALLOC_F_ADDR 0x912000 /*
> > > > > malloc f used before GD_FLG_FULL_MALLOC_INIT set */ +
> > > > > +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image
> > gives a
> > > > error
> > > > > info not panic */ +
> > > > > +#undef CONFIG_DM_MMC
> > > > > +#undef CONFIG_DM_PMIC
> > > > > +#undef CONFIG_DM_PMIC_PFUZE100
> > > >
> > > > Why do you need to undef those config options?
> > > >
> > > > > +
> > > > > +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> > > > > +
> > > > > +#endif
> > > > > +
> > > > > +#define CONFIG_REMAKE_ELF
> > > > > +
> > > > > +#define CONFIG_BOARD_EARLY_INIT_F
> > > > > +#define CONFIG_BOARD_POSTCLK_INIT
> > > > > +#define CONFIG_BOARD_LATE_INIT
> > > > > +
> > > > > +/* Flat Device Tree Definitions */
> > > > > +#define CONFIG_OF_BOARD_SETUP
> > > > > +
> > > > > +#undef CONFIG_CMD_EXPORTENV
> > > > > +#undef CONFIG_CMD_IMPORTENV
> > > > > +#undef CONFIG_CMD_IMLS
> > > > > +
> > > > > +#undef CONFIG_CMD_CRC32
> > > > > +#undef CONFIG_BOOTM_NETBSD
> > > >
> > > > There seems to be some issue with inheritance, as you need to
> > > > undef those values manually.
> > > >
> > > > Why is it needed?
> > > >
> > > > > +
> > > > > +/* ENET Config */
> > > > > +/* ENET1 */
> > > > > +#if defined(CONFIG_CMD_NET)
> > > > > +#define CONFIG_CMD_PING
> > > > > +#define CONFIG_CMD_DHCP
> > > > > +#define CONFIG_CMD_MII
> > > > > +#define CONFIG_MII
> > > > > +#define CONFIG_ETHPRIME "FEC"
> > > > > +
> > > > > +#define CONFIG_FEC_MXC
> > > > > +#define CONFIG_FEC_XCV_TYPE RGMII
> > > > > +#define CONFIG_FEC_MXC_PHYADDR 0
> > > > > +#define FEC_QUIRK_ENET_MAC
> > > > > +
> > > > > +#define CONFIG_PHY_GIGE
> > > > > +#define IMX_FEC_BASE 0x30BE0000
> > > > > +
> > > > > +#define CONFIG_PHYLIB
> > > > > +#define CONFIG_PHY_ATHEROS
> > > > > +#endif
> > > > > +
> > > > > +/* Initial environment variables */
> > > > > +#define CONFIG_EXTRA_ENV_SETTINGS \
> > > > > + "script=boot.scr\0" \
> > > > > + "image=Image\0" \
> > > > > + "console=ttymxc1,115200
> > > > > earlycon=ec_imx6q,0x30890000,115200\0" \
> > > > > + "fdt_addr=0x43000000\0" \
> > > > > + "fdt_high=0xffffffffffffffff\0" \
> > > > > + "boot_fdt=try\0" \
> > > > > + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
> > > > > + "initrd_addr=0x43800000\0" \
> > > > > + "initrd_high=0xffffffffffffffff\0" \
> > > > > + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
> > > > > + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART)
> > > > > "\0" \
> > > > > + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
> > > > > + "mmcautodetect=yes\0" \
> > > > > + "mmcargs=setenv bootargs ${jh_clk} console=${console}
> > > > > root=${mmcroot}\0 " \
> > > > > + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart}
> > > > > ${loadaddr} ${script};\0" \
> > > > > + "bootscript=echo Running bootscript from mmc ...; " \
> > > > > + "source\0" \
> > > > > + "loadimage=fatload mmc ${mmcdev}:${mmcpart}
> > > > > ${loadaddr} ${image}\0" \
> > > > > + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr}
> > > > > ${fdt_file}\0" \
> > > > > + "mmcboot=echo Booting from mmc ...; " \
> > > > > + "run mmcargs; " \
> > > > > + "if test ${boot_fdt} = yes || test
> > > > > ${boot_fdt} = try; then " \
> > > > > + "if run loadfdt; then " \
> > > > > + "booti ${loadaddr} -
> > > > > ${fdt_addr}; " \
> > > > > + "else " \
> > > > > + "echo WARN: Cannot load the
> > > > > DT; " \
> > > > > + "fi; " \
> > > > > + "else " \
> > > > > + "echo wait for boot; " \
> > > > > + "fi;\0" \
> > > > > + "netargs=setenv bootargs ${jh_clk}
> > > > > console=${console} " \
> > > > > + "root=/dev/nfs " \
> > > > > + "ip=dhcp
> > > > > nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
> > > > > + "netboot=echo Booting from net ...; " \
> > > > > + "run netargs; " \
> > > > > + "if test ${ip_dyn} = yes; then " \
> > > > > + "setenv get_cmd dhcp; " \
> > > > > + "else " \
> > > > > + "setenv get_cmd tftp; " \
> > > > > + "fi; " \
> > > > > + "${get_cmd} ${loadaddr} ${image}; " \
> > > > > + "if test ${boot_fdt} = yes || test
> > > > > ${boot_fdt} = try; then " \
> > > > > + "if ${get_cmd} ${fdt_addr}
> > > > > ${fdt_file}; then " \
> > > > > + "booti ${loadaddr} -
> > > > > ${fdt_addr}; " \
> > > > > + "else " \
> > > > > + "echo WARN: Cannot load the
> > > > > DT; " \
> > > > > + "fi; " \
> > > > > + "else " \
> > > > > + "booti; " \
> > > > > + "fi;\0"
> > > > > +
> > > > > +#define CONFIG_BOOTCOMMAND \
> > > > > + "mmc dev ${mmcdev}; if mmc rescan; then " \
> > > > > + "if run loadbootscript; then " \
> > > > > + "run bootscript; " \
> > > > > + "else " \
> > > > > + "if run loadimage; then " \
> > > > > + "run mmcboot; " \
> > > > > + "else run netboot; " \
> > > > > + "fi; " \
> > > > > + "fi; " \
> > > > > + "else booti ${loadaddr} - ${fdt_addr}; fi"
> > > > > +
> > > > > +/* Link Definitions */
> > > > > +#define CONFIG_LOADADDR 0x40480000
> > > > > +
> > > > > +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
> > > > > +
> > > > > +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
> > > > > +#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
> > > > > +#define CONFIG_SYS_INIT_SP_OFFSET \
> > > > > + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> > > > > +#define CONFIG_SYS_INIT_SP_ADDR \
> > > > > + (CONFIG_SYS_INIT_RAM_ADDR +
> > > > > CONFIG_SYS_INIT_SP_OFFSET) +
> > > > > +#define CONFIG_ENV_OVERWRITE
> > > > > +#if defined(CONFIG_ENV_IS_IN_MMC)
> > > > > +#define CONFIG_ENV_OFFSET (64 * SZ_64K)
> > > > > +#endif
> > > > > +#define CONFIG_ENV_SIZE 0x1000
> > > > > +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC2
> > > > > */ +#define
> > > > > CONFIG_MMCROOT "/dev/mmcblk1p2" /*
> > > > > USDHC2 */ + +/* Size of malloc() pool */
> > > > > +#define CONFIG_SYS_MALLOC_LEN SZ_32M
> > > > > +
> > > > > +#define CONFIG_SYS_SDRAM_BASE 0x40000000
> > > > > +#define PHYS_SDRAM 0x40000000
> > > > > +#define PHYS_SDRAM_SIZE 0x80000000 /*
> > > > > 2GB DDR */ +
> > > > > +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
> > > > > +#define CONFIG_SYS_MEMTEST_END
> > > > (CONFIG_SYS_MEMTEST_START +
> > > > > (PHYS_SDRAM_SIZE >> 1)) +
> > > > > +#define CONFIG_BAUDRATE 115200
> > > > > +
> > > > > +#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
> > > > > +
> > > > > +/* Monitor Command Prompt */
> > > > > +#undef CONFIG_SYS_PROMPT
> > > > > +#define CONFIG_SYS_PROMPT "u-boot=> "
> > > > > +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
> > > > > +#define CONFIG_SYS_CBSIZE 2048
> > > > > +#define CONFIG_SYS_MAXARGS 64
> > > > > +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
> > > > > +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE
> > > > > + \ +
> > > > > sizeof(CONFIG_SYS_PROMPT) + 16) +
> > > > > +#define CONFIG_IMX_BOOTAUX
> > > > > +
> > > > > +/* USDHC */
> > > > > +#define CONFIG_CMD_MMC
> > > > > +#define CONFIG_FSL_ESDHC
> > > > > +#define CONFIG_FSL_USDHC
> > > > > +
> > > > > +#define CONFIG_SYS_FSL_USDHC_NUM 2
> > > > > +#define CONFIG_SYS_FSL_ESDHC_ADDR 0
> > > > > +
> > > > > +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
> > > > > +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
> > > > > +
> > > > > +#define CONFIG_MXC_OCOTP
> > > > > +#define CONFIG_CMD_FUSE
> > > > > +
> > > > > +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C
> > > > > bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /*
> > > > > enable I2C bus 2 */ +#define
> > > > > CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
> > > > > +#define CONFIG_SYS_I2C_SPEED 100000
> > > >
> > > > Some of those values are (SYS_I2C_*, MXC_OCOTP, FSL_*) are
> > > > already supported by Kconfig. Please use Kconfig instead.
> > > >
> > > > > +
> > > > > +#define CONFIG_OF_SYSTEM_SETUP
> > > > > +
> > > > > +#endif
> > > >
> > > >
> > > > Best regards,
> > > >
> > > > Lukasz Majewski
> > > >
> > > > --
> > > >
> > > > DENX Software Engineering GmbH, Managing Director: Wolfgang
> > > > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194
> > > > Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax:
> > > > (+49)-8142-66989-80 Email: lukma at denx.de
> >
> >
> >
> >
> > Best regards,
> >
> > Lukasz Majewski
> >
> > --
> >
> > DENX Software Engineering GmbH, Managing Director: Wolfgang
> > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell,
> > Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> > lukma at denx.de
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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^ permalink raw reply [flat|nested] 39+ messages in thread* [U-Boot] [PATCH 20/20] imx: add i.MX8MM EVK board support
2019-01-30 8:37 ` Lukasz Majewski
@ 2019-01-30 8:50 ` Peng Fan
2019-01-30 10:10 ` Lukasz Majewski
0 siblings, 1 reply; 39+ messages in thread
From: Peng Fan @ 2019-01-30 8:50 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: Lukasz Majewski [mailto:lukma at denx.de]
> Sent: 2019年1月30日 16:38
> To: Peng Fan <peng.fan@nxp.com>
> Cc: sbabic at denx.de; Fabio Estevam <fabio.estevam@nxp.com>;
> dl-uboot-imx <uboot-imx@nxp.com>; u-boot at lists.denx.de
> Subject: Re: [U-Boot] [PATCH 20/20] imx: add i.MX8MM EVK board support
>
> On Wed, 30 Jan 2019 07:07:10 +0000
> Peng Fan <peng.fan@nxp.com> wrote:
>
> > > -----Original Message-----
> > > From: Lukasz Majewski [mailto:lukma at denx.de]
> > > Sent: 2019年1月30日 14:54
> > > To: Peng Fan <peng.fan@nxp.com>
> > > Cc: sbabic at denx.de; Fabio Estevam <fabio.estevam@nxp.com>;
> > > dl-uboot-imx <uboot-imx@nxp.com>; u-boot at lists.denx.de
> > > Subject: Re: [U-Boot] [PATCH 20/20] imx: add i.MX8MM EVK board
> > > support
> > >
> > > Hi Peng,
> > >
> > > > > -----Original Message-----
> > > > > From: Lukasz Majewski [mailto:lukma at denx.de]
> > > > > Sent: 2019年1月30日 7:19
> > > > > To: Peng Fan <peng.fan@nxp.com>
> > > > > Cc: sbabic at denx.de; Fabio Estevam <fabio.estevam@nxp.com>;
> > > > > dl-uboot-imx <uboot-imx@nxp.com>; u-boot at lists.denx.de
> > > > > Subject: Re: [U-Boot] [PATCH 20/20] imx: add i.MX8MM EVK board
> > > > > support
> > > > >
> > > > > Hi Peng,
> > > > >
> > > > > > Add i.MX8MM EVK board support.
> > > > > >
> > > > > > Add board and SoC dts
> > > > > > Add ddr training code
> > > > > > support SD/MMC/GPIO/PINCTRL/UART
> > > > > >
> > > > > > U-Boot SPL 2019.01-00148-g1179cffe66 (Jan 28 2019 - 17:37:34
> > > > > > +0800) Normal Boot
> > > > > > Trying to boot from MMC1
> > > > > >
> > > > > > U-Boot 2019.01-00148-g1179cffe66 (Jan 28 2019 - 17:37:34
> > > > > > +0800)
> > > > > >
> > > > > > CPU: Freescale i.MX8MMQ rev1.0 at 1200 MHz
> > > > > > Reset cause: POR
> > > > > > Model: NXP i.MX8MM EVK board
> > > > > > DRAM: 2 GiB
> > > > > > MMC: FSL_SDHC: 1, FSL_SDHC: 2
> > > > > > In: serial
> > > > > > Out: serial
> > > > > > Err: serial
> > > > > > DM
> > > > >
> > > > > You set/adjust latter in the code the fec network driver. Why
> > > > > it is not found?
> > > >
> > > > I dropped network support, could add it in V2.
> > >
> > > From the patch it seems like the ETH is fully supported, at lease
> > > from the source code point of view.
> > >
> > > >
> > > > >
> > > > > Could you also share the output of "dm tree" command?
> > > >
> > > > Sure.
> > > >
> > > > >
> > > > > I suppose/guess that this board shall support as much as
> > > > > possible of the DT/DM conversions?
> > > >
> > > > Ok.
> > >
> > > And I would like to emphasize the need of DDR training code (as a
> > > functions, not pair of offset and value).
> > >
> > > Are you able to provide such code in the next version of the
> > > patch?
> >
> > There is already common code under drivers/ddr/imx8m
>
> Yes. Indeed there code is there.
>
> > For the array in board file, It need ddr tool change, out of my
> > knowledge.
>
> If the code is there - why not use it for this board? In that way we
> would kill two birds with one stone - the code would be tested on
> "blessed" NXP's development board.
It is already used. The lpddr4_timing.c in board file is to provide configuration
and the code in drivers/ddr/imx8m will use that to configure DDRC and DDR PHY.
Thanks,
Peng.
>
> >
> > Thanks,
> > Peng.
> >
> > >
> > > >
> > > > Regards,
> > > > Peng.
> > > >
> > > > >
> > > > > > Hit any key to stop autoboot: 2
> > > > > >
> > > > > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > > > > ---
> > > > > > arch/arm/dts/fsl-imx8mm-evk.dts | 203 +++
> > > > > > arch/arm/dts/fsl-imx8mm.dtsi | 586
> ++++++++
> > > > > > arch/arm/mach-imx/imx8m/Kconfig | 7 +
> > > > > > board/freescale/imx8mm_evk/Kconfig | 12 +
> > > > > > board/freescale/imx8mm_evk/MAINTAINERS | 6 +
> > > > > > board/freescale/imx8mm_evk/Makefile | 12 +
> > > > > > board/freescale/imx8mm_evk/imx8mm_evk.c | 144 ++
> > > > > > board/freescale/imx8mm_evk/lpddr4_timing.c | 1980
> > > > > > ++++++++++++++++++++++++++++
> > > > > > board/freescale/imx8mm_evk/spl.c | 187 +++
> > > > > > configs/imx8mm_evk_defconfig | 41 +
> > > > > > include/configs/imx8mm_evk.h | 221 ++++ 11
> > > > > > files changed, 3399 insertions(+) create mode 100644
> > > > > > arch/arm/dts/fsl-imx8mm-evk.dts create mode 100644
> > > > > > arch/arm/dts/fsl-imx8mm.dtsi create mode 100644
> > > > > > board/freescale/imx8mm_evk/Kconfig create mode 100644
> > > > > > board/freescale/imx8mm_evk/MAINTAINERS create mode 100644
> > > > > > board/freescale/imx8mm_evk/Makefile create mode 100644
> > > > > > board/freescale/imx8mm_evk/imx8mm_evk.c create mode 100644
> > > > > > board/freescale/imx8mm_evk/lpddr4_timing.c create mode 100644
> > > > > > board/freescale/imx8mm_evk/spl.c create mode 100644
> > > > > > configs/imx8mm_evk_defconfig create mode 100644
> > > > > > include/configs/imx8mm_evk.h
> > > > > >
> > > > > > diff --git a/arch/arm/dts/fsl-imx8mm-evk.dts
> > > > > > b/arch/arm/dts/fsl-imx8mm-evk.dts new file mode 100644
> > > > > > index 0000000000..df409eca47
> > > > > > --- /dev/null
> > > > > > +++ b/arch/arm/dts/fsl-imx8mm-evk.dts
> > > > > > @@ -0,0 +1,203 @@
> > > > > > +// SPDX-License-Identifier: GPL-2.0+
> > > > > > +/*
> > > > > > + * Copyright 2019 NXP
> > > > > > + */
> > > > > > +
> > > > > > +/dts-v1/;
> > > > > > +
> > > > > > +#include "fsl-imx8mm.dtsi"
> > > > > > +
> > > > > > +/ {
> > > > > > + model = "NXP i.MX8MM EVK board";
> > > > > > + compatible = "fsl,imx8mm-evk", "fsl,imx8mm";
> > > > > > +
> > > > > > + chosen {
> > > > > > + stdout-path = &uart2;
> > > > > > + };
> > > > > > +
> > > > > > + regulators {
> > > > > > + compatible = "simple-bus";
> > > > > > + #address-cells = <1>;
> > > > > > + #size-cells = <0>;
> > > > > > +
> > > > > > + reg_usdhc2_vmmc: regulator-usdhc2 {
> > > > > > + compatible = "regulator-fixed";
> > > > > > + regulator-name = "VSD_3V3";
> > > > > > + regulator-min-microvolt = <3300000>;
> > > > > > + regulator-max-microvolt = <3300000>;
> > > > > > + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
> > > > > > + off-on-delay = <20000>;
> > > > > > + enable-active-high;
> > > > > > + };
> > > > > > + };
> > > > > > +};
> > > > > > +
> > > > > > +&iomuxc {
> > > > > > + pinctrl-names = "default";
> > > > > > +
> > > > > > + imx8mm-evk {
> > > > > > + pinctrl_fec1: fec1grp {
> > > > > > + fsl,pins = <
> > > > > > +
> > > > > > MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
> > > > > > +
> > > > > > MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
> > > > > > +
> > > > > > MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
> > > > > > +
> > > > > > MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
> > > > > > +
> > > > > > MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
> > > > > > +
> > > > > > MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
> > > > > > +
> > > > > > MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
> > > > > > +
> > > > > > MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
> > > > > > +
> > > > > > MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
> > > > > > +
> > > > > > MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
> > > > > > +
> > > > > > MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
> > > > > > +
> > > > > > MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
> > > > > > +
> > > > > > MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
> > > > > > +
> > > > > > MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
> > > > > > +
> > > > > > MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
> > > > > > + >;
> > > > > > + };
> > > > > > +
> > > > > > + pinctrl_gpio_led: gpioledgrp {
> > > > > > + fsl,pins = <
> > > > > > +
> > > > > > MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
> > > > > > + >;
> > > > > > + };
> > > > > > +
> > > > > > + pinctrl_uart2: uart2grp {
> > > > > > + fsl,pins = <
> > > > > > +
> > > > > > MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
> > > > > > +
> > > > > > MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
> > > > > > + >;
> > > > > > + };
> > > > > > +
> > > > > > + pinctrl_usdhc2_gpio: usdhc2grpgpio {
> > > > > > + fsl,pins = <
> > > > > > +
> > > > > > MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
> > > > > > +
> > > > > > MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
> > > > > > + >;
> > > > > > + };
> > > > > > +
> > > > > > + pinctrl_usdhc2: usdhc2grp {
> > > > > > + fsl,pins = <
> > > > > > +
> > > > > > MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
> > > > > > +
> > > > > > MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
> > > > > > +
> > > > > > MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
> > > > > > +
> > > > > > MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
> > > > > > +
> > > > > > MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
> > > > > > +
> > > > > > MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
> > > > > > +
> > > > > > MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
> > > > > > + >;
> > > > > > + };
> > > > > > +
> > > > > > + pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
> > > > > > + fsl,pins = <
> > > > > > +
> > > > > > MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
> > > > > > +
> > > > > > MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
> > > > > > +
> > > > > > MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
> > > > > > +
> > > > > > MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
> > > > > > +
> > > > > > MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
> > > > > > +
> > > > > > MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
> > > > > > +
> > > > > > MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
> > > > > > + >;
> > > > > > + };
> > > > > > +
> > > > > > + pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
> > > > > > + fsl,pins = <
> > > > > > +
> > > > > > MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
> > > > > > +
> > > > > > MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
> > > > > > +
> > > > > > MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
> > > > > > +
> > > > > > MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
> > > > > > +
> > > > > > MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
> > > > > > +
> > > > > > MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
> > > > > > +
> > > > > > MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
> > > > > > + >;
> > > > > > + };
> > > > > > +
> > > > > > + pinctrl_usdhc3: usdhc3grp {
> > > > > > + fsl,pins = <
> > > > > > +
> > > > > > MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
> > > > > > +
> > > > > > MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
> > > > > > +
> > > > > > MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
> > > > > > +
> > > > > > MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
> > > > > > +
> > > > > > MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
> > > > > > +
> > > > > > MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
> > > > > > +
> > > > > > MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
> > > > > > +
> > > > > > MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
> > > > > > +
> > > > > > MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
> > > > > > +
> > > > > > MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
> > > > > > +
> > > > > > MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE
> 0x190
> > > > > > + >;
> > > > > > + };
> > > > > > +
> > > > > > + pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
> > > > > > + fsl,pins = <
> > > > > > +
> > > > > > MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
> > > > > > +
> > > > > > MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
> > > > > > +
> > > > > > MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
> > > > > > +
> > > > > > MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
> > > > > > +
> > > > > > MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
> > > > > > +
> > > > > > MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
> > > > > > +
> > > > > > MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
> > > > > > +
> > > > > > MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
> > > > > > +
> > > > > > MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
> > > > > > +
> > > > > > MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
> > > > > > +
> > > > > > MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE
> 0x194
> > > > > > + >;
> > > > > > + };
> > > > > > +
> > > > > > + pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
> > > > > > + fsl,pins = <
> > > > > > +
> > > > > > MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
> > > > > > +
> > > > > > MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
> > > > > > +
> > > > > > MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
> > > > > > +
> > > > > > MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
> > > > > > +
> > > > > > MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
> > > > > > +
> > > > > > MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
> > > > > > +
> > > > > > MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
> > > > > > +
> > > > > > MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
> > > > > > +
> > > > > > MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
> > > > > > +
> > > > > > MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
> > > > > > +
> > > > > > MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
> > > > > > + >;
> > > > > > + };
> > > > > > +
> > > > > > + pinctrl_wdog: wdoggrp {
> > > > > > + fsl,pins = <
> > > > > > +
> > > > > > MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
> > > > > > + >;
> > > > > > + };
> > > > > > + };
> > > > > > +};
> > > > > > +
> > > > > > +&uart2 { /* console */
> > > > > > + pinctrl-names = "default";
> > > > > > + pinctrl-0 = <&pinctrl_uart2>;
> > > > > > + status = "okay";
> > > > > > +};
> > > > > > +
> > > > > > +&usdhc2 {
> > > > > > + pinctrl-names = "default", "state_100mhz",
> > > > > > "state_200mhz";
> > > > > > + pinctrl-0 = <&pinctrl_usdhc2>,
> > > > > > <&pinctrl_usdhc2_gpio>;
> > > > > > + pinctrl-1 = <&pinctrl_usdhc2_100mhz>,
> > > > > > <&pinctrl_usdhc2_gpio>;
> > > > > > + pinctrl-2 = <&pinctrl_usdhc2_200mhz>,
> > > > > > <&pinctrl_usdhc2_gpio>;
> > > > > > + cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
> > > > > > + bus-width = <4>;
> > > > > > + vmmc-supply = <®_usdhc2_vmmc>;
> > > > > > + status = "okay";
> > > > > > +};
> > > > > > +
> > > > > > +&usdhc3 {
> > > > > > + pinctrl-names = "default", "state_100mhz",
> > > > > > "state_200mhz";
> > > > > > + pinctrl-0 = <&pinctrl_usdhc3>;
> > > > > > + pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
> > > > > > + pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
> > > > > > + bus-width = <8>;
> > > > > > + non-removable;
> > > > > > + status = "okay";
> > > > > > +};
> > > > > > +
> > > > > > +&wdog1 {
> > > > > > + pinctrl-names = "default";
> > > > > > + pinctrl-0 = <&pinctrl_wdog>;
> > > > > > + fsl,ext-reset-output;
> > > > > > + status = "okay";
> > > > > > +};
> > > > > > diff --git a/arch/arm/dts/fsl-imx8mm.dtsi
> > > > > > b/arch/arm/dts/fsl-imx8mm.dtsi new file mode 100644
> > > > > > index 0000000000..8a808f856d
> > > > > > --- /dev/null
> > > > > > +++ b/arch/arm/dts/fsl-imx8mm.dtsi
> > > > > > @@ -0,0 +1,586 @@
> > > > > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > > > > > +/*
> > > > > > + * Copyright 2017-2019 NXP
> > > > > > + */
> > > > > > +
> > > > > > +#include <dt-bindings/clock/imx8mm-clock.h>
> > > > > > +#include <dt-bindings/gpio/gpio.h>
> > > > > > +#include <dt-bindings/input/input.h>
> > > > > > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > > > > > +#include <dt-bindings/pinctrl/pins-imx8mm.h>
> > > > > > +#include <dt-bindings/thermal/thermal.h>
> > > > > > +
> > > > > > +/ {
> > > > > > + compatible = "fsl,imx8mm";
> > > > > > + interrupt-parent = <&gic>;
> > > > > > + #address-cells = <2>;
> > > > > > + #size-cells = <2>;
> > > > > > +
> > > > > > + aliases {
> > > > > > + i2c0 = &i2c1;
> > > > > > + i2c1 = &i2c2;
> > > > > > + i2c2 = &i2c3;
> > > > > > + i2c3 = &i2c4;
> > > > > > + serial0 = &uart1;
> > > > > > + serial1 = &uart2;
> > > > > > + serial2 = &uart3;
> > > > > > + serial3 = &uart4;
> > > > > > + spi0 = &ecspi1;
> > > > > > + spi1 = &ecspi2;
> > > > > > + spi2 = &ecspi3;
> > > > > > + mmc0 = &usdhc1;
> > > > > > + mmc1 = &usdhc2;
> > > > > > + mmc2 = &usdhc3;
> > > > > > + gpio0 = &gpio1;
> > > > > > + gpio1 = &gpio2;
> > > > > > + gpio2 = &gpio3;
> > > > > > + gpio3 = &gpio4;
> > > > > > + gpio4 = &gpio5;
> > > > > > + };
> > > > > > +
> > > > > > + cpus {
> > > > > > + #address-cells = <1>;
> > > > > > + #size-cells = <0>;
> > > > > > +
> > > > > > + A53_0: cpu at 0 {
> > > > > > + device_type = "cpu";
> > > > > > + compatible = "arm,cortex-a53";
> > > > > > + reg = <0x0>;
> > > > > > + enable-method = "psci";
> > > > > > + next-level-cache = <&A53_L2>;
> > > > > > + };
> > > > > > +
> > > > > > + A53_1: cpu at 1 {
> > > > > > + device_type = "cpu";
> > > > > > + compatible = "arm,cortex-a53";
> > > > > > + reg = <0x1>;
> > > > > > + enable-method = "psci";
> > > > > > + next-level-cache = <&A53_L2>;
> > > > > > + };
> > > > > > +
> > > > > > + A53_2: cpu at 2 {
> > > > > > + device_type = "cpu";
> > > > > > + compatible = "arm,cortex-a53";
> > > > > > + reg = <0x2>;
> > > > > > + enable-method = "psci";
> > > > > > + next-level-cache = <&A53_L2>;
> > > > > > + };
> > > > > > +
> > > > > > + A53_3: cpu at 3 {
> > > > > > + device_type = "cpu";
> > > > > > + compatible = "arm,cortex-a53";
> > > > > > + reg = <0x3>;
> > > > > > + enable-method = "psci";
> > > > > > + next-level-cache = <&A53_L2>;
> > > > > > + };
> > > > > > +
> > > > > > + A53_L2: l2-cache0 {
> > > > > > + compatible = "cache";
> > > > > > + };
> > > > > > + };
> > > > > > +
> > > > > > + memory at 40000000 {
> > > > > > + device_type = "memory";
> > > > > > + reg = <0x0 0x40000000 0 0x80000000>;
> > > > > > + };
> > > > > > +
> > > > > > + clocks {
> > > > > > + #address-cells = <1>;
> > > > > > + #size-cells = <0>;
> > > > > > +
> > > > > > + osc_32k: clock at 0 {
> > > > > > + compatible = "fixed-clock";
> > > > > > + reg = <0>;
> > > > > > + #clock-cells = <0>;
> > > > > > + clock-frequency = <32768>;
> > > > > > + clock-output-names = "osc_32k";
> > > > > > + };
> > > > > > +
> > > > > > + osc_24m: clock at 1 {
> > > > > > + compatible = "fixed-clock";
> > > > > > + reg = <1>;
> > > > > > + #clock-cells = <0>;
> > > > > > + clock-frequency = <24000000>;
> > > > > > + clock-output-names = "osc_24m";
> > > > > > + };
> > > > > > +
> > > > > > + clk_ext1: clock at 2 {
> > > > > > + compatible = "fixed-clock";
> > > > > > + reg = <3>;
> > > > > > + #clock-cells = <0>;
> > > > > > + clock-frequency = <133000000>;
> > > > > > + clock-output-names = "clk_ext1";
> > > > > > + };
> > > > > > +
> > > > > > + clk_ext2: clock at 3 {
> > > > > > + compatible = "fixed-clock";
> > > > > > + reg = <4>;
> > > > > > + #clock-cells = <0>;
> > > > > > + clock-frequency = <133000000>;
> > > > > > + clock-output-names = "clk_ext2";
> > > > > > + };
> > > > > > +
> > > > > > + clk_ext3: clock at 4 {
> > > > > > + compatible = "fixed-clock";
> > > > > > + reg = <5>;
> > > > > > + #clock-cells = <0>;
> > > > > > + clock-frequency = <133000000>;
> > > > > > + clock-output-names = "clk_ext3";
> > > > > > + };
> > > > > > +
> > > > > > + clk_ext4: clock at 5 {
> > > > > > + compatible = "fixed-clock";
> > > > > > + reg = <6>;
> > > > > > + #clock-cells = <0>;
> > > > > > + clock-frequency= <133000000>;
> > > > > > + clock-output-names = "clk_ext4";
> > > > > > + };
> > > > > > + };
> > > > > > +
> > > > > > + gic: interrupt-controller at 38800000 {
> > > > > > + compatible = "arm,gic-v3";
> > > > > > + reg = <0x0 0x38800000 0 0x10000>, /* GIC
> > > > > > Dist */
> > > > > > + <0x0 0x38880000 0 0xC0000>; /* GICR
> > > > > > (RD_base + SGI_base) */
> > > > > > + #interrupt-cells = <3>;
> > > > > > + interrupt-controller;
> > > > > > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> > > > > > + };
> > > > > > +
> > > > > > + psci {
> > > > > > + compatible = "arm,psci-1.0";
> > > > > > + method = "smc";
> > > > > > + };
> > > > > > +
> > > > > > + pmu {
> > > > > > + compatible = "arm,armv8-pmuv3";
> > > > > > + interrupts = <GIC_PPI 7
> > > > > > + (GIC_CPU_MASK_SIMPLE(6) |
> > > > > > IRQ_TYPE_LEVEL_HIGH)>;
> > > > > > + interrupt-affinity = <&A53_0>, <&A53_1>,
> > > > > > <&A53_2>, <&A53_3>;
> > > > > > + };
> > > > > > +
> > > > > > + timer {
> > > > > > + compatible = "arm,armv8-timer";
> > > > > > + interrupts = <GIC_PPI 13
> > > > > > (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical
> > > > > > Secure */
> > > > > > + <GIC_PPI 14
> > > > > > (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical
> > > > > > Non-Secure */
> > > > > > + <GIC_PPI 11
> > > > > > (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual
> */
> > > > > > + <GIC_PPI 10
> > > > > > (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /*
> Hypervisor
> > > > > > */
> > > > > > + clock-frequency = <8000000>;
> > > > > > + arm,no-tick-in-suspend;
> > > > > > + };
> > > > > > +
> > > > > > + soc at 0 {
> > > > > > + compatible = "simple-bus";
> > > > > > + #address-cells = <2>;
> > > > > > + #size-cells = <2>;
> > > > > > + ranges;
> > > > > > +
> > > > > > + aips1: bus at 30000000 {
> > > > > > + compatible = "fsl,aips-bus",
> > > > > > "simple-bus";
> > > > > > + #address-cells = <2>;
> > > > > > + #size-cells = <2>;
> > > > > > + reg = <0x0 0x30000000 0x0 0x400000>;
> > > > > > + ranges;
> > > > > > +
> > > > > > + gpio1: gpio at 30200000 {
> > > > > > + compatible =
> > > > > > "fsl,imx8mm-gpio", "fsl,imx35-gpio";
> > > > > > + reg = <0x0 0x30200000 0x0
> > > > > > 0x10000>;
> > > > > > + interrupts = <GIC_SPI 64
> > > > > > IRQ_TYPE_LEVEL_HIGH>,
> > > > > > + <GIC_SPI 65
> > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > + gpio-controller;
> > > > > > + #gpio-cells = <2>;
> > > > > > + interrupt-controller;
> > > > > > + #interrupt-cells = <2>;
> > > > > > + };
> > > > > > +
> > > > > > + gpio2: gpio at 30210000 {
> > > > > > + compatible =
> > > > > > "fsl,imx8mm-gpio", "fsl,imx35-gpio";
> > > > > > + reg = <0x0 0x30210000 0x0
> > > > > > 0x10000>;
> > > > > > + interrupts = <GIC_SPI 66
> > > > > > IRQ_TYPE_LEVEL_HIGH>,
> > > > > > + <GIC_SPI 67
> > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > + gpio-controller;
> > > > > > + #gpio-cells = <2>;
> > > > > > + interrupt-controller;
> > > > > > + #interrupt-cells = <2>;
> > > > > > + };
> > > > > > +
> > > > > > + gpio3: gpio at 30220000 {
> > > > > > + compatible =
> > > > > > "fsl,imx8mm-gpio", "fsl,imx35-gpio";
> > > > > > + reg = <0x0 0x30220000 0x0
> > > > > > 0x10000>;
> > > > > > + interrupts = <GIC_SPI 68
> > > > > > IRQ_TYPE_LEVEL_HIGH>,
> > > > > > + <GIC_SPI 69
> > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > + gpio-controller;
> > > > > > + #gpio-cells = <2>;
> > > > > > + interrupt-controller;
> > > > > > + #interrupt-cells = <2>;
> > > > > > + };
> > > > > > +
> > > > > > + gpio4: gpio at 30230000 {
> > > > > > + compatible =
> > > > > > "fsl,imx8mm-gpio", "fsl,imx35-gpio";
> > > > > > + reg = <0x0 0x30230000 0x0
> > > > > > 0x10000>;
> > > > > > + interrupts = <GIC_SPI 70
> > > > > > IRQ_TYPE_LEVEL_HIGH>,
> > > > > > + <GIC_SPI 71
> > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > + gpio-controller;
> > > > > > + #gpio-cells = <2>;
> > > > > > + interrupt-controller;
> > > > > > + #interrupt-cells = <2>;
> > > > > > + };
> > > > > > +
> > > > > > + gpio5: gpio at 30240000 {
> > > > > > + compatible =
> > > > > > "fsl,imx8mm-gpio", "fsl,imx35-gpio";
> > > > > > + reg = <0x0 0x30240000 0x0
> > > > > > 0x10000>;
> > > > > > + interrupts = <GIC_SPI 72
> > > > > > IRQ_TYPE_LEVEL_HIGH>,
> > > > > > + <GIC_SPI 73
> > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > + gpio-controller;
> > > > > > + #gpio-cells = <2>;
> > > > > > + interrupt-controller;
> > > > > > + #interrupt-cells = <2>;
> > > > > > + };
> > > > > > +
> > > > > > + wdog1: wdog at 30280000 {
> > > > > > + compatible = "fsl,imx21-wdt";
> > > > > > + reg = <0 0x30280000 0
> > > > > > 0x10000>;
> > > > > > + interrupts = <GIC_SPI 78
> > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > + clocks = <&clk
> > > > > > IMX8MM_CLK_WDOG1_ROOT>;
> > > > > > + status = "disabled";
> > > > > > + };
> > > > > > +
> > > > > > + wdog2: wdog at 30290000 {
> > > > > > + compatible = "fsl,imx21-wdt";
> > > > > > + reg = <0 0x30290000 0
> > > > > > 0x10000>;
> > > > > > + interrupts = <GIC_SPI 79
> > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > + clocks = <&clk
> > > > > > IMX8MM_CLK_WDOG2_ROOT>;
> > > > > > + status = "disabled";
> > > > > > + };
> > > > > > +
> > > > > > + wdog3: wdog at 302a0000 {
> > > > > > + compatible = "fsl,imx21-wdt";
> > > > > > + reg = <0 0x302a0000 0
> > > > > > 0x10000>;
> > > > > > + interrupts = <GIC_SPI 10
> > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > + clocks = <&clk
> > > > > > IMX8MM_CLK_WDOG3_ROOT>;
> > > > > > + status = "disabled";
> > > > > > + };
> > > > > > +
> > > > > > + sdma2: dma-controller at 302c0000 {
> > > > > > + compatible =
> > > > > > "fsl,imx8mq-sdma", "fsl,imx7d-sdma";
> > > > > > + reg = <0x0 0x302c0000 0x0
> > > > > > 0x10000>;
> > > > > > + interrupts = <GIC_SPI 103
> > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > + clocks = <&clk
> > > > > > IMX8MM_CLK_SDMA2_ROOT>,
> > > > > > + <&clk
> > > > > > IMX8MM_CLK_SDMA2_ROOT>;
> > > > > > + clock-names = "ipg", "ahb";
> > > > > > + #dma-cells = <3>;
> > > > > > + fsl,sdma-ram-script-name =
> > > > > > "imx/sdma/sdma-imx7d.bin";
> > > > > > + fsl,ratio-1-1;
> > > > > > + status = "okay";
> > > > > > + };
> > > > > > +
> > > > > > + sdma3: dma-controller at 302b0000 {
> > > > > > + compatible =
> > > > > > "fsl,imx8mq-sdma", "fsl,imx7d-sdma";
> > > > > > + reg = <0x0 0x302b0000 0x0
> > > > > > 0x10000>;
> > > > > > + interrupts = <GIC_SPI 34
> > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > + clocks = <&clk
> > > > > > IMX8MM_CLK_SDMA3_ROOT>,
> > > > > > + <&clk
> > > > > > IMX8MM_CLK_SDMA3_ROOT>;
> > > > > > + clock-names = "ipg", "ahb";
> > > > > > + #dma-cells = <3>;
> > > > > > + fsl,sdma-ram-script-name =
> > > > > > "imx/sdma/sdma-imx7d.bin";
> > > > > > + fsl,ratio-1-1;
> > > > > > + status = "okay";
> > > > > > + };
> > > > > > +
> > > > > > + iomuxc: pinctrl at 30330000 {
> > > > > > + compatible =
> > > > > > "fsl,imx8mm-iomuxc";
> > > > > > + reg = <0x0 0x30330000 0x0
> > > > > > 0x10000>;
> > > > > > + };
> > > > > > +
> > > > > > + gpr: iomuxc-gpr at 30340000 {
> > > > > > + compatible =
> > > > > > "fsl,imx8mm-iomuxc-gpr", "syscon";
> > > > > > + reg = <0x0 0x30340000 0x0
> > > > > > 0x10000>;
> > > > > > + };
> > > > > > +
> > > > > > + ocotp: ocotp-ctrl at 30350000 {
> > > > > > + compatible =
> > > > > > "fsl,imx8mq-ocotp", "fsl,imx7d-ocotp", "syscon";
> > > > > > + reg = <0 0x30350000 0
> > > > > > 0x10000>;
> > > > > > + clocks = <&clk
> > > > > > IMX8MM_CLK_OCOTP_ROOT>;
> > > > > > + /* For nvmem subnodes */
> > > > > > + #address-cells = <1>;
> > > > > > + #size-cells = <1>;
> > > > > > + };
> > > > > > +
> > > > > > + anatop: anatop at 30360000 {
> > > > > > + compatible =
> > > > > > "fsl,imx8mm-anatop", "syscon", "simple-bus";
> > > > > > + reg = <0x0 0x30360000 0x0
> > > > > > 0x10000>;
> > > > > > + };
> > > > > > +
> > > > > > + snvs: snvs at 30370000 {
> > > > > > + compatible =
> > > > > > "fsl,sec-v4.0-mon","syscon", "simple-mfd";
> > > > > > + reg = <0x0 0x30370000 0x0
> > > > > > 0x10000>; +
> > > > > > + snvs_rtc: snvs-rtc-lp{
> > > > > > + compatible =
> > > > > > "fsl,sec-v4.0-mon-rtc-lp";
> > > > > > + regmap =<&snvs>;
> > > > > > + offset = <0x34>;
> > > > > > + interrupts = <GIC_SPI
> > > > > > 19 IRQ_TYPE_LEVEL_HIGH>,
> > > > > > + <GIC_SPI
> > > > > > 20 IRQ_TYPE_LEVEL_HIGH>;
> > > > > > + };
> > > > > > +
> > > > > > + snvs_pwrkey: snvs-powerkey {
> > > > > > + compatible =
> > > > > > "fsl,sec-v4.0-pwrkey";
> > > > > > + regmap = <&snvs>;
> > > > > > + interrupts =
> > > > > > <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
> > > > > > + linux,keycode =
> > > > > > <KEY_POWER>;
> > > > > > + wakeup-source;
> > > > > > + };
> > > > > > + };
> > > > > > +
> > > > > > + clk: clock-controller at 30380000 {
> > > > > > + compatible =
> > > > > > "fsl,imx8mm-ccm";
> > > > > > + reg = <0x0 0x30380000 0x0
> > > > > > 0x10000>;
> > > > > > + #clock-cells = <1>;
> > > > > > + clocks = <&osc_32k>,
> > > > > > <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
> > > > > > + <&clk_ext3>,
> > > > > > <&clk_ext4>;
> > > > > > + clock-names = "osc_32k",
> > > > > > "osc_24m", "clk_ext1", "clk_ext2",
> > > > > > + "clk_ext3",
> > > > > > "clk_ext4";
> > > > > > + };
> > > > > > +
> > > > > > + src: src at 30390000 {
> > > > > > + compatible =
> > > > > > "fsl,imx8mm-src", "syscon";
> > > > > > + reg = <0x0 0x30390000 0x0
> > > > > > 0x10000>;
> > > > > > + interrupts = <GIC_SPI 89
> > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > + #reset-cells = <1>;
> > > > > > + };
> > > > > > +
> > > > > > + gpc: gpc at 303a0000 {
> > > > > > + compatible =
> > > > > > "fsl,imx8mm-gpc", "syscon";
> > > > > > + reg = <0x0 0x303a0000 0x0
> > > > > > 0x10000>;
> > > > > > + interrupt-controller;
> > > > > > + interrupts = <GIC_SPI 87
> > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > + #interrupt-cells = <3>;
> > > > > > + };
> > > > > > + };
> > > > > > +
> > > > > > + aips2: bus at 30400000 {
> > > > > > + compatible = "fsl,aips-bus",
> > > > > > "simple-bus";
> > > > > > + #address-cells = <2>;
> > > > > > + #size-cells = <2>;
> > > > > > + reg = <0x0 0x30400000 0x0 0x400000>;
> > > > > > + ranges;
> > > > > > +
> > > > > > + pwm1: pwm at 30660000 {
> > > > > > + compatible =
> > > > > > "fsl,imx8mm-pwm", "fsl,imx27-pwm";
> > > > > > + reg = <0x0 0x30660000 0x0
> > > > > > 0x10000>;
> > > > > > + interrupts = <GIC_SPI 81
> > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > + clocks = <&clk
> > > > > > IMX8MM_CLK_PWM1_ROOT>,
> > > > > > + <&clk
> > > > > > IMX8MM_CLK_PWM1_ROOT>;
> > > > > > + clock-names = "ipg", "per";
> > > > > > + #pwm-cells = <2>;
> > > > > > + status = "disabled";
> > > > > > + };
> > > > > > +
> > > > > > + pwm2: pwm at 30670000 {
> > > > > > + compatible =
> > > > > > "fsl,imx8mm-pwm", "fsl,imx27-pwm";
> > > > > > + reg = <0x0 0x30670000 0x0
> > > > > > 0x10000>;
> > > > > > + interrupts = <GIC_SPI 82
> > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > + clocks = <&clk
> > > > > > IMX8MM_CLK_PWM2_ROOT>,
> > > > > > + <&clk
> > > > > > IMX8MM_CLK_PWM2_ROOT>;
> > > > > > + clock-names = "ipg", "per";
> > > > > > + #pwm-cells = <2>;
> > > > > > + status = "disabled";
> > > > > > + };
> > > > > > +
> > > > > > + pwm3: pwm at 30680000 {
> > > > > > + compatible =
> > > > > > "fsl,imx8mm-pwm", "fsl,imx27-pwm";
> > > > > > + reg = <0x0 0x30680000 0x0
> > > > > > 0x10000>;
> > > > > > + interrupts = <GIC_SPI 83
> > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > + clocks = <&clk
> > > > > > IMX8MM_CLK_PWM3_ROOT>,
> > > > > > + <&clk
> > > > > > IMX8MM_CLK_PWM3_ROOT>;
> > > > > > + clock-names = "ipg", "per";
> > > > > > + #pwm-cells = <2>;
> > > > > > + status = "disabled";
> > > > > > + };
> > > > > > +
> > > > > > + pwm4: pwm at 30690000 {
> > > > > > + compatible =
> > > > > > "fsl,imx8mm-pwm", "fsl,imx27-pwm";
> > > > > > + reg = <0x0 0x30690000 0x0
> > > > > > 0x10000>;
> > > > > > + interrupts = <GIC_SPI 84
> > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > + clocks = <&clk
> > > > > > IMX8MM_CLK_PWM4_ROOT>,
> > > > > > + <&clk
> > > > > > IMX8MM_CLK_PWM4_ROOT>;
> > > > > > + clock-names = "ipg", "per";
> > > > > > + #pwm-cells = <2>;
> > > > > > + status = "disabled";
> > > > > > + };
> > > > > > + };
> > > > > > +
> > > > > > + aips3: bus at 30800000 {
> > > > > > + compatible = "fsl,aips-bus",
> > > > > > "simple-bus";
> > > > > > + #address-cells = <2>;
> > > > > > + #size-cells = <2>;
> > > > > > + reg = <0x0 0x30800000 0x0 0x400000>;
> > > > > > + ranges;
> > > > > > +
> > > > > > + ecspi1: ecspi at 30820000 {
> > > > > > + #address-cells = <1>;
> > > > > > + #size-cells = <0>;
> > > > > > + compatible =
> > > > > > "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
> > > > > > + reg = <0x0 0x30820000 0x0
> > > > > > 0x10000>;
> > > > > > + interrupts = <GIC_SPI 31
> > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > + clocks = <&clk
> > > > > > IMX8MM_CLK_ECSPI1_ROOT>,
> > > > > > + <&clk
> > > > > > IMX8MM_CLK_ECSPI1_ROOT>;
> > > > > > + clock-names = "ipg", "per";
> > > > > > + status = "disabled";
> > > > > > + };
> > > > > > +
> > > > > > + ecspi2: ecspi at 30830000 {
> > > > > > + #address-cells = <1>;
> > > > > > + #size-cells = <0>;
> > > > > > + compatible =
> > > > > > "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
> > > > > > + reg = <0x0 0x30830000 0x0
> > > > > > 0x10000>;
> > > > > > + interrupts = <GIC_SPI 32
> > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > + clocks = <&clk
> > > > > > IMX8MM_CLK_ECSPI2_ROOT>,
> > > > > > + <&clk
> > > > > > IMX8MM_CLK_ECSPI2_ROOT>;
> > > > > > + clock-names = "ipg", "per";
> > > > > > + status = "disabled";
> > > > > > + };
> > > > > > +
> > > > > > + ecspi3: ecspi at 30840000 {
> > > > > > + #address-cells = <1>;
> > > > > > + #size-cells = <0>;
> > > > > > + compatible =
> > > > > > "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
> > > > > > + reg = <0x0 0x30840000 0x0
> > > > > > 0x10000>;
> > > > > > + interrupts = <GIC_SPI 33
> > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > + clocks = <&clk
> > > > > > IMX8MM_CLK_ECSPI3_ROOT>,
> > > > > > + <&clk
> > > > > > IMX8MM_CLK_ECSPI3_ROOT>;
> > > > > > + clock-names = "ipg", "per";
> > > > > > + status = "disabled";
> > > > > > + };
> > > > > > +
> > > > > > + uart1: serial at 30860000 {
> > > > > > + compatible =
> > > > > > "fsl,imx8mm-uart",
> > > > > > +
> > > > > > "fsl,imx6q-uart", "fsl,imx21-uart";
> > > > > > + reg = <0x0 0x30860000 0x0
> > > > > > 0x10000>;
> > > > > > + interrupts = <GIC_SPI 26
> > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > + clocks = <&clk
> > > > > > IMX8MM_CLK_UART1_ROOT>,
> > > > > > + <&clk
> > > > > > IMX8MM_CLK_UART1_ROOT>;
> > > > > > + clock-names = "ipg", "per";
> > > > > > + status = "disabled";
> > > > > > + };
> > > > > > +
> > > > > > + uart3: serial at 30880000 {
> > > > > > + compatible =
> > > > > > "fsl,imx8mm-uart",
> > > > > > +
> > > > > > "fsl,imx6q-uart", "fsl,imx21-uart";
> > > > > > + reg = <0x0 0x30880000 0x0
> > > > > > 0x10000>;
> > > > > > + interrupts = <GIC_SPI 28
> > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > + clocks = <&clk
> > > > > > IMX8MM_CLK_UART3_ROOT>,
> > > > > > + <&clk
> > > > > > IMX8MM_CLK_UART3_ROOT>;
> > > > > > + clock-names = "ipg", "per";
> > > > > > + status = "disabled";
> > > > > > + };
> > > > > > +
> > > > > > + uart2: serial at 30890000 {
> > > > > > + compatible =
> > > > > > "fsl,imx8mm-uart",
> > > > > > +
> > > > > > "fsl,imx6q-uart", "fsl,imx21-uart";
> > > > > > + reg = <0x0 0x30890000 0x0
> > > > > > 0x10000>;
> > > > > > + interrupts = <GIC_SPI 27
> > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > + clocks = <&clk
> > > > > > IMX8MM_CLK_UART2_ROOT>,
> > > > > > + <&clk
> > > > > > IMX8MM_CLK_UART2_ROOT>;
> > > > > > + clock-names = "ipg", "per";
> > > > > > + status = "disabled";
> > > > > > + };
> > > > > > +
> > > > > > + i2c1: i2c at 30a20000 {
> > > > > > + #address-cells = <1>;
> > > > > > + #size-cells = <0>;
> > > > > > + compatible =
> > > > > > "fsl,imx8mm-i2c", "fsl,imx21-i2c";
> > > > > > + reg = <0x0 0x30a20000 0x0
> > > > > > 0x10000>;
> > > > > > + interrupts = <GIC_SPI 35
> > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > + clocks = <&clk
> > > > > > IMX8MM_CLK_I2C1_ROOT>;
> > > > > > + status = "disabled";
> > > > > > + };
> > > > > > +
> > > > > > + i2c2: i2c at 30a30000 {
> > > > > > + #address-cells = <1>;
> > > > > > + #size-cells = <0>;
> > > > > > + compatible =
> > > > > > "fsl,imx8mm-i2c", "fsl,imx21-i2c";
> > > > > > + reg = <0x0 0x30a30000 0x0
> > > > > > 0x10000>;
> > > > > > + interrupts = <GIC_SPI 36
> > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > + clocks = <&clk
> > > > > > IMX8MM_CLK_I2C2_ROOT>;
> > > > > > + status = "disabled";
> > > > > > + };
> > > > > > +
> > > > > > + i2c3: i2c at 30a40000 {
> > > > > > + #address-cells = <1>;
> > > > > > + #size-cells = <0>;
> > > > > > + compatible =
> > > > > > "fsl,imx8mm-i2c", "fsl,imx21-i2c";
> > > > > > + reg = <0x0 0x30a40000 0x0
> > > > > > 0x10000>;
> > > > > > + interrupts = <GIC_SPI 37
> > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > + clocks = <&clk
> > > > > > IMX8MM_CLK_I2C3_ROOT>;
> > > > > > + status = "disabled";
> > > > > > + };
> > > > > > +
> > > > > > + i2c4: i2c at 30a50000 {
> > > > > > + #address-cells = <1>;
> > > > > > + #size-cells = <0>;
> > > > > > + compatible =
> > > > > > "fsl,imx8mm-i2c", "fsl,imx21-i2c";
> > > > > > + reg = <0x0 0x30a50000 0x0
> > > > > > 0x10000>;
> > > > > > + interrupts = <GIC_SPI 38
> > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > + clocks = <&clk
> > > > > > IMX8MM_CLK_I2C4_ROOT>;
> > > > > > + status = "disabled";
> > > > > > + };
> > > > > > +
> > > > > > + uart4: serial at 30a60000 {
> > > > > > + compatible =
> > > > > > "fsl,imx8mq-uart",
> > > > > > +
> > > > > > "fsl,imx6q-uart", "fsl,imx21-uart";
> > > > > > + reg = <0x0 0x30a60000 0x0
> > > > > > 0x10000>;
> > > > > > + interrupts = <GIC_SPI 29
> > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > + clocks = <&clk
> > > > > > IMX8MM_CLK_UART4_ROOT>,
> > > > > > + <&clk
> > > > > > IMX8MM_CLK_UART4_ROOT>;
> > > > > > + clock-names = "ipg", "per";
> > > > > > + status = "disabled";
> > > > > > + };
> > > > > > +
> > > > > > + usdhc1: mmc at 30b40000 {
> > > > > > + compatible =
> > > > > > "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc";
> > > > > > + reg = <0x0 0x30b40000 0x0
> > > > > > 0x10000>;
> > > > > > + interrupts = <GIC_SPI 22
> > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > + clocks = <&clk
> > > > > > IMX8MM_CLK_DUMMY>,
> > > > > > + <&clk
> > > > > > IMX8MM_CLK_NAND_USDHC_BUS>,
> > > > > > + <&clk
> > > > > > IMX8MM_CLK_USDHC1_ROOT>;
> > > > > > + clock-names = "ipg", "ahb",
> > > > > > "per";
> > > > > > + assigned-clocks = <&clk
> > > > > > IMX8MM_CLK_USDHC1>;
> > > > > > + assigned-clock-rates =
> > > > > > <400000000>;
> > > > > > + fsl,tuning-start-tap = <20>;
> > > > > > + fsl,tuning-step= <2>;
> > > > > > + bus-width = <4>;
> > > > > > + status = "disabled";
> > > > > > + };
> > > > > > +
> > > > > > + usdhc2: mmc at 30b50000 {
> > > > > > + compatible =
> > > > > > "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc";
> > > > > > + reg = <0x0 0x30b50000 0x0
> > > > > > 0x10000>;
> > > > > > + interrupts = <GIC_SPI 23
> > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > + clocks = <&clk
> > > > > > IMX8MM_CLK_DUMMY>,
> > > > > > + <&clk
> > > > > > IMX8MM_CLK_NAND_USDHC_BUS>,
> > > > > > + <&clk
> > > > > > IMX8MM_CLK_USDHC2_ROOT>;
> > > > > > + clock-names = "ipg", "ahb",
> > > > > > "per";
> > > > > > + fsl,tuning-start-tap = <20>;
> > > > > > + fsl,tuning-step= <2>;
> > > > > > + bus-width = <4>;
> > > > > > + status = "disabled";
> > > > > > + };
> > > > > > +
> > > > > > + usdhc3: mmc at 30b60000 {
> > > > > > + compatible =
> > > > > > "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc";
> > > > > > + reg = <0x0 0x30b60000 0x0
> > > > > > 0x10000>;
> > > > > > + interrupts = <GIC_SPI 24
> > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > + clocks = <&clk
> > > > > > IMX8MM_CLK_DUMMY>,
> > > > > > + <&clk
> > > > > > IMX8MM_CLK_NAND_USDHC_BUS>,
> > > > > > + <&clk
> > > > > > IMX8MM_CLK_USDHC3_ROOT>;
> > > > > > + clock-names = "ipg", "ahb",
> > > > > > "per";
> > > > > > + assigned-clocks = <&clk
> > > > > > IMX8MM_CLK_USDHC3_ROOT>;
> > > > > > + assigned-clock-rates =
> > > > > > <400000000>;
> > > > > > + fsl,tuning-start-tap = <20>;
> > > > > > + fsl,tuning-step= <2>;
> > > > > > + bus-width = <4>;
> > > > > > + status = "disabled";
> > > > > > + };
> > > > > > + };
> > > > > > + };
> > > > > > +};
> > > > > > diff --git a/arch/arm/mach-imx/imx8m/Kconfig
> > > > > > b/arch/arm/mach-imx/imx8m/Kconfig index
> > > > > > 35c978e863..f520075875
> > > > > 100644
> > > > > > --- a/arch/arm/mach-imx/imx8m/Kconfig
> > > > > > +++ b/arch/arm/mach-imx/imx8m/Kconfig
> > > > > > @@ -24,8 +24,15 @@ config TARGET_IMX8MQ_EVK
> > > > > > select IMX8MQ
> > > > > > select IMX8M_LPDDR4
> > > > > >
> > > > > > +config TARGET_IMX8MM_EVK
> > > > > > + bool "imx8mm LPDDR4 EVK board"
> > > > > > + select IMX8MM
> > > > > > + select SUPPORT_SPL
> > > > > > + select IMX8M_LPDDR4
> > > > >
> > > > > Here you shall put the select DM_{UART,USDHC, etc}
> > > > >
> > > > > > +
> > > > > > endchoice
> > > > > >
> > > > > > source "board/freescale/imx8mq_evk/Kconfig"
> > > > > > +source "board/freescale/imx8mm_evk/Kconfig"
> > > > > >
> > > > > > endif
> > > > > > diff --git a/board/freescale/imx8mm_evk/Kconfig
> > > > > > b/board/freescale/imx8mm_evk/Kconfig new file mode 100644
> > > > > > index 0000000000..299691a619
> > > > > > --- /dev/null
> > > > > > +++ b/board/freescale/imx8mm_evk/Kconfig
> > > > > > @@ -0,0 +1,12 @@
> > > > > > +if TARGET_IMX8MM_EVK
> > > > > > +
> > > > > > +config SYS_BOARD
> > > > > > + default "imx8mm_evk"
> > > > > > +
> > > > > > +config SYS_VENDOR
> > > > > > + default "freescale"
> > > > > > +
> > > > > > +config SYS_CONFIG_NAME
> > > > > > + default "imx8mm_evk"
> > > > > > +
> > > > > > +endif
> > > > > > diff --git a/board/freescale/imx8mm_evk/MAINTAINERS
> > > > > > b/board/freescale/imx8mm_evk/MAINTAINERS new file mode
> 100644
> > > > > > index 0000000000..b031bb0674
> > > > > > --- /dev/null
> > > > > > +++ b/board/freescale/imx8mm_evk/MAINTAINERS
> > > > > > @@ -0,0 +1,6 @@
> > > > > > +i.MX8MM EVK BOARD
> > > > > > +M: Peng Fan <peng.fan@nxp.com>
> > > > > > +S: Maintained
> > > > > > +F: board/freescale/imx8mm_evk/
> > > > > > +F: include/configs/imx8mm_evk.h
> > > > > > +F: configs/imx8mm_evk_defconfig
> > > > > > diff --git a/board/freescale/imx8mm_evk/Makefile
> > > > > > b/board/freescale/imx8mm_evk/Makefile new file mode 100644
> > > > > > index 0000000000..1db7b62caf
> > > > > > --- /dev/null
> > > > > > +++ b/board/freescale/imx8mm_evk/Makefile
> > > > > > @@ -0,0 +1,12 @@
> > > > > > +#
> > > > > > +# Copyright 2018 NXP
> > > > > > +#
> > > > > > +# SPDX-License-Identifier: GPL-2.0+
> > > > > > +#
> > > > > > +
> > > > > > +obj-y += imx8mm_evk.o
> > > > > > +
> > > > > > +ifdef CONFIG_SPL_BUILD
> > > > > > +obj-y += spl.o
> > > > > > +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
> > > > > > +endif
> > > > > > diff --git a/board/freescale/imx8mm_evk/imx8mm_evk.c
> > > > > > b/board/freescale/imx8mm_evk/imx8mm_evk.c new file mode
> 100644
> > > > > > index 0000000000..a681aca04d
> > > > > > --- /dev/null
> > > > > > +++ b/board/freescale/imx8mm_evk/imx8mm_evk.c
> > > > > > @@ -0,0 +1,144 @@
> > > > > > +// SPDX-License-Identifier: GPL-2.0+
> > > > > > +/*
> > > > > > + * Copyright 2018 NXP
> > > > > > + */
> > > > > > +
> > > > > > +#include <common.h>
> > > > > > +#include <malloc.h>
> > > > > > +#include <errno.h>
> > > > > > +#include <asm/io.h>
> > > > > > +#include <miiphy.h>
> > > > > > +#include <netdev.h>
> > > > > > +#include <asm/mach-imx/iomux-v3.h>
> > > > > > +#include <asm-generic/gpio.h>
> > > > > > +#include <fsl_esdhc.h>
> > > > > > +#include <mmc.h>
> > > > > > +#include <asm/arch/imx8mm_pins.h>
> > > > > > +#include <asm/arch/sys_proto.h>
> > > > > > +#include <asm/mach-imx/gpio.h>
> > > > > > +#include <asm/mach-imx/mxc_i2c.h>
> > > > > > +#include <asm/arch/clock.h>
> > > > > > +#include <spl.h>
> > > > > > +#include <asm/mach-imx/dma.h>
> > > > > > +
> > > > > > +DECLARE_GLOBAL_DATA_PTR;
> > > > > > +
> > > > > > +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
> > > > > > +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE |
> > > > > > PAD_CTL_PUE | PAD_CTL_PE) +
> > > > > > +static iomux_v3_cfg_t const uart_pads[] = {
> > > > > > + IMX8MM_PAD_UART2_RXD_UART2_RX |
> > > > > MUX_PAD_CTRL(UART_PAD_CTRL),
> > > > > > + IMX8MM_PAD_UART2_TXD_UART2_TX |
> > > > > MUX_PAD_CTRL(UART_PAD_CTRL),
> > > > > > +};
> > > > > > +
> > > > > > +static iomux_v3_cfg_t const wdog_pads[] = {
> > > > > > + IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B |
> > > > > > MUX_PAD_CTRL(WDOG_PAD_CTRL), +};
> > > > > > +
> > > > > > +int board_early_init_f(void)
> > > > > > +{
> > > > > > + struct wdog_regs *wdog = (struct wdog_regs
> > > > > > *)WDOG1_BASE_ADDR; +
> > > > > > + imx_iomux_v3_setup_multiple_pads(wdog_pads,
> > > > > > ARRAY_SIZE(wdog_pads)); +
> > > > > > + set_wdog_reset(wdog);
> > > > > > +
> > > > > > + imx_iomux_v3_setup_multiple_pads(uart_pads,
> > > > > > ARRAY_SIZE(uart_pads)); +
> > > > > > + return 0;
> > > > > > +}
> > > > > > +
> > > > > > +#ifdef CONFIG_BOARD_POSTCLK_INIT
> > > > > > +int board_postclk_init(void)
> > > > > > +{
> > > > > > + /* TODO */
> > > > > > + return 0;
> > > > > > +}
> > > > > > +#endif
> > > > > > +
> > > > > > +int dram_init(void)
> > > > > > +{
> > > > > > + /* rom_pointer[1] contains the size of TEE occupies
> > > > > > */
> > > > > > + if (rom_pointer[1])
> > > > > > + gd->ram_size = PHYS_SDRAM_SIZE -
> > > > > > rom_pointer[1];
> > > > > > + else
> > > > > > + gd->ram_size = PHYS_SDRAM_SIZE;
> > > > > > +
> > > > > > + return 0;
> > > > > > +}
> > > > > > +
> > > > > > +#ifdef CONFIG_OF_BOARD_SETUP
> > > > > > +int ft_board_setup(void *blob, bd_t *bd)
> > > > > ^^^ - fdt_board_setup ?
> > > > > > +{
> > > > > > + return 0;
> > > > > > +}
> > > > > > +#endif
> > > > > > +
> > > > > > +#ifdef CONFIG_FEC_MXC
> > > > > > +#define FEC_RST_PAD IMX_GPIO_NR(4, 22)
> > > > > > +static iomux_v3_cfg_t const fec1_rst_pads[] = {
> > > > > > + IMX8MM_PAD_SAI2_RXC_GPIO4_IO22 |
> > > > > MUX_PAD_CTRL(NO_PAD_CTRL),
> > > > >
> > > > > This shall be done with fsl_fec.c DM driver - there is support
> > > > > for adding reset pin (to dts).
> > > > >
> > > > > > +};
> > > > > > +
> > > > > > +static void setup_iomux_fec(void)
> > > > > > +{
> > > > > > + imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
> > > > > > +
> > > > > > ARRAY_SIZE(fec1_rst_pads)); +
> > > > > > + gpio_request(FEC_RST_PAD, "fec1_rst");
> > > > > > + gpio_direction_output(FEC_RST_PAD, 0);
> > > > > > + udelay(500);
> > > > > > + gpio_direction_output(FEC_RST_PAD, 1);
> > > > > > +}
> > > > >
> > > > > This shall be replaced with DM/DTS of the fsl_fec.c driver.
> > > > > Please also note that there are (at least on imx6q) some timing
> > > > > issues when we move the code to DM/DTS (some delay is needed).
> > > > >
> > > > > > +
> > > > > > +static int setup_fec(void)
> > > > > > +{
> > > > > > + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
> > > > > > + = (struct iomuxc_gpr_base_regs
> > > > > > *)IOMUXC_GPR_BASE_ADDR; +
> > > > > > + setup_iomux_fec();
> > > > > > +
> > > > > > + /* Use 125M anatop REF_CLK1 for ENET1, not from
> > > > > > external */
> > > > > > + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
> > > > > > +
> > > > > > IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT, 0);
> > > > > > + return set_clk_enet(ENET_125MHZ);
> > > > > > +}
> > > > > > +
> > > > > > +int board_phy_config(struct phy_device *phydev)
> > > > > > +{
> > > > > > + /* enable rgmii rxc skew and phy mode select to RGMII
> > > > > > copper */
> > > > > > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
> > > > > > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
> > > > > > +
> > > > > > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
> > > > > > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
> > > > > > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
> > > > > > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
> > > > > > +
> > > > > > + if (phydev->drv->config)
> > > > > > + phydev->drv->config(phydev);
> > > > > > + return 0;
> > > > >
> > > > > Which PHY do you use? E.g. KSZ... support passing those values
> > > > > via DTS.
> > > > > > +}
> > > > > > +#endif
> > > > > > +
> > > > > > +int board_init(void)
> > > > > > +{
> > > > > > +#ifdef CONFIG_FEC_MXC
> > > > > > + setup_fec();
> > > > > > +#endif
> > > > > > + return 0;
> > > > > > +}
> > > > > > +
> > > > > > +int board_mmc_get_env_dev(int devno)
> > > > > > +{
> > > > > > + return devno - 1;
> > > > > > +}
> > > > > > +
> > > > > > +int board_late_init(void)
> > > > > > +{
> > > > > > +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> > > > > > + env_set("board_name", "EVK");
> > > > > > + env_set("board_rev", "iMX8MM");
> > > > > > +#endif
> > > > > > + return 0;
> > > > > > +}
> > > > > > diff --git a/board/freescale/imx8mm_evk/lpddr4_timing.c
> > > > > > b/board/freescale/imx8mm_evk/lpddr4_timing.c new file mode
> > > > > > 100644 index 0000000000..4bade5bf74
> > > > > > --- /dev/null
> > > > > > +++ b/board/freescale/imx8mm_evk/lpddr4_timing.c
> > > > > > @@ -0,0 +1,1980 @@
> > > > > > +// SPDX-License-Identifier: GPL-2.0+
> > > > > > +/*
> > > > > > + * Copyright 2018 NXP
> > > > >
> > > > > Author is missing.
> > > > >
> > > > > > + */
> > > > > > +
> > > > > > +#include <linux/kernel.h>
> > > > > > +#include <common.h>
> > > > > > +#include <asm/arch/ddr.h>
> > > > > > +#include <asm/arch/lpddr4_define.h>
> > > > > > +
> > > > > > +struct dram_cfg_param lpddr4_ddrc_cfg[] = {
> > > > > > + /* Start to config, default 3200mbps */
> > > > > > + { DDRC_DBG1(0), 0x00000001 },
> > > > > > + { DDRC_PWRCTL(0), 0x00000001 },
> > > > > > + { DDRC_MSTR(0), 0xa1080020 },
> > > > > > + { DDRC_RFSHTMG(0), 0x005b00d2 },
> > > > > > + { DDRC_INIT0(0), 0xC003061B },
> > > > > > + { DDRC_INIT1(0), 0x009D0000 },
> > > > > > + { DDRC_INIT3(0), 0x00D4002D },
> > > > > > + { DDRC_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 },
> > > > > > + { DDRC_INIT6(0), 0x0066004a },
> > > > > > + { DDRC_INIT7(0), 0x0006004a },
> > > > > > +
> > > > > > + { DDRC_DRAMTMG0(0), 0x1A201B22 },
> > > > > > + { DDRC_DRAMTMG1(0), 0x00060633 },
> > > > > > + { DDRC_DRAMTMG3(0), 0x00C0C000 },
> > > > > > + { DDRC_DRAMTMG4(0), 0x0F04080F },
> > > > > > + { DDRC_DRAMTMG5(0), 0x02040C0C },
> > > > > > + { DDRC_DRAMTMG6(0), 0x01010007 },
> > > > > > + { DDRC_DRAMTMG7(0), 0x00000401 },
> > > > > > + { DDRC_DRAMTMG12(0), 0x00020600 },
> > > > > > + { DDRC_DRAMTMG13(0), 0x0C100002 },
> > > > > > + { DDRC_DRAMTMG14(0), 0x000000E6 },
> > > > > > + { DDRC_DRAMTMG17(0), 0x00A00050 },
> > > > > > +
> > > > > > + { DDRC_ZQCTL0(0), 0x03200018 },
> > > > > > + { DDRC_ZQCTL1(0), 0x028061A8 },
> > > > > > + { DDRC_ZQCTL2(0), 0x00000000 },
> > > > > > +
> > > > > > + { DDRC_DFITMG0(0), 0x0497820A },
> > > > > > + { DDRC_DFITMG2(0), 0x0000170A },
> > > > > > + { DDRC_DRAMTMG2(0), 0x070E171a },
> > > > > > + { DDRC_DBICTL(0), 0x00000001 },
> > > > > > +
> > > > > > + { DDRC_DFITMG1(0), 0x00080303 },
> > > > > > + { DDRC_DFIUPD0(0), 0xE0400018 },
> > > > > > + { DDRC_DFIUPD1(0), 0x00DF00E4 },
> > > > > > + { DDRC_DFIUPD2(0), 0x80000000 },
> > > > > > + { DDRC_DFIMISC(0), 0x00000011 },
> > > > > > +
> > > > > > + { DDRC_DFIPHYMSTR(0), 0x00000000 },
> > > > > > + { DDRC_RANKCTL(0), 0x00000c99 },
> > > > > > +
> > > > > > + /* address mapping */
> > > > > > + { DDRC_ADDRMAP0(0), 0x0000001f },
> > > > > > + { DDRC_ADDRMAP1(0), 0x00080808 },
> > > > > > + { DDRC_ADDRMAP2(0), 0x00000000 },
> > > > > > + { DDRC_ADDRMAP3(0), 0x00000000 },
> > > > > > + { DDRC_ADDRMAP4(0), 0x00001f1f },
> > > > > > + { DDRC_ADDRMAP5(0), 0x07070707 },
> > > > > > + { DDRC_ADDRMAP6(0), 0x07070707 },
> > > > > > + { DDRC_ADDRMAP7(0), 0x00000f0f },
> > > > > > +
> > > > > > + /* performance setting */
> > > > > > + { DDRC_SCHED(0), 0x29001701 },
> > > > > > + { DDRC_SCHED1(0), 0x0000002c },
> > > > > > + { DDRC_PERFHPR1(0), 0x04000030 },
> > > > > > + { DDRC_PERFLPR1(0), 0x900093e7 },
> > > > > > + { DDRC_PERFWR1(0), 0x20005574 },
> > > > > > + { DDRC_PCCFG(0), 0x00000111 },
> > > > > > + { DDRC_PCFGW_0(0), 0x000072ff },
> > > > > > + { DDRC_PCFGQOS0_0(0), 0x02100e07 },
> > > > > > + { DDRC_PCFGQOS1_0(0), 0x00620096 },
> > > > > > + { DDRC_PCFGWQOS0_0(0), 0x01100e07 },
> > > > > > + { DDRC_PCFGWQOS1_0(0), 0x00c8012c },
> > > > > > +
> > > > > > + /* frequency P1&P2 */
> > > > > > + /* Frequency 1: 400mbps */
> > > > > > + { DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c },
> > > > > > + { DDRC_FREQ1_DRAMTMG1(0), 0x00030410 },
> > > > > > + { DDRC_FREQ1_DRAMTMG2(0), 0x0203090c },
> > > > > > + { DDRC_FREQ1_DRAMTMG3(0), 0x00505006 },
> > > > > > + { DDRC_FREQ1_DRAMTMG4(0), 0x05040305 },
> > > > > > + { DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504 },
> > > > > > + { DDRC_FREQ1_DRAMTMG6(0), 0x0a060004 },
> > > > > > + { DDRC_FREQ1_DRAMTMG7(0), 0x0000090e },
> > > > > > + { DDRC_FREQ1_DRAMTMG14(0), 0x00000032 },
> > > > > > + { DDRC_FREQ1_DRAMTMG15(0), 0x00000000 },
> > > > > > + { DDRC_FREQ1_DRAMTMG17(0), 0x0036001b },
> > > > > > + { DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1 },
> > > > > > + { DDRC_FREQ1_DFITMG0(0), 0x03818200 },
> > > > > > + { DDRC_FREQ1_DFITMG2(0), 0x00000000 },
> > > > > > + { DDRC_FREQ1_RFSHTMG(0), 0x000C001c },
> > > > > > + { DDRC_FREQ1_INIT3(0), 0x00840000 },
> > > > > > + { DDRC_FREQ1_INIT4(0), 0x00310000 },
> > > > > > + { DDRC_FREQ1_INIT6(0), 0x0066004a },
> > > > > > + { DDRC_FREQ1_INIT7(0), 0x0006004a },
> > > > > > +
> > > > > > + /* Frequency 2: 100mbps */
> > > > > > + { DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c },
> > > > > > + { DDRC_FREQ2_DRAMTMG1(0), 0x00030410 },
> > > > > > + { DDRC_FREQ2_DRAMTMG2(0), 0x0203090c },
> > > > > > + { DDRC_FREQ2_DRAMTMG3(0), 0x00505006 },
> > > > > > + { DDRC_FREQ2_DRAMTMG4(0), 0x05040305 },
> > > > > > + { DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504 },
> > > > > > + { DDRC_FREQ2_DRAMTMG6(0), 0x0a060004 },
> > > > > > + { DDRC_FREQ2_DRAMTMG7(0), 0x0000090e },
> > > > > > + { DDRC_FREQ2_DRAMTMG14(0), 0x00000032 },
> > > > > > + { DDRC_FREQ2_DRAMTMG17(0), 0x0036001b },
> > > > > > + { DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1 },
> > > > > > + { DDRC_FREQ2_DFITMG0(0), 0x03818200 },
> > > > > > + { DDRC_FREQ2_DFITMG2(0), 0x00000000 },
> > > > > > + { DDRC_FREQ2_RFSHTMG(0), 0x0003800c },
> > > > > > + { DDRC_FREQ2_RFSHTMG(0), 0x00030007 },
> > > > > > + { DDRC_FREQ2_INIT3(0), 0x00840000 },
> > > > > > + { DDRC_FREQ2_INIT4(0), 0x00310008 },
> > > > > > + { DDRC_FREQ2_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 },
> > > > > > + { DDRC_FREQ2_INIT6(0), 0x0066004a },
> > > > > > + { DDRC_FREQ2_INIT7(0), 0x0006004a },
> > > > > > +
> > > > > > + /* boot start point */
> > > > > > + { DDRC_MSTR2(0), 0x2 }, //DDRC_MSTR2
> > > > > > +};
> > > > > > +
> > > > > > +/* PHY Initialize Configuration */
> > > > > > +struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
> > > > > > + { 0x1005f, 0x1ff },
> > > > > > + { 0x1015f, 0x1ff },
> > > > > > + { 0x1105f, 0x1ff },
> > > > > > + { 0x1115f, 0x1ff },
> > > > > > + { 0x1205f, 0x1ff },
> > > > > > + { 0x1215f, 0x1ff },
> > > > > > + { 0x1305f, 0x1ff },
> > > > > > + { 0x1315f, 0x1ff },
> > > > > > +
> > > > > > + { 0x11005f, 0x1ff },
> > > > > > + { 0x11015f, 0x1ff },
> > > > > > + { 0x11105f, 0x1ff },
> > > > > > + { 0x11115f, 0x1ff },
> > > > > > + { 0x11205f, 0x1ff },
> > > > > > + { 0x11215f, 0x1ff },
> > > > > > + { 0x11305f, 0x1ff },
> > > > > > + { 0x11315f, 0x1ff },
> > > > > > +
> > > > > > + { 0x21005f, 0x1ff },
> > > > > > + { 0x21015f, 0x1ff },
> > > > > > + { 0x21105f, 0x1ff },
> > > > > > + { 0x21115f, 0x1ff },
> > > > > > + { 0x21205f, 0x1ff },
> > > > > > + { 0x21215f, 0x1ff },
> > > > > > + { 0x21305f, 0x1ff },
> > > > > > + { 0x21315f, 0x1ff },
> > > > > > +
> > > > > > + { 0x55, 0x1ff },
> > > > > > + { 0x1055, 0x1ff },
> > > > > > + { 0x2055, 0x1ff },
> > > > > > + { 0x3055, 0x1ff },
> > > > > > + { 0x4055, 0x1ff },
> > > > > > + { 0x5055, 0x1ff },
> > > > > > + { 0x6055, 0x1ff },
> > > > > > + { 0x7055, 0x1ff },
> > > > > > + { 0x8055, 0x1ff },
> > > > > > + { 0x9055, 0x1ff },
> > > > > > +
> > > > > > + { 0x200c5, 0x19 },
> > > > > > + { 0x1200c5, 0x7 },
> > > > > > + { 0x2200c5, 0x7 },
> > > > > > +
> > > > > > + { 0x2002e, 0x2 },
> > > > > > + { 0x12002e, 0x2 },
> > > > > > + { 0x22002e, 0x2 },
> > > > > > +
> > > > > > + { 0x90204, 0x0 },
> > > > > > + { 0x190204, 0x0 },
> > > > > > + { 0x290204, 0x0 },
> > > > > > +
> > > > > > + { 0x20024, 0xab },
> > > > > > + { 0x2003a, 0x0 },
> > > > > > +
> > > > > > + { 0x120024, 0xab },
> > > > > > + { 0x2003a, 0x0 },
> > > > > > +
> > > > > > + { 0x220024, 0xab },
> > > > > > + { 0x2003a, 0x0 },
> > > > > > +
> > > > > > + { 0x20056, 0x3 },
> > > > > > + { 0x120056, 0xa },
> > > > > > + { 0x220056, 0xa },
> > > > > > +
> > > > > > + { 0x1004d, 0xe00 },
> > > > > > + { 0x1014d, 0xe00 },
> > > > > > + { 0x1104d, 0xe00 },
> > > > > > + { 0x1114d, 0xe00 },
> > > > > > + { 0x1204d, 0xe00 },
> > > > > > + { 0x1214d, 0xe00 },
> > > > > > + { 0x1304d, 0xe00 },
> > > > > > + { 0x1314d, 0xe00 },
> > > > > > +
> > > > > > + { 0x11004d, 0xe00 },
> > > > > > + { 0x11014d, 0xe00 },
> > > > > > + { 0x11104d, 0xe00 },
> > > > > > + { 0x11114d, 0xe00 },
> > > > > > + { 0x11204d, 0xe00 },
> > > > > > + { 0x11214d, 0xe00 },
> > > > > > + { 0x11304d, 0xe00 },
> > > > > > + { 0x11314d, 0xe00 },
> > > > > > +
> > > > > > + { 0x21004d, 0xe00 },
> > > > > > + { 0x21014d, 0xe00 },
> > > > > > + { 0x21104d, 0xe00 },
> > > > > > + { 0x21114d, 0xe00 },
> > > > > > + { 0x21204d, 0xe00 },
> > > > > > + { 0x21214d, 0xe00 },
> > > > > > + { 0x21304d, 0xe00 },
> > > > > > + { 0x21314d, 0xe00 },
> > > > > > +
> > > > > > + { 0x10049, 0xfbe },
> > > > > > + { 0x10149, 0xfbe },
> > > > > > + { 0x11049, 0xfbe },
> > > > > > + { 0x11149, 0xfbe },
> > > > > > + { 0x12049, 0xfbe },
> > > > > > + { 0x12149, 0xfbe },
> > > > > > + { 0x13049, 0xfbe },
> > > > > > + { 0x13149, 0xfbe },
> > > > > > +
> > > > > > + { 0x110049, 0xfbe },
> > > > > > + { 0x110149, 0xfbe },
> > > > > > + { 0x111049, 0xfbe },
> > > > > > + { 0x111149, 0xfbe },
> > > > > > + { 0x112049, 0xfbe },
> > > > > > + { 0x112149, 0xfbe },
> > > > > > + { 0x113049, 0xfbe },
> > > > > > + { 0x113149, 0xfbe },
> > > > > > +
> > > > > > + { 0x210049, 0xfbe },
> > > > > > + { 0x210149, 0xfbe },
> > > > > > + { 0x211049, 0xfbe },
> > > > > > + { 0x211149, 0xfbe },
> > > > > > + { 0x212049, 0xfbe },
> > > > > > + { 0x212149, 0xfbe },
> > > > > > + { 0x213049, 0xfbe },
> > > > > > + { 0x213149, 0xfbe },
> > > > > > +
> > > > > > + { 0x43, 0x63 },
> > > > > > + { 0x1043, 0x63 },
> > > > > > + { 0x2043, 0x63 },
> > > > > > + { 0x3043, 0x63 },
> > > > > > + { 0x4043, 0x63 },
> > > > > > + { 0x5043, 0x63 },
> > > > > > + { 0x6043, 0x63 },
> > > > > > + { 0x7043, 0x63 },
> > > > > > + { 0x8043, 0x63 },
> > > > > > + { 0x9043, 0x63 },
> > > > > > +
> > > > > > + { 0x20018, 0x3 },
> > > > > > + { 0x20075, 0x4 },
> > > > > > + { 0x20050, 0x0 },
> > > > > > + { 0x20008, 0x2ee },
> > > > > > + { 0x120008, 0x64 },
> > > > > > + { 0x220008, 0x19 },
> > > > > > + { 0x20088, 0x9 },
> > > > > > +
> > > > > > + { 0x200b2, 0x1d4 },
> > > > > > + { 0x10043, 0x5a1 },
> > > > > > + { 0x10143, 0x5a1 },
> > > > > > + { 0x11043, 0x5a1 },
> > > > > > + { 0x11143, 0x5a1 },
> > > > > > + { 0x12043, 0x5a1 },
> > > > > > + { 0x12143, 0x5a1 },
> > > > > > + { 0x13043, 0x5a1 },
> > > > > > + { 0x13143, 0x5a1 },
> > > > > > +
> > > > > > + { 0x1200b2, 0xdc },
> > > > > > + { 0x110043, 0x5a1 },
> > > > > > + { 0x110143, 0x5a1 },
> > > > > > + { 0x111043, 0x5a1 },
> > > > > > + { 0x111143, 0x5a1 },
> > > > > > + { 0x112043, 0x5a1 },
> > > > > > + { 0x112143, 0x5a1 },
> > > > > > + { 0x113043, 0x5a1 },
> > > > > > + { 0x113143, 0x5a1 },
> > > > > > +
> > > > > > + { 0x2200b2, 0xdc },
> > > > > > + { 0x210043, 0x5a1 },
> > > > > > + { 0x210143, 0x5a1 },
> > > > > > + { 0x211043, 0x5a1 },
> > > > > > + { 0x211143, 0x5a1 },
> > > > > > + { 0x212043, 0x5a1 },
> > > > > > + { 0x212143, 0x5a1 },
> > > > > > + { 0x213043, 0x5a1 },
> > > > > > + { 0x213143, 0x5a1 },
> > > > > > +
> > > > > > + { 0x200fa, 0x1 },
> > > > > > + { 0x1200fa, 0x1 },
> > > > > > + { 0x2200fa, 0x1 },
> > > > > > +
> > > > > > + { 0x20019, 0x1 },
> > > > > > + { 0x120019, 0x1 },
> > > > > > + { 0x220019, 0x1 },
> > > > > > +
> > > > > > + { 0x200f0, 0x660 },
> > > > > > + { 0x200f1, 0x0 },
> > > > > > + { 0x200f2, 0x4444 },
> > > > > > + { 0x200f3, 0x8888 },
> > > > > > + { 0x200f4, 0x5665 },
> > > > > > + { 0x200f5, 0x0 },
> > > > > > + { 0x200f6, 0x0 },
> > > > > > + { 0x200f7, 0xf000 },
> > > > > > +
> > > > > > + { 0x20025, 0x0 },
> > > > > > + { 0x2002d, LPDDR4_PHY_DMIPinPresent },
> > > > > > + { 0x12002d, LPDDR4_PHY_DMIPinPresent },
> > > > > > + { 0x22002d, LPDDR4_PHY_DMIPinPresent },
> > > > > > + { 0x200c7, 0x21 },
> > > > > > + { 0x200ca, 0x24 },
> > > > > > + { 0x1200c7, 0x21 },
> > > > > > + { 0x1200ca, 0x24 },
> > > > > > + { 0x2200c7, 0x21 },
> > > > > > + { 0x2200ca, 0x24 },
> > > > >
> > > > > Why do you add tuple - offset and value? Shouldn't we have the
> > > > > DDR training functions here?
> > > > >
> > > > > It is possible to train IMX6Q and Vybrid's DDR3 (as fair as I
> > > > > know). Would it be also possible to add the DDR4 training code
> > > > > for IMX8?
> > > > > > +};
> > > > > > +
> > > > > > +/* ddr phy trained csr */
> > > > > > +struct dram_cfg_param lpddr4_ddrphy_trained_csr[] = {
> > > > > > + { 0x200b2, 0x0 },
> > > > > > + { 0x1200b2, 0x0 },
> > > > > > + { 0x2200b2, 0x0 },
> > > > > > + { 0x200cb, 0x0 },
> > > > > > + { 0x10043, 0x0 },
> > > > > > + { 0x110043, 0x0 },
> > > > > > + { 0x210043, 0x0 },
> > > > > > + { 0x10143, 0x0 },
> > > > > > + { 0x110143, 0x0 },
> > > > > > + { 0x210143, 0x0 },
> > > > > > + { 0x11043, 0x0 },
> > > > > > + { 0x111043, 0x0 },
> > > > > > + { 0x211043, 0x0 },
> > > > > > + { 0x11143, 0x0 },
> > > > > > + { 0x111143, 0x0 },
> > > > > > + { 0x211143, 0x0 },
> > > > > > + { 0x12043, 0x0 },
> > > > > > + { 0x112043, 0x0 },
> > > > > > + { 0x212043, 0x0 },
> > > > > > + { 0x12143, 0x0 },
> > > > > > + { 0x112143, 0x0 },
> > > > > > + { 0x212143, 0x0 },
> > > > > > + { 0x13043, 0x0 },
> > > > > > + { 0x113043, 0x0 },
> > > > > > + { 0x213043, 0x0 },
> > > > > > + { 0x13143, 0x0 },
> > > > > > + { 0x113143, 0x0 },
> > > > > > + { 0x213143, 0x0 },
> > > > > > + { 0x80, 0x0 },
> > > > > > + { 0x100080, 0x0 },
> > > > > > + { 0x200080, 0x0 },
> > > > > > + { 0x1080, 0x0 },
> > > > > > + { 0x101080, 0x0 },
> > > > > > + { 0x201080, 0x0 },
> > > > > > + { 0x2080, 0x0 },
> > > > > > + { 0x102080, 0x0 },
> > > > > > + { 0x202080, 0x0 },
> > > > > > + { 0x3080, 0x0 },
> > > > > > + { 0x103080, 0x0 },
> > > > > > + { 0x203080, 0x0 },
> > > > > > + { 0x4080, 0x0 },
> > > > > > + { 0x104080, 0x0 },
> > > > > > + { 0x204080, 0x0 },
> > > > > > + { 0x5080, 0x0 },
> > > > > > + { 0x105080, 0x0 },
> > > > > > + { 0x205080, 0x0 },
> > > > > > + { 0x6080, 0x0 },
> > > > > > + { 0x106080, 0x0 },
> > > > > > + { 0x206080, 0x0 },
> > > > > > + { 0x7080, 0x0 },
> > > > > > + { 0x107080, 0x0 },
> > > > > > + { 0x207080, 0x0 },
> > > > > > + { 0x8080, 0x0 },
> > > > > > + { 0x108080, 0x0 },
> > > > > > + { 0x208080, 0x0 },
> > > > > > + { 0x9080, 0x0 },
> > > > > > + { 0x109080, 0x0 },
> > > > > > + { 0x209080, 0x0 },
> > > > > > + { 0x10080, 0x0 },
> > > > > > + { 0x110080, 0x0 },
> > > > > > + { 0x210080, 0x0 },
> > > > > > + { 0x10180, 0x0 },
> > > > > > + { 0x110180, 0x0 },
> > > > > > + { 0x210180, 0x0 },
> > > > > > + { 0x11080, 0x0 },
> > > > > > + { 0x111080, 0x0 },
> > > > > > + { 0x211080, 0x0 },
> > > > > > + { 0x11180, 0x0 },
> > > > > > + { 0x111180, 0x0 },
> > > > > > + { 0x211180, 0x0 },
> > > > > > + { 0x12080, 0x0 },
> > > > > > + { 0x112080, 0x0 },
> > > > > > + { 0x212080, 0x0 },
> > > > > > + { 0x12180, 0x0 },
> > > > > > + { 0x112180, 0x0 },
> > > > > > + { 0x212180, 0x0 },
> > > > > > + { 0x13080, 0x0 },
> > > > > > + { 0x113080, 0x0 },
> > > > > > + { 0x213080, 0x0 },
> > > > > > + { 0x13180, 0x0 },
> > > > > > + { 0x113180, 0x0 },
> > > > > > + { 0x213180, 0x0 },
> > > > > > + { 0x10081, 0x0 },
> > > > > > + { 0x110081, 0x0 },
> > > > > > + { 0x210081, 0x0 },
> > > > > > + { 0x10181, 0x0 },
> > > > > > + { 0x110181, 0x0 },
> > > > > > + { 0x210181, 0x0 },
> > > > > > + { 0x11081, 0x0 },
> > > > > > + { 0x111081, 0x0 },
> > > > > > + { 0x211081, 0x0 },
> > > > > > + { 0x11181, 0x0 },
> > > > > > + { 0x111181, 0x0 },
> > > > > > + { 0x211181, 0x0 },
> > > > > > + { 0x12081, 0x0 },
> > > > > > + { 0x112081, 0x0 },
> > > > > > + { 0x212081, 0x0 },
> > > > > > + { 0x12181, 0x0 },
> > > > > > + { 0x112181, 0x0 },
> > > > > > + { 0x212181, 0x0 },
> > > > > > + { 0x13081, 0x0 },
> > > > > > + { 0x113081, 0x0 },
> > > > > > + { 0x213081, 0x0 },
> > > > > > + { 0x13181, 0x0 },
> > > > > > + { 0x113181, 0x0 },
> > > > > > + { 0x213181, 0x0 },
> > > > > > + { 0x100d0, 0x0 },
> > > > > > + { 0x1100d0, 0x0 },
> > > > > > + { 0x2100d0, 0x0 },
> > > > > > + { 0x101d0, 0x0 },
> > > > > > + { 0x1101d0, 0x0 },
> > > > > > + { 0x2101d0, 0x0 },
> > > > > > + { 0x110d0, 0x0 },
> > > > > > + { 0x1110d0, 0x0 },
> > > > > > + { 0x2110d0, 0x0 },
> > > > > > + { 0x111d0, 0x0 },
> > > > > > + { 0x1111d0, 0x0 },
> > > > > > + { 0x2111d0, 0x0 },
> > > > > > + { 0x120d0, 0x0 },
> > > > > > + { 0x1120d0, 0x0 },
> > > > > > + { 0x2120d0, 0x0 },
> > > > > > + { 0x121d0, 0x0 },
> > > > > > + { 0x1121d0, 0x0 },
> > > > > > + { 0x2121d0, 0x0 },
> > > > > > + { 0x130d0, 0x0 },
> > > > > > + { 0x1130d0, 0x0 },
> > > > > > + { 0x2130d0, 0x0 },
> > > > > > + { 0x131d0, 0x0 },
> > > > > > + { 0x1131d0, 0x0 },
> > > > > > + { 0x2131d0, 0x0 },
> > > > > > + { 0x100d1, 0x0 },
> > > > > > + { 0x1100d1, 0x0 },
> > > > > > + { 0x2100d1, 0x0 },
> > > > > > + { 0x101d1, 0x0 },
> > > > > > + { 0x1101d1, 0x0 },
> > > > > > + { 0x2101d1, 0x0 },
> > > > > > + { 0x110d1, 0x0 },
> > > > > > + { 0x1110d1, 0x0 },
> > > > > > + { 0x2110d1, 0x0 },
> > > > > > + { 0x111d1, 0x0 },
> > > > > > + { 0x1111d1, 0x0 },
> > > > > > + { 0x2111d1, 0x0 },
> > > > > > + { 0x120d1, 0x0 },
> > > > > > + { 0x1120d1, 0x0 },
> > > > > > + { 0x2120d1, 0x0 },
> > > > > > + { 0x121d1, 0x0 },
> > > > > > + { 0x1121d1, 0x0 },
> > > > > > + { 0x2121d1, 0x0 },
> > > > > > + { 0x130d1, 0x0 },
> > > > > > + { 0x1130d1, 0x0 },
> > > > > > + { 0x2130d1, 0x0 },
> > > > > > + { 0x131d1, 0x0 },
> > > > > > + { 0x1131d1, 0x0 },
> > > > > > + { 0x2131d1, 0x0 },
> > > > > > + { 0x10068, 0x0 },
> > > > > > + { 0x10168, 0x0 },
> > > > > > + { 0x10268, 0x0 },
> > > > > > + { 0x10368, 0x0 },
> > > > > > + { 0x10468, 0x0 },
> > > > > > + { 0x10568, 0x0 },
> > > > > > + { 0x10668, 0x0 },
> > > > > > + { 0x10768, 0x0 },
> > > > > > + { 0x10868, 0x0 },
> > > > > > + { 0x11068, 0x0 },
> > > > > > + { 0x11168, 0x0 },
> > > > > > + { 0x11268, 0x0 },
> > > > > > + { 0x11368, 0x0 },
> > > > > > + { 0x11468, 0x0 },
> > > > > > + { 0x11568, 0x0 },
> > > > > > + { 0x11668, 0x0 },
> > > > > > + { 0x11768, 0x0 },
> > > > > > + { 0x11868, 0x0 },
> > > > > > + { 0x12068, 0x0 },
> > > > > > + { 0x12168, 0x0 },
> > > > > > + { 0x12268, 0x0 },
> > > > > > + { 0x12368, 0x0 },
> > > > > > + { 0x12468, 0x0 },
> > > > > > + { 0x12568, 0x0 },
> > > > > > + { 0x12668, 0x0 },
> > > > > > + { 0x12768, 0x0 },
> > > > > > + { 0x12868, 0x0 },
> > > > > > + { 0x13068, 0x0 },
> > > > > > + { 0x13168, 0x0 },
> > > > > > + { 0x13268, 0x0 },
> > > > > > + { 0x13368, 0x0 },
> > > > > > + { 0x13468, 0x0 },
> > > > > > + { 0x13568, 0x0 },
> > > > > > + { 0x13668, 0x0 },
> > > > > > + { 0x13768, 0x0 },
> > > > > > + { 0x13868, 0x0 },
> > > > > > + { 0x10069, 0x0 },
> > > > > > + { 0x10169, 0x0 },
> > > > > > + { 0x10269, 0x0 },
> > > > > > + { 0x10369, 0x0 },
> > > > > > + { 0x10469, 0x0 },
> > > > > > + { 0x10569, 0x0 },
> > > > > > + { 0x10669, 0x0 },
> > > > > > + { 0x10769, 0x0 },
> > > > > > + { 0x10869, 0x0 },
> > > > > > + { 0x11069, 0x0 },
> > > > > > + { 0x11169, 0x0 },
> > > > > > + { 0x11269, 0x0 },
> > > > > > + { 0x11369, 0x0 },
> > > > > > + { 0x11469, 0x0 },
> > > > > > + { 0x11569, 0x0 },
> > > > > > + { 0x11669, 0x0 },
> > > > > > + { 0x11769, 0x0 },
> > > > > > + { 0x11869, 0x0 },
> > > > > > + { 0x12069, 0x0 },
> > > > > > + { 0x12169, 0x0 },
> > > > > > + { 0x12269, 0x0 },
> > > > > > + { 0x12369, 0x0 },
> > > > > > + { 0x12469, 0x0 },
> > > > > > + { 0x12569, 0x0 },
> > > > > > + { 0x12669, 0x0 },
> > > > > > + { 0x12769, 0x0 },
> > > > > > + { 0x12869, 0x0 },
> > > > > > + { 0x13069, 0x0 },
> > > > > > + { 0x13169, 0x0 },
> > > > > > + { 0x13269, 0x0 },
> > > > > > + { 0x13369, 0x0 },
> > > > > > + { 0x13469, 0x0 },
> > > > > > + { 0x13569, 0x0 },
> > > > > > + { 0x13669, 0x0 },
> > > > > > + { 0x13769, 0x0 },
> > > > > > + { 0x13869, 0x0 },
> > > > > > + { 0x1008c, 0x0 },
> > > > > > + { 0x11008c, 0x0 },
> > > > > > + { 0x21008c, 0x0 },
> > > > > > + { 0x1018c, 0x0 },
> > > > > > + { 0x11018c, 0x0 },
> > > > > > + { 0x21018c, 0x0 },
> > > > > > + { 0x1108c, 0x0 },
> > > > > > + { 0x11108c, 0x0 },
> > > > > > + { 0x21108c, 0x0 },
> > > > > > + { 0x1118c, 0x0 },
> > > > > > + { 0x11118c, 0x0 },
> > > > > > + { 0x21118c, 0x0 },
> > > > > > + { 0x1208c, 0x0 },
> > > > > > + { 0x11208c, 0x0 },
> > > > > > + { 0x21208c, 0x0 },
> > > > > > + { 0x1218c, 0x0 },
> > > > > > + { 0x11218c, 0x0 },
> > > > > > + { 0x21218c, 0x0 },
> > > > > > + { 0x1308c, 0x0 },
> > > > > > + { 0x11308c, 0x0 },
> > > > > > + { 0x21308c, 0x0 },
> > > > > > + { 0x1318c, 0x0 },
> > > > > > + { 0x11318c, 0x0 },
> > > > > > + { 0x21318c, 0x0 },
> > > > > > + { 0x1008d, 0x0 },
> > > > > > + { 0x11008d, 0x0 },
> > > > > > + { 0x21008d, 0x0 },
> > > > > > + { 0x1018d, 0x0 },
> > > > > > + { 0x11018d, 0x0 },
> > > > > > + { 0x21018d, 0x0 },
> > > > > > + { 0x1108d, 0x0 },
> > > > > > + { 0x11108d, 0x0 },
> > > > > > + { 0x21108d, 0x0 },
> > > > > > + { 0x1118d, 0x0 },
> > > > > > + { 0x11118d, 0x0 },
> > > > > > + { 0x21118d, 0x0 },
> > > > > > + { 0x1208d, 0x0 },
> > > > > > + { 0x11208d, 0x0 },
> > > > > > + { 0x21208d, 0x0 },
> > > > > > + { 0x1218d, 0x0 },
> > > > > > + { 0x11218d, 0x0 },
> > > > > > + { 0x21218d, 0x0 },
> > > > > > + { 0x1308d, 0x0 },
> > > > > > + { 0x11308d, 0x0 },
> > > > > > + { 0x21308d, 0x0 },
> > > > > > + { 0x1318d, 0x0 },
> > > > > > + { 0x11318d, 0x0 },
> > > > > > + { 0x21318d, 0x0 },
> > > > > > + { 0x100c0, 0x0 },
> > > > > > + { 0x1100c0, 0x0 },
> > > > > > + { 0x2100c0, 0x0 },
> > > > > > + { 0x101c0, 0x0 },
> > > > > > + { 0x1101c0, 0x0 },
> > > > > > + { 0x2101c0, 0x0 },
> > > > > > + { 0x102c0, 0x0 },
> > > > > > + { 0x1102c0, 0x0 },
> > > > > > + { 0x2102c0, 0x0 },
> > > > > > + { 0x103c0, 0x0 },
> > > > > > + { 0x1103c0, 0x0 },
> > > > > > + { 0x2103c0, 0x0 },
> > > > > > + { 0x104c0, 0x0 },
> > > > > > + { 0x1104c0, 0x0 },
> > > > > > + { 0x2104c0, 0x0 },
> > > > > > + { 0x105c0, 0x0 },
> > > > > > + { 0x1105c0, 0x0 },
> > > > > > + { 0x2105c0, 0x0 },
> > > > > > + { 0x106c0, 0x0 },
> > > > > > + { 0x1106c0, 0x0 },
> > > > > > + { 0x2106c0, 0x0 },
> > > > > > + { 0x107c0, 0x0 },
> > > > > > + { 0x1107c0, 0x0 },
> > > > > > + { 0x2107c0, 0x0 },
> > > > > > + { 0x108c0, 0x0 },
> > > > > > + { 0x1108c0, 0x0 },
> > > > > > + { 0x2108c0, 0x0 },
> > > > > > + { 0x110c0, 0x0 },
> > > > > > + { 0x1110c0, 0x0 },
> > > > > > + { 0x2110c0, 0x0 },
> > > > > > + { 0x111c0, 0x0 },
> > > > > > + { 0x1111c0, 0x0 },
> > > > > > + { 0x2111c0, 0x0 },
> > > > > > + { 0x112c0, 0x0 },
> > > > > > + { 0x1112c0, 0x0 },
> > > > > > + { 0x2112c0, 0x0 },
> > > > > > + { 0x113c0, 0x0 },
> > > > > > + { 0x1113c0, 0x0 },
> > > > > > + { 0x2113c0, 0x0 },
> > > > > > + { 0x114c0, 0x0 },
> > > > > > + { 0x1114c0, 0x0 },
> > > > > > + { 0x2114c0, 0x0 },
> > > > > > + { 0x115c0, 0x0 },
> > > > > > + { 0x1115c0, 0x0 },
> > > > > > + { 0x2115c0, 0x0 },
> > > > > > + { 0x116c0, 0x0 },
> > > > > > + { 0x1116c0, 0x0 },
> > > > > > + { 0x2116c0, 0x0 },
> > > > > > + { 0x117c0, 0x0 },
> > > > > > + { 0x1117c0, 0x0 },
> > > > > > + { 0x2117c0, 0x0 },
> > > > > > + { 0x118c0, 0x0 },
> > > > > > + { 0x1118c0, 0x0 },
> > > > > > + { 0x2118c0, 0x0 },
> > > > > > + { 0x120c0, 0x0 },
> > > > > > + { 0x1120c0, 0x0 },
> > > > > > + { 0x2120c0, 0x0 },
> > > > > > + { 0x121c0, 0x0 },
> > > > > > + { 0x1121c0, 0x0 },
> > > > > > + { 0x2121c0, 0x0 },
> > > > > > + { 0x122c0, 0x0 },
> > > > > > + { 0x1122c0, 0x0 },
> > > > > > + { 0x2122c0, 0x0 },
> > > > > > + { 0x123c0, 0x0 },
> > > > > > + { 0x1123c0, 0x0 },
> > > > > > + { 0x2123c0, 0x0 },
> > > > > > + { 0x124c0, 0x0 },
> > > > > > + { 0x1124c0, 0x0 },
> > > > > > + { 0x2124c0, 0x0 },
> > > > > > + { 0x125c0, 0x0 },
> > > > > > + { 0x1125c0, 0x0 },
> > > > > > + { 0x2125c0, 0x0 },
> > > > > > + { 0x126c0, 0x0 },
> > > > > > + { 0x1126c0, 0x0 },
> > > > > > + { 0x2126c0, 0x0 },
> > > > > > + { 0x127c0, 0x0 },
> > > > > > + { 0x1127c0, 0x0 },
> > > > > > + { 0x2127c0, 0x0 },
> > > > > > + { 0x128c0, 0x0 },
> > > > > > + { 0x1128c0, 0x0 },
> > > > > > + { 0x2128c0, 0x0 },
> > > > > > + { 0x130c0, 0x0 },
> > > > > > + { 0x1130c0, 0x0 },
> > > > > > + { 0x2130c0, 0x0 },
> > > > > > + { 0x131c0, 0x0 },
> > > > > > + { 0x1131c0, 0x0 },
> > > > > > + { 0x2131c0, 0x0 },
> > > > > > + { 0x132c0, 0x0 },
> > > > > > + { 0x1132c0, 0x0 },
> > > > > > + { 0x2132c0, 0x0 },
> > > > > > + { 0x133c0, 0x0 },
> > > > > > + { 0x1133c0, 0x0 },
> > > > > > + { 0x2133c0, 0x0 },
> > > > > > + { 0x134c0, 0x0 },
> > > > > > + { 0x1134c0, 0x0 },
> > > > > > + { 0x2134c0, 0x0 },
> > > > > > + { 0x135c0, 0x0 },
> > > > > > + { 0x1135c0, 0x0 },
> > > > > > + { 0x2135c0, 0x0 },
> > > > > > + { 0x136c0, 0x0 },
> > > > > > + { 0x1136c0, 0x0 },
> > > > > > + { 0x2136c0, 0x0 },
> > > > > > + { 0x137c0, 0x0 },
> > > > > > + { 0x1137c0, 0x0 },
> > > > > > + { 0x2137c0, 0x0 },
> > > > > > + { 0x138c0, 0x0 },
> > > > > > + { 0x1138c0, 0x0 },
> > > > > > + { 0x2138c0, 0x0 },
> > > > > > + { 0x100c1, 0x0 },
> > > > > > + { 0x1100c1, 0x0 },
> > > > > > + { 0x2100c1, 0x0 },
> > > > > > + { 0x101c1, 0x0 },
> > > > > > + { 0x1101c1, 0x0 },
> > > > > > + { 0x2101c1, 0x0 },
> > > > > > + { 0x102c1, 0x0 },
> > > > > > + { 0x1102c1, 0x0 },
> > > > > > + { 0x2102c1, 0x0 },
> > > > > > + { 0x103c1, 0x0 },
> > > > > > + { 0x1103c1, 0x0 },
> > > > > > + { 0x2103c1, 0x0 },
> > > > > > + { 0x104c1, 0x0 },
> > > > > > + { 0x1104c1, 0x0 },
> > > > > > + { 0x2104c1, 0x0 },
> > > > > > + { 0x105c1, 0x0 },
> > > > > > + { 0x1105c1, 0x0 },
> > > > > > + { 0x2105c1, 0x0 },
> > > > > > + { 0x106c1, 0x0 },
> > > > > > + { 0x1106c1, 0x0 },
> > > > > > + { 0x2106c1, 0x0 },
> > > > > > + { 0x107c1, 0x0 },
> > > > > > + { 0x1107c1, 0x0 },
> > > > > > + { 0x2107c1, 0x0 },
> > > > > > + { 0x108c1, 0x0 },
> > > > > > + { 0x1108c1, 0x0 },
> > > > > > + { 0x2108c1, 0x0 },
> > > > > > + { 0x110c1, 0x0 },
> > > > > > + { 0x1110c1, 0x0 },
> > > > > > + { 0x2110c1, 0x0 },
> > > > > > + { 0x111c1, 0x0 },
> > > > > > + { 0x1111c1, 0x0 },
> > > > > > + { 0x2111c1, 0x0 },
> > > > > > + { 0x112c1, 0x0 },
> > > > > > + { 0x1112c1, 0x0 },
> > > > > > + { 0x2112c1, 0x0 },
> > > > > > + { 0x113c1, 0x0 },
> > > > > > + { 0x1113c1, 0x0 },
> > > > > > + { 0x2113c1, 0x0 },
> > > > > > + { 0x114c1, 0x0 },
> > > > > > + { 0x1114c1, 0x0 },
> > > > > > + { 0x2114c1, 0x0 },
> > > > > > + { 0x115c1, 0x0 },
> > > > > > + { 0x1115c1, 0x0 },
> > > > > > + { 0x2115c1, 0x0 },
> > > > > > + { 0x116c1, 0x0 },
> > > > > > + { 0x1116c1, 0x0 },
> > > > > > + { 0x2116c1, 0x0 },
> > > > > > + { 0x117c1, 0x0 },
> > > > > > + { 0x1117c1, 0x0 },
> > > > > > + { 0x2117c1, 0x0 },
> > > > > > + { 0x118c1, 0x0 },
> > > > > > + { 0x1118c1, 0x0 },
> > > > > > + { 0x2118c1, 0x0 },
> > > > > > + { 0x120c1, 0x0 },
> > > > > > + { 0x1120c1, 0x0 },
> > > > > > + { 0x2120c1, 0x0 },
> > > > > > + { 0x121c1, 0x0 },
> > > > > > + { 0x1121c1, 0x0 },
> > > > > > + { 0x2121c1, 0x0 },
> > > > > > + { 0x122c1, 0x0 },
> > > > > > + { 0x1122c1, 0x0 },
> > > > > > + { 0x2122c1, 0x0 },
> > > > > > + { 0x123c1, 0x0 },
> > > > > > + { 0x1123c1, 0x0 },
> > > > > > + { 0x2123c1, 0x0 },
> > > > > > + { 0x124c1, 0x0 },
> > > > > > + { 0x1124c1, 0x0 },
> > > > > > + { 0x2124c1, 0x0 },
> > > > > > + { 0x125c1, 0x0 },
> > > > > > + { 0x1125c1, 0x0 },
> > > > > > + { 0x2125c1, 0x0 },
> > > > > > + { 0x126c1, 0x0 },
> > > > > > + { 0x1126c1, 0x0 },
> > > > > > + { 0x2126c1, 0x0 },
> > > > > > + { 0x127c1, 0x0 },
> > > > > > + { 0x1127c1, 0x0 },
> > > > > > + { 0x2127c1, 0x0 },
> > > > > > + { 0x128c1, 0x0 },
> > > > > > + { 0x1128c1, 0x0 },
> > > > > > + { 0x2128c1, 0x0 },
> > > > > > + { 0x130c1, 0x0 },
> > > > > > + { 0x1130c1, 0x0 },
> > > > > > + { 0x2130c1, 0x0 },
> > > > > > + { 0x131c1, 0x0 },
> > > > > > + { 0x1131c1, 0x0 },
> > > > > > + { 0x2131c1, 0x0 },
> > > > > > + { 0x132c1, 0x0 },
> > > > > > + { 0x1132c1, 0x0 },
> > > > > > + { 0x2132c1, 0x0 },
> > > > > > + { 0x133c1, 0x0 },
> > > > > > + { 0x1133c1, 0x0 },
> > > > > > + { 0x2133c1, 0x0 },
> > > > > > + { 0x134c1, 0x0 },
> > > > > > + { 0x1134c1, 0x0 },
> > > > > > + { 0x2134c1, 0x0 },
> > > > > > + { 0x135c1, 0x0 },
> > > > > > + { 0x1135c1, 0x0 },
> > > > > > + { 0x2135c1, 0x0 },
> > > > > > + { 0x136c1, 0x0 },
> > > > > > + { 0x1136c1, 0x0 },
> > > > > > + { 0x2136c1, 0x0 },
> > > > > > + { 0x137c1, 0x0 },
> > > > > > + { 0x1137c1, 0x0 },
> > > > > > + { 0x2137c1, 0x0 },
> > > > > > + { 0x138c1, 0x0 },
> > > > > > + { 0x1138c1, 0x0 },
> > > > > > + { 0x2138c1, 0x0 },
> > > > > > + { 0x10020, 0x0 },
> > > > > > + { 0x110020, 0x0 },
> > > > > > + { 0x210020, 0x0 },
> > > > > > + { 0x11020, 0x0 },
> > > > > > + { 0x111020, 0x0 },
> > > > > > + { 0x211020, 0x0 },
> > > > > > + { 0x12020, 0x0 },
> > > > > > + { 0x112020, 0x0 },
> > > > > > + { 0x212020, 0x0 },
> > > > > > + { 0x13020, 0x0 },
> > > > > > + { 0x113020, 0x0 },
> > > > > > + { 0x213020, 0x0 },
> > > > > > + { 0x20072, 0x0 },
> > > > > > + { 0x20073, 0x0 },
> > > > > > + { 0x20074, 0x0 },
> > > > > > + { 0x100aa, 0x0 },
> > > > > > + { 0x110aa, 0x0 },
> > > > > > + { 0x120aa, 0x0 },
> > > > > > + { 0x130aa, 0x0 },
> > > > > > + { 0x20010, 0x0 },
> > > > > > + { 0x120010, 0x0 },
> > > > > > + { 0x220010, 0x0 },
> > > > > > + { 0x20011, 0x0 },
> > > > > > + { 0x120011, 0x0 },
> > > > > > + { 0x220011, 0x0 },
> > > > > > + { 0x100ae, 0x0 },
> > > > > > + { 0x1100ae, 0x0 },
> > > > > > + { 0x2100ae, 0x0 },
> > > > > > + { 0x100af, 0x0 },
> > > > > > + { 0x1100af, 0x0 },
> > > > > > + { 0x2100af, 0x0 },
> > > > > > + { 0x110ae, 0x0 },
> > > > > > + { 0x1110ae, 0x0 },
> > > > > > + { 0x2110ae, 0x0 },
> > > > > > + { 0x110af, 0x0 },
> > > > > > + { 0x1110af, 0x0 },
> > > > > > + { 0x2110af, 0x0 },
> > > > > > + { 0x120ae, 0x0 },
> > > > > > + { 0x1120ae, 0x0 },
> > > > > > + { 0x2120ae, 0x0 },
> > > > > > + { 0x120af, 0x0 },
> > > > > > + { 0x1120af, 0x0 },
> > > > > > + { 0x2120af, 0x0 },
> > > > > > + { 0x130ae, 0x0 },
> > > > > > + { 0x1130ae, 0x0 },
> > > > > > + { 0x2130ae, 0x0 },
> > > > > > + { 0x130af, 0x0 },
> > > > > > + { 0x1130af, 0x0 },
> > > > > > + { 0x2130af, 0x0 },
> > > > > > + { 0x20020, 0x0 },
> > > > > > + { 0x120020, 0x0 },
> > > > > > + { 0x220020, 0x0 },
> > > > > > + { 0x100a0, 0x0 },
> > > > > > + { 0x100a1, 0x0 },
> > > > > > + { 0x100a2, 0x0 },
> > > > > > + { 0x100a3, 0x0 },
> > > > > > + { 0x100a4, 0x0 },
> > > > > > + { 0x100a5, 0x0 },
> > > > > > + { 0x100a6, 0x0 },
> > > > > > + { 0x100a7, 0x0 },
> > > > > > + { 0x110a0, 0x0 },
> > > > > > + { 0x110a1, 0x0 },
> > > > > > + { 0x110a2, 0x0 },
> > > > > > + { 0x110a3, 0x0 },
> > > > > > + { 0x110a4, 0x0 },
> > > > > > + { 0x110a5, 0x0 },
> > > > > > + { 0x110a6, 0x0 },
> > > > > > + { 0x110a7, 0x0 },
> > > > > > + { 0x120a0, 0x0 },
> > > > > > + { 0x120a1, 0x0 },
> > > > > > + { 0x120a2, 0x0 },
> > > > > > + { 0x120a3, 0x0 },
> > > > > > + { 0x120a4, 0x0 },
> > > > > > + { 0x120a5, 0x0 },
> > > > > > + { 0x120a6, 0x0 },
> > > > > > + { 0x120a7, 0x0 },
> > > > > > + { 0x130a0, 0x0 },
> > > > > > + { 0x130a1, 0x0 },
> > > > > > + { 0x130a2, 0x0 },
> > > > > > + { 0x130a3, 0x0 },
> > > > > > + { 0x130a4, 0x0 },
> > > > > > + { 0x130a5, 0x0 },
> > > > > > + { 0x130a6, 0x0 },
> > > > > > + { 0x130a7, 0x0 },
> > > > > > + { 0x2007c, 0x0 },
> > > > > > + { 0x12007c, 0x0 },
> > > > > > + { 0x22007c, 0x0 },
> > > > > > + { 0x2007d, 0x0 },
> > > > > > + { 0x12007d, 0x0 },
> > > > > > + { 0x22007d, 0x0 },
> > > > > > + { 0x400fd, 0x0 },
> > > > > > + { 0x400c0, 0x0 },
> > > > > > + { 0x90201, 0x0 },
> > > > > > + { 0x190201, 0x0 },
> > > > > > + { 0x290201, 0x0 },
> > > > > > + { 0x90202, 0x0 },
> > > > > > + { 0x190202, 0x0 },
> > > > > > + { 0x290202, 0x0 },
> > > > > > + { 0x90203, 0x0 },
> > > > > > + { 0x190203, 0x0 },
> > > > > > + { 0x290203, 0x0 },
> > > > > > + { 0x90204, 0x0 },
> > > > > > + { 0x190204, 0x0 },
> > > > > > + { 0x290204, 0x0 },
> > > > > > + { 0x90205, 0x0 },
> > > > > > + { 0x190205, 0x0 },
> > > > > > + { 0x290205, 0x0 },
> > > > > > + { 0x90206, 0x0 },
> > > > > > + { 0x190206, 0x0 },
> > > > > > + { 0x290206, 0x0 },
> > > > > > + { 0x90207, 0x0 },
> > > > > > + { 0x190207, 0x0 },
> > > > > > + { 0x290207, 0x0 },
> > > > > > + { 0x90208, 0x0 },
> > > > > > + { 0x190208, 0x0 },
> > > > > > + { 0x290208, 0x0 },
> > > > > > + { 0x10062, 0x0 },
> > > > > > + { 0x10162, 0x0 },
> > > > > > + { 0x10262, 0x0 },
> > > > > > + { 0x10362, 0x0 },
> > > > > > + { 0x10462, 0x0 },
> > > > > > + { 0x10562, 0x0 },
> > > > > > + { 0x10662, 0x0 },
> > > > > > + { 0x10762, 0x0 },
> > > > > > + { 0x10862, 0x0 },
> > > > > > + { 0x11062, 0x0 },
> > > > > > + { 0x11162, 0x0 },
> > > > > > + { 0x11262, 0x0 },
> > > > > > + { 0x11362, 0x0 },
> > > > > > + { 0x11462, 0x0 },
> > > > > > + { 0x11562, 0x0 },
> > > > > > + { 0x11662, 0x0 },
> > > > > > + { 0x11762, 0x0 },
> > > > > > + { 0x11862, 0x0 },
> > > > > > + { 0x12062, 0x0 },
> > > > > > + { 0x12162, 0x0 },
> > > > > > + { 0x12262, 0x0 },
> > > > > > + { 0x12362, 0x0 },
> > > > > > + { 0x12462, 0x0 },
> > > > > > + { 0x12562, 0x0 },
> > > > > > + { 0x12662, 0x0 },
> > > > > > + { 0x12762, 0x0 },
> > > > > > + { 0x12862, 0x0 },
> > > > > > + { 0x13062, 0x0 },
> > > > > > + { 0x13162, 0x0 },
> > > > > > + { 0x13262, 0x0 },
> > > > > > + { 0x13362, 0x0 },
> > > > > > + { 0x13462, 0x0 },
> > > > > > + { 0x13562, 0x0 },
> > > > > > + { 0x13662, 0x0 },
> > > > > > + { 0x13762, 0x0 },
> > > > > > + { 0x13862, 0x0 },
> > > > > > + { 0x20077, 0x0 },
> > > > > > + { 0x10001, 0x0 },
> > > > > > + { 0x11001, 0x0 },
> > > > > > + { 0x12001, 0x0 },
> > > > > > + { 0x13001, 0x0 },
> > > > > > + { 0x10040, 0x0 },
> > > > > > + { 0x10140, 0x0 },
> > > > > > + { 0x10240, 0x0 },
> > > > > > + { 0x10340, 0x0 },
> > > > > > + { 0x10440, 0x0 },
> > > > > > + { 0x10540, 0x0 },
> > > > > > + { 0x10640, 0x0 },
> > > > > > + { 0x10740, 0x0 },
> > > > > > + { 0x10840, 0x0 },
> > > > > > + { 0x10030, 0x0 },
> > > > > > + { 0x10130, 0x0 },
> > > > > > + { 0x10230, 0x0 },
> > > > > > + { 0x10330, 0x0 },
> > > > > > + { 0x10430, 0x0 },
> > > > > > + { 0x10530, 0x0 },
> > > > > > + { 0x10630, 0x0 },
> > > > > > + { 0x10730, 0x0 },
> > > > > > + { 0x10830, 0x0 },
> > > > > > + { 0x11040, 0x0 },
> > > > > > + { 0x11140, 0x0 },
> > > > > > + { 0x11240, 0x0 },
> > > > > > + { 0x11340, 0x0 },
> > > > > > + { 0x11440, 0x0 },
> > > > > > + { 0x11540, 0x0 },
> > > > > > + { 0x11640, 0x0 },
> > > > > > + { 0x11740, 0x0 },
> > > > > > + { 0x11840, 0x0 },
> > > > > > + { 0x11030, 0x0 },
> > > > > > + { 0x11130, 0x0 },
> > > > > > + { 0x11230, 0x0 },
> > > > > > + { 0x11330, 0x0 },
> > > > > > + { 0x11430, 0x0 },
> > > > > > + { 0x11530, 0x0 },
> > > > > > + { 0x11630, 0x0 },
> > > > > > + { 0x11730, 0x0 },
> > > > > > + { 0x11830, 0x0 },
> > > > > > + { 0x12040, 0x0 },
> > > > > > + { 0x12140, 0x0 },
> > > > > > + { 0x12240, 0x0 },
> > > > > > + { 0x12340, 0x0 },
> > > > > > + { 0x12440, 0x0 },
> > > > > > + { 0x12540, 0x0 },
> > > > > > + { 0x12640, 0x0 },
> > > > > > + { 0x12740, 0x0 },
> > > > > > + { 0x12840, 0x0 },
> > > > > > + { 0x12030, 0x0 },
> > > > > > + { 0x12130, 0x0 },
> > > > > > + { 0x12230, 0x0 },
> > > > > > + { 0x12330, 0x0 },
> > > > > > + { 0x12430, 0x0 },
> > > > > > + { 0x12530, 0x0 },
> > > > > > + { 0x12630, 0x0 },
> > > > > > + { 0x12730, 0x0 },
> > > > > > + { 0x12830, 0x0 },
> > > > > > + { 0x13040, 0x0 },
> > > > > > + { 0x13140, 0x0 },
> > > > > > + { 0x13240, 0x0 },
> > > > > > + { 0x13340, 0x0 },
> > > > > > + { 0x13440, 0x0 },
> > > > > > + { 0x13540, 0x0 },
> > > > > > + { 0x13640, 0x0 },
> > > > > > + { 0x13740, 0x0 },
> > > > > > + { 0x13840, 0x0 },
> > > > > > + { 0x13030, 0x0 },
> > > > > > + { 0x13130, 0x0 },
> > > > > > + { 0x13230, 0x0 },
> > > > > > + { 0x13330, 0x0 },
> > > > > > + { 0x13430, 0x0 },
> > > > > > + { 0x13530, 0x0 },
> > > > > > + { 0x13630, 0x0 },
> > > > > > + { 0x13730, 0x0 },
> > > > > > + { 0x13830, 0x0 },
> > > > > > +};
> > > > >
> > > > > The same as above. Please look into imx6q DDR3 training code.
> > > > >
> > > > > > +
> > > > > > +/* P0 message block paremeter for training firmware */
> > > > > > +struct dram_cfg_param lpddr4_fsp0_cfg[] = {
> > > > > > + { 0xd0000, 0x0 },
> > > > > > + { 0x54000, 0x0 },
> > > > > > + { 0x54001, 0x0 },
> > > > > > + { 0x54002, 0x0 },
> > > > > > + { 0x54003, 0xbb8 },
> > > > > > + { 0x54004, 0x2 },
> > > > > > + { 0x54005, ((LPDDR4_PHY_RON << 8) |
> > > > > > LPDDR4_PHY_RTT) },//PHY Ron/Rtt
> > > > > > + { 0x54006, LPDDR4_PHY_VREF_VALUE },
> > > > > > + { 0x54007, 0x0 },
> > > > > > + { 0x54008, 0x131f },
> > > > > > + { 0x54009, 0xc8 },
> > > > > > + { 0x5400a, 0x0 },
> > > > > > + { 0x5400b, 0x2 },
> > > > > > + { 0x5400c, 0x0 },
> > > > > > + { 0x5400d, 0x0 },
> > > > > > + { 0x5400e, 0x0 },
> > > > > > + { 0x5400f, 0x0 },
> > > > > > + { 0x54010, 0x0 },
> > > > > > + { 0x54011, 0x0 },
> > > > > > + { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
> > > > > > + { 0x54013, 0x0 },
> > > > > > + { 0x54014, 0x0 },
> > > > > > + { 0x54015, 0x0 },
> > > > > > + { 0x54016, 0x0 },
> > > > > > + { 0x54017, 0x0 },
> > > > > > + { 0x54018, 0x0 },
> > > > > > + { 0x54019, 0x2dd4 },
> > > > > > + { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
> > > > > > + { 0x5401b, 0x4d66 },
> > > > > > + { 0x5401c, 0x4d08 },
> > > > > > + { 0x5401d, 0x0 },
> > > > > > + { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
> > > > > > + { 0x5401f, 0x2dd4 },
> > > > > > + { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
> > > > > > + { 0x54021, 0x4d66 },
> > > > > > + { 0x54022, 0x4d08 },
> > > > > > + { 0x54023, 0x0 },
> > > > > > + { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
> > > > > > + { 0x54025, 0x0 },
> > > > > > + { 0x54026, 0x0 },
> > > > > > + { 0x54027, 0x0 },
> > > > > > + { 0x54028, 0x0 },
> > > > > > + { 0x54029, 0x0 },
> > > > > > + { 0x5402a, 0x0 },
> > > > > > + { 0x5402b, 0x1000 },
> > > > > > + { 0x5402c, LPDDR4_CS },
> > > > > > + { 0x5402d, 0x0 },
> > > > > > + { 0x5402e, 0x0 },
> > > > > > + { 0x5402f, 0x0 },
> > > > > > + { 0x54030, 0x0 },
> > > > > > + { 0x54031, 0x0 },
> > > > > > + { 0x54032, 0xd400 },
> > > > > > + { 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
> > > > > > + { 0x54034, 0x6600 },
> > > > > > + { 0x54035, 0x84d },
> > > > > > + { 0x54036, 0x4d },
> > > > > > + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
> > > > > > + { 0x54038, 0xd400 },
> > > > > > + { 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
> > > > > > + { 0x5403a, 0x6600 },
> > > > > > + { 0x5403b, 0x84d },
> > > > > > + { 0x5403c, 0x4d },
> > > > > > + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
> > > > > > + { 0x5403e, 0x0 },
> > > > > > + { 0x5403f, 0x0 },
> > > > > > + { 0x54040, 0x0 },
> > > > > > + { 0x54041, 0x0 },
> > > > > > + { 0x54042, 0x0 },
> > > > > > + { 0x54043, 0x0 },
> > > > > > + { 0x54044, 0x0 },
> > > > > > + { 0xd0000, 0x1 },
> > > > > > +};
> > > > > > +
> > > > > > +/* P1 message block paremeter for training firmware */
> > > > > > +struct dram_cfg_param lpddr4_fsp1_cfg[] = {
> > > > > > + { 0xd0000, 0x0 },
> > > > > > + { 0x54000, 0x0 },
> > > > > > + { 0x54001, 0x0 },
> > > > > > + { 0x54002, 0x101 },
> > > > > > + { 0x54003, 0x190 },
> > > > > > + { 0x54004, 0x2 },
> > > > > > + { 0x54005, ((LPDDR4_PHY_RON << 8) |
> > > > > > LPDDR4_PHY_RTT) },//PHY Ron/Rtt
> > > > > > + { 0x54006, LPDDR4_PHY_VREF_VALUE },
> > > > > > + { 0x54007, 0x0 },
> > > > > > + { 0x54008, 0x121f },
> > > > > > + { 0x54009, 0xc8 },
> > > > > > + { 0x5400a, 0x0 },
> > > > > > + { 0x5400b, 0x2 },
> > > > > > + { 0x5400c, 0x0 },
> > > > > > + { 0x5400d, 0x0 },
> > > > > > + { 0x5400e, 0x0 },
> > > > > > + { 0x5400f, 0x0 },
> > > > > > + { 0x54010, 0x0 },
> > > > > > + { 0x54011, 0x0 },
> > > > > > + { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
> > > > > > + { 0x54013, 0x0 },
> > > > > > + { 0x54014, 0x0 },
> > > > > > + { 0x54015, 0x0 },
> > > > > > + { 0x54016, 0x0 },
> > > > > > + { 0x54017, 0x0 },
> > > > > > + { 0x54018, 0x0 },
> > > > > > + { 0x54019, 0x84 },
> > > > > > + { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
> > > > > > + { 0x5401b, 0x4d66 },
> > > > > > + { 0x5401c, 0x4d08 },
> > > > > > + { 0x5401d, 0x0 },
> > > > > > + { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
> > > > > > + { 0x5401f, 0x84 },
> > > > > > + { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
> > > > > > + { 0x54021, 0x4d66 },
> > > > > > + { 0x54022, 0x4d08 },
> > > > > > + { 0x54023, 0x0 },
> > > > > > + { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
> > > > > > + { 0x54025, 0x0 },
> > > > > > + { 0x54026, 0x0 },
> > > > > > + { 0x54027, 0x0 },
> > > > > > + { 0x54028, 0x0 },
> > > > > > + { 0x54029, 0x0 },
> > > > > > + { 0x5402a, 0x0 },
> > > > > > + { 0x5402b, 0x1000 },
> > > > > > + { 0x5402c, LPDDR4_CS },
> > > > > > + { 0x5402d, 0x0 },
> > > > > > + { 0x5402e, 0x0 },
> > > > > > + { 0x5402f, 0x0 },
> > > > > > + { 0x54030, 0x0 },
> > > > > > + { 0x54031, 0x0 },
> > > > > > + { 0x54032, 0x8400 },
> > > > > > + { 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
> > > > > > + { 0x54034, 0x6600 },
> > > > > > + { 0x54035, 0x84d },
> > > > > > + { 0x54036, 0x4d },
> > > > > > + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
> > > > > > + { 0x54038, 0x8400 },
> > > > > > + { 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
> > > > > > + { 0x5403a, 0x6600 },
> > > > > > + { 0x5403b, 0x84d },
> > > > > > + { 0x5403c, 0x4d },
> > > > > > + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
> > > > > > + { 0x5403e, 0x0 },
> > > > > > + { 0x5403f, 0x0 },
> > > > > > + { 0x54040, 0x0 },
> > > > > > + { 0x54041, 0x0 },
> > > > > > + { 0x54042, 0x0 },
> > > > > > + { 0x54043, 0x0 },
> > > > > > + { 0x54044, 0x0 },
> > > > > > + { 0xd0000, 0x1 },
> > > > > > +};
> > > > > > +
> > > > > > +/* P1 message block paremeter for training firmware */
> > > > > > +struct dram_cfg_param lpddr4_fsp2_cfg[] = {
> > > > > > + { 0xd0000, 0x0 },
> > > > > > + { 0x54000, 0x0 },
> > > > > > + { 0x54001, 0x0 },
> > > > > > + { 0x54002, 0x102 },
> > > > > > + { 0x54003, 0x64 },
> > > > > > + { 0x54004, 0x2 },
> > > > > > + { 0x54005, ((LPDDR4_PHY_RON << 8) |
> > > > > > LPDDR4_PHY_RTT) },//PHY Ron/Rtt
> > > > > > + { 0x54006, LPDDR4_PHY_VREF_VALUE },
> > > > > > + { 0x54007, 0x0 },
> > > > > > + { 0x54008, 0x121f },
> > > > > > + { 0x54009, 0xc8 },
> > > > > > + { 0x5400a, 0x0 },
> > > > > > + { 0x5400b, 0x2 },
> > > > > > + { 0x5400c, 0x0 },
> > > > > > + { 0x5400d, 0x0 },
> > > > > > + { 0x5400e, 0x0 },
> > > > > > + { 0x5400f, 0x0 },
> > > > > > + { 0x54010, 0x0 },
> > > > > > + { 0x54011, 0x0 },
> > > > > > + { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
> > > > > > + { 0x54013, 0x0 },
> > > > > > + { 0x54014, 0x0 },
> > > > > > + { 0x54015, 0x0 },
> > > > > > + { 0x54016, 0x0 },
> > > > > > + { 0x54017, 0x0 },
> > > > > > + { 0x54018, 0x0 },
> > > > > > + { 0x54019, 0x84 },
> > > > > > + { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
> > > > > > + { 0x5401b, 0x4d66 },
> > > > > > + { 0x5401c, 0x4d08 },
> > > > > > + { 0x5401d, 0x0 },
> > > > > > + { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
> > > > > > + { 0x5401f, 0x84 },
> > > > > > + { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
> > > > > > + { 0x54021, 0x4d66 },
> > > > > > + { 0x54022, 0x4d08 },
> > > > > > + { 0x54023, 0x0 },
> > > > > > + { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
> > > > > > + { 0x54025, 0x0 },
> > > > > > + { 0x54026, 0x0 },
> > > > > > + { 0x54027, 0x0 },
> > > > > > + { 0x54028, 0x0 },
> > > > > > + { 0x54029, 0x0 },
> > > > > > + { 0x5402a, 0x0 },
> > > > > > + { 0x5402b, 0x1000 },
> > > > > > + { 0x5402c, LPDDR4_CS },
> > > > > > + { 0x5402d, 0x0 },
> > > > > > + { 0x5402e, 0x0 },
> > > > > > + { 0x5402f, 0x0 },
> > > > > > + { 0x54030, 0x0 },
> > > > > > + { 0x54031, 0x0 },
> > > > > > + { 0x54032, 0x8400 },
> > > > > > + { 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
> > > > > > + { 0x54034, 0x6600 },
> > > > > > + { 0x54035, 0x84d },
> > > > > > + { 0x54036, 0x4d },
> > > > > > + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
> > > > > > + { 0x54038, 0x8400 },
> > > > > > + { 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
> > > > > > + { 0x5403a, 0x6600 },
> > > > > > + { 0x5403b, 0x84d },
> > > > > > + { 0x5403c, 0x4d },
> > > > > > + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
> > > > > > + { 0x5403e, 0x0 },
> > > > > > + { 0x5403f, 0x0 },
> > > > > > + { 0x54040, 0x0 },
> > > > > > + { 0x54041, 0x0 },
> > > > > > + { 0x54042, 0x0 },
> > > > > > + { 0x54043, 0x0 },
> > > > > > + { 0x54044, 0x0 },
> > > > > > + { 0xd0000, 0x1 },
> > > > > > +};
> > > > > > +
> > > > > > +/* P0 2D message block paremeter for training firmware */
> > > > > > +struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
> > > > > > + { 0xd0000, 0x0 },
> > > > > > + { 0x54000, 0x0 },
> > > > > > + { 0x54001, 0x0 },
> > > > > > + { 0x54002, 0x0 },
> > > > > > + { 0x54003, 0xbb8 },
> > > > > > + { 0x54004, 0x2 },
> > > > > > + { 0x54005, ((LPDDR4_PHY_RON << 8) |
> > > > > > LPDDR4_PHY_RTT) },//PHY Ron/Rtt
> > > > > > + { 0x54006, LPDDR4_PHY_VREF_VALUE },
> > > > > > + { 0x54007, 0x0 },
> > > > > > + { 0x54008, 0x61 },
> > > > > > + { 0x54009, 0xc8 },
> > > > > > + { 0x5400a, 0x0 },
> > > > > > + { 0x5400b, 0x2 },
> > > > > > + { 0x5400c, 0x0 },
> > > > > > + { 0x5400d, 0x0 },
> > > > > > + { 0x5400e, 0x0 },
> > > > > > + { 0x5400f, 0x100 },
> > > > > > + { 0x54010, 0x1f7f },
> > > > > > + { 0x54011, 0x0 },
> > > > > > + { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
> > > > > > + { 0x54013, 0x0 },
> > > > > > + { 0x54014, 0x0 },
> > > > > > + { 0x54015, 0x0 },
> > > > > > + { 0x54016, 0x0 },
> > > > > > + { 0x54017, 0x0 },
> > > > > > + { 0x54018, 0x0 },
> > > > > > + { 0x54019, 0x2dd4 },
> > > > > > + { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
> > > > > > + { 0x5401b, 0x4d66 },
> > > > > > + { 0x5401c, 0x4d08 },
> > > > > > + { 0x5401d, 0x0 },
> > > > > > + { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
> > > > > > + { 0x5401f, 0x2dd4 },
> > > > > > + { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
> > > > > > + { 0x54021, 0x4d66 },
> > > > > > + { 0x54022, 0x4d08 },
> > > > > > + { 0x54023, 0x0 },
> > > > > > + { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
> > > > > > + { 0x54025, 0x0 },
> > > > > > + { 0x54026, 0x0 },
> > > > > > + { 0x54027, 0x0 },
> > > > > > + { 0x54028, 0x0 },
> > > > > > + { 0x54029, 0x0 },
> > > > > > + { 0x5402a, 0x0 },
> > > > > > + { 0x5402b, 0x1000 },
> > > > > > + { 0x5402c, LPDDR4_CS },
> > > > > > + { 0x5402d, 0x0 },
> > > > > > + { 0x5402e, 0x0 },
> > > > > > + { 0x5402f, 0x0 },
> > > > > > + { 0x54030, 0x0 },
> > > > > > + { 0x54031, 0x0 },
> > > > > > + { 0x54032, 0xd400 },
> > > > > > + { 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
> > > > > > + { 0x54034, 0x6600 },
> > > > > > + { 0x54035, 0x84d },
> > > > > > + { 0x54036, 0x4d },
> > > > > > + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
> > > > > > + { 0x54038, 0xd400 },
> > > > > > + { 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
> > > > > > + { 0x5403a, 0x6600 },
> > > > > > + { 0x5403b, 0x84d },
> > > > > > + { 0x5403c, 0x4d },
> > > > > > + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
> > > > > > + { 0x5403e, 0x0 },
> > > > > > + { 0x5403f, 0x0 },
> > > > > > + { 0x54040, 0x0 },
> > > > > > + { 0x54041, 0x0 },
> > > > > > + { 0x54042, 0x0 },
> > > > > > + { 0x54043, 0x0 },
> > > > > > + { 0x54044, 0x0 },
> > > > > > + { 0xd0000, 0x1 },
> > > > > > +};
> > > > > > +
> > > > > > +/* DRAM PHY init engine image */
> > > > > > +struct dram_cfg_param lpddr4_phy_pie[] = {
> > > > > > + { 0xd0000, 0x0 },
> > > > > > + { 0x90000, 0x10 },
> > > > > > + { 0x90001, 0x400 },
> > > > > > + { 0x90002, 0x10e },
> > > > > > + { 0x90003, 0x0 },
> > > > > > + { 0x90004, 0x0 },
> > > > > > + { 0x90005, 0x8 },
> > > > > > + { 0x90029, 0xb },
> > > > > > + { 0x9002a, 0x480 },
> > > > > > + { 0x9002b, 0x109 },
> > > > > > + { 0x9002c, 0x8 },
> > > > > > + { 0x9002d, 0x448 },
> > > > > > + { 0x9002e, 0x139 },
> > > > > > + { 0x9002f, 0x8 },
> > > > > > + { 0x90030, 0x478 },
> > > > > > + { 0x90031, 0x109 },
> > > > > > + { 0x90032, 0x0 },
> > > > > > + { 0x90033, 0xe8 },
> > > > > > + { 0x90034, 0x109 },
> > > > > > + { 0x90035, 0x2 },
> > > > > > + { 0x90036, 0x10 },
> > > > > > + { 0x90037, 0x139 },
> > > > > > + { 0x90038, 0xf },
> > > > > > + { 0x90039, 0x7c0 },
> > > > > > + { 0x9003a, 0x139 },
> > > > > > + { 0x9003b, 0x44 },
> > > > > > + { 0x9003c, 0x630 },
> > > > > > + { 0x9003d, 0x159 },
> > > > > > + { 0x9003e, 0x14f },
> > > > > > + { 0x9003f, 0x630 },
> > > > > > + { 0x90040, 0x159 },
> > > > > > + { 0x90041, 0x47 },
> > > > > > + { 0x90042, 0x630 },
> > > > > > + { 0x90043, 0x149 },
> > > > > > + { 0x90044, 0x4f },
> > > > > > + { 0x90045, 0x630 },
> > > > > > + { 0x90046, 0x179 },
> > > > > > + { 0x90047, 0x8 },
> > > > > > + { 0x90048, 0xe0 },
> > > > > > + { 0x90049, 0x109 },
> > > > > > + { 0x9004a, 0x0 },
> > > > > > + { 0x9004b, 0x7c8 },
> > > > > > + { 0x9004c, 0x109 },
> > > > > > + { 0x9004d, 0x0 },
> > > > > > + { 0x9004e, 0x1 },
> > > > > > + { 0x9004f, 0x8 },
> > > > > > + { 0x90050, 0x0 },
> > > > > > + { 0x90051, 0x45a },
> > > > > > + { 0x90052, 0x9 },
> > > > > > + { 0x90053, 0x0 },
> > > > > > + { 0x90054, 0x448 },
> > > > > > + { 0x90055, 0x109 },
> > > > > > + { 0x90056, 0x40 },
> > > > > > + { 0x90057, 0x630 },
> > > > > > + { 0x90058, 0x179 },
> > > > > > + { 0x90059, 0x1 },
> > > > > > + { 0x9005a, 0x618 },
> > > > > > + { 0x9005b, 0x109 },
> > > > > > + { 0x9005c, 0x40c0 },
> > > > > > + { 0x9005d, 0x630 },
> > > > > > + { 0x9005e, 0x149 },
> > > > > > + { 0x9005f, 0x8 },
> > > > > > + { 0x90060, 0x4 },
> > > > > > + { 0x90061, 0x48 },
> > > > > > + { 0x90062, 0x4040 },
> > > > > > + { 0x90063, 0x630 },
> > > > > > + { 0x90064, 0x149 },
> > > > > > + { 0x90065, 0x0 },
> > > > > > + { 0x90066, 0x4 },
> > > > > > + { 0x90067, 0x48 },
> > > > > > + { 0x90068, 0x40 },
> > > > > > + { 0x90069, 0x630 },
> > > > > > + { 0x9006a, 0x149 },
> > > > > > + { 0x9006b, 0x10 },
> > > > > > + { 0x9006c, 0x4 },
> > > > > > + { 0x9006d, 0x18 },
> > > > > > + { 0x9006e, 0x0 },
> > > > > > + { 0x9006f, 0x4 },
> > > > > > + { 0x90070, 0x78 },
> > > > > > + { 0x90071, 0x549 },
> > > > > > + { 0x90072, 0x630 },
> > > > > > + { 0x90073, 0x159 },
> > > > > > + { 0x90074, 0xd49 },
> > > > > > + { 0x90075, 0x630 },
> > > > > > + { 0x90076, 0x159 },
> > > > > > + { 0x90077, 0x94a },
> > > > > > + { 0x90078, 0x630 },
> > > > > > + { 0x90079, 0x159 },
> > > > > > + { 0x9007a, 0x441 },
> > > > > > + { 0x9007b, 0x630 },
> > > > > > + { 0x9007c, 0x149 },
> > > > > > + { 0x9007d, 0x42 },
> > > > > > + { 0x9007e, 0x630 },
> > > > > > + { 0x9007f, 0x149 },
> > > > > > + { 0x90080, 0x1 },
> > > > > > + { 0x90081, 0x630 },
> > > > > > + { 0x90082, 0x149 },
> > > > > > + { 0x90083, 0x0 },
> > > > > > + { 0x90084, 0xe0 },
> > > > > > + { 0x90085, 0x109 },
> > > > > > + { 0x90086, 0xa },
> > > > > > + { 0x90087, 0x10 },
> > > > > > + { 0x90088, 0x109 },
> > > > > > + { 0x90089, 0x9 },
> > > > > > + { 0x9008a, 0x3c0 },
> > > > > > + { 0x9008b, 0x149 },
> > > > > > + { 0x9008c, 0x9 },
> > > > > > + { 0x9008d, 0x3c0 },
> > > > > > + { 0x9008e, 0x159 },
> > > > > > + { 0x9008f, 0x18 },
> > > > > > + { 0x90090, 0x10 },
> > > > > > + { 0x90091, 0x109 },
> > > > > > + { 0x90092, 0x0 },
> > > > > > + { 0x90093, 0x3c0 },
> > > > > > + { 0x90094, 0x109 },
> > > > > > + { 0x90095, 0x18 },
> > > > > > + { 0x90096, 0x4 },
> > > > > > + { 0x90097, 0x48 },
> > > > > > + { 0x90098, 0x18 },
> > > > > > + { 0x90099, 0x4 },
> > > > > > + { 0x9009a, 0x58 },
> > > > > > + { 0x9009b, 0xa },
> > > > > > + { 0x9009c, 0x10 },
> > > > > > + { 0x9009d, 0x109 },
> > > > > > + { 0x9009e, 0x2 },
> > > > > > + { 0x9009f, 0x10 },
> > > > > > + { 0x900a0, 0x109 },
> > > > > > + { 0x900a1, 0x5 },
> > > > > > + { 0x900a2, 0x7c0 },
> > > > > > + { 0x900a3, 0x109 },
> > > > > > + { 0x900a4, 0x10 },
> > > > > > + { 0x900a5, 0x10 },
> > > > > > + { 0x900a6, 0x109 },
> > > > > > + { 0x40000, 0x811 },
> > > > > > + { 0x40020, 0x880 },
> > > > > > + { 0x40040, 0x0 },
> > > > > > + { 0x40060, 0x0 },
> > > > > > + { 0x40001, 0x4008 },
> > > > > > + { 0x40021, 0x83 },
> > > > > > + { 0x40041, 0x4f },
> > > > > > + { 0x40061, 0x0 },
> > > > > > + { 0x40002, 0x4040 },
> > > > > > + { 0x40022, 0x83 },
> > > > > > + { 0x40042, 0x51 },
> > > > > > + { 0x40062, 0x0 },
> > > > > > + { 0x40003, 0x811 },
> > > > > > + { 0x40023, 0x880 },
> > > > > > + { 0x40043, 0x0 },
> > > > > > + { 0x40063, 0x0 },
> > > > > > + { 0x40004, 0x720 },
> > > > > > + { 0x40024, 0xf },
> > > > > > + { 0x40044, 0x1740 },
> > > > > > + { 0x40064, 0x0 },
> > > > > > + { 0x40005, 0x16 },
> > > > > > + { 0x40025, 0x83 },
> > > > > > + { 0x40045, 0x4b },
> > > > > > + { 0x40065, 0x0 },
> > > > > > + { 0x40006, 0x716 },
> > > > > > + { 0x40026, 0xf },
> > > > > > + { 0x40046, 0x2001 },
> > > > > > + { 0x40066, 0x0 },
> > > > > > + { 0x40007, 0x716 },
> > > > > > + { 0x40027, 0xf },
> > > > > > + { 0x40047, 0x2800 },
> > > > > > + { 0x40067, 0x0 },
> > > > > > + { 0x40008, 0x716 },
> > > > > > + { 0x40028, 0xf },
> > > > > > + { 0x40048, 0xf00 },
> > > > > > + { 0x40068, 0x0 },
> > > > > > + { 0x40009, 0x720 },
> > > > > > + { 0x40029, 0xf },
> > > > > > + { 0x40049, 0x1400 },
> > > > > > + { 0x40069, 0x0 },
> > > > > > + { 0x4000a, 0xe08 },
> > > > > > + { 0x4002a, 0xc15 },
> > > > > > + { 0x4004a, 0x0 },
> > > > > > + { 0x4006a, 0x0 },
> > > > > > + { 0x4000b, 0x623 },
> > > > > > + { 0x4002b, 0x15 },
> > > > > > + { 0x4004b, 0x0 },
> > > > > > + { 0x4006b, 0x0 },
> > > > > > + { 0x4000c, 0x4028 },
> > > > > > + { 0x4002c, 0x80 },
> > > > > > + { 0x4004c, 0x0 },
> > > > > > + { 0x4006c, 0x0 },
> > > > > > + { 0x4000d, 0xe08 },
> > > > > > + { 0x4002d, 0xc1a },
> > > > > > + { 0x4004d, 0x0 },
> > > > > > + { 0x4006d, 0x0 },
> > > > > > + { 0x4000e, 0x623 },
> > > > > > + { 0x4002e, 0x1a },
> > > > > > + { 0x4004e, 0x0 },
> > > > > > + { 0x4006e, 0x0 },
> > > > > > + { 0x4000f, 0x4040 },
> > > > > > + { 0x4002f, 0x80 },
> > > > > > + { 0x4004f, 0x0 },
> > > > > > + { 0x4006f, 0x0 },
> > > > > > + { 0x40010, 0x2604 },
> > > > > > + { 0x40030, 0x15 },
> > > > > > + { 0x40050, 0x0 },
> > > > > > + { 0x40070, 0x0 },
> > > > > > + { 0x40011, 0x708 },
> > > > > > + { 0x40031, 0x5 },
> > > > > > + { 0x40051, 0x0 },
> > > > > > + { 0x40071, 0x2002 },
> > > > > > + { 0x40012, 0x8 },
> > > > > > + { 0x40032, 0x80 },
> > > > > > + { 0x40052, 0x0 },
> > > > > > + { 0x40072, 0x0 },
> > > > > > + { 0x40013, 0x2604 },
> > > > > > + { 0x40033, 0x1a },
> > > > > > + { 0x40053, 0x0 },
> > > > > > + { 0x40073, 0x0 },
> > > > > > + { 0x40014, 0x708 },
> > > > > > + { 0x40034, 0xa },
> > > > > > + { 0x40054, 0x0 },
> > > > > > + { 0x40074, 0x2002 },
> > > > > > + { 0x40015, 0x4040 },
> > > > > > + { 0x40035, 0x80 },
> > > > > > + { 0x40055, 0x0 },
> > > > > > + { 0x40075, 0x0 },
> > > > > > + { 0x40016, 0x60a },
> > > > > > + { 0x40036, 0x15 },
> > > > > > + { 0x40056, 0x1200 },
> > > > > > + { 0x40076, 0x0 },
> > > > > > + { 0x40017, 0x61a },
> > > > > > + { 0x40037, 0x15 },
> > > > > > + { 0x40057, 0x1300 },
> > > > > > + { 0x40077, 0x0 },
> > > > > > + { 0x40018, 0x60a },
> > > > > > + { 0x40038, 0x1a },
> > > > > > + { 0x40058, 0x1200 },
> > > > > > + { 0x40078, 0x0 },
> > > > > > + { 0x40019, 0x642 },
> > > > > > + { 0x40039, 0x1a },
> > > > > > + { 0x40059, 0x1300 },
> > > > > > + { 0x40079, 0x0 },
> > > > > > + { 0x4001a, 0x4808 },
> > > > > > + { 0x4003a, 0x880 },
> > > > > > + { 0x4005a, 0x0 },
> > > > > > + { 0x4007a, 0x0 },
> > > > > > + { 0x900a7, 0x0 },
> > > > > > + { 0x900a8, 0x790 },
> > > > > > + { 0x900a9, 0x11a },
> > > > > > + { 0x900aa, 0x8 },
> > > > > > + { 0x900ab, 0x7aa },
> > > > > > + { 0x900ac, 0x2a },
> > > > > > + { 0x900ad, 0x10 },
> > > > > > + { 0x900ae, 0x7b2 },
> > > > > > + { 0x900af, 0x2a },
> > > > > > + { 0x900b0, 0x0 },
> > > > > > + { 0x900b1, 0x7c8 },
> > > > > > + { 0x900b2, 0x109 },
> > > > > > + { 0x900b3, 0x10 },
> > > > > > + { 0x900b4, 0x2a8 },
> > > > > > + { 0x900b5, 0x129 },
> > > > > > + { 0x900b6, 0x8 },
> > > > > > + { 0x900b7, 0x370 },
> > > > > > + { 0x900b8, 0x129 },
> > > > > > + { 0x900b9, 0xa },
> > > > > > + { 0x900ba, 0x3c8 },
> > > > > > + { 0x900bb, 0x1a9 },
> > > > > > + { 0x900bc, 0xc },
> > > > > > + { 0x900bd, 0x408 },
> > > > > > + { 0x900be, 0x199 },
> > > > > > + { 0x900bf, 0x14 },
> > > > > > + { 0x900c0, 0x790 },
> > > > > > + { 0x900c1, 0x11a },
> > > > > > + { 0x900c2, 0x8 },
> > > > > > + { 0x900c3, 0x4 },
> > > > > > + { 0x900c4, 0x18 },
> > > > > > + { 0x900c5, 0xe },
> > > > > > + { 0x900c6, 0x408 },
> > > > > > + { 0x900c7, 0x199 },
> > > > > > + { 0x900c8, 0x8 },
> > > > > > + { 0x900c9, 0x8568 },
> > > > > > + { 0x900ca, 0x108 },
> > > > > > + { 0x900cb, 0x18 },
> > > > > > + { 0x900cc, 0x790 },
> > > > > > + { 0x900cd, 0x16a },
> > > > > > + { 0x900ce, 0x8 },
> > > > > > + { 0x900cf, 0x1d8 },
> > > > > > + { 0x900d0, 0x169 },
> > > > > > + { 0x900d1, 0x10 },
> > > > > > + { 0x900d2, 0x8558 },
> > > > > > + { 0x900d3, 0x168 },
> > > > > > + { 0x900d4, 0x70 },
> > > > > > + { 0x900d5, 0x788 },
> > > > > > + { 0x900d6, 0x16a },
> > > > > > + { 0x900d7, 0x1ff8 },
> > > > > > + { 0x900d8, 0x85a8 },
> > > > > > + { 0x900d9, 0x1e8 },
> > > > > > + { 0x900da, 0x50 },
> > > > > > + { 0x900db, 0x798 },
> > > > > > + { 0x900dc, 0x16a },
> > > > > > + { 0x900dd, 0x60 },
> > > > > > + { 0x900de, 0x7a0 },
> > > > > > + { 0x900df, 0x16a },
> > > > > > + { 0x900e0, 0x8 },
> > > > > > + { 0x900e1, 0x8310 },
> > > > > > + { 0x900e2, 0x168 },
> > > > > > + { 0x900e3, 0x8 },
> > > > > > + { 0x900e4, 0xa310 },
> > > > > > + { 0x900e5, 0x168 },
> > > > > > + { 0x900e6, 0xa },
> > > > > > + { 0x900e7, 0x408 },
> > > > > > + { 0x900e8, 0x169 },
> > > > > > + { 0x900e9, 0x6e },
> > > > > > + { 0x900ea, 0x0 },
> > > > > > + { 0x900eb, 0x68 },
> > > > > > + { 0x900ec, 0x0 },
> > > > > > + { 0x900ed, 0x408 },
> > > > > > + { 0x900ee, 0x169 },
> > > > > > + { 0x900ef, 0x0 },
> > > > > > + { 0x900f0, 0x8310 },
> > > > > > + { 0x900f1, 0x168 },
> > > > > > + { 0x900f2, 0x0 },
> > > > > > + { 0x900f3, 0xa310 },
> > > > > > + { 0x900f4, 0x168 },
> > > > > > + { 0x900f5, 0x1ff8 },
> > > > > > + { 0x900f6, 0x85a8 },
> > > > > > + { 0x900f7, 0x1e8 },
> > > > > > + { 0x900f8, 0x68 },
> > > > > > + { 0x900f9, 0x798 },
> > > > > > + { 0x900fa, 0x16a },
> > > > > > + { 0x900fb, 0x78 },
> > > > > > + { 0x900fc, 0x7a0 },
> > > > > > + { 0x900fd, 0x16a },
> > > > > > + { 0x900fe, 0x68 },
> > > > > > + { 0x900ff, 0x790 },
> > > > > > + { 0x90100, 0x16a },
> > > > > > + { 0x90101, 0x8 },
> > > > > > + { 0x90102, 0x8b10 },
> > > > > > + { 0x90103, 0x168 },
> > > > > > + { 0x90104, 0x8 },
> > > > > > + { 0x90105, 0xab10 },
> > > > > > + { 0x90106, 0x168 },
> > > > > > + { 0x90107, 0xa },
> > > > > > + { 0x90108, 0x408 },
> > > > > > + { 0x90109, 0x169 },
> > > > > > + { 0x9010a, 0x58 },
> > > > > > + { 0x9010b, 0x0 },
> > > > > > + { 0x9010c, 0x68 },
> > > > > > + { 0x9010d, 0x0 },
> > > > > > + { 0x9010e, 0x408 },
> > > > > > + { 0x9010f, 0x169 },
> > > > > > + { 0x90110, 0x0 },
> > > > > > + { 0x90111, 0x8b10 },
> > > > > > + { 0x90112, 0x168 },
> > > > > > + { 0x90113, 0x0 },
> > > > > > + { 0x90114, 0xab10 },
> > > > > > + { 0x90115, 0x168 },
> > > > > > + { 0x90116, 0x0 },
> > > > > > + { 0x90117, 0x1d8 },
> > > > > > + { 0x90118, 0x169 },
> > > > > > + { 0x90119, 0x80 },
> > > > > > + { 0x9011a, 0x790 },
> > > > > > + { 0x9011b, 0x16a },
> > > > > > + { 0x9011c, 0x18 },
> > > > > > + { 0x9011d, 0x7aa },
> > > > > > + { 0x9011e, 0x6a },
> > > > > > + { 0x9011f, 0xa },
> > > > > > + { 0x90120, 0x0 },
> > > > > > + { 0x90121, 0x1e9 },
> > > > > > + { 0x90122, 0x8 },
> > > > > > + { 0x90123, 0x8080 },
> > > > > > + { 0x90124, 0x108 },
> > > > > > + { 0x90125, 0xf },
> > > > > > + { 0x90126, 0x408 },
> > > > > > + { 0x90127, 0x169 },
> > > > > > + { 0x90128, 0xc },
> > > > > > + { 0x90129, 0x0 },
> > > > > > + { 0x9012a, 0x68 },
> > > > > > + { 0x9012b, 0x9 },
> > > > > > + { 0x9012c, 0x0 },
> > > > > > + { 0x9012d, 0x1a9 },
> > > > > > + { 0x9012e, 0x0 },
> > > > > > + { 0x9012f, 0x408 },
> > > > > > + { 0x90130, 0x169 },
> > > > > > + { 0x90131, 0x0 },
> > > > > > + { 0x90132, 0x8080 },
> > > > > > + { 0x90133, 0x108 },
> > > > > > + { 0x90134, 0x8 },
> > > > > > + { 0x90135, 0x7aa },
> > > > > > + { 0x90136, 0x6a },
> > > > > > + { 0x90137, 0x0 },
> > > > > > + { 0x90138, 0x8568 },
> > > > > > + { 0x90139, 0x108 },
> > > > > > + { 0x9013a, 0xb7 },
> > > > > > + { 0x9013b, 0x790 },
> > > > > > + { 0x9013c, 0x16a },
> > > > > > + { 0x9013d, 0x1f },
> > > > > > + { 0x9013e, 0x0 },
> > > > > > + { 0x9013f, 0x68 },
> > > > > > + { 0x90140, 0x8 },
> > > > > > + { 0x90141, 0x8558 },
> > > > > > + { 0x90142, 0x168 },
> > > > > > + { 0x90143, 0xf },
> > > > > > + { 0x90144, 0x408 },
> > > > > > + { 0x90145, 0x169 },
> > > > > > + { 0x90146, 0xc },
> > > > > > + { 0x90147, 0x0 },
> > > > > > + { 0x90148, 0x68 },
> > > > > > + { 0x90149, 0x0 },
> > > > > > + { 0x9014a, 0x408 },
> > > > > > + { 0x9014b, 0x169 },
> > > > > > + { 0x9014c, 0x0 },
> > > > > > + { 0x9014d, 0x8558 },
> > > > > > + { 0x9014e, 0x168 },
> > > > > > + { 0x9014f, 0x8 },
> > > > > > + { 0x90150, 0x3c8 },
> > > > > > + { 0x90151, 0x1a9 },
> > > > > > + { 0x90152, 0x3 },
> > > > > > + { 0x90153, 0x370 },
> > > > > > + { 0x90154, 0x129 },
> > > > > > + { 0x90155, 0x20 },
> > > > > > + { 0x90156, 0x2aa },
> > > > > > + { 0x90157, 0x9 },
> > > > > > + { 0x90158, 0x0 },
> > > > > > + { 0x90159, 0x400 },
> > > > > > + { 0x9015a, 0x10e },
> > > > > > + { 0x9015b, 0x8 },
> > > > > > + { 0x9015c, 0xe8 },
> > > > > > + { 0x9015d, 0x109 },
> > > > > > + { 0x9015e, 0x0 },
> > > > > > + { 0x9015f, 0x8140 },
> > > > > > + { 0x90160, 0x10c },
> > > > > > + { 0x90161, 0x10 },
> > > > > > + { 0x90162, 0x8138 },
> > > > > > + { 0x90163, 0x10c },
> > > > > > + { 0x90164, 0x8 },
> > > > > > + { 0x90165, 0x7c8 },
> > > > > > + { 0x90166, 0x101 },
> > > > > > + { 0x90167, 0x8 },
> > > > > > + { 0x90168, 0x0 },
> > > > > > + { 0x90169, 0x8 },
> > > > > > + { 0x9016a, 0x8 },
> > > > > > + { 0x9016b, 0x448 },
> > > > > > + { 0x9016c, 0x109 },
> > > > > > + { 0x9016d, 0xf },
> > > > > > + { 0x9016e, 0x7c0 },
> > > > > > + { 0x9016f, 0x109 },
> > > > > > + { 0x90170, 0x0 },
> > > > > > + { 0x90171, 0xe8 },
> > > > > > + { 0x90172, 0x109 },
> > > > > > + { 0x90173, 0x47 },
> > > > > > + { 0x90174, 0x630 },
> > > > > > + { 0x90175, 0x109 },
> > > > > > + { 0x90176, 0x8 },
> > > > > > + { 0x90177, 0x618 },
> > > > > > + { 0x90178, 0x109 },
> > > > > > + { 0x90179, 0x8 },
> > > > > > + { 0x9017a, 0xe0 },
> > > > > > + { 0x9017b, 0x109 },
> > > > > > + { 0x9017c, 0x0 },
> > > > > > + { 0x9017d, 0x7c8 },
> > > > > > + { 0x9017e, 0x109 },
> > > > > > + { 0x9017f, 0x8 },
> > > > > > + { 0x90180, 0x8140 },
> > > > > > + { 0x90181, 0x10c },
> > > > > > + { 0x90182, 0x0 },
> > > > > > + { 0x90183, 0x1 },
> > > > > > + { 0x90184, 0x8 },
> > > > > > + { 0x90185, 0x8 },
> > > > > > + { 0x90186, 0x4 },
> > > > > > + { 0x90187, 0x8 },
> > > > > > + { 0x90188, 0x8 },
> > > > > > + { 0x90189, 0x7c8 },
> > > > > > + { 0x9018a, 0x101 },
> > > > > > + { 0x90006, 0x0 },
> > > > > > + { 0x90007, 0x0 },
> > > > > > + { 0x90008, 0x8 },
> > > > > > + { 0x90009, 0x0 },
> > > > > > + { 0x9000a, 0x0 },
> > > > > > + { 0x9000b, 0x0 },
> > > > > > + { 0xd00e7, 0x400 },
> > > > > > + { 0x90017, 0x0 },
> > > > > > + { 0x9001f, 0x2a },
> > > > > > + { 0x90026, 0x6a },
> > > > > > + { 0x400d0, 0x0 },
> > > > > > + { 0x400d1, 0x101 },
> > > > > > + { 0x400d2, 0x105 },
> > > > > > + { 0x400d3, 0x107 },
> > > > > > + { 0x400d4, 0x10f },
> > > > > > + { 0x400d5, 0x202 },
> > > > > > + { 0x400d6, 0x20a },
> > > > > > + { 0x400d7, 0x20b },
> > > > > > + { 0x2003a, 0x2 },
> > > > > > + { 0x2000b, 0x5d },
> > > > > > + { 0x2000c, 0xbb },
> > > > > > + { 0x2000d, 0x753 },
> > > > > > + { 0x2000e, 0x2c },
> > > > > > + { 0x12000b, 0xc },
> > > > > > + { 0x12000c, 0x19 },
> > > > > > + { 0x12000d, 0xfa },
> > > > > > + { 0x12000e, 0x10 },
> > > > > > + { 0x22000b, 0x3 },
> > > > > > + { 0x22000c, 0x6 },
> > > > > > + { 0x22000d, 0x3e },
> > > > > > + { 0x22000e, 0x10 },
> > > > > > + { 0x9000c, 0x0 },
> > > > > > + { 0x9000d, 0x173 },
> > > > > > + { 0x9000e, 0x60 },
> > > > > > + { 0x9000f, 0x6110 },
> > > > > > + { 0x90010, 0x2152 },
> > > > > > + { 0x90011, 0xdfbd },
> > > > > > + { 0x90012, 0x60 },
> > > > > > + { 0x90013, 0x6152 },
> > > > > > + { 0x20010, 0x5a },
> > > > > > + { 0x20011, 0x3 },
> > > > > > + { 0x40080, 0xe0 },
> > > > > > + { 0x40081, 0x12 },
> > > > > > + { 0x40082, 0xe0 },
> > > > > > + { 0x40083, 0x12 },
> > > > > > + { 0x40084, 0xe0 },
> > > > > > + { 0x40085, 0x12 },
> > > > > > + { 0x140080, 0xe0 },
> > > > > > + { 0x140081, 0x12 },
> > > > > > + { 0x140082, 0xe0 },
> > > > > > + { 0x140083, 0x12 },
> > > > > > + { 0x140084, 0xe0 },
> > > > > > + { 0x140085, 0x12 },
> > > > > > + { 0x240080, 0xe0 },
> > > > > > + { 0x240081, 0x12 },
> > > > > > + { 0x240082, 0xe0 },
> > > > > > + { 0x240083, 0x12 },
> > > > > > + { 0x240084, 0xe0 },
> > > > > > + { 0x240085, 0x12 },
> > > > > > + { 0x400fd, 0xf },
> > > > > > + { 0x10011, 0x1 },
> > > > > > + { 0x10012, 0x1 },
> > > > > > + { 0x10013, 0x180 },
> > > > > > + { 0x10018, 0x1 },
> > > > > > + { 0x10002, 0x6209 },
> > > > > > + { 0x100b2, 0x1 },
> > > > > > + { 0x101b4, 0x1 },
> > > > > > + { 0x102b4, 0x1 },
> > > > > > + { 0x103b4, 0x1 },
> > > > > > + { 0x104b4, 0x1 },
> > > > > > + { 0x105b4, 0x1 },
> > > > > > + { 0x106b4, 0x1 },
> > > > > > + { 0x107b4, 0x1 },
> > > > > > + { 0x108b4, 0x1 },
> > > > > > + { 0x11011, 0x1 },
> > > > > > + { 0x11012, 0x1 },
> > > > > > + { 0x11013, 0x180 },
> > > > > > + { 0x11018, 0x1 },
> > > > > > + { 0x11002, 0x6209 },
> > > > > > + { 0x110b2, 0x1 },
> > > > > > + { 0x111b4, 0x1 },
> > > > > > + { 0x112b4, 0x1 },
> > > > > > + { 0x113b4, 0x1 },
> > > > > > + { 0x114b4, 0x1 },
> > > > > > + { 0x115b4, 0x1 },
> > > > > > + { 0x116b4, 0x1 },
> > > > > > + { 0x117b4, 0x1 },
> > > > > > + { 0x118b4, 0x1 },
> > > > > > + { 0x12011, 0x1 },
> > > > > > + { 0x12012, 0x1 },
> > > > > > + { 0x12013, 0x180 },
> > > > > > + { 0x12018, 0x1 },
> > > > > > + { 0x12002, 0x6209 },
> > > > > > + { 0x120b2, 0x1 },
> > > > > > + { 0x121b4, 0x1 },
> > > > > > + { 0x122b4, 0x1 },
> > > > > > + { 0x123b4, 0x1 },
> > > > > > + { 0x124b4, 0x1 },
> > > > > > + { 0x125b4, 0x1 },
> > > > > > + { 0x126b4, 0x1 },
> > > > > > + { 0x127b4, 0x1 },
> > > > > > + { 0x128b4, 0x1 },
> > > > > > + { 0x13011, 0x1 },
> > > > > > + { 0x13012, 0x1 },
> > > > > > + { 0x13013, 0x180 },
> > > > > > + { 0x13018, 0x1 },
> > > > > > + { 0x13002, 0x6209 },
> > > > > > + { 0x130b2, 0x1 },
> > > > > > + { 0x131b4, 0x1 },
> > > > > > + { 0x132b4, 0x1 },
> > > > > > + { 0x133b4, 0x1 },
> > > > > > + { 0x134b4, 0x1 },
> > > > > > + { 0x135b4, 0x1 },
> > > > > > + { 0x136b4, 0x1 },
> > > > > > + { 0x137b4, 0x1 },
> > > > > > + { 0x138b4, 0x1 },
> > > > > > + { 0x2003a, 0x2 },
> > > > > > + { 0xc0080, 0x2 },
> > > > > > + { 0xd0000, 0x1 },
> > > > > > +};
> > > > >
> > > > > The same as above.
> > > > >
> > > > > > +
> > > > > > +struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
> > > > > > + {
> > > > > > + /* P0 3000mts 1D */
> > > > > > + .drate = 3000,
> > > > > > + .fw_type = FW_1D_IMAGE,
> > > > > > + .fsp_cfg = lpddr4_fsp0_cfg,
> > > > > > + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg),
> > > > > > + },
> > > > > > + {
> > > > > > + /* P0 3000mts 2D */
> > > > > > + .drate = 3000,
> > > > > > + .fw_type = FW_2D_IMAGE,
> > > > > > + .fsp_cfg = lpddr4_fsp0_2d_cfg,
> > > > > > + .fsp_cfg_num =
> > > > > > ARRAY_SIZE(lpddr4_fsp0_2d_cfg),
> > > > > > + },
> > > > > > + {
> > > > > > + /* P1 400mts 1D */
> > > > > > + .drate = 400,
> > > > > > + .fw_type = FW_1D_IMAGE,
> > > > > > + .fsp_cfg = lpddr4_fsp1_cfg,
> > > > > > + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg),
> > > > > > + },
> > > > > > + {
> > > > > > + /* P1 100mts 1D */
> > > > > > + .drate = 100,
> > > > > > + .fw_type = FW_1D_IMAGE,
> > > > > > + .fsp_cfg = lpddr4_fsp2_cfg,
> > > > > > + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg),
> > > > > > + },
> > > > > > +};
> > > > > > +
> > > > > > +/* lpddr4 timing config params on EVK board */
> > > > > > +struct dram_timing_info dram_timing = {
> > > > > > + .ddrc_cfg = lpddr4_ddrc_cfg,
> > > > > > + .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
> > > > > > + .ddrphy_cfg = lpddr4_ddrphy_cfg,
> > > > > > + .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg),
> > > > > > + .fsp_msg = lpddr4_dram_fsp_msg,
> > > > > > + .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg),
> > > > > > + .ddrphy_trained_csr = lpddr4_ddrphy_trained_csr,
> > > > > > + .ddrphy_trained_csr_num =
> > > > > > ARRAY_SIZE(lpddr4_ddrphy_trained_csr),
> > > > > > + .ddrphy_pie = lpddr4_phy_pie,
> > > > > > + .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
> > > > >
> > > > > It would be best to get the above values calculated dynamically
> > > > > for this SoC.
> > > > >
> > > > > > +};
> > > > > > diff --git a/board/freescale/imx8mm_evk/spl.c
> > > > > > b/board/freescale/imx8mm_evk/spl.c new file mode 100644
> > > > > > index 0000000000..cf1dfc2c2a
> > > > > > --- /dev/null
> > > > > > +++ b/board/freescale/imx8mm_evk/spl.c
> > > > > > @@ -0,0 +1,187 @@
> > > > > > +// SPDX-License-Identifier: GPL-2.0+
> > > > > > +/*
> > > > > > + * Copyright 2019 NXP
> > > > > > + */
> > > > > > +
> > > > > > +#include <common.h>
> > > > > > +#include <spl.h>
> > > > > > +#include <asm/io.h>
> > > > > > +#include <errno.h>
> > > > > > +#include <asm/io.h>
> > > > > > +#include <asm/mach-imx/iomux-v3.h>
> > > > > > +#include <asm/arch/imx8mm_pins.h>
> > > > > > +#include <asm/arch/sys_proto.h>
> > > > > > +#include <power/pmic.h>
> > > > > > +#include <asm/arch/clock.h>
> > > > > > +#include <asm/mach-imx/gpio.h>
> > > > > > +#include <asm/mach-imx/mxc_i2c.h>
> > > > > > +#include <fsl_esdhc.h>
> > > > > > +#include <mmc.h>
> > > > > > +#include <asm/arch/ddr.h>
> > > > > > +
> > > > > > +DECLARE_GLOBAL_DATA_PTR;
> > > > > > +
> > > > > > +void spl_dram_init(void)
> > > > > > +{
> > > > > > + ddr_init(&dram_timing);
> > > > > > +}
> > > > > > +
> > > > > > +#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 18)
> > > > > > +#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
> > > > > > +
> > > > > > +#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS |
> > > > > PAD_CTL_PUE | \
> > > > > > + PAD_CTL_PE | PAD_CTL_FSEL2)
> > > > > > +#define USDHC_GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE1)
> > > > > > +
> > > > > > +static iomux_v3_cfg_t const usdhc3_pads[] = {
> > > > > > + IMX8MM_PAD_NAND_WE_B_USDHC3_CLK |
> > > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > > + IMX8MM_PAD_NAND_WP_B_USDHC3_CMD |
> > > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > > + IMX8MM_PAD_NAND_DATA04_USDHC3_DATA0 |
> > > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > > + IMX8MM_PAD_NAND_DATA05_USDHC3_DATA1 |
> > > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > > + IMX8MM_PAD_NAND_DATA06_USDHC3_DATA2 |
> > > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > > + IMX8MM_PAD_NAND_DATA07_USDHC3_DATA3 |
> > > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > > + IMX8MM_PAD_NAND_RE_B_USDHC3_DATA4 |
> > > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > > + IMX8MM_PAD_NAND_CE2_B_USDHC3_DATA5 |
> > > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > > + IMX8MM_PAD_NAND_CE3_B_USDHC3_DATA6 |
> > > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > > + IMX8MM_PAD_NAND_CLE_USDHC3_DATA7 |
> > > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL), +};
> > > > > > +
> > > > > > +static iomux_v3_cfg_t const usdhc2_pads[] = {
> > > > > > + IMX8MM_PAD_SD2_CLK_USDHC2_CLK |
> > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > > + IMX8MM_PAD_SD2_CMD_USDHC2_CMD |
> > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > > + IMX8MM_PAD_SD2_DATA0_USDHC2_DATA0 |
> > > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > > + IMX8MM_PAD_SD2_DATA1_USDHC2_DATA1 |
> > > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > > + IMX8MM_PAD_SD2_DATA2_USDHC2_DATA2 |
> > > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > > + IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 |
> > > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > > + IMX8MM_PAD_SD2_RESET_B_GPIO2_IO19 |
> > > > > > MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), +};
> > > > > > +
> > > > > > +/*
> > > > > > + * The evk board uses DAT3 to detect CD card plugin,
> > > > > > + * in u-boot we mux the pin to GPIO when doing
> > > > > > board_mmc_getcd.
> > > > > > + */
> > > > > > +static iomux_v3_cfg_t const usdhc2_cd_pad =
> > > > > > + IMX8MM_PAD_SD2_DATA3_GPIO2_IO18 |
> > > > > > MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL); +
> > > > > > +static iomux_v3_cfg_t const usdhc2_dat3_pad =
> > > > > > + IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 |
> > > > > > + MUX_PAD_CTRL(USDHC_PAD_CTRL);
> > > > > > +
> > > > > > +static struct fsl_esdhc_cfg usdhc_cfg[2] = {
> > > > > > + {USDHC2_BASE_ADDR, 0, 1},
> > > > > > + {USDHC3_BASE_ADDR, 0, 1},
> > > > > > +};
> > > > > > +
> > > > > > +int board_mmc_init(bd_t *bis)
> > > > > > +{
> > > > > > + int i, ret;
> > > > > > + /*
> > > > > > + * According to the board_mmc_init() the following
> > > > > > map is done:
> > > > > > + * (U-Boot device node) (Physical Port)
> > > > > > + * mmc0 USDHC1
> > > > > > + * mmc1 USDHC2
> > > > > > + */
> > > > > > + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
> > > > > > + switch (i) {
> > > > > > + case 0:
> > > > > > + usdhc_cfg[0].sdhc_clk =
> > > > > > mxc_get_clock(MXC_ESDHC2_CLK);
> > > > > > +
> > > > > > imx_iomux_v3_setup_multiple_pads(usdhc2_pads, +
> > > > > > ARRAY_SIZE(usdhc2_pads));
> > > > > > + gpio_request(USDHC2_PWR_GPIO,
> > > > > > "usdhc2_reset");
> > > > > > +
> > > > > > gpio_direction_output(USDHC2_PWR_GPIO, 0);
> > > > > > + udelay(500);
> > > > > > +
> > > > > > gpio_direction_output(USDHC2_PWR_GPIO, 1);
> > > > > > + break;
> > > > > > + case 1:
> > > > > > + usdhc_cfg[1].sdhc_clk =
> > > > > > mxc_get_clock(MXC_ESDHC3_CLK);
> > > > > > +
> > > > > > imx_iomux_v3_setup_multiple_pads(usdhc3_pads, +
> > > > > > ARRAY_SIZE(usdhc3_pads));
> > > > > > + break;
> > > > >
> > > > > It would be best if you could enable DM/DTS in SPL too from the
> > > > > outset (and share the SPL size).
> > > > >
> > > > > Do you have any timeline for converting SPL to DM/DTS?
> > > > >
> > > > > > + default:
> > > > > > + printf("USDHC controllers %d not
> > > > > > supported \n", i + 1);
> > > > > > + return -EINVAL;
> > > > > > + }
> > > > > > +
> > > > > > + ret = fsl_esdhc_initialize(bis,
> > > > > > &usdhc_cfg[i]);
> > > > > > + if (ret)
> > > > > > + return ret;
> > > > > > + }
> > > > > > +
> > > > > > + return 0;
> > > > > > +}
> > > > > > +
> > > > > > +int board_mmc_getcd(struct mmc *mmc)
> > > > > > +{
> > > > > > + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg
> > > > > > *)mmc->priv;
> > > > > > + int ret = 0;
> > > > > > +
> > > > > > + switch (cfg->esdhc_base) {
> > > > > > + case USDHC3_BASE_ADDR:
> > > > > > + ret = 1;
> > > > > > + break;
> > > > > > + case USDHC2_BASE_ADDR:
> > > > > > + imx_iomux_v3_setup_pad(usdhc2_cd_pad);
> > > > > > + gpio_request(USDHC2_CD_GPIO, "usdhc2 cd");
> > > > > > + gpio_direction_input(USDHC2_CD_GPIO);
> > > > > > +
> > > > > > + /*
> > > > > > + * Since it is the DAT3 pin, this pin is
> > > > > > pulled to
> > > > > > + * low voltage if no card
> > > > > > + */
> > > > > > + ret = gpio_get_value(USDHC2_CD_GPIO);
> > > > > > +
> > > > > > + imx_iomux_v3_setup_pad(usdhc2_dat3_pad);
> > > > > > + return ret;
> > > > > > + }
> > > > > > +
> > > > > > + return 1;
> > > > > > +}
> > > > > > +
> > > > > > +void spl_board_init(void)
> > > > > > +{
> > > > > > + puts("Normal Boot\n");
> > > > > > +}
> > > > > > +
> > > > > > +#ifdef CONFIG_SPL_LOAD_FIT
> > > > > > +int board_fit_config_name_match(const char *name)
> > > > > > +{
> > > > > > + /* Just empty function now - can't decide what to
> > > > > > choose */
> > > > > > + debug("%s: %s\n", __func__, name);
> > > > > > +
> > > > > > + return 0;
> > > > > > +}
> > > > > > +#endif
> > > > > > +
> > > > > > +void board_init_f(ulong dummy)
> > > > > > +{
> > > > > > + int ret;
> > > > > > +
> > > > > > + /* Clear global data */
> > > > > > + memset((void *)gd, 0, sizeof(gd_t));
> > > > > > +
> > > > > > + arch_cpu_init();
> > > > > > +
> > > > > > + init_uart_clk(1);
> > > > > > +
> > > > > > + board_early_init_f();
> > > > > > +
> > > > > > + timer_init();
> > > > > > +
> > > > > > + preloader_console_init();
> > > > > > +
> > > > > > + /* Clear the BSS. */
> > > > > > + memset(__bss_start, 0, __bss_end - __bss_start);
> > > > > > +
> > > > > > + ret = spl_init();
> > > > > > + if (ret) {
> > > > > > + debug("spl_init() failed: %d\n", ret);
> > > > > > + hang();
> > > > > > + }
> > > > > > +
> > > > > > + enable_tzc380();
> > > > > > +
> > > > > > + /* DDR initialization */
> > > > > > + spl_dram_init();
> > > > > > +
> > > > > > + board_init_r(NULL, 0);
> > > > > > +}
> > > > > > diff --git a/configs/imx8mm_evk_defconfig
> > > > > > b/configs/imx8mm_evk_defconfig new file mode 100644
> > > > > > index 0000000000..6110f23e38
> > > > > > --- /dev/null
> > > > > > +++ b/configs/imx8mm_evk_defconfig
> > > > > > @@ -0,0 +1,41 @@
> > > > > > +CONFIG_ARM=y
> > > > > > +CONFIG_ARCH_IMX8M=y
> > > > > > +CONFIG_SYS_TEXT_BASE=0x40200000
> > > > > > +CONFIG_SPL_GPIO_SUPPORT=y
> > > > > > +CONFIG_SYS_MALLOC_F_LEN=0x2000
> > > > > > +CONFIG_TARGET_IMX8MM_EVK=y
> > > > > > +CONFIG_SPL_MMC_SUPPORT=y
> > > > > > +CONFIG_SPL_SERIAL_SUPPORT=y
> > > > > > +CONFIG_SPL=y
> > > > > > +CONFIG_FIT=y
> > > > > > +CONFIG_FIT_EXTERNAL_OFFSET=0x3000
> > > > > > +CONFIG_SPL_LOAD_FIT=y
> > > > > >
> > >
> +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
> > > > > >
> > > > >
> > >
> +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m
> > > > > /imximage.cfg,SPL_TEXT_BASE=0x7E1000"
> > > > > > +CONFIG_DEFAULT_FDT_FILE="fsl-imx8mm-evk.dtb"
> > > > > > +CONFIG_SPL_BOARD_INIT=y
> > > > > > +CONFIG_SPL_I2C_SUPPORT=y
> > > > > > +CONFIG_HUSH_PARSER=y
> > > > > > +CONFIG_CMD_GPIO=y
> > > > > > +CONFIG_CMD_I2C=y
> > > > > > +CONFIG_CMD_CACHE=y
> > > > > > +CONFIG_CMD_REGULATOR=y
> > > > > > +CONFIG_CMD_EXT2=y
> > > > > > +CONFIG_CMD_EXT4=y
> > > > > > +CONFIG_CMD_EXT4_WRITE=y
> > > > > > +CONFIG_CMD_FAT=y
> > > > > > +CONFIG_OF_CONTROL=y
> > > > > > +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mm-evk"
> > > > > > +CONFIG_DM_GPIO=y
> > > > > > +CONFIG_MXC_GPIO=y
> > > > > > +CONFIG_DM_I2C=y
> > > > > > +CONFIG_SYS_I2C_MXC=y
> > > > > > +CONFIG_DM_MMC=y
> > > > > > +CONFIG_DM_ETH=y
> > > > >
> > > > > Here you enable the DM_ETH, but the welcome u-boot info says:
> > > > >
> > > > > "Net: No ethernet found."
> > > > >
> > > > > > +CONFIG_PINCTRL=y
> > > > > > +CONFIG_PINCTRL_IMX8M=y
> > > > > > +CONFIG_DM_REGULATOR=y
> > > > > > +CONFIG_DM_REGULATOR_FIXED=y
> > > > > > +CONFIG_DM_REGULATOR_GPIO=y
> > > > > > +CONFIG_MXC_UART=y
> > > > > > +CONFIG_DM_THERMAL=y
> > > > > > diff --git a/include/configs/imx8mm_evk.h
> > > > > > b/include/configs/imx8mm_evk.h new file mode 100644
> > > > > > index 0000000000..f944308757
> > > > > > --- /dev/null
> > > > > > +++ b/include/configs/imx8mm_evk.h
> > > > > > @@ -0,0 +1,221 @@
> > > > > > +/* SPDX-License-Identifier: GPL-2.0+ */
> > > > > > +/*
> > > > > > + * Copyright 2018 NXP
> > > > > > + */
> > > > > > +
> > > > > > +#ifndef __IMX8MM_EVK_H
> > > > > > +#define __IMX8MM_EVK_H
> > > > > > +
> > > > > > +#include <linux/sizes.h>
> > > > > > +#include <asm/arch/imx-regs.h>
> > > > > > +
> > > > > > +#ifdef CONFIG_SECURE_BOOT
> > > > > > +#define CONFIG_CSF_SIZE 0x2000 /* 8K
> > > > > > region */ +#endif
> > > > > > +
> > > > > > +#define CONFIG_SPL_MAX_SIZE (148 * 1024)
> > > > > > +#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
> > > > > > +#define
> CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
> > > > > > +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
> > > 0x300
> > > > > > +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
> > > > > > +#define CONFIG_SYS_UBOOT_BASE \
> > > > > > + (QSPI0_AMBA_BASE +
> > > > > CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR *
> > > > > > 512) +
> > > > > > +#ifdef CONFIG_SPL_BUILD
> > > > > > +/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
> > > > > > +#define CONFIG_SPL_WATCHDOG_SUPPORT
> > > > > > +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
> > > > > > +#define CONFIG_SPL_POWER_SUPPORT
> > > > > > +#define
> > > > > > CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
> > > > > > +#define CONFIG_SPL_STACK 0x91fff0 +#define
> > > > > > CONFIG_SPL_LIBCOMMON_SUPPORT +#define
> > > > > CONFIG_SPL_LIBGENERIC_SUPPORT
> > > > > > +#define CONFIG_SPL_BSS_START_ADDR 0x00910000
> > > > > > +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB
> > > > > > */ +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
> > > > > > +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512
> > > > > > KB */ +#define CONFIG_SYS_ICACHE_OFF
> > > > > > +#define CONFIG_SYS_DCACHE_OFF
> > > > > > +
> > > > > > +#define CONFIG_MALLOC_F_ADDR 0x912000 /*
> > > > > > malloc f used before GD_FLG_FULL_MALLOC_INIT set */ +
> > > > > > +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image
> > > gives a
> > > > > error
> > > > > > info not panic */ +
> > > > > > +#undef CONFIG_DM_MMC
> > > > > > +#undef CONFIG_DM_PMIC
> > > > > > +#undef CONFIG_DM_PMIC_PFUZE100
> > > > >
> > > > > Why do you need to undef those config options?
> > > > >
> > > > > > +
> > > > > > +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> > > > > > +
> > > > > > +#endif
> > > > > > +
> > > > > > +#define CONFIG_REMAKE_ELF
> > > > > > +
> > > > > > +#define CONFIG_BOARD_EARLY_INIT_F
> > > > > > +#define CONFIG_BOARD_POSTCLK_INIT
> > > > > > +#define CONFIG_BOARD_LATE_INIT
> > > > > > +
> > > > > > +/* Flat Device Tree Definitions */
> > > > > > +#define CONFIG_OF_BOARD_SETUP
> > > > > > +
> > > > > > +#undef CONFIG_CMD_EXPORTENV
> > > > > > +#undef CONFIG_CMD_IMPORTENV
> > > > > > +#undef CONFIG_CMD_IMLS
> > > > > > +
> > > > > > +#undef CONFIG_CMD_CRC32
> > > > > > +#undef CONFIG_BOOTM_NETBSD
> > > > >
> > > > > There seems to be some issue with inheritance, as you need to
> > > > > undef those values manually.
> > > > >
> > > > > Why is it needed?
> > > > >
> > > > > > +
> > > > > > +/* ENET Config */
> > > > > > +/* ENET1 */
> > > > > > +#if defined(CONFIG_CMD_NET)
> > > > > > +#define CONFIG_CMD_PING
> > > > > > +#define CONFIG_CMD_DHCP
> > > > > > +#define CONFIG_CMD_MII
> > > > > > +#define CONFIG_MII
> > > > > > +#define CONFIG_ETHPRIME "FEC"
> > > > > > +
> > > > > > +#define CONFIG_FEC_MXC
> > > > > > +#define CONFIG_FEC_XCV_TYPE RGMII
> > > > > > +#define CONFIG_FEC_MXC_PHYADDR 0
> > > > > > +#define FEC_QUIRK_ENET_MAC
> > > > > > +
> > > > > > +#define CONFIG_PHY_GIGE
> > > > > > +#define IMX_FEC_BASE 0x30BE0000
> > > > > > +
> > > > > > +#define CONFIG_PHYLIB
> > > > > > +#define CONFIG_PHY_ATHEROS
> > > > > > +#endif
> > > > > > +
> > > > > > +/* Initial environment variables */
> > > > > > +#define CONFIG_EXTRA_ENV_SETTINGS \
> > > > > > + "script=boot.scr\0" \
> > > > > > + "image=Image\0" \
> > > > > > + "console=ttymxc1,115200
> > > > > > earlycon=ec_imx6q,0x30890000,115200\0" \
> > > > > > + "fdt_addr=0x43000000\0" \
> > > > > > + "fdt_high=0xffffffffffffffff\0" \
> > > > > > + "boot_fdt=try\0" \
> > > > > > + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
> > > > > > + "initrd_addr=0x43800000\0" \
> > > > > > + "initrd_high=0xffffffffffffffff\0" \
> > > > > > + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
> > > > > > + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART)
> > > > > > "\0" \
> > > > > > + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
> > > > > > + "mmcautodetect=yes\0" \
> > > > > > + "mmcargs=setenv bootargs ${jh_clk} console=${console}
> > > > > > root=${mmcroot}\0 " \
> > > > > > + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart}
> > > > > > ${loadaddr} ${script};\0" \
> > > > > > + "bootscript=echo Running bootscript from mmc ...; " \
> > > > > > + "source\0" \
> > > > > > + "loadimage=fatload mmc ${mmcdev}:${mmcpart}
> > > > > > ${loadaddr} ${image}\0" \
> > > > > > + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr}
> > > > > > ${fdt_file}\0" \
> > > > > > + "mmcboot=echo Booting from mmc ...; " \
> > > > > > + "run mmcargs; " \
> > > > > > + "if test ${boot_fdt} = yes || test
> > > > > > ${boot_fdt} = try; then " \
> > > > > > + "if run loadfdt; then " \
> > > > > > + "booti ${loadaddr} -
> > > > > > ${fdt_addr}; " \
> > > > > > + "else " \
> > > > > > + "echo WARN: Cannot load the
> > > > > > DT; " \
> > > > > > + "fi; " \
> > > > > > + "else " \
> > > > > > + "echo wait for boot; " \
> > > > > > + "fi;\0" \
> > > > > > + "netargs=setenv bootargs ${jh_clk}
> > > > > > console=${console} " \
> > > > > > + "root=/dev/nfs " \
> > > > > > + "ip=dhcp
> > > > > > nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
> > > > > > + "netboot=echo Booting from net ...; " \
> > > > > > + "run netargs; " \
> > > > > > + "if test ${ip_dyn} = yes; then " \
> > > > > > + "setenv get_cmd dhcp; " \
> > > > > > + "else " \
> > > > > > + "setenv get_cmd tftp; " \
> > > > > > + "fi; " \
> > > > > > + "${get_cmd} ${loadaddr} ${image}; " \
> > > > > > + "if test ${boot_fdt} = yes || test
> > > > > > ${boot_fdt} = try; then " \
> > > > > > + "if ${get_cmd} ${fdt_addr}
> > > > > > ${fdt_file}; then " \
> > > > > > + "booti ${loadaddr} -
> > > > > > ${fdt_addr}; " \
> > > > > > + "else " \
> > > > > > + "echo WARN: Cannot load the
> > > > > > DT; " \
> > > > > > + "fi; " \
> > > > > > + "else " \
> > > > > > + "booti; " \
> > > > > > + "fi;\0"
> > > > > > +
> > > > > > +#define CONFIG_BOOTCOMMAND \
> > > > > > + "mmc dev ${mmcdev}; if mmc rescan; then " \
> > > > > > + "if run loadbootscript; then " \
> > > > > > + "run bootscript; " \
> > > > > > + "else " \
> > > > > > + "if run loadimage; then " \
> > > > > > + "run mmcboot; " \
> > > > > > + "else run netboot; " \
> > > > > > + "fi; " \
> > > > > > + "fi; " \
> > > > > > + "else booti ${loadaddr} - ${fdt_addr}; fi"
> > > > > > +
> > > > > > +/* Link Definitions */
> > > > > > +#define CONFIG_LOADADDR 0x40480000
> > > > > > +
> > > > > > +#define CONFIG_SYS_LOAD_ADDR
> CONFIG_LOADADDR
> > > > > > +
> > > > > > +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
> > > > > > +#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
> > > > > > +#define CONFIG_SYS_INIT_SP_OFFSET \
> > > > > > + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> > > > > > +#define CONFIG_SYS_INIT_SP_ADDR \
> > > > > > + (CONFIG_SYS_INIT_RAM_ADDR +
> > > > > > CONFIG_SYS_INIT_SP_OFFSET) +
> > > > > > +#define CONFIG_ENV_OVERWRITE
> > > > > > +#if defined(CONFIG_ENV_IS_IN_MMC)
> > > > > > +#define CONFIG_ENV_OFFSET (64 * SZ_64K)
> > > > > > +#endif
> > > > > > +#define CONFIG_ENV_SIZE 0x1000
> > > > > > +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC2
> > > > > > */ +#define
> > > > > > CONFIG_MMCROOT "/dev/mmcblk1p2" /*
> > > > > > USDHC2 */ + +/* Size of malloc() pool */
> > > > > > +#define CONFIG_SYS_MALLOC_LEN SZ_32M
> > > > > > +
> > > > > > +#define CONFIG_SYS_SDRAM_BASE 0x40000000
> > > > > > +#define PHYS_SDRAM 0x40000000
> > > > > > +#define PHYS_SDRAM_SIZE 0x80000000 /*
> > > > > > 2GB DDR */ +
> > > > > > +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
> > > > > > +#define CONFIG_SYS_MEMTEST_END
> > > > > (CONFIG_SYS_MEMTEST_START +
> > > > > > (PHYS_SDRAM_SIZE >> 1)) +
> > > > > > +#define CONFIG_BAUDRATE 115200
> > > > > > +
> > > > > > +#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
> > > > > > +
> > > > > > +/* Monitor Command Prompt */
> > > > > > +#undef CONFIG_SYS_PROMPT
> > > > > > +#define CONFIG_SYS_PROMPT "u-boot=> "
> > > > > > +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
> > > > > > +#define CONFIG_SYS_CBSIZE 2048
> > > > > > +#define CONFIG_SYS_MAXARGS 64
> > > > > > +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
> > > > > > +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE
> > > > > > + \ +
> > > > > > sizeof(CONFIG_SYS_PROMPT) + 16) +
> > > > > > +#define CONFIG_IMX_BOOTAUX
> > > > > > +
> > > > > > +/* USDHC */
> > > > > > +#define CONFIG_CMD_MMC
> > > > > > +#define CONFIG_FSL_ESDHC
> > > > > > +#define CONFIG_FSL_USDHC
> > > > > > +
> > > > > > +#define CONFIG_SYS_FSL_USDHC_NUM 2
> > > > > > +#define CONFIG_SYS_FSL_ESDHC_ADDR 0
> > > > > > +
> > > > > > +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
> > > > > > +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
> > > > > > +
> > > > > > +#define CONFIG_MXC_OCOTP
> > > > > > +#define CONFIG_CMD_FUSE
> > > > > > +
> > > > > > +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C
> > > > > > bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /*
> > > > > > enable I2C bus 2 */ +#define
> > > > > > CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
> > > > > > +#define CONFIG_SYS_I2C_SPEED 100000
> > > > >
> > > > > Some of those values are (SYS_I2C_*, MXC_OCOTP, FSL_*) are
> > > > > already supported by Kconfig. Please use Kconfig instead.
> > > > >
> > > > > > +
> > > > > > +#define CONFIG_OF_SYSTEM_SETUP
> > > > > > +
> > > > > > +#endif
> > > > >
> > > > >
> > > > > Best regards,
> > > > >
> > > > > Lukasz Majewski
> > > > >
> > > > > --
> > > > >
> > > > > DENX Software Engineering GmbH, Managing Director:
> Wolfgang
> > > > > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194
> > > > > Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax:
> > > > > (+49)-8142-66989-80 Email: lukma at denx.de
> > >
> > >
> > >
> > >
> > > Best regards,
> > >
> > > Lukasz Majewski
> > >
> > > --
> > >
> > > DENX Software Engineering GmbH, Managing Director: Wolfgang
> > > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell,
> > > Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> > > lukma at denx.de
>
>
>
>
> Best regards,
>
> Lukasz Majewski
>
> --
>
> DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> lukma at denx.de
^ permalink raw reply [flat|nested] 39+ messages in thread* [U-Boot] [PATCH 20/20] imx: add i.MX8MM EVK board support
2019-01-30 8:50 ` Peng Fan
@ 2019-01-30 10:10 ` Lukasz Majewski
0 siblings, 0 replies; 39+ messages in thread
From: Lukasz Majewski @ 2019-01-30 10:10 UTC (permalink / raw)
To: u-boot
Hi Peng,
> > -----Original Message-----
> > From: Lukasz Majewski [mailto:lukma at denx.de]
> > Sent: 2019年1月30日 16:38
> > To: Peng Fan <peng.fan@nxp.com>
> > Cc: sbabic at denx.de; Fabio Estevam <fabio.estevam@nxp.com>;
> > dl-uboot-imx <uboot-imx@nxp.com>; u-boot at lists.denx.de
> > Subject: Re: [U-Boot] [PATCH 20/20] imx: add i.MX8MM EVK board
> > support
> >
> > On Wed, 30 Jan 2019 07:07:10 +0000
> > Peng Fan <peng.fan@nxp.com> wrote:
> >
> > > > -----Original Message-----
> > > > From: Lukasz Majewski [mailto:lukma at denx.de]
> > > > Sent: 2019年1月30日 14:54
> > > > To: Peng Fan <peng.fan@nxp.com>
> > > > Cc: sbabic at denx.de; Fabio Estevam <fabio.estevam@nxp.com>;
> > > > dl-uboot-imx <uboot-imx@nxp.com>; u-boot at lists.denx.de
> > > > Subject: Re: [U-Boot] [PATCH 20/20] imx: add i.MX8MM EVK board
> > > > support
> > > >
> > > > Hi Peng,
> > > >
> > > > > > -----Original Message-----
> > > > > > From: Lukasz Majewski [mailto:lukma at denx.de]
> > > > > > Sent: 2019年1月30日 7:19
> > > > > > To: Peng Fan <peng.fan@nxp.com>
> > > > > > Cc: sbabic at denx.de; Fabio Estevam <fabio.estevam@nxp.com>;
> > > > > > dl-uboot-imx <uboot-imx@nxp.com>; u-boot at lists.denx.de
> > > > > > Subject: Re: [U-Boot] [PATCH 20/20] imx: add i.MX8MM EVK
> > > > > > board support
> > > > > >
> > > > > > Hi Peng,
> > > > > >
> > > > > > > Add i.MX8MM EVK board support.
> > > > > > >
> > > > > > > Add board and SoC dts
> > > > > > > Add ddr training code
> > > > > > > support SD/MMC/GPIO/PINCTRL/UART
> > > > > > >
> > > > > > > U-Boot SPL 2019.01-00148-g1179cffe66 (Jan 28 2019 -
> > > > > > > 17:37:34 +0800) Normal Boot
> > > > > > > Trying to boot from MMC1
> > > > > > >
> > > > > > > U-Boot 2019.01-00148-g1179cffe66 (Jan 28 2019 - 17:37:34
> > > > > > > +0800)
> > > > > > >
> > > > > > > CPU: Freescale i.MX8MMQ rev1.0 at 1200 MHz
> > > > > > > Reset cause: POR
> > > > > > > Model: NXP i.MX8MM EVK board
> > > > > > > DRAM: 2 GiB
> > > > > > > MMC: FSL_SDHC: 1, FSL_SDHC: 2
> > > > > > > In: serial
> > > > > > > Out: serial
> > > > > > > Err: serial
> > > > > > > DM
> > > > > >
> > > > > > You set/adjust latter in the code the fec network driver.
> > > > > > Why it is not found?
> > > > >
> > > > > I dropped network support, could add it in V2.
> > > >
> > > > From the patch it seems like the ETH is fully supported, at
> > > > lease from the source code point of view.
> > > >
> > > > >
> > > > > >
> > > > > > Could you also share the output of "dm tree" command?
> > > > >
> > > > > Sure.
> > > > >
> > > > > >
> > > > > > I suppose/guess that this board shall support as much as
> > > > > > possible of the DT/DM conversions?
> > > > >
> > > > > Ok.
> > > >
> > > > And I would like to emphasize the need of DDR training code (as
> > > > a functions, not pair of offset and value).
> > > >
> > > > Are you able to provide such code in the next version of the
> > > > patch?
> > >
> > > There is already common code under drivers/ddr/imx8m
> >
> > Yes. Indeed there code is there.
> >
> > > For the array in board file, It need ddr tool change, out of my
> > > knowledge.
> >
> > If the code is there - why not use it for this board? In that way we
> > would kill two birds with one stone - the code would be tested on
> > "blessed" NXP's development board.
>
> It is already used. The lpddr4_timing.c in board file is to provide
> configuration and the code in drivers/ddr/imx8m will use that to
> configure DDRC and DDR PHY.
Sorry to ask this - maybe I've misunderstood something. If we already
use the training code - why do we need to pass the long set of "offset,
value" tuples?
>
> Thanks,
> Peng.
>
> >
> > >
> > > Thanks,
> > > Peng.
> > >
> > > >
> > > > >
> > > > > Regards,
> > > > > Peng.
> > > > >
> > > > > >
> > > > > > > Hit any key to stop autoboot: 2
> > > > > > >
> > > > > > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > > > > > ---
> > > > > > > arch/arm/dts/fsl-imx8mm-evk.dts | 203 +++
> > > > > > > arch/arm/dts/fsl-imx8mm.dtsi | 586
> > ++++++++
> > > > > > > arch/arm/mach-imx/imx8m/Kconfig | 7 +
> > > > > > > board/freescale/imx8mm_evk/Kconfig | 12 +
> > > > > > > board/freescale/imx8mm_evk/MAINTAINERS | 6 +
> > > > > > > board/freescale/imx8mm_evk/Makefile | 12 +
> > > > > > > board/freescale/imx8mm_evk/imx8mm_evk.c | 144 ++
> > > > > > > board/freescale/imx8mm_evk/lpddr4_timing.c | 1980
> > > > > > > ++++++++++++++++++++++++++++
> > > > > > > board/freescale/imx8mm_evk/spl.c | 187 +++
> > > > > > > configs/imx8mm_evk_defconfig | 41 +
> > > > > > > include/configs/imx8mm_evk.h | 221 ++++ 11
> > > > > > > files changed, 3399 insertions(+) create mode 100644
> > > > > > > arch/arm/dts/fsl-imx8mm-evk.dts create mode 100644
> > > > > > > arch/arm/dts/fsl-imx8mm.dtsi create mode 100644
> > > > > > > board/freescale/imx8mm_evk/Kconfig create mode 100644
> > > > > > > board/freescale/imx8mm_evk/MAINTAINERS create mode 100644
> > > > > > > board/freescale/imx8mm_evk/Makefile create mode 100644
> > > > > > > board/freescale/imx8mm_evk/imx8mm_evk.c create mode 100644
> > > > > > > board/freescale/imx8mm_evk/lpddr4_timing.c create mode
> > > > > > > 100644 board/freescale/imx8mm_evk/spl.c create mode 100644
> > > > > > > configs/imx8mm_evk_defconfig create mode 100644
> > > > > > > include/configs/imx8mm_evk.h
> > > > > > >
> > > > > > > diff --git a/arch/arm/dts/fsl-imx8mm-evk.dts
> > > > > > > b/arch/arm/dts/fsl-imx8mm-evk.dts new file mode 100644
> > > > > > > index 0000000000..df409eca47
> > > > > > > --- /dev/null
> > > > > > > +++ b/arch/arm/dts/fsl-imx8mm-evk.dts
> > > > > > > @@ -0,0 +1,203 @@
> > > > > > > +// SPDX-License-Identifier: GPL-2.0+
> > > > > > > +/*
> > > > > > > + * Copyright 2019 NXP
> > > > > > > + */
> > > > > > > +
> > > > > > > +/dts-v1/;
> > > > > > > +
> > > > > > > +#include "fsl-imx8mm.dtsi"
> > > > > > > +
> > > > > > > +/ {
> > > > > > > + model = "NXP i.MX8MM EVK board";
> > > > > > > + compatible = "fsl,imx8mm-evk", "fsl,imx8mm";
> > > > > > > +
> > > > > > > + chosen {
> > > > > > > + stdout-path = &uart2;
> > > > > > > + };
> > > > > > > +
> > > > > > > + regulators {
> > > > > > > + compatible = "simple-bus";
> > > > > > > + #address-cells = <1>;
> > > > > > > + #size-cells = <0>;
> > > > > > > +
> > > > > > > + reg_usdhc2_vmmc: regulator-usdhc2 {
> > > > > > > + compatible = "regulator-fixed";
> > > > > > > + regulator-name = "VSD_3V3";
> > > > > > > + regulator-min-microvolt =
> > > > > > > <3300000>;
> > > > > > > + regulator-max-microvolt =
> > > > > > > <3300000>;
> > > > > > > + gpio = <&gpio2 19
> > > > > > > GPIO_ACTIVE_HIGH>;
> > > > > > > + off-on-delay = <20000>;
> > > > > > > + enable-active-high;
> > > > > > > + };
> > > > > > > + };
> > > > > > > +};
> > > > > > > +
> > > > > > > +&iomuxc {
> > > > > > > + pinctrl-names = "default";
> > > > > > > +
> > > > > > > + imx8mm-evk {
> > > > > > > + pinctrl_fec1: fec1grp {
> > > > > > > + fsl,pins = <
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
> > > > > > > + >;
> > > > > > > + };
> > > > > > > +
> > > > > > > + pinctrl_gpio_led: gpioledgrp {
> > > > > > > + fsl,pins = <
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
> > > > > > > + >;
> > > > > > > + };
> > > > > > > +
> > > > > > > + pinctrl_uart2: uart2grp {
> > > > > > > + fsl,pins = <
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
> > > > > > > + >;
> > > > > > > + };
> > > > > > > +
> > > > > > > + pinctrl_usdhc2_gpio: usdhc2grpgpio {
> > > > > > > + fsl,pins = <
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
> > > > > > > + >;
> > > > > > > + };
> > > > > > > +
> > > > > > > + pinctrl_usdhc2: usdhc2grp {
> > > > > > > + fsl,pins = <
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
> > > > > > > + >;
> > > > > > > + };
> > > > > > > +
> > > > > > > + pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
> > > > > > > + fsl,pins = <
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
> > > > > > > + >;
> > > > > > > + };
> > > > > > > +
> > > > > > > + pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
> > > > > > > + fsl,pins = <
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
> > > > > > > + >;
> > > > > > > + };
> > > > > > > +
> > > > > > > + pinctrl_usdhc3: usdhc3grp {
> > > > > > > + fsl,pins = <
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE
> > 0x190
> > > > > > > + >;
> > > > > > > + };
> > > > > > > +
> > > > > > > + pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
> > > > > > > + fsl,pins = <
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE
> > 0x194
> > > > > > > + >;
> > > > > > > + };
> > > > > > > +
> > > > > > > + pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
> > > > > > > + fsl,pins = <
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
> > > > > > > + >;
> > > > > > > + };
> > > > > > > +
> > > > > > > + pinctrl_wdog: wdoggrp {
> > > > > > > + fsl,pins = <
> > > > > > > +
> > > > > > > MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
> > > > > > > + >;
> > > > > > > + };
> > > > > > > + };
> > > > > > > +};
> > > > > > > +
> > > > > > > +&uart2 { /* console */
> > > > > > > + pinctrl-names = "default";
> > > > > > > + pinctrl-0 = <&pinctrl_uart2>;
> > > > > > > + status = "okay";
> > > > > > > +};
> > > > > > > +
> > > > > > > +&usdhc2 {
> > > > > > > + pinctrl-names = "default", "state_100mhz",
> > > > > > > "state_200mhz";
> > > > > > > + pinctrl-0 = <&pinctrl_usdhc2>,
> > > > > > > <&pinctrl_usdhc2_gpio>;
> > > > > > > + pinctrl-1 = <&pinctrl_usdhc2_100mhz>,
> > > > > > > <&pinctrl_usdhc2_gpio>;
> > > > > > > + pinctrl-2 = <&pinctrl_usdhc2_200mhz>,
> > > > > > > <&pinctrl_usdhc2_gpio>;
> > > > > > > + cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
> > > > > > > + bus-width = <4>;
> > > > > > > + vmmc-supply = <®_usdhc2_vmmc>;
> > > > > > > + status = "okay";
> > > > > > > +};
> > > > > > > +
> > > > > > > +&usdhc3 {
> > > > > > > + pinctrl-names = "default", "state_100mhz",
> > > > > > > "state_200mhz";
> > > > > > > + pinctrl-0 = <&pinctrl_usdhc3>;
> > > > > > > + pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
> > > > > > > + pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
> > > > > > > + bus-width = <8>;
> > > > > > > + non-removable;
> > > > > > > + status = "okay";
> > > > > > > +};
> > > > > > > +
> > > > > > > +&wdog1 {
> > > > > > > + pinctrl-names = "default";
> > > > > > > + pinctrl-0 = <&pinctrl_wdog>;
> > > > > > > + fsl,ext-reset-output;
> > > > > > > + status = "okay";
> > > > > > > +};
> > > > > > > diff --git a/arch/arm/dts/fsl-imx8mm.dtsi
> > > > > > > b/arch/arm/dts/fsl-imx8mm.dtsi new file mode 100644
> > > > > > > index 0000000000..8a808f856d
> > > > > > > --- /dev/null
> > > > > > > +++ b/arch/arm/dts/fsl-imx8mm.dtsi
> > > > > > > @@ -0,0 +1,586 @@
> > > > > > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > > > > > > +/*
> > > > > > > + * Copyright 2017-2019 NXP
> > > > > > > + */
> > > > > > > +
> > > > > > > +#include <dt-bindings/clock/imx8mm-clock.h>
> > > > > > > +#include <dt-bindings/gpio/gpio.h>
> > > > > > > +#include <dt-bindings/input/input.h>
> > > > > > > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > > > > > > +#include <dt-bindings/pinctrl/pins-imx8mm.h>
> > > > > > > +#include <dt-bindings/thermal/thermal.h>
> > > > > > > +
> > > > > > > +/ {
> > > > > > > + compatible = "fsl,imx8mm";
> > > > > > > + interrupt-parent = <&gic>;
> > > > > > > + #address-cells = <2>;
> > > > > > > + #size-cells = <2>;
> > > > > > > +
> > > > > > > + aliases {
> > > > > > > + i2c0 = &i2c1;
> > > > > > > + i2c1 = &i2c2;
> > > > > > > + i2c2 = &i2c3;
> > > > > > > + i2c3 = &i2c4;
> > > > > > > + serial0 = &uart1;
> > > > > > > + serial1 = &uart2;
> > > > > > > + serial2 = &uart3;
> > > > > > > + serial3 = &uart4;
> > > > > > > + spi0 = &ecspi1;
> > > > > > > + spi1 = &ecspi2;
> > > > > > > + spi2 = &ecspi3;
> > > > > > > + mmc0 = &usdhc1;
> > > > > > > + mmc1 = &usdhc2;
> > > > > > > + mmc2 = &usdhc3;
> > > > > > > + gpio0 = &gpio1;
> > > > > > > + gpio1 = &gpio2;
> > > > > > > + gpio2 = &gpio3;
> > > > > > > + gpio3 = &gpio4;
> > > > > > > + gpio4 = &gpio5;
> > > > > > > + };
> > > > > > > +
> > > > > > > + cpus {
> > > > > > > + #address-cells = <1>;
> > > > > > > + #size-cells = <0>;
> > > > > > > +
> > > > > > > + A53_0: cpu at 0 {
> > > > > > > + device_type = "cpu";
> > > > > > > + compatible = "arm,cortex-a53";
> > > > > > > + reg = <0x0>;
> > > > > > > + enable-method = "psci";
> > > > > > > + next-level-cache = <&A53_L2>;
> > > > > > > + };
> > > > > > > +
> > > > > > > + A53_1: cpu at 1 {
> > > > > > > + device_type = "cpu";
> > > > > > > + compatible = "arm,cortex-a53";
> > > > > > > + reg = <0x1>;
> > > > > > > + enable-method = "psci";
> > > > > > > + next-level-cache = <&A53_L2>;
> > > > > > > + };
> > > > > > > +
> > > > > > > + A53_2: cpu at 2 {
> > > > > > > + device_type = "cpu";
> > > > > > > + compatible = "arm,cortex-a53";
> > > > > > > + reg = <0x2>;
> > > > > > > + enable-method = "psci";
> > > > > > > + next-level-cache = <&A53_L2>;
> > > > > > > + };
> > > > > > > +
> > > > > > > + A53_3: cpu at 3 {
> > > > > > > + device_type = "cpu";
> > > > > > > + compatible = "arm,cortex-a53";
> > > > > > > + reg = <0x3>;
> > > > > > > + enable-method = "psci";
> > > > > > > + next-level-cache = <&A53_L2>;
> > > > > > > + };
> > > > > > > +
> > > > > > > + A53_L2: l2-cache0 {
> > > > > > > + compatible = "cache";
> > > > > > > + };
> > > > > > > + };
> > > > > > > +
> > > > > > > + memory at 40000000 {
> > > > > > > + device_type = "memory";
> > > > > > > + reg = <0x0 0x40000000 0 0x80000000>;
> > > > > > > + };
> > > > > > > +
> > > > > > > + clocks {
> > > > > > > + #address-cells = <1>;
> > > > > > > + #size-cells = <0>;
> > > > > > > +
> > > > > > > + osc_32k: clock at 0 {
> > > > > > > + compatible = "fixed-clock";
> > > > > > > + reg = <0>;
> > > > > > > + #clock-cells = <0>;
> > > > > > > + clock-frequency = <32768>;
> > > > > > > + clock-output-names = "osc_32k";
> > > > > > > + };
> > > > > > > +
> > > > > > > + osc_24m: clock at 1 {
> > > > > > > + compatible = "fixed-clock";
> > > > > > > + reg = <1>;
> > > > > > > + #clock-cells = <0>;
> > > > > > > + clock-frequency = <24000000>;
> > > > > > > + clock-output-names = "osc_24m";
> > > > > > > + };
> > > > > > > +
> > > > > > > + clk_ext1: clock at 2 {
> > > > > > > + compatible = "fixed-clock";
> > > > > > > + reg = <3>;
> > > > > > > + #clock-cells = <0>;
> > > > > > > + clock-frequency = <133000000>;
> > > > > > > + clock-output-names = "clk_ext1";
> > > > > > > + };
> > > > > > > +
> > > > > > > + clk_ext2: clock at 3 {
> > > > > > > + compatible = "fixed-clock";
> > > > > > > + reg = <4>;
> > > > > > > + #clock-cells = <0>;
> > > > > > > + clock-frequency = <133000000>;
> > > > > > > + clock-output-names = "clk_ext2";
> > > > > > > + };
> > > > > > > +
> > > > > > > + clk_ext3: clock at 4 {
> > > > > > > + compatible = "fixed-clock";
> > > > > > > + reg = <5>;
> > > > > > > + #clock-cells = <0>;
> > > > > > > + clock-frequency = <133000000>;
> > > > > > > + clock-output-names = "clk_ext3";
> > > > > > > + };
> > > > > > > +
> > > > > > > + clk_ext4: clock at 5 {
> > > > > > > + compatible = "fixed-clock";
> > > > > > > + reg = <6>;
> > > > > > > + #clock-cells = <0>;
> > > > > > > + clock-frequency= <133000000>;
> > > > > > > + clock-output-names = "clk_ext4";
> > > > > > > + };
> > > > > > > + };
> > > > > > > +
> > > > > > > + gic: interrupt-controller at 38800000 {
> > > > > > > + compatible = "arm,gic-v3";
> > > > > > > + reg = <0x0 0x38800000 0 0x10000>, /* GIC
> > > > > > > Dist */
> > > > > > > + <0x0 0x38880000 0 0xC0000>; /* GICR
> > > > > > > (RD_base + SGI_base) */
> > > > > > > + #interrupt-cells = <3>;
> > > > > > > + interrupt-controller;
> > > > > > > + interrupts = <GIC_PPI 9
> > > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > + };
> > > > > > > +
> > > > > > > + psci {
> > > > > > > + compatible = "arm,psci-1.0";
> > > > > > > + method = "smc";
> > > > > > > + };
> > > > > > > +
> > > > > > > + pmu {
> > > > > > > + compatible = "arm,armv8-pmuv3";
> > > > > > > + interrupts = <GIC_PPI 7
> > > > > > > + (GIC_CPU_MASK_SIMPLE(6) |
> > > > > > > IRQ_TYPE_LEVEL_HIGH)>;
> > > > > > > + interrupt-affinity = <&A53_0>, <&A53_1>,
> > > > > > > <&A53_2>, <&A53_3>;
> > > > > > > + };
> > > > > > > +
> > > > > > > + timer {
> > > > > > > + compatible = "arm,armv8-timer";
> > > > > > > + interrupts = <GIC_PPI 13
> > > > > > > (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /*
> > > > > > > Physical Secure */
> > > > > > > + <GIC_PPI 14
> > > > > > > (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /*
> > > > > > > Physical Non-Secure */
> > > > > > > + <GIC_PPI 11
> > > > > > > (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /*
> > > > > > > Virtual
> > */
> > > > > > > + <GIC_PPI 10
> > > > > > > (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /*
> > Hypervisor
> > > > > > > */
> > > > > > > + clock-frequency = <8000000>;
> > > > > > > + arm,no-tick-in-suspend;
> > > > > > > + };
> > > > > > > +
> > > > > > > + soc at 0 {
> > > > > > > + compatible = "simple-bus";
> > > > > > > + #address-cells = <2>;
> > > > > > > + #size-cells = <2>;
> > > > > > > + ranges;
> > > > > > > +
> > > > > > > + aips1: bus at 30000000 {
> > > > > > > + compatible = "fsl,aips-bus",
> > > > > > > "simple-bus";
> > > > > > > + #address-cells = <2>;
> > > > > > > + #size-cells = <2>;
> > > > > > > + reg = <0x0 0x30000000 0x0
> > > > > > > 0x400000>;
> > > > > > > + ranges;
> > > > > > > +
> > > > > > > + gpio1: gpio at 30200000 {
> > > > > > > + compatible =
> > > > > > > "fsl,imx8mm-gpio", "fsl,imx35-gpio";
> > > > > > > + reg = <0x0 0x30200000
> > > > > > > 0x0
> > > > > > > 0x10000>;
> > > > > > > + interrupts = <GIC_SPI
> > > > > > > 64 IRQ_TYPE_LEVEL_HIGH>,
> > > > > > > + <GIC_SPI
> > > > > > > 65 IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > + gpio-controller;
> > > > > > > + #gpio-cells = <2>;
> > > > > > > + interrupt-controller;
> > > > > > > + #interrupt-cells = <2>;
> > > > > > > + };
> > > > > > > +
> > > > > > > + gpio2: gpio at 30210000 {
> > > > > > > + compatible =
> > > > > > > "fsl,imx8mm-gpio", "fsl,imx35-gpio";
> > > > > > > + reg = <0x0 0x30210000
> > > > > > > 0x0
> > > > > > > 0x10000>;
> > > > > > > + interrupts = <GIC_SPI
> > > > > > > 66 IRQ_TYPE_LEVEL_HIGH>,
> > > > > > > + <GIC_SPI
> > > > > > > 67 IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > + gpio-controller;
> > > > > > > + #gpio-cells = <2>;
> > > > > > > + interrupt-controller;
> > > > > > > + #interrupt-cells = <2>;
> > > > > > > + };
> > > > > > > +
> > > > > > > + gpio3: gpio at 30220000 {
> > > > > > > + compatible =
> > > > > > > "fsl,imx8mm-gpio", "fsl,imx35-gpio";
> > > > > > > + reg = <0x0 0x30220000
> > > > > > > 0x0
> > > > > > > 0x10000>;
> > > > > > > + interrupts = <GIC_SPI
> > > > > > > 68 IRQ_TYPE_LEVEL_HIGH>,
> > > > > > > + <GIC_SPI
> > > > > > > 69 IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > + gpio-controller;
> > > > > > > + #gpio-cells = <2>;
> > > > > > > + interrupt-controller;
> > > > > > > + #interrupt-cells = <2>;
> > > > > > > + };
> > > > > > > +
> > > > > > > + gpio4: gpio at 30230000 {
> > > > > > > + compatible =
> > > > > > > "fsl,imx8mm-gpio", "fsl,imx35-gpio";
> > > > > > > + reg = <0x0 0x30230000
> > > > > > > 0x0
> > > > > > > 0x10000>;
> > > > > > > + interrupts = <GIC_SPI
> > > > > > > 70 IRQ_TYPE_LEVEL_HIGH>,
> > > > > > > + <GIC_SPI
> > > > > > > 71 IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > + gpio-controller;
> > > > > > > + #gpio-cells = <2>;
> > > > > > > + interrupt-controller;
> > > > > > > + #interrupt-cells = <2>;
> > > > > > > + };
> > > > > > > +
> > > > > > > + gpio5: gpio at 30240000 {
> > > > > > > + compatible =
> > > > > > > "fsl,imx8mm-gpio", "fsl,imx35-gpio";
> > > > > > > + reg = <0x0 0x30240000
> > > > > > > 0x0
> > > > > > > 0x10000>;
> > > > > > > + interrupts = <GIC_SPI
> > > > > > > 72 IRQ_TYPE_LEVEL_HIGH>,
> > > > > > > + <GIC_SPI
> > > > > > > 73 IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > + gpio-controller;
> > > > > > > + #gpio-cells = <2>;
> > > > > > > + interrupt-controller;
> > > > > > > + #interrupt-cells = <2>;
> > > > > > > + };
> > > > > > > +
> > > > > > > + wdog1: wdog at 30280000 {
> > > > > > > + compatible =
> > > > > > > "fsl,imx21-wdt";
> > > > > > > + reg = <0 0x30280000 0
> > > > > > > 0x10000>;
> > > > > > > + interrupts = <GIC_SPI
> > > > > > > 78 IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > + clocks = <&clk
> > > > > > > IMX8MM_CLK_WDOG1_ROOT>;
> > > > > > > + status = "disabled";
> > > > > > > + };
> > > > > > > +
> > > > > > > + wdog2: wdog at 30290000 {
> > > > > > > + compatible =
> > > > > > > "fsl,imx21-wdt";
> > > > > > > + reg = <0 0x30290000 0
> > > > > > > 0x10000>;
> > > > > > > + interrupts = <GIC_SPI
> > > > > > > 79 IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > + clocks = <&clk
> > > > > > > IMX8MM_CLK_WDOG2_ROOT>;
> > > > > > > + status = "disabled";
> > > > > > > + };
> > > > > > > +
> > > > > > > + wdog3: wdog at 302a0000 {
> > > > > > > + compatible =
> > > > > > > "fsl,imx21-wdt";
> > > > > > > + reg = <0 0x302a0000 0
> > > > > > > 0x10000>;
> > > > > > > + interrupts = <GIC_SPI
> > > > > > > 10 IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > + clocks = <&clk
> > > > > > > IMX8MM_CLK_WDOG3_ROOT>;
> > > > > > > + status = "disabled";
> > > > > > > + };
> > > > > > > +
> > > > > > > + sdma2: dma-controller at 302c0000 {
> > > > > > > + compatible =
> > > > > > > "fsl,imx8mq-sdma", "fsl,imx7d-sdma";
> > > > > > > + reg = <0x0 0x302c0000
> > > > > > > 0x0
> > > > > > > 0x10000>;
> > > > > > > + interrupts = <GIC_SPI
> > > > > > > 103 IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > + clocks = <&clk
> > > > > > > IMX8MM_CLK_SDMA2_ROOT>,
> > > > > > > + <&clk
> > > > > > > IMX8MM_CLK_SDMA2_ROOT>;
> > > > > > > + clock-names = "ipg",
> > > > > > > "ahb";
> > > > > > > + #dma-cells = <3>;
> > > > > > > + fsl,sdma-ram-script-name
> > > > > > > = "imx/sdma/sdma-imx7d.bin";
> > > > > > > + fsl,ratio-1-1;
> > > > > > > + status = "okay";
> > > > > > > + };
> > > > > > > +
> > > > > > > + sdma3: dma-controller at 302b0000 {
> > > > > > > + compatible =
> > > > > > > "fsl,imx8mq-sdma", "fsl,imx7d-sdma";
> > > > > > > + reg = <0x0 0x302b0000
> > > > > > > 0x0
> > > > > > > 0x10000>;
> > > > > > > + interrupts = <GIC_SPI
> > > > > > > 34 IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > + clocks = <&clk
> > > > > > > IMX8MM_CLK_SDMA3_ROOT>,
> > > > > > > + <&clk
> > > > > > > IMX8MM_CLK_SDMA3_ROOT>;
> > > > > > > + clock-names = "ipg",
> > > > > > > "ahb";
> > > > > > > + #dma-cells = <3>;
> > > > > > > + fsl,sdma-ram-script-name
> > > > > > > = "imx/sdma/sdma-imx7d.bin";
> > > > > > > + fsl,ratio-1-1;
> > > > > > > + status = "okay";
> > > > > > > + };
> > > > > > > +
> > > > > > > + iomuxc: pinctrl at 30330000 {
> > > > > > > + compatible =
> > > > > > > "fsl,imx8mm-iomuxc";
> > > > > > > + reg = <0x0 0x30330000
> > > > > > > 0x0
> > > > > > > 0x10000>;
> > > > > > > + };
> > > > > > > +
> > > > > > > + gpr: iomuxc-gpr at 30340000 {
> > > > > > > + compatible =
> > > > > > > "fsl,imx8mm-iomuxc-gpr", "syscon";
> > > > > > > + reg = <0x0 0x30340000
> > > > > > > 0x0
> > > > > > > 0x10000>;
> > > > > > > + };
> > > > > > > +
> > > > > > > + ocotp: ocotp-ctrl at 30350000 {
> > > > > > > + compatible =
> > > > > > > "fsl,imx8mq-ocotp", "fsl,imx7d-ocotp", "syscon";
> > > > > > > + reg = <0 0x30350000 0
> > > > > > > 0x10000>;
> > > > > > > + clocks = <&clk
> > > > > > > IMX8MM_CLK_OCOTP_ROOT>;
> > > > > > > + /* For nvmem subnodes */
> > > > > > > + #address-cells = <1>;
> > > > > > > + #size-cells = <1>;
> > > > > > > + };
> > > > > > > +
> > > > > > > + anatop: anatop at 30360000 {
> > > > > > > + compatible =
> > > > > > > "fsl,imx8mm-anatop", "syscon", "simple-bus";
> > > > > > > + reg = <0x0 0x30360000
> > > > > > > 0x0
> > > > > > > 0x10000>;
> > > > > > > + };
> > > > > > > +
> > > > > > > + snvs: snvs at 30370000 {
> > > > > > > + compatible =
> > > > > > > "fsl,sec-v4.0-mon","syscon", "simple-mfd";
> > > > > > > + reg = <0x0 0x30370000
> > > > > > > 0x0
> > > > > > > 0x10000>; +
> > > > > > > + snvs_rtc: snvs-rtc-lp{
> > > > > > > + compatible =
> > > > > > > "fsl,sec-v4.0-mon-rtc-lp";
> > > > > > > + regmap =<&snvs>;
> > > > > > > + offset = <0x34>;
> > > > > > > + interrupts =
> > > > > > > <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
> > > > > > > +
> > > > > > > <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > + };
> > > > > > > +
> > > > > > > + snvs_pwrkey:
> > > > > > > snvs-powerkey {
> > > > > > > + compatible =
> > > > > > > "fsl,sec-v4.0-pwrkey";
> > > > > > > + regmap = <&snvs>;
> > > > > > > + interrupts =
> > > > > > > <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > + linux,keycode =
> > > > > > > <KEY_POWER>;
> > > > > > > + wakeup-source;
> > > > > > > + };
> > > > > > > + };
> > > > > > > +
> > > > > > > + clk: clock-controller at 30380000 {
> > > > > > > + compatible =
> > > > > > > "fsl,imx8mm-ccm";
> > > > > > > + reg = <0x0 0x30380000
> > > > > > > 0x0
> > > > > > > 0x10000>;
> > > > > > > + #clock-cells = <1>;
> > > > > > > + clocks = <&osc_32k>,
> > > > > > > <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
> > > > > > > + <&clk_ext3>,
> > > > > > > <&clk_ext4>;
> > > > > > > + clock-names = "osc_32k",
> > > > > > > "osc_24m", "clk_ext1", "clk_ext2",
> > > > > > > + "clk_ext3",
> > > > > > > "clk_ext4";
> > > > > > > + };
> > > > > > > +
> > > > > > > + src: src at 30390000 {
> > > > > > > + compatible =
> > > > > > > "fsl,imx8mm-src", "syscon";
> > > > > > > + reg = <0x0 0x30390000
> > > > > > > 0x0
> > > > > > > 0x10000>;
> > > > > > > + interrupts = <GIC_SPI
> > > > > > > 89 IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > + #reset-cells = <1>;
> > > > > > > + };
> > > > > > > +
> > > > > > > + gpc: gpc at 303a0000 {
> > > > > > > + compatible =
> > > > > > > "fsl,imx8mm-gpc", "syscon";
> > > > > > > + reg = <0x0 0x303a0000
> > > > > > > 0x0
> > > > > > > 0x10000>;
> > > > > > > + interrupt-controller;
> > > > > > > + interrupts = <GIC_SPI
> > > > > > > 87 IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > + #interrupt-cells = <3>;
> > > > > > > + };
> > > > > > > + };
> > > > > > > +
> > > > > > > + aips2: bus at 30400000 {
> > > > > > > + compatible = "fsl,aips-bus",
> > > > > > > "simple-bus";
> > > > > > > + #address-cells = <2>;
> > > > > > > + #size-cells = <2>;
> > > > > > > + reg = <0x0 0x30400000 0x0
> > > > > > > 0x400000>;
> > > > > > > + ranges;
> > > > > > > +
> > > > > > > + pwm1: pwm at 30660000 {
> > > > > > > + compatible =
> > > > > > > "fsl,imx8mm-pwm", "fsl,imx27-pwm";
> > > > > > > + reg = <0x0 0x30660000
> > > > > > > 0x0
> > > > > > > 0x10000>;
> > > > > > > + interrupts = <GIC_SPI
> > > > > > > 81 IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > + clocks = <&clk
> > > > > > > IMX8MM_CLK_PWM1_ROOT>,
> > > > > > > + <&clk
> > > > > > > IMX8MM_CLK_PWM1_ROOT>;
> > > > > > > + clock-names = "ipg",
> > > > > > > "per";
> > > > > > > + #pwm-cells = <2>;
> > > > > > > + status = "disabled";
> > > > > > > + };
> > > > > > > +
> > > > > > > + pwm2: pwm at 30670000 {
> > > > > > > + compatible =
> > > > > > > "fsl,imx8mm-pwm", "fsl,imx27-pwm";
> > > > > > > + reg = <0x0 0x30670000
> > > > > > > 0x0
> > > > > > > 0x10000>;
> > > > > > > + interrupts = <GIC_SPI
> > > > > > > 82 IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > + clocks = <&clk
> > > > > > > IMX8MM_CLK_PWM2_ROOT>,
> > > > > > > + <&clk
> > > > > > > IMX8MM_CLK_PWM2_ROOT>;
> > > > > > > + clock-names = "ipg",
> > > > > > > "per";
> > > > > > > + #pwm-cells = <2>;
> > > > > > > + status = "disabled";
> > > > > > > + };
> > > > > > > +
> > > > > > > + pwm3: pwm at 30680000 {
> > > > > > > + compatible =
> > > > > > > "fsl,imx8mm-pwm", "fsl,imx27-pwm";
> > > > > > > + reg = <0x0 0x30680000
> > > > > > > 0x0
> > > > > > > 0x10000>;
> > > > > > > + interrupts = <GIC_SPI
> > > > > > > 83 IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > + clocks = <&clk
> > > > > > > IMX8MM_CLK_PWM3_ROOT>,
> > > > > > > + <&clk
> > > > > > > IMX8MM_CLK_PWM3_ROOT>;
> > > > > > > + clock-names = "ipg",
> > > > > > > "per";
> > > > > > > + #pwm-cells = <2>;
> > > > > > > + status = "disabled";
> > > > > > > + };
> > > > > > > +
> > > > > > > + pwm4: pwm at 30690000 {
> > > > > > > + compatible =
> > > > > > > "fsl,imx8mm-pwm", "fsl,imx27-pwm";
> > > > > > > + reg = <0x0 0x30690000
> > > > > > > 0x0
> > > > > > > 0x10000>;
> > > > > > > + interrupts = <GIC_SPI
> > > > > > > 84 IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > + clocks = <&clk
> > > > > > > IMX8MM_CLK_PWM4_ROOT>,
> > > > > > > + <&clk
> > > > > > > IMX8MM_CLK_PWM4_ROOT>;
> > > > > > > + clock-names = "ipg",
> > > > > > > "per";
> > > > > > > + #pwm-cells = <2>;
> > > > > > > + status = "disabled";
> > > > > > > + };
> > > > > > > + };
> > > > > > > +
> > > > > > > + aips3: bus at 30800000 {
> > > > > > > + compatible = "fsl,aips-bus",
> > > > > > > "simple-bus";
> > > > > > > + #address-cells = <2>;
> > > > > > > + #size-cells = <2>;
> > > > > > > + reg = <0x0 0x30800000 0x0
> > > > > > > 0x400000>;
> > > > > > > + ranges;
> > > > > > > +
> > > > > > > + ecspi1: ecspi at 30820000 {
> > > > > > > + #address-cells = <1>;
> > > > > > > + #size-cells = <0>;
> > > > > > > + compatible =
> > > > > > > "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
> > > > > > > + reg = <0x0 0x30820000
> > > > > > > 0x0
> > > > > > > 0x10000>;
> > > > > > > + interrupts = <GIC_SPI
> > > > > > > 31 IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > + clocks = <&clk
> > > > > > > IMX8MM_CLK_ECSPI1_ROOT>,
> > > > > > > + <&clk
> > > > > > > IMX8MM_CLK_ECSPI1_ROOT>;
> > > > > > > + clock-names = "ipg",
> > > > > > > "per";
> > > > > > > + status = "disabled";
> > > > > > > + };
> > > > > > > +
> > > > > > > + ecspi2: ecspi at 30830000 {
> > > > > > > + #address-cells = <1>;
> > > > > > > + #size-cells = <0>;
> > > > > > > + compatible =
> > > > > > > "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
> > > > > > > + reg = <0x0 0x30830000
> > > > > > > 0x0
> > > > > > > 0x10000>;
> > > > > > > + interrupts = <GIC_SPI
> > > > > > > 32 IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > + clocks = <&clk
> > > > > > > IMX8MM_CLK_ECSPI2_ROOT>,
> > > > > > > + <&clk
> > > > > > > IMX8MM_CLK_ECSPI2_ROOT>;
> > > > > > > + clock-names = "ipg",
> > > > > > > "per";
> > > > > > > + status = "disabled";
> > > > > > > + };
> > > > > > > +
> > > > > > > + ecspi3: ecspi at 30840000 {
> > > > > > > + #address-cells = <1>;
> > > > > > > + #size-cells = <0>;
> > > > > > > + compatible =
> > > > > > > "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
> > > > > > > + reg = <0x0 0x30840000
> > > > > > > 0x0
> > > > > > > 0x10000>;
> > > > > > > + interrupts = <GIC_SPI
> > > > > > > 33 IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > + clocks = <&clk
> > > > > > > IMX8MM_CLK_ECSPI3_ROOT>,
> > > > > > > + <&clk
> > > > > > > IMX8MM_CLK_ECSPI3_ROOT>;
> > > > > > > + clock-names = "ipg",
> > > > > > > "per";
> > > > > > > + status = "disabled";
> > > > > > > + };
> > > > > > > +
> > > > > > > + uart1: serial at 30860000 {
> > > > > > > + compatible =
> > > > > > > "fsl,imx8mm-uart",
> > > > > > > +
> > > > > > > "fsl,imx6q-uart", "fsl,imx21-uart";
> > > > > > > + reg = <0x0 0x30860000
> > > > > > > 0x0
> > > > > > > 0x10000>;
> > > > > > > + interrupts = <GIC_SPI
> > > > > > > 26 IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > + clocks = <&clk
> > > > > > > IMX8MM_CLK_UART1_ROOT>,
> > > > > > > + <&clk
> > > > > > > IMX8MM_CLK_UART1_ROOT>;
> > > > > > > + clock-names = "ipg",
> > > > > > > "per";
> > > > > > > + status = "disabled";
> > > > > > > + };
> > > > > > > +
> > > > > > > + uart3: serial at 30880000 {
> > > > > > > + compatible =
> > > > > > > "fsl,imx8mm-uart",
> > > > > > > +
> > > > > > > "fsl,imx6q-uart", "fsl,imx21-uart";
> > > > > > > + reg = <0x0 0x30880000
> > > > > > > 0x0
> > > > > > > 0x10000>;
> > > > > > > + interrupts = <GIC_SPI
> > > > > > > 28 IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > + clocks = <&clk
> > > > > > > IMX8MM_CLK_UART3_ROOT>,
> > > > > > > + <&clk
> > > > > > > IMX8MM_CLK_UART3_ROOT>;
> > > > > > > + clock-names = "ipg",
> > > > > > > "per";
> > > > > > > + status = "disabled";
> > > > > > > + };
> > > > > > > +
> > > > > > > + uart2: serial at 30890000 {
> > > > > > > + compatible =
> > > > > > > "fsl,imx8mm-uart",
> > > > > > > +
> > > > > > > "fsl,imx6q-uart", "fsl,imx21-uart";
> > > > > > > + reg = <0x0 0x30890000
> > > > > > > 0x0
> > > > > > > 0x10000>;
> > > > > > > + interrupts = <GIC_SPI
> > > > > > > 27 IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > + clocks = <&clk
> > > > > > > IMX8MM_CLK_UART2_ROOT>,
> > > > > > > + <&clk
> > > > > > > IMX8MM_CLK_UART2_ROOT>;
> > > > > > > + clock-names = "ipg",
> > > > > > > "per";
> > > > > > > + status = "disabled";
> > > > > > > + };
> > > > > > > +
> > > > > > > + i2c1: i2c at 30a20000 {
> > > > > > > + #address-cells = <1>;
> > > > > > > + #size-cells = <0>;
> > > > > > > + compatible =
> > > > > > > "fsl,imx8mm-i2c", "fsl,imx21-i2c";
> > > > > > > + reg = <0x0 0x30a20000
> > > > > > > 0x0
> > > > > > > 0x10000>;
> > > > > > > + interrupts = <GIC_SPI
> > > > > > > 35 IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > + clocks = <&clk
> > > > > > > IMX8MM_CLK_I2C1_ROOT>;
> > > > > > > + status = "disabled";
> > > > > > > + };
> > > > > > > +
> > > > > > > + i2c2: i2c at 30a30000 {
> > > > > > > + #address-cells = <1>;
> > > > > > > + #size-cells = <0>;
> > > > > > > + compatible =
> > > > > > > "fsl,imx8mm-i2c", "fsl,imx21-i2c";
> > > > > > > + reg = <0x0 0x30a30000
> > > > > > > 0x0
> > > > > > > 0x10000>;
> > > > > > > + interrupts = <GIC_SPI
> > > > > > > 36 IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > + clocks = <&clk
> > > > > > > IMX8MM_CLK_I2C2_ROOT>;
> > > > > > > + status = "disabled";
> > > > > > > + };
> > > > > > > +
> > > > > > > + i2c3: i2c at 30a40000 {
> > > > > > > + #address-cells = <1>;
> > > > > > > + #size-cells = <0>;
> > > > > > > + compatible =
> > > > > > > "fsl,imx8mm-i2c", "fsl,imx21-i2c";
> > > > > > > + reg = <0x0 0x30a40000
> > > > > > > 0x0
> > > > > > > 0x10000>;
> > > > > > > + interrupts = <GIC_SPI
> > > > > > > 37 IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > + clocks = <&clk
> > > > > > > IMX8MM_CLK_I2C3_ROOT>;
> > > > > > > + status = "disabled";
> > > > > > > + };
> > > > > > > +
> > > > > > > + i2c4: i2c at 30a50000 {
> > > > > > > + #address-cells = <1>;
> > > > > > > + #size-cells = <0>;
> > > > > > > + compatible =
> > > > > > > "fsl,imx8mm-i2c", "fsl,imx21-i2c";
> > > > > > > + reg = <0x0 0x30a50000
> > > > > > > 0x0
> > > > > > > 0x10000>;
> > > > > > > + interrupts = <GIC_SPI
> > > > > > > 38 IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > + clocks = <&clk
> > > > > > > IMX8MM_CLK_I2C4_ROOT>;
> > > > > > > + status = "disabled";
> > > > > > > + };
> > > > > > > +
> > > > > > > + uart4: serial at 30a60000 {
> > > > > > > + compatible =
> > > > > > > "fsl,imx8mq-uart",
> > > > > > > +
> > > > > > > "fsl,imx6q-uart", "fsl,imx21-uart";
> > > > > > > + reg = <0x0 0x30a60000
> > > > > > > 0x0
> > > > > > > 0x10000>;
> > > > > > > + interrupts = <GIC_SPI
> > > > > > > 29 IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > + clocks = <&clk
> > > > > > > IMX8MM_CLK_UART4_ROOT>,
> > > > > > > + <&clk
> > > > > > > IMX8MM_CLK_UART4_ROOT>;
> > > > > > > + clock-names = "ipg",
> > > > > > > "per";
> > > > > > > + status = "disabled";
> > > > > > > + };
> > > > > > > +
> > > > > > > + usdhc1: mmc at 30b40000 {
> > > > > > > + compatible =
> > > > > > > "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc";
> > > > > > > + reg = <0x0 0x30b40000
> > > > > > > 0x0
> > > > > > > 0x10000>;
> > > > > > > + interrupts = <GIC_SPI
> > > > > > > 22 IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > + clocks = <&clk
> > > > > > > IMX8MM_CLK_DUMMY>,
> > > > > > > + <&clk
> > > > > > > IMX8MM_CLK_NAND_USDHC_BUS>,
> > > > > > > + <&clk
> > > > > > > IMX8MM_CLK_USDHC1_ROOT>;
> > > > > > > + clock-names = "ipg",
> > > > > > > "ahb", "per";
> > > > > > > + assigned-clocks = <&clk
> > > > > > > IMX8MM_CLK_USDHC1>;
> > > > > > > + assigned-clock-rates =
> > > > > > > <400000000>;
> > > > > > > + fsl,tuning-start-tap =
> > > > > > > <20>;
> > > > > > > + fsl,tuning-step= <2>;
> > > > > > > + bus-width = <4>;
> > > > > > > + status = "disabled";
> > > > > > > + };
> > > > > > > +
> > > > > > > + usdhc2: mmc at 30b50000 {
> > > > > > > + compatible =
> > > > > > > "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc";
> > > > > > > + reg = <0x0 0x30b50000
> > > > > > > 0x0
> > > > > > > 0x10000>;
> > > > > > > + interrupts = <GIC_SPI
> > > > > > > 23 IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > + clocks = <&clk
> > > > > > > IMX8MM_CLK_DUMMY>,
> > > > > > > + <&clk
> > > > > > > IMX8MM_CLK_NAND_USDHC_BUS>,
> > > > > > > + <&clk
> > > > > > > IMX8MM_CLK_USDHC2_ROOT>;
> > > > > > > + clock-names = "ipg",
> > > > > > > "ahb", "per";
> > > > > > > + fsl,tuning-start-tap =
> > > > > > > <20>;
> > > > > > > + fsl,tuning-step= <2>;
> > > > > > > + bus-width = <4>;
> > > > > > > + status = "disabled";
> > > > > > > + };
> > > > > > > +
> > > > > > > + usdhc3: mmc at 30b60000 {
> > > > > > > + compatible =
> > > > > > > "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc";
> > > > > > > + reg = <0x0 0x30b60000
> > > > > > > 0x0
> > > > > > > 0x10000>;
> > > > > > > + interrupts = <GIC_SPI
> > > > > > > 24 IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > + clocks = <&clk
> > > > > > > IMX8MM_CLK_DUMMY>,
> > > > > > > + <&clk
> > > > > > > IMX8MM_CLK_NAND_USDHC_BUS>,
> > > > > > > + <&clk
> > > > > > > IMX8MM_CLK_USDHC3_ROOT>;
> > > > > > > + clock-names = "ipg",
> > > > > > > "ahb", "per";
> > > > > > > + assigned-clocks = <&clk
> > > > > > > IMX8MM_CLK_USDHC3_ROOT>;
> > > > > > > + assigned-clock-rates =
> > > > > > > <400000000>;
> > > > > > > + fsl,tuning-start-tap =
> > > > > > > <20>;
> > > > > > > + fsl,tuning-step= <2>;
> > > > > > > + bus-width = <4>;
> > > > > > > + status = "disabled";
> > > > > > > + };
> > > > > > > + };
> > > > > > > + };
> > > > > > > +};
> > > > > > > diff --git a/arch/arm/mach-imx/imx8m/Kconfig
> > > > > > > b/arch/arm/mach-imx/imx8m/Kconfig index
> > > > > > > 35c978e863..f520075875
> > > > > > 100644
> > > > > > > --- a/arch/arm/mach-imx/imx8m/Kconfig
> > > > > > > +++ b/arch/arm/mach-imx/imx8m/Kconfig
> > > > > > > @@ -24,8 +24,15 @@ config TARGET_IMX8MQ_EVK
> > > > > > > select IMX8MQ
> > > > > > > select IMX8M_LPDDR4
> > > > > > >
> > > > > > > +config TARGET_IMX8MM_EVK
> > > > > > > + bool "imx8mm LPDDR4 EVK board"
> > > > > > > + select IMX8MM
> > > > > > > + select SUPPORT_SPL
> > > > > > > + select IMX8M_LPDDR4
> > > > > >
> > > > > > Here you shall put the select DM_{UART,USDHC, etc}
> > > > > >
> > > > > > > +
> > > > > > > endchoice
> > > > > > >
> > > > > > > source "board/freescale/imx8mq_evk/Kconfig"
> > > > > > > +source "board/freescale/imx8mm_evk/Kconfig"
> > > > > > >
> > > > > > > endif
> > > > > > > diff --git a/board/freescale/imx8mm_evk/Kconfig
> > > > > > > b/board/freescale/imx8mm_evk/Kconfig new file mode 100644
> > > > > > > index 0000000000..299691a619
> > > > > > > --- /dev/null
> > > > > > > +++ b/board/freescale/imx8mm_evk/Kconfig
> > > > > > > @@ -0,0 +1,12 @@
> > > > > > > +if TARGET_IMX8MM_EVK
> > > > > > > +
> > > > > > > +config SYS_BOARD
> > > > > > > + default "imx8mm_evk"
> > > > > > > +
> > > > > > > +config SYS_VENDOR
> > > > > > > + default "freescale"
> > > > > > > +
> > > > > > > +config SYS_CONFIG_NAME
> > > > > > > + default "imx8mm_evk"
> > > > > > > +
> > > > > > > +endif
> > > > > > > diff --git a/board/freescale/imx8mm_evk/MAINTAINERS
> > > > > > > b/board/freescale/imx8mm_evk/MAINTAINERS new file mode
> > 100644
> > > > > > > index 0000000000..b031bb0674
> > > > > > > --- /dev/null
> > > > > > > +++ b/board/freescale/imx8mm_evk/MAINTAINERS
> > > > > > > @@ -0,0 +1,6 @@
> > > > > > > +i.MX8MM EVK BOARD
> > > > > > > +M: Peng Fan <peng.fan@nxp.com>
> > > > > > > +S: Maintained
> > > > > > > +F: board/freescale/imx8mm_evk/
> > > > > > > +F: include/configs/imx8mm_evk.h
> > > > > > > +F: configs/imx8mm_evk_defconfig
> > > > > > > diff --git a/board/freescale/imx8mm_evk/Makefile
> > > > > > > b/board/freescale/imx8mm_evk/Makefile new file mode 100644
> > > > > > > index 0000000000..1db7b62caf
> > > > > > > --- /dev/null
> > > > > > > +++ b/board/freescale/imx8mm_evk/Makefile
> > > > > > > @@ -0,0 +1,12 @@
> > > > > > > +#
> > > > > > > +# Copyright 2018 NXP
> > > > > > > +#
> > > > > > > +# SPDX-License-Identifier: GPL-2.0+
> > > > > > > +#
> > > > > > > +
> > > > > > > +obj-y += imx8mm_evk.o
> > > > > > > +
> > > > > > > +ifdef CONFIG_SPL_BUILD
> > > > > > > +obj-y += spl.o
> > > > > > > +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
> > > > > > > +endif
> > > > > > > diff --git a/board/freescale/imx8mm_evk/imx8mm_evk.c
> > > > > > > b/board/freescale/imx8mm_evk/imx8mm_evk.c new file mode
> > 100644
> > > > > > > index 0000000000..a681aca04d
> > > > > > > --- /dev/null
> > > > > > > +++ b/board/freescale/imx8mm_evk/imx8mm_evk.c
> > > > > > > @@ -0,0 +1,144 @@
> > > > > > > +// SPDX-License-Identifier: GPL-2.0+
> > > > > > > +/*
> > > > > > > + * Copyright 2018 NXP
> > > > > > > + */
> > > > > > > +
> > > > > > > +#include <common.h>
> > > > > > > +#include <malloc.h>
> > > > > > > +#include <errno.h>
> > > > > > > +#include <asm/io.h>
> > > > > > > +#include <miiphy.h>
> > > > > > > +#include <netdev.h>
> > > > > > > +#include <asm/mach-imx/iomux-v3.h>
> > > > > > > +#include <asm-generic/gpio.h>
> > > > > > > +#include <fsl_esdhc.h>
> > > > > > > +#include <mmc.h>
> > > > > > > +#include <asm/arch/imx8mm_pins.h>
> > > > > > > +#include <asm/arch/sys_proto.h>
> > > > > > > +#include <asm/mach-imx/gpio.h>
> > > > > > > +#include <asm/mach-imx/mxc_i2c.h>
> > > > > > > +#include <asm/arch/clock.h>
> > > > > > > +#include <spl.h>
> > > > > > > +#include <asm/mach-imx/dma.h>
> > > > > > > +
> > > > > > > +DECLARE_GLOBAL_DATA_PTR;
> > > > > > > +
> > > > > > > +#define UART_PAD_CTRL (PAD_CTL_DSE6 |
> > > > > > > PAD_CTL_FSEL1) +#define WDOG_PAD_CTRL
> > > > > > > (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) +
> > > > > > > +static iomux_v3_cfg_t const uart_pads[] = {
> > > > > > > + IMX8MM_PAD_UART2_RXD_UART2_RX |
> > > > > > MUX_PAD_CTRL(UART_PAD_CTRL),
> > > > > > > + IMX8MM_PAD_UART2_TXD_UART2_TX |
> > > > > > MUX_PAD_CTRL(UART_PAD_CTRL),
> > > > > > > +};
> > > > > > > +
> > > > > > > +static iomux_v3_cfg_t const wdog_pads[] = {
> > > > > > > + IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B |
> > > > > > > MUX_PAD_CTRL(WDOG_PAD_CTRL), +};
> > > > > > > +
> > > > > > > +int board_early_init_f(void)
> > > > > > > +{
> > > > > > > + struct wdog_regs *wdog = (struct wdog_regs
> > > > > > > *)WDOG1_BASE_ADDR; +
> > > > > > > + imx_iomux_v3_setup_multiple_pads(wdog_pads,
> > > > > > > ARRAY_SIZE(wdog_pads)); +
> > > > > > > + set_wdog_reset(wdog);
> > > > > > > +
> > > > > > > + imx_iomux_v3_setup_multiple_pads(uart_pads,
> > > > > > > ARRAY_SIZE(uart_pads)); +
> > > > > > > + return 0;
> > > > > > > +}
> > > > > > > +
> > > > > > > +#ifdef CONFIG_BOARD_POSTCLK_INIT
> > > > > > > +int board_postclk_init(void)
> > > > > > > +{
> > > > > > > + /* TODO */
> > > > > > > + return 0;
> > > > > > > +}
> > > > > > > +#endif
> > > > > > > +
> > > > > > > +int dram_init(void)
> > > > > > > +{
> > > > > > > + /* rom_pointer[1] contains the size of TEE
> > > > > > > occupies */
> > > > > > > + if (rom_pointer[1])
> > > > > > > + gd->ram_size = PHYS_SDRAM_SIZE -
> > > > > > > rom_pointer[1];
> > > > > > > + else
> > > > > > > + gd->ram_size = PHYS_SDRAM_SIZE;
> > > > > > > +
> > > > > > > + return 0;
> > > > > > > +}
> > > > > > > +
> > > > > > > +#ifdef CONFIG_OF_BOARD_SETUP
> > > > > > > +int ft_board_setup(void *blob, bd_t *bd)
> > > > > > ^^^ - fdt_board_setup ?
> > > > > > > +{
> > > > > > > + return 0;
> > > > > > > +}
> > > > > > > +#endif
> > > > > > > +
> > > > > > > +#ifdef CONFIG_FEC_MXC
> > > > > > > +#define FEC_RST_PAD IMX_GPIO_NR(4, 22)
> > > > > > > +static iomux_v3_cfg_t const fec1_rst_pads[] = {
> > > > > > > + IMX8MM_PAD_SAI2_RXC_GPIO4_IO22 |
> > > > > > MUX_PAD_CTRL(NO_PAD_CTRL),
> > > > > >
> > > > > > This shall be done with fsl_fec.c DM driver - there is
> > > > > > support for adding reset pin (to dts).
> > > > > >
> > > > > > > +};
> > > > > > > +
> > > > > > > +static void setup_iomux_fec(void)
> > > > > > > +{
> > > > > > > + imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
> > > > > > > +
> > > > > > > ARRAY_SIZE(fec1_rst_pads)); +
> > > > > > > + gpio_request(FEC_RST_PAD, "fec1_rst");
> > > > > > > + gpio_direction_output(FEC_RST_PAD, 0);
> > > > > > > + udelay(500);
> > > > > > > + gpio_direction_output(FEC_RST_PAD, 1);
> > > > > > > +}
> > > > > >
> > > > > > This shall be replaced with DM/DTS of the fsl_fec.c driver.
> > > > > > Please also note that there are (at least on imx6q) some
> > > > > > timing issues when we move the code to DM/DTS (some delay
> > > > > > is needed).
> > > > > > > +
> > > > > > > +static int setup_fec(void)
> > > > > > > +{
> > > > > > > + struct iomuxc_gpr_base_regs *const
> > > > > > > iomuxc_gpr_regs
> > > > > > > + = (struct iomuxc_gpr_base_regs
> > > > > > > *)IOMUXC_GPR_BASE_ADDR; +
> > > > > > > + setup_iomux_fec();
> > > > > > > +
> > > > > > > + /* Use 125M anatop REF_CLK1 for ENET1, not from
> > > > > > > external */
> > > > > > > + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
> > > > > > > +
> > > > > > > IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT, 0);
> > > > > > > + return set_clk_enet(ENET_125MHZ);
> > > > > > > +}
> > > > > > > +
> > > > > > > +int board_phy_config(struct phy_device *phydev)
> > > > > > > +{
> > > > > > > + /* enable rgmii rxc skew and phy mode select to
> > > > > > > RGMII copper */
> > > > > > > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
> > > > > > > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
> > > > > > > +
> > > > > > > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
> > > > > > > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
> > > > > > > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
> > > > > > > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
> > > > > > > +
> > > > > > > + if (phydev->drv->config)
> > > > > > > + phydev->drv->config(phydev);
> > > > > > > + return 0;
> > > > > >
> > > > > > Which PHY do you use? E.g. KSZ... support passing those
> > > > > > values via DTS.
> > > > > > > +}
> > > > > > > +#endif
> > > > > > > +
> > > > > > > +int board_init(void)
> > > > > > > +{
> > > > > > > +#ifdef CONFIG_FEC_MXC
> > > > > > > + setup_fec();
> > > > > > > +#endif
> > > > > > > + return 0;
> > > > > > > +}
> > > > > > > +
> > > > > > > +int board_mmc_get_env_dev(int devno)
> > > > > > > +{
> > > > > > > + return devno - 1;
> > > > > > > +}
> > > > > > > +
> > > > > > > +int board_late_init(void)
> > > > > > > +{
> > > > > > > +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> > > > > > > + env_set("board_name", "EVK");
> > > > > > > + env_set("board_rev", "iMX8MM");
> > > > > > > +#endif
> > > > > > > + return 0;
> > > > > > > +}
> > > > > > > diff --git a/board/freescale/imx8mm_evk/lpddr4_timing.c
> > > > > > > b/board/freescale/imx8mm_evk/lpddr4_timing.c new file mode
> > > > > > > 100644 index 0000000000..4bade5bf74
> > > > > > > --- /dev/null
> > > > > > > +++ b/board/freescale/imx8mm_evk/lpddr4_timing.c
> > > > > > > @@ -0,0 +1,1980 @@
> > > > > > > +// SPDX-License-Identifier: GPL-2.0+
> > > > > > > +/*
> > > > > > > + * Copyright 2018 NXP
> > > > > >
> > > > > > Author is missing.
> > > > > >
> > > > > > > + */
> > > > > > > +
> > > > > > > +#include <linux/kernel.h>
> > > > > > > +#include <common.h>
> > > > > > > +#include <asm/arch/ddr.h>
> > > > > > > +#include <asm/arch/lpddr4_define.h>
> > > > > > > +
> > > > > > > +struct dram_cfg_param lpddr4_ddrc_cfg[] = {
> > > > > > > + /* Start to config, default 3200mbps */
> > > > > > > + { DDRC_DBG1(0), 0x00000001 },
> > > > > > > + { DDRC_PWRCTL(0), 0x00000001 },
> > > > > > > + { DDRC_MSTR(0), 0xa1080020 },
> > > > > > > + { DDRC_RFSHTMG(0), 0x005b00d2 },
> > > > > > > + { DDRC_INIT0(0), 0xC003061B },
> > > > > > > + { DDRC_INIT1(0), 0x009D0000 },
> > > > > > > + { DDRC_INIT3(0), 0x00D4002D },
> > > > > > > + { DDRC_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 },
> > > > > > > + { DDRC_INIT6(0), 0x0066004a },
> > > > > > > + { DDRC_INIT7(0), 0x0006004a },
> > > > > > > +
> > > > > > > + { DDRC_DRAMTMG0(0), 0x1A201B22 },
> > > > > > > + { DDRC_DRAMTMG1(0), 0x00060633 },
> > > > > > > + { DDRC_DRAMTMG3(0), 0x00C0C000 },
> > > > > > > + { DDRC_DRAMTMG4(0), 0x0F04080F },
> > > > > > > + { DDRC_DRAMTMG5(0), 0x02040C0C },
> > > > > > > + { DDRC_DRAMTMG6(0), 0x01010007 },
> > > > > > > + { DDRC_DRAMTMG7(0), 0x00000401 },
> > > > > > > + { DDRC_DRAMTMG12(0), 0x00020600 },
> > > > > > > + { DDRC_DRAMTMG13(0), 0x0C100002 },
> > > > > > > + { DDRC_DRAMTMG14(0), 0x000000E6 },
> > > > > > > + { DDRC_DRAMTMG17(0), 0x00A00050 },
> > > > > > > +
> > > > > > > + { DDRC_ZQCTL0(0), 0x03200018 },
> > > > > > > + { DDRC_ZQCTL1(0), 0x028061A8 },
> > > > > > > + { DDRC_ZQCTL2(0), 0x00000000 },
> > > > > > > +
> > > > > > > + { DDRC_DFITMG0(0), 0x0497820A },
> > > > > > > + { DDRC_DFITMG2(0), 0x0000170A },
> > > > > > > + { DDRC_DRAMTMG2(0), 0x070E171a },
> > > > > > > + { DDRC_DBICTL(0), 0x00000001 },
> > > > > > > +
> > > > > > > + { DDRC_DFITMG1(0), 0x00080303 },
> > > > > > > + { DDRC_DFIUPD0(0), 0xE0400018 },
> > > > > > > + { DDRC_DFIUPD1(0), 0x00DF00E4 },
> > > > > > > + { DDRC_DFIUPD2(0), 0x80000000 },
> > > > > > > + { DDRC_DFIMISC(0), 0x00000011 },
> > > > > > > +
> > > > > > > + { DDRC_DFIPHYMSTR(0), 0x00000000 },
> > > > > > > + { DDRC_RANKCTL(0), 0x00000c99 },
> > > > > > > +
> > > > > > > + /* address mapping */
> > > > > > > + { DDRC_ADDRMAP0(0), 0x0000001f },
> > > > > > > + { DDRC_ADDRMAP1(0), 0x00080808 },
> > > > > > > + { DDRC_ADDRMAP2(0), 0x00000000 },
> > > > > > > + { DDRC_ADDRMAP3(0), 0x00000000 },
> > > > > > > + { DDRC_ADDRMAP4(0), 0x00001f1f },
> > > > > > > + { DDRC_ADDRMAP5(0), 0x07070707 },
> > > > > > > + { DDRC_ADDRMAP6(0), 0x07070707 },
> > > > > > > + { DDRC_ADDRMAP7(0), 0x00000f0f },
> > > > > > > +
> > > > > > > + /* performance setting */
> > > > > > > + { DDRC_SCHED(0), 0x29001701 },
> > > > > > > + { DDRC_SCHED1(0), 0x0000002c },
> > > > > > > + { DDRC_PERFHPR1(0), 0x04000030 },
> > > > > > > + { DDRC_PERFLPR1(0), 0x900093e7 },
> > > > > > > + { DDRC_PERFWR1(0), 0x20005574 },
> > > > > > > + { DDRC_PCCFG(0), 0x00000111 },
> > > > > > > + { DDRC_PCFGW_0(0), 0x000072ff },
> > > > > > > + { DDRC_PCFGQOS0_0(0), 0x02100e07 },
> > > > > > > + { DDRC_PCFGQOS1_0(0), 0x00620096 },
> > > > > > > + { DDRC_PCFGWQOS0_0(0), 0x01100e07 },
> > > > > > > + { DDRC_PCFGWQOS1_0(0), 0x00c8012c },
> > > > > > > +
> > > > > > > + /* frequency P1&P2 */
> > > > > > > + /* Frequency 1: 400mbps */
> > > > > > > + { DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c },
> > > > > > > + { DDRC_FREQ1_DRAMTMG1(0), 0x00030410 },
> > > > > > > + { DDRC_FREQ1_DRAMTMG2(0), 0x0203090c },
> > > > > > > + { DDRC_FREQ1_DRAMTMG3(0), 0x00505006 },
> > > > > > > + { DDRC_FREQ1_DRAMTMG4(0), 0x05040305 },
> > > > > > > + { DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504 },
> > > > > > > + { DDRC_FREQ1_DRAMTMG6(0), 0x0a060004 },
> > > > > > > + { DDRC_FREQ1_DRAMTMG7(0), 0x0000090e },
> > > > > > > + { DDRC_FREQ1_DRAMTMG14(0), 0x00000032 },
> > > > > > > + { DDRC_FREQ1_DRAMTMG15(0), 0x00000000 },
> > > > > > > + { DDRC_FREQ1_DRAMTMG17(0), 0x0036001b },
> > > > > > > + { DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1 },
> > > > > > > + { DDRC_FREQ1_DFITMG0(0), 0x03818200 },
> > > > > > > + { DDRC_FREQ1_DFITMG2(0), 0x00000000 },
> > > > > > > + { DDRC_FREQ1_RFSHTMG(0), 0x000C001c },
> > > > > > > + { DDRC_FREQ1_INIT3(0), 0x00840000 },
> > > > > > > + { DDRC_FREQ1_INIT4(0), 0x00310000 },
> > > > > > > + { DDRC_FREQ1_INIT6(0), 0x0066004a },
> > > > > > > + { DDRC_FREQ1_INIT7(0), 0x0006004a },
> > > > > > > +
> > > > > > > + /* Frequency 2: 100mbps */
> > > > > > > + { DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c },
> > > > > > > + { DDRC_FREQ2_DRAMTMG1(0), 0x00030410 },
> > > > > > > + { DDRC_FREQ2_DRAMTMG2(0), 0x0203090c },
> > > > > > > + { DDRC_FREQ2_DRAMTMG3(0), 0x00505006 },
> > > > > > > + { DDRC_FREQ2_DRAMTMG4(0), 0x05040305 },
> > > > > > > + { DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504 },
> > > > > > > + { DDRC_FREQ2_DRAMTMG6(0), 0x0a060004 },
> > > > > > > + { DDRC_FREQ2_DRAMTMG7(0), 0x0000090e },
> > > > > > > + { DDRC_FREQ2_DRAMTMG14(0), 0x00000032 },
> > > > > > > + { DDRC_FREQ2_DRAMTMG17(0), 0x0036001b },
> > > > > > > + { DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1 },
> > > > > > > + { DDRC_FREQ2_DFITMG0(0), 0x03818200 },
> > > > > > > + { DDRC_FREQ2_DFITMG2(0), 0x00000000 },
> > > > > > > + { DDRC_FREQ2_RFSHTMG(0), 0x0003800c },
> > > > > > > + { DDRC_FREQ2_RFSHTMG(0), 0x00030007 },
> > > > > > > + { DDRC_FREQ2_INIT3(0), 0x00840000 },
> > > > > > > + { DDRC_FREQ2_INIT4(0), 0x00310008 },
> > > > > > > + { DDRC_FREQ2_INIT4(0), (LPDDR4_MR3 << 16) |
> > > > > > > 0x0000 },
> > > > > > > + { DDRC_FREQ2_INIT6(0), 0x0066004a },
> > > > > > > + { DDRC_FREQ2_INIT7(0), 0x0006004a },
> > > > > > > +
> > > > > > > + /* boot start point */
> > > > > > > + { DDRC_MSTR2(0), 0x2 }, //DDRC_MSTR2
> > > > > > > +};
> > > > > > > +
> > > > > > > +/* PHY Initialize Configuration */
> > > > > > > +struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
> > > > > > > + { 0x1005f, 0x1ff },
> > > > > > > + { 0x1015f, 0x1ff },
> > > > > > > + { 0x1105f, 0x1ff },
> > > > > > > + { 0x1115f, 0x1ff },
> > > > > > > + { 0x1205f, 0x1ff },
> > > > > > > + { 0x1215f, 0x1ff },
> > > > > > > + { 0x1305f, 0x1ff },
> > > > > > > + { 0x1315f, 0x1ff },
> > > > > > > +
> > > > > > > + { 0x11005f, 0x1ff },
> > > > > > > + { 0x11015f, 0x1ff },
> > > > > > > + { 0x11105f, 0x1ff },
> > > > > > > + { 0x11115f, 0x1ff },
> > > > > > > + { 0x11205f, 0x1ff },
> > > > > > > + { 0x11215f, 0x1ff },
> > > > > > > + { 0x11305f, 0x1ff },
> > > > > > > + { 0x11315f, 0x1ff },
> > > > > > > +
> > > > > > > + { 0x21005f, 0x1ff },
> > > > > > > + { 0x21015f, 0x1ff },
> > > > > > > + { 0x21105f, 0x1ff },
> > > > > > > + { 0x21115f, 0x1ff },
> > > > > > > + { 0x21205f, 0x1ff },
> > > > > > > + { 0x21215f, 0x1ff },
> > > > > > > + { 0x21305f, 0x1ff },
> > > > > > > + { 0x21315f, 0x1ff },
> > > > > > > +
> > > > > > > + { 0x55, 0x1ff },
> > > > > > > + { 0x1055, 0x1ff },
> > > > > > > + { 0x2055, 0x1ff },
> > > > > > > + { 0x3055, 0x1ff },
> > > > > > > + { 0x4055, 0x1ff },
> > > > > > > + { 0x5055, 0x1ff },
> > > > > > > + { 0x6055, 0x1ff },
> > > > > > > + { 0x7055, 0x1ff },
> > > > > > > + { 0x8055, 0x1ff },
> > > > > > > + { 0x9055, 0x1ff },
> > > > > > > +
> > > > > > > + { 0x200c5, 0x19 },
> > > > > > > + { 0x1200c5, 0x7 },
> > > > > > > + { 0x2200c5, 0x7 },
> > > > > > > +
> > > > > > > + { 0x2002e, 0x2 },
> > > > > > > + { 0x12002e, 0x2 },
> > > > > > > + { 0x22002e, 0x2 },
> > > > > > > +
> > > > > > > + { 0x90204, 0x0 },
> > > > > > > + { 0x190204, 0x0 },
> > > > > > > + { 0x290204, 0x0 },
> > > > > > > +
> > > > > > > + { 0x20024, 0xab },
> > > > > > > + { 0x2003a, 0x0 },
> > > > > > > +
> > > > > > > + { 0x120024, 0xab },
> > > > > > > + { 0x2003a, 0x0 },
> > > > > > > +
> > > > > > > + { 0x220024, 0xab },
> > > > > > > + { 0x2003a, 0x0 },
> > > > > > > +
> > > > > > > + { 0x20056, 0x3 },
> > > > > > > + { 0x120056, 0xa },
> > > > > > > + { 0x220056, 0xa },
> > > > > > > +
> > > > > > > + { 0x1004d, 0xe00 },
> > > > > > > + { 0x1014d, 0xe00 },
> > > > > > > + { 0x1104d, 0xe00 },
> > > > > > > + { 0x1114d, 0xe00 },
> > > > > > > + { 0x1204d, 0xe00 },
> > > > > > > + { 0x1214d, 0xe00 },
> > > > > > > + { 0x1304d, 0xe00 },
> > > > > > > + { 0x1314d, 0xe00 },
> > > > > > > +
> > > > > > > + { 0x11004d, 0xe00 },
> > > > > > > + { 0x11014d, 0xe00 },
> > > > > > > + { 0x11104d, 0xe00 },
> > > > > > > + { 0x11114d, 0xe00 },
> > > > > > > + { 0x11204d, 0xe00 },
> > > > > > > + { 0x11214d, 0xe00 },
> > > > > > > + { 0x11304d, 0xe00 },
> > > > > > > + { 0x11314d, 0xe00 },
> > > > > > > +
> > > > > > > + { 0x21004d, 0xe00 },
> > > > > > > + { 0x21014d, 0xe00 },
> > > > > > > + { 0x21104d, 0xe00 },
> > > > > > > + { 0x21114d, 0xe00 },
> > > > > > > + { 0x21204d, 0xe00 },
> > > > > > > + { 0x21214d, 0xe00 },
> > > > > > > + { 0x21304d, 0xe00 },
> > > > > > > + { 0x21314d, 0xe00 },
> > > > > > > +
> > > > > > > + { 0x10049, 0xfbe },
> > > > > > > + { 0x10149, 0xfbe },
> > > > > > > + { 0x11049, 0xfbe },
> > > > > > > + { 0x11149, 0xfbe },
> > > > > > > + { 0x12049, 0xfbe },
> > > > > > > + { 0x12149, 0xfbe },
> > > > > > > + { 0x13049, 0xfbe },
> > > > > > > + { 0x13149, 0xfbe },
> > > > > > > +
> > > > > > > + { 0x110049, 0xfbe },
> > > > > > > + { 0x110149, 0xfbe },
> > > > > > > + { 0x111049, 0xfbe },
> > > > > > > + { 0x111149, 0xfbe },
> > > > > > > + { 0x112049, 0xfbe },
> > > > > > > + { 0x112149, 0xfbe },
> > > > > > > + { 0x113049, 0xfbe },
> > > > > > > + { 0x113149, 0xfbe },
> > > > > > > +
> > > > > > > + { 0x210049, 0xfbe },
> > > > > > > + { 0x210149, 0xfbe },
> > > > > > > + { 0x211049, 0xfbe },
> > > > > > > + { 0x211149, 0xfbe },
> > > > > > > + { 0x212049, 0xfbe },
> > > > > > > + { 0x212149, 0xfbe },
> > > > > > > + { 0x213049, 0xfbe },
> > > > > > > + { 0x213149, 0xfbe },
> > > > > > > +
> > > > > > > + { 0x43, 0x63 },
> > > > > > > + { 0x1043, 0x63 },
> > > > > > > + { 0x2043, 0x63 },
> > > > > > > + { 0x3043, 0x63 },
> > > > > > > + { 0x4043, 0x63 },
> > > > > > > + { 0x5043, 0x63 },
> > > > > > > + { 0x6043, 0x63 },
> > > > > > > + { 0x7043, 0x63 },
> > > > > > > + { 0x8043, 0x63 },
> > > > > > > + { 0x9043, 0x63 },
> > > > > > > +
> > > > > > > + { 0x20018, 0x3 },
> > > > > > > + { 0x20075, 0x4 },
> > > > > > > + { 0x20050, 0x0 },
> > > > > > > + { 0x20008, 0x2ee },
> > > > > > > + { 0x120008, 0x64 },
> > > > > > > + { 0x220008, 0x19 },
> > > > > > > + { 0x20088, 0x9 },
> > > > > > > +
> > > > > > > + { 0x200b2, 0x1d4 },
> > > > > > > + { 0x10043, 0x5a1 },
> > > > > > > + { 0x10143, 0x5a1 },
> > > > > > > + { 0x11043, 0x5a1 },
> > > > > > > + { 0x11143, 0x5a1 },
> > > > > > > + { 0x12043, 0x5a1 },
> > > > > > > + { 0x12143, 0x5a1 },
> > > > > > > + { 0x13043, 0x5a1 },
> > > > > > > + { 0x13143, 0x5a1 },
> > > > > > > +
> > > > > > > + { 0x1200b2, 0xdc },
> > > > > > > + { 0x110043, 0x5a1 },
> > > > > > > + { 0x110143, 0x5a1 },
> > > > > > > + { 0x111043, 0x5a1 },
> > > > > > > + { 0x111143, 0x5a1 },
> > > > > > > + { 0x112043, 0x5a1 },
> > > > > > > + { 0x112143, 0x5a1 },
> > > > > > > + { 0x113043, 0x5a1 },
> > > > > > > + { 0x113143, 0x5a1 },
> > > > > > > +
> > > > > > > + { 0x2200b2, 0xdc },
> > > > > > > + { 0x210043, 0x5a1 },
> > > > > > > + { 0x210143, 0x5a1 },
> > > > > > > + { 0x211043, 0x5a1 },
> > > > > > > + { 0x211143, 0x5a1 },
> > > > > > > + { 0x212043, 0x5a1 },
> > > > > > > + { 0x212143, 0x5a1 },
> > > > > > > + { 0x213043, 0x5a1 },
> > > > > > > + { 0x213143, 0x5a1 },
> > > > > > > +
> > > > > > > + { 0x200fa, 0x1 },
> > > > > > > + { 0x1200fa, 0x1 },
> > > > > > > + { 0x2200fa, 0x1 },
> > > > > > > +
> > > > > > > + { 0x20019, 0x1 },
> > > > > > > + { 0x120019, 0x1 },
> > > > > > > + { 0x220019, 0x1 },
> > > > > > > +
> > > > > > > + { 0x200f0, 0x660 },
> > > > > > > + { 0x200f1, 0x0 },
> > > > > > > + { 0x200f2, 0x4444 },
> > > > > > > + { 0x200f3, 0x8888 },
> > > > > > > + { 0x200f4, 0x5665 },
> > > > > > > + { 0x200f5, 0x0 },
> > > > > > > + { 0x200f6, 0x0 },
> > > > > > > + { 0x200f7, 0xf000 },
> > > > > > > +
> > > > > > > + { 0x20025, 0x0 },
> > > > > > > + { 0x2002d, LPDDR4_PHY_DMIPinPresent },
> > > > > > > + { 0x12002d, LPDDR4_PHY_DMIPinPresent },
> > > > > > > + { 0x22002d, LPDDR4_PHY_DMIPinPresent },
> > > > > > > + { 0x200c7, 0x21 },
> > > > > > > + { 0x200ca, 0x24 },
> > > > > > > + { 0x1200c7, 0x21 },
> > > > > > > + { 0x1200ca, 0x24 },
> > > > > > > + { 0x2200c7, 0x21 },
> > > > > > > + { 0x2200ca, 0x24 },
> > > > > >
> > > > > > Why do you add tuple - offset and value? Shouldn't we have
> > > > > > the DDR training functions here?
> > > > > >
> > > > > > It is possible to train IMX6Q and Vybrid's DDR3 (as fair as
> > > > > > I know). Would it be also possible to add the DDR4 training
> > > > > > code for IMX8?
> > > > > > > +};
> > > > > > > +
> > > > > > > +/* ddr phy trained csr */
> > > > > > > +struct dram_cfg_param lpddr4_ddrphy_trained_csr[] = {
> > > > > > > + { 0x200b2, 0x0 },
> > > > > > > + { 0x1200b2, 0x0 },
> > > > > > > + { 0x2200b2, 0x0 },
> > > > > > > + { 0x200cb, 0x0 },
> > > > > > > + { 0x10043, 0x0 },
> > > > > > > + { 0x110043, 0x0 },
> > > > > > > + { 0x210043, 0x0 },
> > > > > > > + { 0x10143, 0x0 },
> > > > > > > + { 0x110143, 0x0 },
> > > > > > > + { 0x210143, 0x0 },
> > > > > > > + { 0x11043, 0x0 },
> > > > > > > + { 0x111043, 0x0 },
> > > > > > > + { 0x211043, 0x0 },
> > > > > > > + { 0x11143, 0x0 },
> > > > > > > + { 0x111143, 0x0 },
> > > > > > > + { 0x211143, 0x0 },
> > > > > > > + { 0x12043, 0x0 },
> > > > > > > + { 0x112043, 0x0 },
> > > > > > > + { 0x212043, 0x0 },
> > > > > > > + { 0x12143, 0x0 },
> > > > > > > + { 0x112143, 0x0 },
> > > > > > > + { 0x212143, 0x0 },
> > > > > > > + { 0x13043, 0x0 },
> > > > > > > + { 0x113043, 0x0 },
> > > > > > > + { 0x213043, 0x0 },
> > > > > > > + { 0x13143, 0x0 },
> > > > > > > + { 0x113143, 0x0 },
> > > > > > > + { 0x213143, 0x0 },
> > > > > > > + { 0x80, 0x0 },
> > > > > > > + { 0x100080, 0x0 },
> > > > > > > + { 0x200080, 0x0 },
> > > > > > > + { 0x1080, 0x0 },
> > > > > > > + { 0x101080, 0x0 },
> > > > > > > + { 0x201080, 0x0 },
> > > > > > > + { 0x2080, 0x0 },
> > > > > > > + { 0x102080, 0x0 },
> > > > > > > + { 0x202080, 0x0 },
> > > > > > > + { 0x3080, 0x0 },
> > > > > > > + { 0x103080, 0x0 },
> > > > > > > + { 0x203080, 0x0 },
> > > > > > > + { 0x4080, 0x0 },
> > > > > > > + { 0x104080, 0x0 },
> > > > > > > + { 0x204080, 0x0 },
> > > > > > > + { 0x5080, 0x0 },
> > > > > > > + { 0x105080, 0x0 },
> > > > > > > + { 0x205080, 0x0 },
> > > > > > > + { 0x6080, 0x0 },
> > > > > > > + { 0x106080, 0x0 },
> > > > > > > + { 0x206080, 0x0 },
> > > > > > > + { 0x7080, 0x0 },
> > > > > > > + { 0x107080, 0x0 },
> > > > > > > + { 0x207080, 0x0 },
> > > > > > > + { 0x8080, 0x0 },
> > > > > > > + { 0x108080, 0x0 },
> > > > > > > + { 0x208080, 0x0 },
> > > > > > > + { 0x9080, 0x0 },
> > > > > > > + { 0x109080, 0x0 },
> > > > > > > + { 0x209080, 0x0 },
> > > > > > > + { 0x10080, 0x0 },
> > > > > > > + { 0x110080, 0x0 },
> > > > > > > + { 0x210080, 0x0 },
> > > > > > > + { 0x10180, 0x0 },
> > > > > > > + { 0x110180, 0x0 },
> > > > > > > + { 0x210180, 0x0 },
> > > > > > > + { 0x11080, 0x0 },
> > > > > > > + { 0x111080, 0x0 },
> > > > > > > + { 0x211080, 0x0 },
> > > > > > > + { 0x11180, 0x0 },
> > > > > > > + { 0x111180, 0x0 },
> > > > > > > + { 0x211180, 0x0 },
> > > > > > > + { 0x12080, 0x0 },
> > > > > > > + { 0x112080, 0x0 },
> > > > > > > + { 0x212080, 0x0 },
> > > > > > > + { 0x12180, 0x0 },
> > > > > > > + { 0x112180, 0x0 },
> > > > > > > + { 0x212180, 0x0 },
> > > > > > > + { 0x13080, 0x0 },
> > > > > > > + { 0x113080, 0x0 },
> > > > > > > + { 0x213080, 0x0 },
> > > > > > > + { 0x13180, 0x0 },
> > > > > > > + { 0x113180, 0x0 },
> > > > > > > + { 0x213180, 0x0 },
> > > > > > > + { 0x10081, 0x0 },
> > > > > > > + { 0x110081, 0x0 },
> > > > > > > + { 0x210081, 0x0 },
> > > > > > > + { 0x10181, 0x0 },
> > > > > > > + { 0x110181, 0x0 },
> > > > > > > + { 0x210181, 0x0 },
> > > > > > > + { 0x11081, 0x0 },
> > > > > > > + { 0x111081, 0x0 },
> > > > > > > + { 0x211081, 0x0 },
> > > > > > > + { 0x11181, 0x0 },
> > > > > > > + { 0x111181, 0x0 },
> > > > > > > + { 0x211181, 0x0 },
> > > > > > > + { 0x12081, 0x0 },
> > > > > > > + { 0x112081, 0x0 },
> > > > > > > + { 0x212081, 0x0 },
> > > > > > > + { 0x12181, 0x0 },
> > > > > > > + { 0x112181, 0x0 },
> > > > > > > + { 0x212181, 0x0 },
> > > > > > > + { 0x13081, 0x0 },
> > > > > > > + { 0x113081, 0x0 },
> > > > > > > + { 0x213081, 0x0 },
> > > > > > > + { 0x13181, 0x0 },
> > > > > > > + { 0x113181, 0x0 },
> > > > > > > + { 0x213181, 0x0 },
> > > > > > > + { 0x100d0, 0x0 },
> > > > > > > + { 0x1100d0, 0x0 },
> > > > > > > + { 0x2100d0, 0x0 },
> > > > > > > + { 0x101d0, 0x0 },
> > > > > > > + { 0x1101d0, 0x0 },
> > > > > > > + { 0x2101d0, 0x0 },
> > > > > > > + { 0x110d0, 0x0 },
> > > > > > > + { 0x1110d0, 0x0 },
> > > > > > > + { 0x2110d0, 0x0 },
> > > > > > > + { 0x111d0, 0x0 },
> > > > > > > + { 0x1111d0, 0x0 },
> > > > > > > + { 0x2111d0, 0x0 },
> > > > > > > + { 0x120d0, 0x0 },
> > > > > > > + { 0x1120d0, 0x0 },
> > > > > > > + { 0x2120d0, 0x0 },
> > > > > > > + { 0x121d0, 0x0 },
> > > > > > > + { 0x1121d0, 0x0 },
> > > > > > > + { 0x2121d0, 0x0 },
> > > > > > > + { 0x130d0, 0x0 },
> > > > > > > + { 0x1130d0, 0x0 },
> > > > > > > + { 0x2130d0, 0x0 },
> > > > > > > + { 0x131d0, 0x0 },
> > > > > > > + { 0x1131d0, 0x0 },
> > > > > > > + { 0x2131d0, 0x0 },
> > > > > > > + { 0x100d1, 0x0 },
> > > > > > > + { 0x1100d1, 0x0 },
> > > > > > > + { 0x2100d1, 0x0 },
> > > > > > > + { 0x101d1, 0x0 },
> > > > > > > + { 0x1101d1, 0x0 },
> > > > > > > + { 0x2101d1, 0x0 },
> > > > > > > + { 0x110d1, 0x0 },
> > > > > > > + { 0x1110d1, 0x0 },
> > > > > > > + { 0x2110d1, 0x0 },
> > > > > > > + { 0x111d1, 0x0 },
> > > > > > > + { 0x1111d1, 0x0 },
> > > > > > > + { 0x2111d1, 0x0 },
> > > > > > > + { 0x120d1, 0x0 },
> > > > > > > + { 0x1120d1, 0x0 },
> > > > > > > + { 0x2120d1, 0x0 },
> > > > > > > + { 0x121d1, 0x0 },
> > > > > > > + { 0x1121d1, 0x0 },
> > > > > > > + { 0x2121d1, 0x0 },
> > > > > > > + { 0x130d1, 0x0 },
> > > > > > > + { 0x1130d1, 0x0 },
> > > > > > > + { 0x2130d1, 0x0 },
> > > > > > > + { 0x131d1, 0x0 },
> > > > > > > + { 0x1131d1, 0x0 },
> > > > > > > + { 0x2131d1, 0x0 },
> > > > > > > + { 0x10068, 0x0 },
> > > > > > > + { 0x10168, 0x0 },
> > > > > > > + { 0x10268, 0x0 },
> > > > > > > + { 0x10368, 0x0 },
> > > > > > > + { 0x10468, 0x0 },
> > > > > > > + { 0x10568, 0x0 },
> > > > > > > + { 0x10668, 0x0 },
> > > > > > > + { 0x10768, 0x0 },
> > > > > > > + { 0x10868, 0x0 },
> > > > > > > + { 0x11068, 0x0 },
> > > > > > > + { 0x11168, 0x0 },
> > > > > > > + { 0x11268, 0x0 },
> > > > > > > + { 0x11368, 0x0 },
> > > > > > > + { 0x11468, 0x0 },
> > > > > > > + { 0x11568, 0x0 },
> > > > > > > + { 0x11668, 0x0 },
> > > > > > > + { 0x11768, 0x0 },
> > > > > > > + { 0x11868, 0x0 },
> > > > > > > + { 0x12068, 0x0 },
> > > > > > > + { 0x12168, 0x0 },
> > > > > > > + { 0x12268, 0x0 },
> > > > > > > + { 0x12368, 0x0 },
> > > > > > > + { 0x12468, 0x0 },
> > > > > > > + { 0x12568, 0x0 },
> > > > > > > + { 0x12668, 0x0 },
> > > > > > > + { 0x12768, 0x0 },
> > > > > > > + { 0x12868, 0x0 },
> > > > > > > + { 0x13068, 0x0 },
> > > > > > > + { 0x13168, 0x0 },
> > > > > > > + { 0x13268, 0x0 },
> > > > > > > + { 0x13368, 0x0 },
> > > > > > > + { 0x13468, 0x0 },
> > > > > > > + { 0x13568, 0x0 },
> > > > > > > + { 0x13668, 0x0 },
> > > > > > > + { 0x13768, 0x0 },
> > > > > > > + { 0x13868, 0x0 },
> > > > > > > + { 0x10069, 0x0 },
> > > > > > > + { 0x10169, 0x0 },
> > > > > > > + { 0x10269, 0x0 },
> > > > > > > + { 0x10369, 0x0 },
> > > > > > > + { 0x10469, 0x0 },
> > > > > > > + { 0x10569, 0x0 },
> > > > > > > + { 0x10669, 0x0 },
> > > > > > > + { 0x10769, 0x0 },
> > > > > > > + { 0x10869, 0x0 },
> > > > > > > + { 0x11069, 0x0 },
> > > > > > > + { 0x11169, 0x0 },
> > > > > > > + { 0x11269, 0x0 },
> > > > > > > + { 0x11369, 0x0 },
> > > > > > > + { 0x11469, 0x0 },
> > > > > > > + { 0x11569, 0x0 },
> > > > > > > + { 0x11669, 0x0 },
> > > > > > > + { 0x11769, 0x0 },
> > > > > > > + { 0x11869, 0x0 },
> > > > > > > + { 0x12069, 0x0 },
> > > > > > > + { 0x12169, 0x0 },
> > > > > > > + { 0x12269, 0x0 },
> > > > > > > + { 0x12369, 0x0 },
> > > > > > > + { 0x12469, 0x0 },
> > > > > > > + { 0x12569, 0x0 },
> > > > > > > + { 0x12669, 0x0 },
> > > > > > > + { 0x12769, 0x0 },
> > > > > > > + { 0x12869, 0x0 },
> > > > > > > + { 0x13069, 0x0 },
> > > > > > > + { 0x13169, 0x0 },
> > > > > > > + { 0x13269, 0x0 },
> > > > > > > + { 0x13369, 0x0 },
> > > > > > > + { 0x13469, 0x0 },
> > > > > > > + { 0x13569, 0x0 },
> > > > > > > + { 0x13669, 0x0 },
> > > > > > > + { 0x13769, 0x0 },
> > > > > > > + { 0x13869, 0x0 },
> > > > > > > + { 0x1008c, 0x0 },
> > > > > > > + { 0x11008c, 0x0 },
> > > > > > > + { 0x21008c, 0x0 },
> > > > > > > + { 0x1018c, 0x0 },
> > > > > > > + { 0x11018c, 0x0 },
> > > > > > > + { 0x21018c, 0x0 },
> > > > > > > + { 0x1108c, 0x0 },
> > > > > > > + { 0x11108c, 0x0 },
> > > > > > > + { 0x21108c, 0x0 },
> > > > > > > + { 0x1118c, 0x0 },
> > > > > > > + { 0x11118c, 0x0 },
> > > > > > > + { 0x21118c, 0x0 },
> > > > > > > + { 0x1208c, 0x0 },
> > > > > > > + { 0x11208c, 0x0 },
> > > > > > > + { 0x21208c, 0x0 },
> > > > > > > + { 0x1218c, 0x0 },
> > > > > > > + { 0x11218c, 0x0 },
> > > > > > > + { 0x21218c, 0x0 },
> > > > > > > + { 0x1308c, 0x0 },
> > > > > > > + { 0x11308c, 0x0 },
> > > > > > > + { 0x21308c, 0x0 },
> > > > > > > + { 0x1318c, 0x0 },
> > > > > > > + { 0x11318c, 0x0 },
> > > > > > > + { 0x21318c, 0x0 },
> > > > > > > + { 0x1008d, 0x0 },
> > > > > > > + { 0x11008d, 0x0 },
> > > > > > > + { 0x21008d, 0x0 },
> > > > > > > + { 0x1018d, 0x0 },
> > > > > > > + { 0x11018d, 0x0 },
> > > > > > > + { 0x21018d, 0x0 },
> > > > > > > + { 0x1108d, 0x0 },
> > > > > > > + { 0x11108d, 0x0 },
> > > > > > > + { 0x21108d, 0x0 },
> > > > > > > + { 0x1118d, 0x0 },
> > > > > > > + { 0x11118d, 0x0 },
> > > > > > > + { 0x21118d, 0x0 },
> > > > > > > + { 0x1208d, 0x0 },
> > > > > > > + { 0x11208d, 0x0 },
> > > > > > > + { 0x21208d, 0x0 },
> > > > > > > + { 0x1218d, 0x0 },
> > > > > > > + { 0x11218d, 0x0 },
> > > > > > > + { 0x21218d, 0x0 },
> > > > > > > + { 0x1308d, 0x0 },
> > > > > > > + { 0x11308d, 0x0 },
> > > > > > > + { 0x21308d, 0x0 },
> > > > > > > + { 0x1318d, 0x0 },
> > > > > > > + { 0x11318d, 0x0 },
> > > > > > > + { 0x21318d, 0x0 },
> > > > > > > + { 0x100c0, 0x0 },
> > > > > > > + { 0x1100c0, 0x0 },
> > > > > > > + { 0x2100c0, 0x0 },
> > > > > > > + { 0x101c0, 0x0 },
> > > > > > > + { 0x1101c0, 0x0 },
> > > > > > > + { 0x2101c0, 0x0 },
> > > > > > > + { 0x102c0, 0x0 },
> > > > > > > + { 0x1102c0, 0x0 },
> > > > > > > + { 0x2102c0, 0x0 },
> > > > > > > + { 0x103c0, 0x0 },
> > > > > > > + { 0x1103c0, 0x0 },
> > > > > > > + { 0x2103c0, 0x0 },
> > > > > > > + { 0x104c0, 0x0 },
> > > > > > > + { 0x1104c0, 0x0 },
> > > > > > > + { 0x2104c0, 0x0 },
> > > > > > > + { 0x105c0, 0x0 },
> > > > > > > + { 0x1105c0, 0x0 },
> > > > > > > + { 0x2105c0, 0x0 },
> > > > > > > + { 0x106c0, 0x0 },
> > > > > > > + { 0x1106c0, 0x0 },
> > > > > > > + { 0x2106c0, 0x0 },
> > > > > > > + { 0x107c0, 0x0 },
> > > > > > > + { 0x1107c0, 0x0 },
> > > > > > > + { 0x2107c0, 0x0 },
> > > > > > > + { 0x108c0, 0x0 },
> > > > > > > + { 0x1108c0, 0x0 },
> > > > > > > + { 0x2108c0, 0x0 },
> > > > > > > + { 0x110c0, 0x0 },
> > > > > > > + { 0x1110c0, 0x0 },
> > > > > > > + { 0x2110c0, 0x0 },
> > > > > > > + { 0x111c0, 0x0 },
> > > > > > > + { 0x1111c0, 0x0 },
> > > > > > > + { 0x2111c0, 0x0 },
> > > > > > > + { 0x112c0, 0x0 },
> > > > > > > + { 0x1112c0, 0x0 },
> > > > > > > + { 0x2112c0, 0x0 },
> > > > > > > + { 0x113c0, 0x0 },
> > > > > > > + { 0x1113c0, 0x0 },
> > > > > > > + { 0x2113c0, 0x0 },
> > > > > > > + { 0x114c0, 0x0 },
> > > > > > > + { 0x1114c0, 0x0 },
> > > > > > > + { 0x2114c0, 0x0 },
> > > > > > > + { 0x115c0, 0x0 },
> > > > > > > + { 0x1115c0, 0x0 },
> > > > > > > + { 0x2115c0, 0x0 },
> > > > > > > + { 0x116c0, 0x0 },
> > > > > > > + { 0x1116c0, 0x0 },
> > > > > > > + { 0x2116c0, 0x0 },
> > > > > > > + { 0x117c0, 0x0 },
> > > > > > > + { 0x1117c0, 0x0 },
> > > > > > > + { 0x2117c0, 0x0 },
> > > > > > > + { 0x118c0, 0x0 },
> > > > > > > + { 0x1118c0, 0x0 },
> > > > > > > + { 0x2118c0, 0x0 },
> > > > > > > + { 0x120c0, 0x0 },
> > > > > > > + { 0x1120c0, 0x0 },
> > > > > > > + { 0x2120c0, 0x0 },
> > > > > > > + { 0x121c0, 0x0 },
> > > > > > > + { 0x1121c0, 0x0 },
> > > > > > > + { 0x2121c0, 0x0 },
> > > > > > > + { 0x122c0, 0x0 },
> > > > > > > + { 0x1122c0, 0x0 },
> > > > > > > + { 0x2122c0, 0x0 },
> > > > > > > + { 0x123c0, 0x0 },
> > > > > > > + { 0x1123c0, 0x0 },
> > > > > > > + { 0x2123c0, 0x0 },
> > > > > > > + { 0x124c0, 0x0 },
> > > > > > > + { 0x1124c0, 0x0 },
> > > > > > > + { 0x2124c0, 0x0 },
> > > > > > > + { 0x125c0, 0x0 },
> > > > > > > + { 0x1125c0, 0x0 },
> > > > > > > + { 0x2125c0, 0x0 },
> > > > > > > + { 0x126c0, 0x0 },
> > > > > > > + { 0x1126c0, 0x0 },
> > > > > > > + { 0x2126c0, 0x0 },
> > > > > > > + { 0x127c0, 0x0 },
> > > > > > > + { 0x1127c0, 0x0 },
> > > > > > > + { 0x2127c0, 0x0 },
> > > > > > > + { 0x128c0, 0x0 },
> > > > > > > + { 0x1128c0, 0x0 },
> > > > > > > + { 0x2128c0, 0x0 },
> > > > > > > + { 0x130c0, 0x0 },
> > > > > > > + { 0x1130c0, 0x0 },
> > > > > > > + { 0x2130c0, 0x0 },
> > > > > > > + { 0x131c0, 0x0 },
> > > > > > > + { 0x1131c0, 0x0 },
> > > > > > > + { 0x2131c0, 0x0 },
> > > > > > > + { 0x132c0, 0x0 },
> > > > > > > + { 0x1132c0, 0x0 },
> > > > > > > + { 0x2132c0, 0x0 },
> > > > > > > + { 0x133c0, 0x0 },
> > > > > > > + { 0x1133c0, 0x0 },
> > > > > > > + { 0x2133c0, 0x0 },
> > > > > > > + { 0x134c0, 0x0 },
> > > > > > > + { 0x1134c0, 0x0 },
> > > > > > > + { 0x2134c0, 0x0 },
> > > > > > > + { 0x135c0, 0x0 },
> > > > > > > + { 0x1135c0, 0x0 },
> > > > > > > + { 0x2135c0, 0x0 },
> > > > > > > + { 0x136c0, 0x0 },
> > > > > > > + { 0x1136c0, 0x0 },
> > > > > > > + { 0x2136c0, 0x0 },
> > > > > > > + { 0x137c0, 0x0 },
> > > > > > > + { 0x1137c0, 0x0 },
> > > > > > > + { 0x2137c0, 0x0 },
> > > > > > > + { 0x138c0, 0x0 },
> > > > > > > + { 0x1138c0, 0x0 },
> > > > > > > + { 0x2138c0, 0x0 },
> > > > > > > + { 0x100c1, 0x0 },
> > > > > > > + { 0x1100c1, 0x0 },
> > > > > > > + { 0x2100c1, 0x0 },
> > > > > > > + { 0x101c1, 0x0 },
> > > > > > > + { 0x1101c1, 0x0 },
> > > > > > > + { 0x2101c1, 0x0 },
> > > > > > > + { 0x102c1, 0x0 },
> > > > > > > + { 0x1102c1, 0x0 },
> > > > > > > + { 0x2102c1, 0x0 },
> > > > > > > + { 0x103c1, 0x0 },
> > > > > > > + { 0x1103c1, 0x0 },
> > > > > > > + { 0x2103c1, 0x0 },
> > > > > > > + { 0x104c1, 0x0 },
> > > > > > > + { 0x1104c1, 0x0 },
> > > > > > > + { 0x2104c1, 0x0 },
> > > > > > > + { 0x105c1, 0x0 },
> > > > > > > + { 0x1105c1, 0x0 },
> > > > > > > + { 0x2105c1, 0x0 },
> > > > > > > + { 0x106c1, 0x0 },
> > > > > > > + { 0x1106c1, 0x0 },
> > > > > > > + { 0x2106c1, 0x0 },
> > > > > > > + { 0x107c1, 0x0 },
> > > > > > > + { 0x1107c1, 0x0 },
> > > > > > > + { 0x2107c1, 0x0 },
> > > > > > > + { 0x108c1, 0x0 },
> > > > > > > + { 0x1108c1, 0x0 },
> > > > > > > + { 0x2108c1, 0x0 },
> > > > > > > + { 0x110c1, 0x0 },
> > > > > > > + { 0x1110c1, 0x0 },
> > > > > > > + { 0x2110c1, 0x0 },
> > > > > > > + { 0x111c1, 0x0 },
> > > > > > > + { 0x1111c1, 0x0 },
> > > > > > > + { 0x2111c1, 0x0 },
> > > > > > > + { 0x112c1, 0x0 },
> > > > > > > + { 0x1112c1, 0x0 },
> > > > > > > + { 0x2112c1, 0x0 },
> > > > > > > + { 0x113c1, 0x0 },
> > > > > > > + { 0x1113c1, 0x0 },
> > > > > > > + { 0x2113c1, 0x0 },
> > > > > > > + { 0x114c1, 0x0 },
> > > > > > > + { 0x1114c1, 0x0 },
> > > > > > > + { 0x2114c1, 0x0 },
> > > > > > > + { 0x115c1, 0x0 },
> > > > > > > + { 0x1115c1, 0x0 },
> > > > > > > + { 0x2115c1, 0x0 },
> > > > > > > + { 0x116c1, 0x0 },
> > > > > > > + { 0x1116c1, 0x0 },
> > > > > > > + { 0x2116c1, 0x0 },
> > > > > > > + { 0x117c1, 0x0 },
> > > > > > > + { 0x1117c1, 0x0 },
> > > > > > > + { 0x2117c1, 0x0 },
> > > > > > > + { 0x118c1, 0x0 },
> > > > > > > + { 0x1118c1, 0x0 },
> > > > > > > + { 0x2118c1, 0x0 },
> > > > > > > + { 0x120c1, 0x0 },
> > > > > > > + { 0x1120c1, 0x0 },
> > > > > > > + { 0x2120c1, 0x0 },
> > > > > > > + { 0x121c1, 0x0 },
> > > > > > > + { 0x1121c1, 0x0 },
> > > > > > > + { 0x2121c1, 0x0 },
> > > > > > > + { 0x122c1, 0x0 },
> > > > > > > + { 0x1122c1, 0x0 },
> > > > > > > + { 0x2122c1, 0x0 },
> > > > > > > + { 0x123c1, 0x0 },
> > > > > > > + { 0x1123c1, 0x0 },
> > > > > > > + { 0x2123c1, 0x0 },
> > > > > > > + { 0x124c1, 0x0 },
> > > > > > > + { 0x1124c1, 0x0 },
> > > > > > > + { 0x2124c1, 0x0 },
> > > > > > > + { 0x125c1, 0x0 },
> > > > > > > + { 0x1125c1, 0x0 },
> > > > > > > + { 0x2125c1, 0x0 },
> > > > > > > + { 0x126c1, 0x0 },
> > > > > > > + { 0x1126c1, 0x0 },
> > > > > > > + { 0x2126c1, 0x0 },
> > > > > > > + { 0x127c1, 0x0 },
> > > > > > > + { 0x1127c1, 0x0 },
> > > > > > > + { 0x2127c1, 0x0 },
> > > > > > > + { 0x128c1, 0x0 },
> > > > > > > + { 0x1128c1, 0x0 },
> > > > > > > + { 0x2128c1, 0x0 },
> > > > > > > + { 0x130c1, 0x0 },
> > > > > > > + { 0x1130c1, 0x0 },
> > > > > > > + { 0x2130c1, 0x0 },
> > > > > > > + { 0x131c1, 0x0 },
> > > > > > > + { 0x1131c1, 0x0 },
> > > > > > > + { 0x2131c1, 0x0 },
> > > > > > > + { 0x132c1, 0x0 },
> > > > > > > + { 0x1132c1, 0x0 },
> > > > > > > + { 0x2132c1, 0x0 },
> > > > > > > + { 0x133c1, 0x0 },
> > > > > > > + { 0x1133c1, 0x0 },
> > > > > > > + { 0x2133c1, 0x0 },
> > > > > > > + { 0x134c1, 0x0 },
> > > > > > > + { 0x1134c1, 0x0 },
> > > > > > > + { 0x2134c1, 0x0 },
> > > > > > > + { 0x135c1, 0x0 },
> > > > > > > + { 0x1135c1, 0x0 },
> > > > > > > + { 0x2135c1, 0x0 },
> > > > > > > + { 0x136c1, 0x0 },
> > > > > > > + { 0x1136c1, 0x0 },
> > > > > > > + { 0x2136c1, 0x0 },
> > > > > > > + { 0x137c1, 0x0 },
> > > > > > > + { 0x1137c1, 0x0 },
> > > > > > > + { 0x2137c1, 0x0 },
> > > > > > > + { 0x138c1, 0x0 },
> > > > > > > + { 0x1138c1, 0x0 },
> > > > > > > + { 0x2138c1, 0x0 },
> > > > > > > + { 0x10020, 0x0 },
> > > > > > > + { 0x110020, 0x0 },
> > > > > > > + { 0x210020, 0x0 },
> > > > > > > + { 0x11020, 0x0 },
> > > > > > > + { 0x111020, 0x0 },
> > > > > > > + { 0x211020, 0x0 },
> > > > > > > + { 0x12020, 0x0 },
> > > > > > > + { 0x112020, 0x0 },
> > > > > > > + { 0x212020, 0x0 },
> > > > > > > + { 0x13020, 0x0 },
> > > > > > > + { 0x113020, 0x0 },
> > > > > > > + { 0x213020, 0x0 },
> > > > > > > + { 0x20072, 0x0 },
> > > > > > > + { 0x20073, 0x0 },
> > > > > > > + { 0x20074, 0x0 },
> > > > > > > + { 0x100aa, 0x0 },
> > > > > > > + { 0x110aa, 0x0 },
> > > > > > > + { 0x120aa, 0x0 },
> > > > > > > + { 0x130aa, 0x0 },
> > > > > > > + { 0x20010, 0x0 },
> > > > > > > + { 0x120010, 0x0 },
> > > > > > > + { 0x220010, 0x0 },
> > > > > > > + { 0x20011, 0x0 },
> > > > > > > + { 0x120011, 0x0 },
> > > > > > > + { 0x220011, 0x0 },
> > > > > > > + { 0x100ae, 0x0 },
> > > > > > > + { 0x1100ae, 0x0 },
> > > > > > > + { 0x2100ae, 0x0 },
> > > > > > > + { 0x100af, 0x0 },
> > > > > > > + { 0x1100af, 0x0 },
> > > > > > > + { 0x2100af, 0x0 },
> > > > > > > + { 0x110ae, 0x0 },
> > > > > > > + { 0x1110ae, 0x0 },
> > > > > > > + { 0x2110ae, 0x0 },
> > > > > > > + { 0x110af, 0x0 },
> > > > > > > + { 0x1110af, 0x0 },
> > > > > > > + { 0x2110af, 0x0 },
> > > > > > > + { 0x120ae, 0x0 },
> > > > > > > + { 0x1120ae, 0x0 },
> > > > > > > + { 0x2120ae, 0x0 },
> > > > > > > + { 0x120af, 0x0 },
> > > > > > > + { 0x1120af, 0x0 },
> > > > > > > + { 0x2120af, 0x0 },
> > > > > > > + { 0x130ae, 0x0 },
> > > > > > > + { 0x1130ae, 0x0 },
> > > > > > > + { 0x2130ae, 0x0 },
> > > > > > > + { 0x130af, 0x0 },
> > > > > > > + { 0x1130af, 0x0 },
> > > > > > > + { 0x2130af, 0x0 },
> > > > > > > + { 0x20020, 0x0 },
> > > > > > > + { 0x120020, 0x0 },
> > > > > > > + { 0x220020, 0x0 },
> > > > > > > + { 0x100a0, 0x0 },
> > > > > > > + { 0x100a1, 0x0 },
> > > > > > > + { 0x100a2, 0x0 },
> > > > > > > + { 0x100a3, 0x0 },
> > > > > > > + { 0x100a4, 0x0 },
> > > > > > > + { 0x100a5, 0x0 },
> > > > > > > + { 0x100a6, 0x0 },
> > > > > > > + { 0x100a7, 0x0 },
> > > > > > > + { 0x110a0, 0x0 },
> > > > > > > + { 0x110a1, 0x0 },
> > > > > > > + { 0x110a2, 0x0 },
> > > > > > > + { 0x110a3, 0x0 },
> > > > > > > + { 0x110a4, 0x0 },
> > > > > > > + { 0x110a5, 0x0 },
> > > > > > > + { 0x110a6, 0x0 },
> > > > > > > + { 0x110a7, 0x0 },
> > > > > > > + { 0x120a0, 0x0 },
> > > > > > > + { 0x120a1, 0x0 },
> > > > > > > + { 0x120a2, 0x0 },
> > > > > > > + { 0x120a3, 0x0 },
> > > > > > > + { 0x120a4, 0x0 },
> > > > > > > + { 0x120a5, 0x0 },
> > > > > > > + { 0x120a6, 0x0 },
> > > > > > > + { 0x120a7, 0x0 },
> > > > > > > + { 0x130a0, 0x0 },
> > > > > > > + { 0x130a1, 0x0 },
> > > > > > > + { 0x130a2, 0x0 },
> > > > > > > + { 0x130a3, 0x0 },
> > > > > > > + { 0x130a4, 0x0 },
> > > > > > > + { 0x130a5, 0x0 },
> > > > > > > + { 0x130a6, 0x0 },
> > > > > > > + { 0x130a7, 0x0 },
> > > > > > > + { 0x2007c, 0x0 },
> > > > > > > + { 0x12007c, 0x0 },
> > > > > > > + { 0x22007c, 0x0 },
> > > > > > > + { 0x2007d, 0x0 },
> > > > > > > + { 0x12007d, 0x0 },
> > > > > > > + { 0x22007d, 0x0 },
> > > > > > > + { 0x400fd, 0x0 },
> > > > > > > + { 0x400c0, 0x0 },
> > > > > > > + { 0x90201, 0x0 },
> > > > > > > + { 0x190201, 0x0 },
> > > > > > > + { 0x290201, 0x0 },
> > > > > > > + { 0x90202, 0x0 },
> > > > > > > + { 0x190202, 0x0 },
> > > > > > > + { 0x290202, 0x0 },
> > > > > > > + { 0x90203, 0x0 },
> > > > > > > + { 0x190203, 0x0 },
> > > > > > > + { 0x290203, 0x0 },
> > > > > > > + { 0x90204, 0x0 },
> > > > > > > + { 0x190204, 0x0 },
> > > > > > > + { 0x290204, 0x0 },
> > > > > > > + { 0x90205, 0x0 },
> > > > > > > + { 0x190205, 0x0 },
> > > > > > > + { 0x290205, 0x0 },
> > > > > > > + { 0x90206, 0x0 },
> > > > > > > + { 0x190206, 0x0 },
> > > > > > > + { 0x290206, 0x0 },
> > > > > > > + { 0x90207, 0x0 },
> > > > > > > + { 0x190207, 0x0 },
> > > > > > > + { 0x290207, 0x0 },
> > > > > > > + { 0x90208, 0x0 },
> > > > > > > + { 0x190208, 0x0 },
> > > > > > > + { 0x290208, 0x0 },
> > > > > > > + { 0x10062, 0x0 },
> > > > > > > + { 0x10162, 0x0 },
> > > > > > > + { 0x10262, 0x0 },
> > > > > > > + { 0x10362, 0x0 },
> > > > > > > + { 0x10462, 0x0 },
> > > > > > > + { 0x10562, 0x0 },
> > > > > > > + { 0x10662, 0x0 },
> > > > > > > + { 0x10762, 0x0 },
> > > > > > > + { 0x10862, 0x0 },
> > > > > > > + { 0x11062, 0x0 },
> > > > > > > + { 0x11162, 0x0 },
> > > > > > > + { 0x11262, 0x0 },
> > > > > > > + { 0x11362, 0x0 },
> > > > > > > + { 0x11462, 0x0 },
> > > > > > > + { 0x11562, 0x0 },
> > > > > > > + { 0x11662, 0x0 },
> > > > > > > + { 0x11762, 0x0 },
> > > > > > > + { 0x11862, 0x0 },
> > > > > > > + { 0x12062, 0x0 },
> > > > > > > + { 0x12162, 0x0 },
> > > > > > > + { 0x12262, 0x0 },
> > > > > > > + { 0x12362, 0x0 },
> > > > > > > + { 0x12462, 0x0 },
> > > > > > > + { 0x12562, 0x0 },
> > > > > > > + { 0x12662, 0x0 },
> > > > > > > + { 0x12762, 0x0 },
> > > > > > > + { 0x12862, 0x0 },
> > > > > > > + { 0x13062, 0x0 },
> > > > > > > + { 0x13162, 0x0 },
> > > > > > > + { 0x13262, 0x0 },
> > > > > > > + { 0x13362, 0x0 },
> > > > > > > + { 0x13462, 0x0 },
> > > > > > > + { 0x13562, 0x0 },
> > > > > > > + { 0x13662, 0x0 },
> > > > > > > + { 0x13762, 0x0 },
> > > > > > > + { 0x13862, 0x0 },
> > > > > > > + { 0x20077, 0x0 },
> > > > > > > + { 0x10001, 0x0 },
> > > > > > > + { 0x11001, 0x0 },
> > > > > > > + { 0x12001, 0x0 },
> > > > > > > + { 0x13001, 0x0 },
> > > > > > > + { 0x10040, 0x0 },
> > > > > > > + { 0x10140, 0x0 },
> > > > > > > + { 0x10240, 0x0 },
> > > > > > > + { 0x10340, 0x0 },
> > > > > > > + { 0x10440, 0x0 },
> > > > > > > + { 0x10540, 0x0 },
> > > > > > > + { 0x10640, 0x0 },
> > > > > > > + { 0x10740, 0x0 },
> > > > > > > + { 0x10840, 0x0 },
> > > > > > > + { 0x10030, 0x0 },
> > > > > > > + { 0x10130, 0x0 },
> > > > > > > + { 0x10230, 0x0 },
> > > > > > > + { 0x10330, 0x0 },
> > > > > > > + { 0x10430, 0x0 },
> > > > > > > + { 0x10530, 0x0 },
> > > > > > > + { 0x10630, 0x0 },
> > > > > > > + { 0x10730, 0x0 },
> > > > > > > + { 0x10830, 0x0 },
> > > > > > > + { 0x11040, 0x0 },
> > > > > > > + { 0x11140, 0x0 },
> > > > > > > + { 0x11240, 0x0 },
> > > > > > > + { 0x11340, 0x0 },
> > > > > > > + { 0x11440, 0x0 },
> > > > > > > + { 0x11540, 0x0 },
> > > > > > > + { 0x11640, 0x0 },
> > > > > > > + { 0x11740, 0x0 },
> > > > > > > + { 0x11840, 0x0 },
> > > > > > > + { 0x11030, 0x0 },
> > > > > > > + { 0x11130, 0x0 },
> > > > > > > + { 0x11230, 0x0 },
> > > > > > > + { 0x11330, 0x0 },
> > > > > > > + { 0x11430, 0x0 },
> > > > > > > + { 0x11530, 0x0 },
> > > > > > > + { 0x11630, 0x0 },
> > > > > > > + { 0x11730, 0x0 },
> > > > > > > + { 0x11830, 0x0 },
> > > > > > > + { 0x12040, 0x0 },
> > > > > > > + { 0x12140, 0x0 },
> > > > > > > + { 0x12240, 0x0 },
> > > > > > > + { 0x12340, 0x0 },
> > > > > > > + { 0x12440, 0x0 },
> > > > > > > + { 0x12540, 0x0 },
> > > > > > > + { 0x12640, 0x0 },
> > > > > > > + { 0x12740, 0x0 },
> > > > > > > + { 0x12840, 0x0 },
> > > > > > > + { 0x12030, 0x0 },
> > > > > > > + { 0x12130, 0x0 },
> > > > > > > + { 0x12230, 0x0 },
> > > > > > > + { 0x12330, 0x0 },
> > > > > > > + { 0x12430, 0x0 },
> > > > > > > + { 0x12530, 0x0 },
> > > > > > > + { 0x12630, 0x0 },
> > > > > > > + { 0x12730, 0x0 },
> > > > > > > + { 0x12830, 0x0 },
> > > > > > > + { 0x13040, 0x0 },
> > > > > > > + { 0x13140, 0x0 },
> > > > > > > + { 0x13240, 0x0 },
> > > > > > > + { 0x13340, 0x0 },
> > > > > > > + { 0x13440, 0x0 },
> > > > > > > + { 0x13540, 0x0 },
> > > > > > > + { 0x13640, 0x0 },
> > > > > > > + { 0x13740, 0x0 },
> > > > > > > + { 0x13840, 0x0 },
> > > > > > > + { 0x13030, 0x0 },
> > > > > > > + { 0x13130, 0x0 },
> > > > > > > + { 0x13230, 0x0 },
> > > > > > > + { 0x13330, 0x0 },
> > > > > > > + { 0x13430, 0x0 },
> > > > > > > + { 0x13530, 0x0 },
> > > > > > > + { 0x13630, 0x0 },
> > > > > > > + { 0x13730, 0x0 },
> > > > > > > + { 0x13830, 0x0 },
> > > > > > > +};
> > > > > >
> > > > > > The same as above. Please look into imx6q DDR3 training
> > > > > > code.
> > > > > > > +
> > > > > > > +/* P0 message block paremeter for training firmware */
> > > > > > > +struct dram_cfg_param lpddr4_fsp0_cfg[] = {
> > > > > > > + { 0xd0000, 0x0 },
> > > > > > > + { 0x54000, 0x0 },
> > > > > > > + { 0x54001, 0x0 },
> > > > > > > + { 0x54002, 0x0 },
> > > > > > > + { 0x54003, 0xbb8 },
> > > > > > > + { 0x54004, 0x2 },
> > > > > > > + { 0x54005, ((LPDDR4_PHY_RON << 8) |
> > > > > > > LPDDR4_PHY_RTT) },//PHY Ron/Rtt
> > > > > > > + { 0x54006, LPDDR4_PHY_VREF_VALUE },
> > > > > > > + { 0x54007, 0x0 },
> > > > > > > + { 0x54008, 0x131f },
> > > > > > > + { 0x54009, 0xc8 },
> > > > > > > + { 0x5400a, 0x0 },
> > > > > > > + { 0x5400b, 0x2 },
> > > > > > > + { 0x5400c, 0x0 },
> > > > > > > + { 0x5400d, 0x0 },
> > > > > > > + { 0x5400e, 0x0 },
> > > > > > > + { 0x5400f, 0x0 },
> > > > > > > + { 0x54010, 0x0 },
> > > > > > > + { 0x54011, 0x0 },
> > > > > > > + { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
> > > > > > > + { 0x54013, 0x0 },
> > > > > > > + { 0x54014, 0x0 },
> > > > > > > + { 0x54015, 0x0 },
> > > > > > > + { 0x54016, 0x0 },
> > > > > > > + { 0x54017, 0x0 },
> > > > > > > + { 0x54018, 0x0 },
> > > > > > > + { 0x54019, 0x2dd4 },
> > > > > > > + { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
> > > > > > > + { 0x5401b, 0x4d66 },
> > > > > > > + { 0x5401c, 0x4d08 },
> > > > > > > + { 0x5401d, 0x0 },
> > > > > > > + { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
> > > > > > > + { 0x5401f, 0x2dd4 },
> > > > > > > + { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
> > > > > > > + { 0x54021, 0x4d66 },
> > > > > > > + { 0x54022, 0x4d08 },
> > > > > > > + { 0x54023, 0x0 },
> > > > > > > + { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
> > > > > > > + { 0x54025, 0x0 },
> > > > > > > + { 0x54026, 0x0 },
> > > > > > > + { 0x54027, 0x0 },
> > > > > > > + { 0x54028, 0x0 },
> > > > > > > + { 0x54029, 0x0 },
> > > > > > > + { 0x5402a, 0x0 },
> > > > > > > + { 0x5402b, 0x1000 },
> > > > > > > + { 0x5402c, LPDDR4_CS },
> > > > > > > + { 0x5402d, 0x0 },
> > > > > > > + { 0x5402e, 0x0 },
> > > > > > > + { 0x5402f, 0x0 },
> > > > > > > + { 0x54030, 0x0 },
> > > > > > > + { 0x54031, 0x0 },
> > > > > > > + { 0x54032, 0xd400 },
> > > > > > > + { 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
> > > > > > > + { 0x54034, 0x6600 },
> > > > > > > + { 0x54035, 0x84d },
> > > > > > > + { 0x54036, 0x4d },
> > > > > > > + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
> > > > > > > + { 0x54038, 0xd400 },
> > > > > > > + { 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
> > > > > > > + { 0x5403a, 0x6600 },
> > > > > > > + { 0x5403b, 0x84d },
> > > > > > > + { 0x5403c, 0x4d },
> > > > > > > + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
> > > > > > > + { 0x5403e, 0x0 },
> > > > > > > + { 0x5403f, 0x0 },
> > > > > > > + { 0x54040, 0x0 },
> > > > > > > + { 0x54041, 0x0 },
> > > > > > > + { 0x54042, 0x0 },
> > > > > > > + { 0x54043, 0x0 },
> > > > > > > + { 0x54044, 0x0 },
> > > > > > > + { 0xd0000, 0x1 },
> > > > > > > +};
> > > > > > > +
> > > > > > > +/* P1 message block paremeter for training firmware */
> > > > > > > +struct dram_cfg_param lpddr4_fsp1_cfg[] = {
> > > > > > > + { 0xd0000, 0x0 },
> > > > > > > + { 0x54000, 0x0 },
> > > > > > > + { 0x54001, 0x0 },
> > > > > > > + { 0x54002, 0x101 },
> > > > > > > + { 0x54003, 0x190 },
> > > > > > > + { 0x54004, 0x2 },
> > > > > > > + { 0x54005, ((LPDDR4_PHY_RON << 8) |
> > > > > > > LPDDR4_PHY_RTT) },//PHY Ron/Rtt
> > > > > > > + { 0x54006, LPDDR4_PHY_VREF_VALUE },
> > > > > > > + { 0x54007, 0x0 },
> > > > > > > + { 0x54008, 0x121f },
> > > > > > > + { 0x54009, 0xc8 },
> > > > > > > + { 0x5400a, 0x0 },
> > > > > > > + { 0x5400b, 0x2 },
> > > > > > > + { 0x5400c, 0x0 },
> > > > > > > + { 0x5400d, 0x0 },
> > > > > > > + { 0x5400e, 0x0 },
> > > > > > > + { 0x5400f, 0x0 },
> > > > > > > + { 0x54010, 0x0 },
> > > > > > > + { 0x54011, 0x0 },
> > > > > > > + { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
> > > > > > > + { 0x54013, 0x0 },
> > > > > > > + { 0x54014, 0x0 },
> > > > > > > + { 0x54015, 0x0 },
> > > > > > > + { 0x54016, 0x0 },
> > > > > > > + { 0x54017, 0x0 },
> > > > > > > + { 0x54018, 0x0 },
> > > > > > > + { 0x54019, 0x84 },
> > > > > > > + { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
> > > > > > > + { 0x5401b, 0x4d66 },
> > > > > > > + { 0x5401c, 0x4d08 },
> > > > > > > + { 0x5401d, 0x0 },
> > > > > > > + { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
> > > > > > > + { 0x5401f, 0x84 },
> > > > > > > + { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
> > > > > > > + { 0x54021, 0x4d66 },
> > > > > > > + { 0x54022, 0x4d08 },
> > > > > > > + { 0x54023, 0x0 },
> > > > > > > + { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
> > > > > > > + { 0x54025, 0x0 },
> > > > > > > + { 0x54026, 0x0 },
> > > > > > > + { 0x54027, 0x0 },
> > > > > > > + { 0x54028, 0x0 },
> > > > > > > + { 0x54029, 0x0 },
> > > > > > > + { 0x5402a, 0x0 },
> > > > > > > + { 0x5402b, 0x1000 },
> > > > > > > + { 0x5402c, LPDDR4_CS },
> > > > > > > + { 0x5402d, 0x0 },
> > > > > > > + { 0x5402e, 0x0 },
> > > > > > > + { 0x5402f, 0x0 },
> > > > > > > + { 0x54030, 0x0 },
> > > > > > > + { 0x54031, 0x0 },
> > > > > > > + { 0x54032, 0x8400 },
> > > > > > > + { 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
> > > > > > > + { 0x54034, 0x6600 },
> > > > > > > + { 0x54035, 0x84d },
> > > > > > > + { 0x54036, 0x4d },
> > > > > > > + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
> > > > > > > + { 0x54038, 0x8400 },
> > > > > > > + { 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
> > > > > > > + { 0x5403a, 0x6600 },
> > > > > > > + { 0x5403b, 0x84d },
> > > > > > > + { 0x5403c, 0x4d },
> > > > > > > + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
> > > > > > > + { 0x5403e, 0x0 },
> > > > > > > + { 0x5403f, 0x0 },
> > > > > > > + { 0x54040, 0x0 },
> > > > > > > + { 0x54041, 0x0 },
> > > > > > > + { 0x54042, 0x0 },
> > > > > > > + { 0x54043, 0x0 },
> > > > > > > + { 0x54044, 0x0 },
> > > > > > > + { 0xd0000, 0x1 },
> > > > > > > +};
> > > > > > > +
> > > > > > > +/* P1 message block paremeter for training firmware */
> > > > > > > +struct dram_cfg_param lpddr4_fsp2_cfg[] = {
> > > > > > > + { 0xd0000, 0x0 },
> > > > > > > + { 0x54000, 0x0 },
> > > > > > > + { 0x54001, 0x0 },
> > > > > > > + { 0x54002, 0x102 },
> > > > > > > + { 0x54003, 0x64 },
> > > > > > > + { 0x54004, 0x2 },
> > > > > > > + { 0x54005, ((LPDDR4_PHY_RON << 8) |
> > > > > > > LPDDR4_PHY_RTT) },//PHY Ron/Rtt
> > > > > > > + { 0x54006, LPDDR4_PHY_VREF_VALUE },
> > > > > > > + { 0x54007, 0x0 },
> > > > > > > + { 0x54008, 0x121f },
> > > > > > > + { 0x54009, 0xc8 },
> > > > > > > + { 0x5400a, 0x0 },
> > > > > > > + { 0x5400b, 0x2 },
> > > > > > > + { 0x5400c, 0x0 },
> > > > > > > + { 0x5400d, 0x0 },
> > > > > > > + { 0x5400e, 0x0 },
> > > > > > > + { 0x5400f, 0x0 },
> > > > > > > + { 0x54010, 0x0 },
> > > > > > > + { 0x54011, 0x0 },
> > > > > > > + { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
> > > > > > > + { 0x54013, 0x0 },
> > > > > > > + { 0x54014, 0x0 },
> > > > > > > + { 0x54015, 0x0 },
> > > > > > > + { 0x54016, 0x0 },
> > > > > > > + { 0x54017, 0x0 },
> > > > > > > + { 0x54018, 0x0 },
> > > > > > > + { 0x54019, 0x84 },
> > > > > > > + { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
> > > > > > > + { 0x5401b, 0x4d66 },
> > > > > > > + { 0x5401c, 0x4d08 },
> > > > > > > + { 0x5401d, 0x0 },
> > > > > > > + { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
> > > > > > > + { 0x5401f, 0x84 },
> > > > > > > + { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
> > > > > > > + { 0x54021, 0x4d66 },
> > > > > > > + { 0x54022, 0x4d08 },
> > > > > > > + { 0x54023, 0x0 },
> > > > > > > + { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
> > > > > > > + { 0x54025, 0x0 },
> > > > > > > + { 0x54026, 0x0 },
> > > > > > > + { 0x54027, 0x0 },
> > > > > > > + { 0x54028, 0x0 },
> > > > > > > + { 0x54029, 0x0 },
> > > > > > > + { 0x5402a, 0x0 },
> > > > > > > + { 0x5402b, 0x1000 },
> > > > > > > + { 0x5402c, LPDDR4_CS },
> > > > > > > + { 0x5402d, 0x0 },
> > > > > > > + { 0x5402e, 0x0 },
> > > > > > > + { 0x5402f, 0x0 },
> > > > > > > + { 0x54030, 0x0 },
> > > > > > > + { 0x54031, 0x0 },
> > > > > > > + { 0x54032, 0x8400 },
> > > > > > > + { 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
> > > > > > > + { 0x54034, 0x6600 },
> > > > > > > + { 0x54035, 0x84d },
> > > > > > > + { 0x54036, 0x4d },
> > > > > > > + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
> > > > > > > + { 0x54038, 0x8400 },
> > > > > > > + { 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
> > > > > > > + { 0x5403a, 0x6600 },
> > > > > > > + { 0x5403b, 0x84d },
> > > > > > > + { 0x5403c, 0x4d },
> > > > > > > + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
> > > > > > > + { 0x5403e, 0x0 },
> > > > > > > + { 0x5403f, 0x0 },
> > > > > > > + { 0x54040, 0x0 },
> > > > > > > + { 0x54041, 0x0 },
> > > > > > > + { 0x54042, 0x0 },
> > > > > > > + { 0x54043, 0x0 },
> > > > > > > + { 0x54044, 0x0 },
> > > > > > > + { 0xd0000, 0x1 },
> > > > > > > +};
> > > > > > > +
> > > > > > > +/* P0 2D message block paremeter for training firmware */
> > > > > > > +struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
> > > > > > > + { 0xd0000, 0x0 },
> > > > > > > + { 0x54000, 0x0 },
> > > > > > > + { 0x54001, 0x0 },
> > > > > > > + { 0x54002, 0x0 },
> > > > > > > + { 0x54003, 0xbb8 },
> > > > > > > + { 0x54004, 0x2 },
> > > > > > > + { 0x54005, ((LPDDR4_PHY_RON << 8) |
> > > > > > > LPDDR4_PHY_RTT) },//PHY Ron/Rtt
> > > > > > > + { 0x54006, LPDDR4_PHY_VREF_VALUE },
> > > > > > > + { 0x54007, 0x0 },
> > > > > > > + { 0x54008, 0x61 },
> > > > > > > + { 0x54009, 0xc8 },
> > > > > > > + { 0x5400a, 0x0 },
> > > > > > > + { 0x5400b, 0x2 },
> > > > > > > + { 0x5400c, 0x0 },
> > > > > > > + { 0x5400d, 0x0 },
> > > > > > > + { 0x5400e, 0x0 },
> > > > > > > + { 0x5400f, 0x100 },
> > > > > > > + { 0x54010, 0x1f7f },
> > > > > > > + { 0x54011, 0x0 },
> > > > > > > + { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
> > > > > > > + { 0x54013, 0x0 },
> > > > > > > + { 0x54014, 0x0 },
> > > > > > > + { 0x54015, 0x0 },
> > > > > > > + { 0x54016, 0x0 },
> > > > > > > + { 0x54017, 0x0 },
> > > > > > > + { 0x54018, 0x0 },
> > > > > > > + { 0x54019, 0x2dd4 },
> > > > > > > + { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
> > > > > > > + { 0x5401b, 0x4d66 },
> > > > > > > + { 0x5401c, 0x4d08 },
> > > > > > > + { 0x5401d, 0x0 },
> > > > > > > + { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
> > > > > > > + { 0x5401f, 0x2dd4 },
> > > > > > > + { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
> > > > > > > + { 0x54021, 0x4d66 },
> > > > > > > + { 0x54022, 0x4d08 },
> > > > > > > + { 0x54023, 0x0 },
> > > > > > > + { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
> > > > > > > + { 0x54025, 0x0 },
> > > > > > > + { 0x54026, 0x0 },
> > > > > > > + { 0x54027, 0x0 },
> > > > > > > + { 0x54028, 0x0 },
> > > > > > > + { 0x54029, 0x0 },
> > > > > > > + { 0x5402a, 0x0 },
> > > > > > > + { 0x5402b, 0x1000 },
> > > > > > > + { 0x5402c, LPDDR4_CS },
> > > > > > > + { 0x5402d, 0x0 },
> > > > > > > + { 0x5402e, 0x0 },
> > > > > > > + { 0x5402f, 0x0 },
> > > > > > > + { 0x54030, 0x0 },
> > > > > > > + { 0x54031, 0x0 },
> > > > > > > + { 0x54032, 0xd400 },
> > > > > > > + { 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
> > > > > > > + { 0x54034, 0x6600 },
> > > > > > > + { 0x54035, 0x84d },
> > > > > > > + { 0x54036, 0x4d },
> > > > > > > + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
> > > > > > > + { 0x54038, 0xd400 },
> > > > > > > + { 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
> > > > > > > + { 0x5403a, 0x6600 },
> > > > > > > + { 0x5403b, 0x84d },
> > > > > > > + { 0x5403c, 0x4d },
> > > > > > > + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
> > > > > > > + { 0x5403e, 0x0 },
> > > > > > > + { 0x5403f, 0x0 },
> > > > > > > + { 0x54040, 0x0 },
> > > > > > > + { 0x54041, 0x0 },
> > > > > > > + { 0x54042, 0x0 },
> > > > > > > + { 0x54043, 0x0 },
> > > > > > > + { 0x54044, 0x0 },
> > > > > > > + { 0xd0000, 0x1 },
> > > > > > > +};
> > > > > > > +
> > > > > > > +/* DRAM PHY init engine image */
> > > > > > > +struct dram_cfg_param lpddr4_phy_pie[] = {
> > > > > > > + { 0xd0000, 0x0 },
> > > > > > > + { 0x90000, 0x10 },
> > > > > > > + { 0x90001, 0x400 },
> > > > > > > + { 0x90002, 0x10e },
> > > > > > > + { 0x90003, 0x0 },
> > > > > > > + { 0x90004, 0x0 },
> > > > > > > + { 0x90005, 0x8 },
> > > > > > > + { 0x90029, 0xb },
> > > > > > > + { 0x9002a, 0x480 },
> > > > > > > + { 0x9002b, 0x109 },
> > > > > > > + { 0x9002c, 0x8 },
> > > > > > > + { 0x9002d, 0x448 },
> > > > > > > + { 0x9002e, 0x139 },
> > > > > > > + { 0x9002f, 0x8 },
> > > > > > > + { 0x90030, 0x478 },
> > > > > > > + { 0x90031, 0x109 },
> > > > > > > + { 0x90032, 0x0 },
> > > > > > > + { 0x90033, 0xe8 },
> > > > > > > + { 0x90034, 0x109 },
> > > > > > > + { 0x90035, 0x2 },
> > > > > > > + { 0x90036, 0x10 },
> > > > > > > + { 0x90037, 0x139 },
> > > > > > > + { 0x90038, 0xf },
> > > > > > > + { 0x90039, 0x7c0 },
> > > > > > > + { 0x9003a, 0x139 },
> > > > > > > + { 0x9003b, 0x44 },
> > > > > > > + { 0x9003c, 0x630 },
> > > > > > > + { 0x9003d, 0x159 },
> > > > > > > + { 0x9003e, 0x14f },
> > > > > > > + { 0x9003f, 0x630 },
> > > > > > > + { 0x90040, 0x159 },
> > > > > > > + { 0x90041, 0x47 },
> > > > > > > + { 0x90042, 0x630 },
> > > > > > > + { 0x90043, 0x149 },
> > > > > > > + { 0x90044, 0x4f },
> > > > > > > + { 0x90045, 0x630 },
> > > > > > > + { 0x90046, 0x179 },
> > > > > > > + { 0x90047, 0x8 },
> > > > > > > + { 0x90048, 0xe0 },
> > > > > > > + { 0x90049, 0x109 },
> > > > > > > + { 0x9004a, 0x0 },
> > > > > > > + { 0x9004b, 0x7c8 },
> > > > > > > + { 0x9004c, 0x109 },
> > > > > > > + { 0x9004d, 0x0 },
> > > > > > > + { 0x9004e, 0x1 },
> > > > > > > + { 0x9004f, 0x8 },
> > > > > > > + { 0x90050, 0x0 },
> > > > > > > + { 0x90051, 0x45a },
> > > > > > > + { 0x90052, 0x9 },
> > > > > > > + { 0x90053, 0x0 },
> > > > > > > + { 0x90054, 0x448 },
> > > > > > > + { 0x90055, 0x109 },
> > > > > > > + { 0x90056, 0x40 },
> > > > > > > + { 0x90057, 0x630 },
> > > > > > > + { 0x90058, 0x179 },
> > > > > > > + { 0x90059, 0x1 },
> > > > > > > + { 0x9005a, 0x618 },
> > > > > > > + { 0x9005b, 0x109 },
> > > > > > > + { 0x9005c, 0x40c0 },
> > > > > > > + { 0x9005d, 0x630 },
> > > > > > > + { 0x9005e, 0x149 },
> > > > > > > + { 0x9005f, 0x8 },
> > > > > > > + { 0x90060, 0x4 },
> > > > > > > + { 0x90061, 0x48 },
> > > > > > > + { 0x90062, 0x4040 },
> > > > > > > + { 0x90063, 0x630 },
> > > > > > > + { 0x90064, 0x149 },
> > > > > > > + { 0x90065, 0x0 },
> > > > > > > + { 0x90066, 0x4 },
> > > > > > > + { 0x90067, 0x48 },
> > > > > > > + { 0x90068, 0x40 },
> > > > > > > + { 0x90069, 0x630 },
> > > > > > > + { 0x9006a, 0x149 },
> > > > > > > + { 0x9006b, 0x10 },
> > > > > > > + { 0x9006c, 0x4 },
> > > > > > > + { 0x9006d, 0x18 },
> > > > > > > + { 0x9006e, 0x0 },
> > > > > > > + { 0x9006f, 0x4 },
> > > > > > > + { 0x90070, 0x78 },
> > > > > > > + { 0x90071, 0x549 },
> > > > > > > + { 0x90072, 0x630 },
> > > > > > > + { 0x90073, 0x159 },
> > > > > > > + { 0x90074, 0xd49 },
> > > > > > > + { 0x90075, 0x630 },
> > > > > > > + { 0x90076, 0x159 },
> > > > > > > + { 0x90077, 0x94a },
> > > > > > > + { 0x90078, 0x630 },
> > > > > > > + { 0x90079, 0x159 },
> > > > > > > + { 0x9007a, 0x441 },
> > > > > > > + { 0x9007b, 0x630 },
> > > > > > > + { 0x9007c, 0x149 },
> > > > > > > + { 0x9007d, 0x42 },
> > > > > > > + { 0x9007e, 0x630 },
> > > > > > > + { 0x9007f, 0x149 },
> > > > > > > + { 0x90080, 0x1 },
> > > > > > > + { 0x90081, 0x630 },
> > > > > > > + { 0x90082, 0x149 },
> > > > > > > + { 0x90083, 0x0 },
> > > > > > > + { 0x90084, 0xe0 },
> > > > > > > + { 0x90085, 0x109 },
> > > > > > > + { 0x90086, 0xa },
> > > > > > > + { 0x90087, 0x10 },
> > > > > > > + { 0x90088, 0x109 },
> > > > > > > + { 0x90089, 0x9 },
> > > > > > > + { 0x9008a, 0x3c0 },
> > > > > > > + { 0x9008b, 0x149 },
> > > > > > > + { 0x9008c, 0x9 },
> > > > > > > + { 0x9008d, 0x3c0 },
> > > > > > > + { 0x9008e, 0x159 },
> > > > > > > + { 0x9008f, 0x18 },
> > > > > > > + { 0x90090, 0x10 },
> > > > > > > + { 0x90091, 0x109 },
> > > > > > > + { 0x90092, 0x0 },
> > > > > > > + { 0x90093, 0x3c0 },
> > > > > > > + { 0x90094, 0x109 },
> > > > > > > + { 0x90095, 0x18 },
> > > > > > > + { 0x90096, 0x4 },
> > > > > > > + { 0x90097, 0x48 },
> > > > > > > + { 0x90098, 0x18 },
> > > > > > > + { 0x90099, 0x4 },
> > > > > > > + { 0x9009a, 0x58 },
> > > > > > > + { 0x9009b, 0xa },
> > > > > > > + { 0x9009c, 0x10 },
> > > > > > > + { 0x9009d, 0x109 },
> > > > > > > + { 0x9009e, 0x2 },
> > > > > > > + { 0x9009f, 0x10 },
> > > > > > > + { 0x900a0, 0x109 },
> > > > > > > + { 0x900a1, 0x5 },
> > > > > > > + { 0x900a2, 0x7c0 },
> > > > > > > + { 0x900a3, 0x109 },
> > > > > > > + { 0x900a4, 0x10 },
> > > > > > > + { 0x900a5, 0x10 },
> > > > > > > + { 0x900a6, 0x109 },
> > > > > > > + { 0x40000, 0x811 },
> > > > > > > + { 0x40020, 0x880 },
> > > > > > > + { 0x40040, 0x0 },
> > > > > > > + { 0x40060, 0x0 },
> > > > > > > + { 0x40001, 0x4008 },
> > > > > > > + { 0x40021, 0x83 },
> > > > > > > + { 0x40041, 0x4f },
> > > > > > > + { 0x40061, 0x0 },
> > > > > > > + { 0x40002, 0x4040 },
> > > > > > > + { 0x40022, 0x83 },
> > > > > > > + { 0x40042, 0x51 },
> > > > > > > + { 0x40062, 0x0 },
> > > > > > > + { 0x40003, 0x811 },
> > > > > > > + { 0x40023, 0x880 },
> > > > > > > + { 0x40043, 0x0 },
> > > > > > > + { 0x40063, 0x0 },
> > > > > > > + { 0x40004, 0x720 },
> > > > > > > + { 0x40024, 0xf },
> > > > > > > + { 0x40044, 0x1740 },
> > > > > > > + { 0x40064, 0x0 },
> > > > > > > + { 0x40005, 0x16 },
> > > > > > > + { 0x40025, 0x83 },
> > > > > > > + { 0x40045, 0x4b },
> > > > > > > + { 0x40065, 0x0 },
> > > > > > > + { 0x40006, 0x716 },
> > > > > > > + { 0x40026, 0xf },
> > > > > > > + { 0x40046, 0x2001 },
> > > > > > > + { 0x40066, 0x0 },
> > > > > > > + { 0x40007, 0x716 },
> > > > > > > + { 0x40027, 0xf },
> > > > > > > + { 0x40047, 0x2800 },
> > > > > > > + { 0x40067, 0x0 },
> > > > > > > + { 0x40008, 0x716 },
> > > > > > > + { 0x40028, 0xf },
> > > > > > > + { 0x40048, 0xf00 },
> > > > > > > + { 0x40068, 0x0 },
> > > > > > > + { 0x40009, 0x720 },
> > > > > > > + { 0x40029, 0xf },
> > > > > > > + { 0x40049, 0x1400 },
> > > > > > > + { 0x40069, 0x0 },
> > > > > > > + { 0x4000a, 0xe08 },
> > > > > > > + { 0x4002a, 0xc15 },
> > > > > > > + { 0x4004a, 0x0 },
> > > > > > > + { 0x4006a, 0x0 },
> > > > > > > + { 0x4000b, 0x623 },
> > > > > > > + { 0x4002b, 0x15 },
> > > > > > > + { 0x4004b, 0x0 },
> > > > > > > + { 0x4006b, 0x0 },
> > > > > > > + { 0x4000c, 0x4028 },
> > > > > > > + { 0x4002c, 0x80 },
> > > > > > > + { 0x4004c, 0x0 },
> > > > > > > + { 0x4006c, 0x0 },
> > > > > > > + { 0x4000d, 0xe08 },
> > > > > > > + { 0x4002d, 0xc1a },
> > > > > > > + { 0x4004d, 0x0 },
> > > > > > > + { 0x4006d, 0x0 },
> > > > > > > + { 0x4000e, 0x623 },
> > > > > > > + { 0x4002e, 0x1a },
> > > > > > > + { 0x4004e, 0x0 },
> > > > > > > + { 0x4006e, 0x0 },
> > > > > > > + { 0x4000f, 0x4040 },
> > > > > > > + { 0x4002f, 0x80 },
> > > > > > > + { 0x4004f, 0x0 },
> > > > > > > + { 0x4006f, 0x0 },
> > > > > > > + { 0x40010, 0x2604 },
> > > > > > > + { 0x40030, 0x15 },
> > > > > > > + { 0x40050, 0x0 },
> > > > > > > + { 0x40070, 0x0 },
> > > > > > > + { 0x40011, 0x708 },
> > > > > > > + { 0x40031, 0x5 },
> > > > > > > + { 0x40051, 0x0 },
> > > > > > > + { 0x40071, 0x2002 },
> > > > > > > + { 0x40012, 0x8 },
> > > > > > > + { 0x40032, 0x80 },
> > > > > > > + { 0x40052, 0x0 },
> > > > > > > + { 0x40072, 0x0 },
> > > > > > > + { 0x40013, 0x2604 },
> > > > > > > + { 0x40033, 0x1a },
> > > > > > > + { 0x40053, 0x0 },
> > > > > > > + { 0x40073, 0x0 },
> > > > > > > + { 0x40014, 0x708 },
> > > > > > > + { 0x40034, 0xa },
> > > > > > > + { 0x40054, 0x0 },
> > > > > > > + { 0x40074, 0x2002 },
> > > > > > > + { 0x40015, 0x4040 },
> > > > > > > + { 0x40035, 0x80 },
> > > > > > > + { 0x40055, 0x0 },
> > > > > > > + { 0x40075, 0x0 },
> > > > > > > + { 0x40016, 0x60a },
> > > > > > > + { 0x40036, 0x15 },
> > > > > > > + { 0x40056, 0x1200 },
> > > > > > > + { 0x40076, 0x0 },
> > > > > > > + { 0x40017, 0x61a },
> > > > > > > + { 0x40037, 0x15 },
> > > > > > > + { 0x40057, 0x1300 },
> > > > > > > + { 0x40077, 0x0 },
> > > > > > > + { 0x40018, 0x60a },
> > > > > > > + { 0x40038, 0x1a },
> > > > > > > + { 0x40058, 0x1200 },
> > > > > > > + { 0x40078, 0x0 },
> > > > > > > + { 0x40019, 0x642 },
> > > > > > > + { 0x40039, 0x1a },
> > > > > > > + { 0x40059, 0x1300 },
> > > > > > > + { 0x40079, 0x0 },
> > > > > > > + { 0x4001a, 0x4808 },
> > > > > > > + { 0x4003a, 0x880 },
> > > > > > > + { 0x4005a, 0x0 },
> > > > > > > + { 0x4007a, 0x0 },
> > > > > > > + { 0x900a7, 0x0 },
> > > > > > > + { 0x900a8, 0x790 },
> > > > > > > + { 0x900a9, 0x11a },
> > > > > > > + { 0x900aa, 0x8 },
> > > > > > > + { 0x900ab, 0x7aa },
> > > > > > > + { 0x900ac, 0x2a },
> > > > > > > + { 0x900ad, 0x10 },
> > > > > > > + { 0x900ae, 0x7b2 },
> > > > > > > + { 0x900af, 0x2a },
> > > > > > > + { 0x900b0, 0x0 },
> > > > > > > + { 0x900b1, 0x7c8 },
> > > > > > > + { 0x900b2, 0x109 },
> > > > > > > + { 0x900b3, 0x10 },
> > > > > > > + { 0x900b4, 0x2a8 },
> > > > > > > + { 0x900b5, 0x129 },
> > > > > > > + { 0x900b6, 0x8 },
> > > > > > > + { 0x900b7, 0x370 },
> > > > > > > + { 0x900b8, 0x129 },
> > > > > > > + { 0x900b9, 0xa },
> > > > > > > + { 0x900ba, 0x3c8 },
> > > > > > > + { 0x900bb, 0x1a9 },
> > > > > > > + { 0x900bc, 0xc },
> > > > > > > + { 0x900bd, 0x408 },
> > > > > > > + { 0x900be, 0x199 },
> > > > > > > + { 0x900bf, 0x14 },
> > > > > > > + { 0x900c0, 0x790 },
> > > > > > > + { 0x900c1, 0x11a },
> > > > > > > + { 0x900c2, 0x8 },
> > > > > > > + { 0x900c3, 0x4 },
> > > > > > > + { 0x900c4, 0x18 },
> > > > > > > + { 0x900c5, 0xe },
> > > > > > > + { 0x900c6, 0x408 },
> > > > > > > + { 0x900c7, 0x199 },
> > > > > > > + { 0x900c8, 0x8 },
> > > > > > > + { 0x900c9, 0x8568 },
> > > > > > > + { 0x900ca, 0x108 },
> > > > > > > + { 0x900cb, 0x18 },
> > > > > > > + { 0x900cc, 0x790 },
> > > > > > > + { 0x900cd, 0x16a },
> > > > > > > + { 0x900ce, 0x8 },
> > > > > > > + { 0x900cf, 0x1d8 },
> > > > > > > + { 0x900d0, 0x169 },
> > > > > > > + { 0x900d1, 0x10 },
> > > > > > > + { 0x900d2, 0x8558 },
> > > > > > > + { 0x900d3, 0x168 },
> > > > > > > + { 0x900d4, 0x70 },
> > > > > > > + { 0x900d5, 0x788 },
> > > > > > > + { 0x900d6, 0x16a },
> > > > > > > + { 0x900d7, 0x1ff8 },
> > > > > > > + { 0x900d8, 0x85a8 },
> > > > > > > + { 0x900d9, 0x1e8 },
> > > > > > > + { 0x900da, 0x50 },
> > > > > > > + { 0x900db, 0x798 },
> > > > > > > + { 0x900dc, 0x16a },
> > > > > > > + { 0x900dd, 0x60 },
> > > > > > > + { 0x900de, 0x7a0 },
> > > > > > > + { 0x900df, 0x16a },
> > > > > > > + { 0x900e0, 0x8 },
> > > > > > > + { 0x900e1, 0x8310 },
> > > > > > > + { 0x900e2, 0x168 },
> > > > > > > + { 0x900e3, 0x8 },
> > > > > > > + { 0x900e4, 0xa310 },
> > > > > > > + { 0x900e5, 0x168 },
> > > > > > > + { 0x900e6, 0xa },
> > > > > > > + { 0x900e7, 0x408 },
> > > > > > > + { 0x900e8, 0x169 },
> > > > > > > + { 0x900e9, 0x6e },
> > > > > > > + { 0x900ea, 0x0 },
> > > > > > > + { 0x900eb, 0x68 },
> > > > > > > + { 0x900ec, 0x0 },
> > > > > > > + { 0x900ed, 0x408 },
> > > > > > > + { 0x900ee, 0x169 },
> > > > > > > + { 0x900ef, 0x0 },
> > > > > > > + { 0x900f0, 0x8310 },
> > > > > > > + { 0x900f1, 0x168 },
> > > > > > > + { 0x900f2, 0x0 },
> > > > > > > + { 0x900f3, 0xa310 },
> > > > > > > + { 0x900f4, 0x168 },
> > > > > > > + { 0x900f5, 0x1ff8 },
> > > > > > > + { 0x900f6, 0x85a8 },
> > > > > > > + { 0x900f7, 0x1e8 },
> > > > > > > + { 0x900f8, 0x68 },
> > > > > > > + { 0x900f9, 0x798 },
> > > > > > > + { 0x900fa, 0x16a },
> > > > > > > + { 0x900fb, 0x78 },
> > > > > > > + { 0x900fc, 0x7a0 },
> > > > > > > + { 0x900fd, 0x16a },
> > > > > > > + { 0x900fe, 0x68 },
> > > > > > > + { 0x900ff, 0x790 },
> > > > > > > + { 0x90100, 0x16a },
> > > > > > > + { 0x90101, 0x8 },
> > > > > > > + { 0x90102, 0x8b10 },
> > > > > > > + { 0x90103, 0x168 },
> > > > > > > + { 0x90104, 0x8 },
> > > > > > > + { 0x90105, 0xab10 },
> > > > > > > + { 0x90106, 0x168 },
> > > > > > > + { 0x90107, 0xa },
> > > > > > > + { 0x90108, 0x408 },
> > > > > > > + { 0x90109, 0x169 },
> > > > > > > + { 0x9010a, 0x58 },
> > > > > > > + { 0x9010b, 0x0 },
> > > > > > > + { 0x9010c, 0x68 },
> > > > > > > + { 0x9010d, 0x0 },
> > > > > > > + { 0x9010e, 0x408 },
> > > > > > > + { 0x9010f, 0x169 },
> > > > > > > + { 0x90110, 0x0 },
> > > > > > > + { 0x90111, 0x8b10 },
> > > > > > > + { 0x90112, 0x168 },
> > > > > > > + { 0x90113, 0x0 },
> > > > > > > + { 0x90114, 0xab10 },
> > > > > > > + { 0x90115, 0x168 },
> > > > > > > + { 0x90116, 0x0 },
> > > > > > > + { 0x90117, 0x1d8 },
> > > > > > > + { 0x90118, 0x169 },
> > > > > > > + { 0x90119, 0x80 },
> > > > > > > + { 0x9011a, 0x790 },
> > > > > > > + { 0x9011b, 0x16a },
> > > > > > > + { 0x9011c, 0x18 },
> > > > > > > + { 0x9011d, 0x7aa },
> > > > > > > + { 0x9011e, 0x6a },
> > > > > > > + { 0x9011f, 0xa },
> > > > > > > + { 0x90120, 0x0 },
> > > > > > > + { 0x90121, 0x1e9 },
> > > > > > > + { 0x90122, 0x8 },
> > > > > > > + { 0x90123, 0x8080 },
> > > > > > > + { 0x90124, 0x108 },
> > > > > > > + { 0x90125, 0xf },
> > > > > > > + { 0x90126, 0x408 },
> > > > > > > + { 0x90127, 0x169 },
> > > > > > > + { 0x90128, 0xc },
> > > > > > > + { 0x90129, 0x0 },
> > > > > > > + { 0x9012a, 0x68 },
> > > > > > > + { 0x9012b, 0x9 },
> > > > > > > + { 0x9012c, 0x0 },
> > > > > > > + { 0x9012d, 0x1a9 },
> > > > > > > + { 0x9012e, 0x0 },
> > > > > > > + { 0x9012f, 0x408 },
> > > > > > > + { 0x90130, 0x169 },
> > > > > > > + { 0x90131, 0x0 },
> > > > > > > + { 0x90132, 0x8080 },
> > > > > > > + { 0x90133, 0x108 },
> > > > > > > + { 0x90134, 0x8 },
> > > > > > > + { 0x90135, 0x7aa },
> > > > > > > + { 0x90136, 0x6a },
> > > > > > > + { 0x90137, 0x0 },
> > > > > > > + { 0x90138, 0x8568 },
> > > > > > > + { 0x90139, 0x108 },
> > > > > > > + { 0x9013a, 0xb7 },
> > > > > > > + { 0x9013b, 0x790 },
> > > > > > > + { 0x9013c, 0x16a },
> > > > > > > + { 0x9013d, 0x1f },
> > > > > > > + { 0x9013e, 0x0 },
> > > > > > > + { 0x9013f, 0x68 },
> > > > > > > + { 0x90140, 0x8 },
> > > > > > > + { 0x90141, 0x8558 },
> > > > > > > + { 0x90142, 0x168 },
> > > > > > > + { 0x90143, 0xf },
> > > > > > > + { 0x90144, 0x408 },
> > > > > > > + { 0x90145, 0x169 },
> > > > > > > + { 0x90146, 0xc },
> > > > > > > + { 0x90147, 0x0 },
> > > > > > > + { 0x90148, 0x68 },
> > > > > > > + { 0x90149, 0x0 },
> > > > > > > + { 0x9014a, 0x408 },
> > > > > > > + { 0x9014b, 0x169 },
> > > > > > > + { 0x9014c, 0x0 },
> > > > > > > + { 0x9014d, 0x8558 },
> > > > > > > + { 0x9014e, 0x168 },
> > > > > > > + { 0x9014f, 0x8 },
> > > > > > > + { 0x90150, 0x3c8 },
> > > > > > > + { 0x90151, 0x1a9 },
> > > > > > > + { 0x90152, 0x3 },
> > > > > > > + { 0x90153, 0x370 },
> > > > > > > + { 0x90154, 0x129 },
> > > > > > > + { 0x90155, 0x20 },
> > > > > > > + { 0x90156, 0x2aa },
> > > > > > > + { 0x90157, 0x9 },
> > > > > > > + { 0x90158, 0x0 },
> > > > > > > + { 0x90159, 0x400 },
> > > > > > > + { 0x9015a, 0x10e },
> > > > > > > + { 0x9015b, 0x8 },
> > > > > > > + { 0x9015c, 0xe8 },
> > > > > > > + { 0x9015d, 0x109 },
> > > > > > > + { 0x9015e, 0x0 },
> > > > > > > + { 0x9015f, 0x8140 },
> > > > > > > + { 0x90160, 0x10c },
> > > > > > > + { 0x90161, 0x10 },
> > > > > > > + { 0x90162, 0x8138 },
> > > > > > > + { 0x90163, 0x10c },
> > > > > > > + { 0x90164, 0x8 },
> > > > > > > + { 0x90165, 0x7c8 },
> > > > > > > + { 0x90166, 0x101 },
> > > > > > > + { 0x90167, 0x8 },
> > > > > > > + { 0x90168, 0x0 },
> > > > > > > + { 0x90169, 0x8 },
> > > > > > > + { 0x9016a, 0x8 },
> > > > > > > + { 0x9016b, 0x448 },
> > > > > > > + { 0x9016c, 0x109 },
> > > > > > > + { 0x9016d, 0xf },
> > > > > > > + { 0x9016e, 0x7c0 },
> > > > > > > + { 0x9016f, 0x109 },
> > > > > > > + { 0x90170, 0x0 },
> > > > > > > + { 0x90171, 0xe8 },
> > > > > > > + { 0x90172, 0x109 },
> > > > > > > + { 0x90173, 0x47 },
> > > > > > > + { 0x90174, 0x630 },
> > > > > > > + { 0x90175, 0x109 },
> > > > > > > + { 0x90176, 0x8 },
> > > > > > > + { 0x90177, 0x618 },
> > > > > > > + { 0x90178, 0x109 },
> > > > > > > + { 0x90179, 0x8 },
> > > > > > > + { 0x9017a, 0xe0 },
> > > > > > > + { 0x9017b, 0x109 },
> > > > > > > + { 0x9017c, 0x0 },
> > > > > > > + { 0x9017d, 0x7c8 },
> > > > > > > + { 0x9017e, 0x109 },
> > > > > > > + { 0x9017f, 0x8 },
> > > > > > > + { 0x90180, 0x8140 },
> > > > > > > + { 0x90181, 0x10c },
> > > > > > > + { 0x90182, 0x0 },
> > > > > > > + { 0x90183, 0x1 },
> > > > > > > + { 0x90184, 0x8 },
> > > > > > > + { 0x90185, 0x8 },
> > > > > > > + { 0x90186, 0x4 },
> > > > > > > + { 0x90187, 0x8 },
> > > > > > > + { 0x90188, 0x8 },
> > > > > > > + { 0x90189, 0x7c8 },
> > > > > > > + { 0x9018a, 0x101 },
> > > > > > > + { 0x90006, 0x0 },
> > > > > > > + { 0x90007, 0x0 },
> > > > > > > + { 0x90008, 0x8 },
> > > > > > > + { 0x90009, 0x0 },
> > > > > > > + { 0x9000a, 0x0 },
> > > > > > > + { 0x9000b, 0x0 },
> > > > > > > + { 0xd00e7, 0x400 },
> > > > > > > + { 0x90017, 0x0 },
> > > > > > > + { 0x9001f, 0x2a },
> > > > > > > + { 0x90026, 0x6a },
> > > > > > > + { 0x400d0, 0x0 },
> > > > > > > + { 0x400d1, 0x101 },
> > > > > > > + { 0x400d2, 0x105 },
> > > > > > > + { 0x400d3, 0x107 },
> > > > > > > + { 0x400d4, 0x10f },
> > > > > > > + { 0x400d5, 0x202 },
> > > > > > > + { 0x400d6, 0x20a },
> > > > > > > + { 0x400d7, 0x20b },
> > > > > > > + { 0x2003a, 0x2 },
> > > > > > > + { 0x2000b, 0x5d },
> > > > > > > + { 0x2000c, 0xbb },
> > > > > > > + { 0x2000d, 0x753 },
> > > > > > > + { 0x2000e, 0x2c },
> > > > > > > + { 0x12000b, 0xc },
> > > > > > > + { 0x12000c, 0x19 },
> > > > > > > + { 0x12000d, 0xfa },
> > > > > > > + { 0x12000e, 0x10 },
> > > > > > > + { 0x22000b, 0x3 },
> > > > > > > + { 0x22000c, 0x6 },
> > > > > > > + { 0x22000d, 0x3e },
> > > > > > > + { 0x22000e, 0x10 },
> > > > > > > + { 0x9000c, 0x0 },
> > > > > > > + { 0x9000d, 0x173 },
> > > > > > > + { 0x9000e, 0x60 },
> > > > > > > + { 0x9000f, 0x6110 },
> > > > > > > + { 0x90010, 0x2152 },
> > > > > > > + { 0x90011, 0xdfbd },
> > > > > > > + { 0x90012, 0x60 },
> > > > > > > + { 0x90013, 0x6152 },
> > > > > > > + { 0x20010, 0x5a },
> > > > > > > + { 0x20011, 0x3 },
> > > > > > > + { 0x40080, 0xe0 },
> > > > > > > + { 0x40081, 0x12 },
> > > > > > > + { 0x40082, 0xe0 },
> > > > > > > + { 0x40083, 0x12 },
> > > > > > > + { 0x40084, 0xe0 },
> > > > > > > + { 0x40085, 0x12 },
> > > > > > > + { 0x140080, 0xe0 },
> > > > > > > + { 0x140081, 0x12 },
> > > > > > > + { 0x140082, 0xe0 },
> > > > > > > + { 0x140083, 0x12 },
> > > > > > > + { 0x140084, 0xe0 },
> > > > > > > + { 0x140085, 0x12 },
> > > > > > > + { 0x240080, 0xe0 },
> > > > > > > + { 0x240081, 0x12 },
> > > > > > > + { 0x240082, 0xe0 },
> > > > > > > + { 0x240083, 0x12 },
> > > > > > > + { 0x240084, 0xe0 },
> > > > > > > + { 0x240085, 0x12 },
> > > > > > > + { 0x400fd, 0xf },
> > > > > > > + { 0x10011, 0x1 },
> > > > > > > + { 0x10012, 0x1 },
> > > > > > > + { 0x10013, 0x180 },
> > > > > > > + { 0x10018, 0x1 },
> > > > > > > + { 0x10002, 0x6209 },
> > > > > > > + { 0x100b2, 0x1 },
> > > > > > > + { 0x101b4, 0x1 },
> > > > > > > + { 0x102b4, 0x1 },
> > > > > > > + { 0x103b4, 0x1 },
> > > > > > > + { 0x104b4, 0x1 },
> > > > > > > + { 0x105b4, 0x1 },
> > > > > > > + { 0x106b4, 0x1 },
> > > > > > > + { 0x107b4, 0x1 },
> > > > > > > + { 0x108b4, 0x1 },
> > > > > > > + { 0x11011, 0x1 },
> > > > > > > + { 0x11012, 0x1 },
> > > > > > > + { 0x11013, 0x180 },
> > > > > > > + { 0x11018, 0x1 },
> > > > > > > + { 0x11002, 0x6209 },
> > > > > > > + { 0x110b2, 0x1 },
> > > > > > > + { 0x111b4, 0x1 },
> > > > > > > + { 0x112b4, 0x1 },
> > > > > > > + { 0x113b4, 0x1 },
> > > > > > > + { 0x114b4, 0x1 },
> > > > > > > + { 0x115b4, 0x1 },
> > > > > > > + { 0x116b4, 0x1 },
> > > > > > > + { 0x117b4, 0x1 },
> > > > > > > + { 0x118b4, 0x1 },
> > > > > > > + { 0x12011, 0x1 },
> > > > > > > + { 0x12012, 0x1 },
> > > > > > > + { 0x12013, 0x180 },
> > > > > > > + { 0x12018, 0x1 },
> > > > > > > + { 0x12002, 0x6209 },
> > > > > > > + { 0x120b2, 0x1 },
> > > > > > > + { 0x121b4, 0x1 },
> > > > > > > + { 0x122b4, 0x1 },
> > > > > > > + { 0x123b4, 0x1 },
> > > > > > > + { 0x124b4, 0x1 },
> > > > > > > + { 0x125b4, 0x1 },
> > > > > > > + { 0x126b4, 0x1 },
> > > > > > > + { 0x127b4, 0x1 },
> > > > > > > + { 0x128b4, 0x1 },
> > > > > > > + { 0x13011, 0x1 },
> > > > > > > + { 0x13012, 0x1 },
> > > > > > > + { 0x13013, 0x180 },
> > > > > > > + { 0x13018, 0x1 },
> > > > > > > + { 0x13002, 0x6209 },
> > > > > > > + { 0x130b2, 0x1 },
> > > > > > > + { 0x131b4, 0x1 },
> > > > > > > + { 0x132b4, 0x1 },
> > > > > > > + { 0x133b4, 0x1 },
> > > > > > > + { 0x134b4, 0x1 },
> > > > > > > + { 0x135b4, 0x1 },
> > > > > > > + { 0x136b4, 0x1 },
> > > > > > > + { 0x137b4, 0x1 },
> > > > > > > + { 0x138b4, 0x1 },
> > > > > > > + { 0x2003a, 0x2 },
> > > > > > > + { 0xc0080, 0x2 },
> > > > > > > + { 0xd0000, 0x1 },
> > > > > > > +};
> > > > > >
> > > > > > The same as above.
> > > > > >
> > > > > > > +
> > > > > > > +struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
> > > > > > > + {
> > > > > > > + /* P0 3000mts 1D */
> > > > > > > + .drate = 3000,
> > > > > > > + .fw_type = FW_1D_IMAGE,
> > > > > > > + .fsp_cfg = lpddr4_fsp0_cfg,
> > > > > > > + .fsp_cfg_num =
> > > > > > > ARRAY_SIZE(lpddr4_fsp0_cfg),
> > > > > > > + },
> > > > > > > + {
> > > > > > > + /* P0 3000mts 2D */
> > > > > > > + .drate = 3000,
> > > > > > > + .fw_type = FW_2D_IMAGE,
> > > > > > > + .fsp_cfg = lpddr4_fsp0_2d_cfg,
> > > > > > > + .fsp_cfg_num =
> > > > > > > ARRAY_SIZE(lpddr4_fsp0_2d_cfg),
> > > > > > > + },
> > > > > > > + {
> > > > > > > + /* P1 400mts 1D */
> > > > > > > + .drate = 400,
> > > > > > > + .fw_type = FW_1D_IMAGE,
> > > > > > > + .fsp_cfg = lpddr4_fsp1_cfg,
> > > > > > > + .fsp_cfg_num =
> > > > > > > ARRAY_SIZE(lpddr4_fsp1_cfg),
> > > > > > > + },
> > > > > > > + {
> > > > > > > + /* P1 100mts 1D */
> > > > > > > + .drate = 100,
> > > > > > > + .fw_type = FW_1D_IMAGE,
> > > > > > > + .fsp_cfg = lpddr4_fsp2_cfg,
> > > > > > > + .fsp_cfg_num =
> > > > > > > ARRAY_SIZE(lpddr4_fsp2_cfg),
> > > > > > > + },
> > > > > > > +};
> > > > > > > +
> > > > > > > +/* lpddr4 timing config params on EVK board */
> > > > > > > +struct dram_timing_info dram_timing = {
> > > > > > > + .ddrc_cfg = lpddr4_ddrc_cfg,
> > > > > > > + .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
> > > > > > > + .ddrphy_cfg = lpddr4_ddrphy_cfg,
> > > > > > > + .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg),
> > > > > > > + .fsp_msg = lpddr4_dram_fsp_msg,
> > > > > > > + .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg),
> > > > > > > + .ddrphy_trained_csr = lpddr4_ddrphy_trained_csr,
> > > > > > > + .ddrphy_trained_csr_num =
> > > > > > > ARRAY_SIZE(lpddr4_ddrphy_trained_csr),
> > > > > > > + .ddrphy_pie = lpddr4_phy_pie,
> > > > > > > + .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
> > > > > >
> > > > > > It would be best to get the above values calculated
> > > > > > dynamically for this SoC.
> > > > > >
> > > > > > > +};
> > > > > > > diff --git a/board/freescale/imx8mm_evk/spl.c
> > > > > > > b/board/freescale/imx8mm_evk/spl.c new file mode 100644
> > > > > > > index 0000000000..cf1dfc2c2a
> > > > > > > --- /dev/null
> > > > > > > +++ b/board/freescale/imx8mm_evk/spl.c
> > > > > > > @@ -0,0 +1,187 @@
> > > > > > > +// SPDX-License-Identifier: GPL-2.0+
> > > > > > > +/*
> > > > > > > + * Copyright 2019 NXP
> > > > > > > + */
> > > > > > > +
> > > > > > > +#include <common.h>
> > > > > > > +#include <spl.h>
> > > > > > > +#include <asm/io.h>
> > > > > > > +#include <errno.h>
> > > > > > > +#include <asm/io.h>
> > > > > > > +#include <asm/mach-imx/iomux-v3.h>
> > > > > > > +#include <asm/arch/imx8mm_pins.h>
> > > > > > > +#include <asm/arch/sys_proto.h>
> > > > > > > +#include <power/pmic.h>
> > > > > > > +#include <asm/arch/clock.h>
> > > > > > > +#include <asm/mach-imx/gpio.h>
> > > > > > > +#include <asm/mach-imx/mxc_i2c.h>
> > > > > > > +#include <fsl_esdhc.h>
> > > > > > > +#include <mmc.h>
> > > > > > > +#include <asm/arch/ddr.h>
> > > > > > > +
> > > > > > > +DECLARE_GLOBAL_DATA_PTR;
> > > > > > > +
> > > > > > > +void spl_dram_init(void)
> > > > > > > +{
> > > > > > > + ddr_init(&dram_timing);
> > > > > > > +}
> > > > > > > +
> > > > > > > +#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 18)
> > > > > > > +#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
> > > > > > > +
> > > > > > > +#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS |
> > > > > > PAD_CTL_PUE | \
> > > > > > > + PAD_CTL_PE | PAD_CTL_FSEL2)
> > > > > > > +#define USDHC_GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE1)
> > > > > > > +
> > > > > > > +static iomux_v3_cfg_t const usdhc3_pads[] = {
> > > > > > > + IMX8MM_PAD_NAND_WE_B_USDHC3_CLK |
> > > > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > > > + IMX8MM_PAD_NAND_WP_B_USDHC3_CMD |
> > > > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > > > + IMX8MM_PAD_NAND_DATA04_USDHC3_DATA0 |
> > > > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > > > + IMX8MM_PAD_NAND_DATA05_USDHC3_DATA1 |
> > > > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > > > + IMX8MM_PAD_NAND_DATA06_USDHC3_DATA2 |
> > > > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > > > + IMX8MM_PAD_NAND_DATA07_USDHC3_DATA3 |
> > > > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > > > + IMX8MM_PAD_NAND_RE_B_USDHC3_DATA4 |
> > > > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > > > + IMX8MM_PAD_NAND_CE2_B_USDHC3_DATA5 |
> > > > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > > > + IMX8MM_PAD_NAND_CE3_B_USDHC3_DATA6 |
> > > > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > > > + IMX8MM_PAD_NAND_CLE_USDHC3_DATA7 |
> > > > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL), +};
> > > > > > > +
> > > > > > > +static iomux_v3_cfg_t const usdhc2_pads[] = {
> > > > > > > + IMX8MM_PAD_SD2_CLK_USDHC2_CLK |
> > > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > > > + IMX8MM_PAD_SD2_CMD_USDHC2_CMD |
> > > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > > > + IMX8MM_PAD_SD2_DATA0_USDHC2_DATA0 |
> > > > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > > > + IMX8MM_PAD_SD2_DATA1_USDHC2_DATA1 |
> > > > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > > > + IMX8MM_PAD_SD2_DATA2_USDHC2_DATA2 |
> > > > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > > > + IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 |
> > > > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > > > + IMX8MM_PAD_SD2_RESET_B_GPIO2_IO19 |
> > > > > > > MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), +};
> > > > > > > +
> > > > > > > +/*
> > > > > > > + * The evk board uses DAT3 to detect CD card plugin,
> > > > > > > + * in u-boot we mux the pin to GPIO when doing
> > > > > > > board_mmc_getcd.
> > > > > > > + */
> > > > > > > +static iomux_v3_cfg_t const usdhc2_cd_pad =
> > > > > > > + IMX8MM_PAD_SD2_DATA3_GPIO2_IO18 |
> > > > > > > MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL); +
> > > > > > > +static iomux_v3_cfg_t const usdhc2_dat3_pad =
> > > > > > > + IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 |
> > > > > > > + MUX_PAD_CTRL(USDHC_PAD_CTRL);
> > > > > > > +
> > > > > > > +static struct fsl_esdhc_cfg usdhc_cfg[2] = {
> > > > > > > + {USDHC2_BASE_ADDR, 0, 1},
> > > > > > > + {USDHC3_BASE_ADDR, 0, 1},
> > > > > > > +};
> > > > > > > +
> > > > > > > +int board_mmc_init(bd_t *bis)
> > > > > > > +{
> > > > > > > + int i, ret;
> > > > > > > + /*
> > > > > > > + * According to the board_mmc_init() the
> > > > > > > following map is done:
> > > > > > > + * (U-Boot device node) (Physical Port)
> > > > > > > + * mmc0 USDHC1
> > > > > > > + * mmc1 USDHC2
> > > > > > > + */
> > > > > > > + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
> > > > > > > + switch (i) {
> > > > > > > + case 0:
> > > > > > > + usdhc_cfg[0].sdhc_clk =
> > > > > > > mxc_get_clock(MXC_ESDHC2_CLK);
> > > > > > > +
> > > > > > > imx_iomux_v3_setup_multiple_pads(usdhc2_pads, +
> > > > > > > ARRAY_SIZE(usdhc2_pads));
> > > > > > > + gpio_request(USDHC2_PWR_GPIO,
> > > > > > > "usdhc2_reset");
> > > > > > > +
> > > > > > > gpio_direction_output(USDHC2_PWR_GPIO, 0);
> > > > > > > + udelay(500);
> > > > > > > +
> > > > > > > gpio_direction_output(USDHC2_PWR_GPIO, 1);
> > > > > > > + break;
> > > > > > > + case 1:
> > > > > > > + usdhc_cfg[1].sdhc_clk =
> > > > > > > mxc_get_clock(MXC_ESDHC3_CLK);
> > > > > > > +
> > > > > > > imx_iomux_v3_setup_multiple_pads(usdhc3_pads, +
> > > > > > > ARRAY_SIZE(usdhc3_pads));
> > > > > > > + break;
> > > > > >
> > > > > > It would be best if you could enable DM/DTS in SPL too from
> > > > > > the outset (and share the SPL size).
> > > > > >
> > > > > > Do you have any timeline for converting SPL to DM/DTS?
> > > > > >
> > > > > > > + default:
> > > > > > > + printf("USDHC controllers %d not
> > > > > > > supported \n", i + 1);
> > > > > > > + return -EINVAL;
> > > > > > > + }
> > > > > > > +
> > > > > > > + ret = fsl_esdhc_initialize(bis,
> > > > > > > &usdhc_cfg[i]);
> > > > > > > + if (ret)
> > > > > > > + return ret;
> > > > > > > + }
> > > > > > > +
> > > > > > > + return 0;
> > > > > > > +}
> > > > > > > +
> > > > > > > +int board_mmc_getcd(struct mmc *mmc)
> > > > > > > +{
> > > > > > > + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg
> > > > > > > *)mmc->priv;
> > > > > > > + int ret = 0;
> > > > > > > +
> > > > > > > + switch (cfg->esdhc_base) {
> > > > > > > + case USDHC3_BASE_ADDR:
> > > > > > > + ret = 1;
> > > > > > > + break;
> > > > > > > + case USDHC2_BASE_ADDR:
> > > > > > > + imx_iomux_v3_setup_pad(usdhc2_cd_pad);
> > > > > > > + gpio_request(USDHC2_CD_GPIO, "usdhc2
> > > > > > > cd");
> > > > > > > + gpio_direction_input(USDHC2_CD_GPIO);
> > > > > > > +
> > > > > > > + /*
> > > > > > > + * Since it is the DAT3 pin, this pin is
> > > > > > > pulled to
> > > > > > > + * low voltage if no card
> > > > > > > + */
> > > > > > > + ret = gpio_get_value(USDHC2_CD_GPIO);
> > > > > > > +
> > > > > > > + imx_iomux_v3_setup_pad(usdhc2_dat3_pad);
> > > > > > > + return ret;
> > > > > > > + }
> > > > > > > +
> > > > > > > + return 1;
> > > > > > > +}
> > > > > > > +
> > > > > > > +void spl_board_init(void)
> > > > > > > +{
> > > > > > > + puts("Normal Boot\n");
> > > > > > > +}
> > > > > > > +
> > > > > > > +#ifdef CONFIG_SPL_LOAD_FIT
> > > > > > > +int board_fit_config_name_match(const char *name)
> > > > > > > +{
> > > > > > > + /* Just empty function now - can't decide what to
> > > > > > > choose */
> > > > > > > + debug("%s: %s\n", __func__, name);
> > > > > > > +
> > > > > > > + return 0;
> > > > > > > +}
> > > > > > > +#endif
> > > > > > > +
> > > > > > > +void board_init_f(ulong dummy)
> > > > > > > +{
> > > > > > > + int ret;
> > > > > > > +
> > > > > > > + /* Clear global data */
> > > > > > > + memset((void *)gd, 0, sizeof(gd_t));
> > > > > > > +
> > > > > > > + arch_cpu_init();
> > > > > > > +
> > > > > > > + init_uart_clk(1);
> > > > > > > +
> > > > > > > + board_early_init_f();
> > > > > > > +
> > > > > > > + timer_init();
> > > > > > > +
> > > > > > > + preloader_console_init();
> > > > > > > +
> > > > > > > + /* Clear the BSS. */
> > > > > > > + memset(__bss_start, 0, __bss_end - __bss_start);
> > > > > > > +
> > > > > > > + ret = spl_init();
> > > > > > > + if (ret) {
> > > > > > > + debug("spl_init() failed: %d\n", ret);
> > > > > > > + hang();
> > > > > > > + }
> > > > > > > +
> > > > > > > + enable_tzc380();
> > > > > > > +
> > > > > > > + /* DDR initialization */
> > > > > > > + spl_dram_init();
> > > > > > > +
> > > > > > > + board_init_r(NULL, 0);
> > > > > > > +}
> > > > > > > diff --git a/configs/imx8mm_evk_defconfig
> > > > > > > b/configs/imx8mm_evk_defconfig new file mode 100644
> > > > > > > index 0000000000..6110f23e38
> > > > > > > --- /dev/null
> > > > > > > +++ b/configs/imx8mm_evk_defconfig
> > > > > > > @@ -0,0 +1,41 @@
> > > > > > > +CONFIG_ARM=y
> > > > > > > +CONFIG_ARCH_IMX8M=y
> > > > > > > +CONFIG_SYS_TEXT_BASE=0x40200000
> > > > > > > +CONFIG_SPL_GPIO_SUPPORT=y
> > > > > > > +CONFIG_SYS_MALLOC_F_LEN=0x2000
> > > > > > > +CONFIG_TARGET_IMX8MM_EVK=y
> > > > > > > +CONFIG_SPL_MMC_SUPPORT=y
> > > > > > > +CONFIG_SPL_SERIAL_SUPPORT=y
> > > > > > > +CONFIG_SPL=y
> > > > > > > +CONFIG_FIT=y
> > > > > > > +CONFIG_FIT_EXTERNAL_OFFSET=0x3000
> > > > > > > +CONFIG_SPL_LOAD_FIT=y
> > > > > > >
> > > >
> > +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
> > > > > > >
> > > > > >
> > > >
> > +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m
> > > > > > /imximage.cfg,SPL_TEXT_BASE=0x7E1000"
> > > > > > > +CONFIG_DEFAULT_FDT_FILE="fsl-imx8mm-evk.dtb"
> > > > > > > +CONFIG_SPL_BOARD_INIT=y
> > > > > > > +CONFIG_SPL_I2C_SUPPORT=y
> > > > > > > +CONFIG_HUSH_PARSER=y
> > > > > > > +CONFIG_CMD_GPIO=y
> > > > > > > +CONFIG_CMD_I2C=y
> > > > > > > +CONFIG_CMD_CACHE=y
> > > > > > > +CONFIG_CMD_REGULATOR=y
> > > > > > > +CONFIG_CMD_EXT2=y
> > > > > > > +CONFIG_CMD_EXT4=y
> > > > > > > +CONFIG_CMD_EXT4_WRITE=y
> > > > > > > +CONFIG_CMD_FAT=y
> > > > > > > +CONFIG_OF_CONTROL=y
> > > > > > > +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mm-evk"
> > > > > > > +CONFIG_DM_GPIO=y
> > > > > > > +CONFIG_MXC_GPIO=y
> > > > > > > +CONFIG_DM_I2C=y
> > > > > > > +CONFIG_SYS_I2C_MXC=y
> > > > > > > +CONFIG_DM_MMC=y
> > > > > > > +CONFIG_DM_ETH=y
> > > > > >
> > > > > > Here you enable the DM_ETH, but the welcome u-boot info
> > > > > > says:
> > > > > >
> > > > > > "Net: No ethernet found."
> > > > > >
> > > > > > > +CONFIG_PINCTRL=y
> > > > > > > +CONFIG_PINCTRL_IMX8M=y
> > > > > > > +CONFIG_DM_REGULATOR=y
> > > > > > > +CONFIG_DM_REGULATOR_FIXED=y
> > > > > > > +CONFIG_DM_REGULATOR_GPIO=y
> > > > > > > +CONFIG_MXC_UART=y
> > > > > > > +CONFIG_DM_THERMAL=y
> > > > > > > diff --git a/include/configs/imx8mm_evk.h
> > > > > > > b/include/configs/imx8mm_evk.h new file mode 100644
> > > > > > > index 0000000000..f944308757
> > > > > > > --- /dev/null
> > > > > > > +++ b/include/configs/imx8mm_evk.h
> > > > > > > @@ -0,0 +1,221 @@
> > > > > > > +/* SPDX-License-Identifier: GPL-2.0+ */
> > > > > > > +/*
> > > > > > > + * Copyright 2018 NXP
> > > > > > > + */
> > > > > > > +
> > > > > > > +#ifndef __IMX8MM_EVK_H
> > > > > > > +#define __IMX8MM_EVK_H
> > > > > > > +
> > > > > > > +#include <linux/sizes.h>
> > > > > > > +#include <asm/arch/imx-regs.h>
> > > > > > > +
> > > > > > > +#ifdef CONFIG_SECURE_BOOT
> > > > > > > +#define CONFIG_CSF_SIZE 0x2000 /*
> > > > > > > 8K region */ +#endif
> > > > > > > +
> > > > > > > +#define CONFIG_SPL_MAX_SIZE (148 * 1024)
> > > > > > > +#define CONFIG_SYS_MONITOR_LEN (512 *
> > > > > > > 1024) +#define
> > CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
> > > > > > > +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
> > > > 0x300
> > > > > > > +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
> > > > > > > +#define CONFIG_SYS_UBOOT_BASE \
> > > > > > > + (QSPI0_AMBA_BASE +
> > > > > > CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR *
> > > > > > > 512) +
> > > > > > > +#ifdef CONFIG_SPL_BUILD
> > > > > > > +/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
> > > > > > > +#define CONFIG_SPL_WATCHDOG_SUPPORT
> > > > > > > +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
> > > > > > > +#define CONFIG_SPL_POWER_SUPPORT
> > > > > > > +#define
> > > > > > > CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
> > > > > > > +#define CONFIG_SPL_STACK 0x91fff0 +#define
> > > > > > > CONFIG_SPL_LIBCOMMON_SUPPORT +#define
> > > > > > CONFIG_SPL_LIBGENERIC_SUPPORT
> > > > > > > +#define CONFIG_SPL_BSS_START_ADDR 0x00910000
> > > > > > > +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /*
> > > > > > > 8 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
> > > > > > > +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /*
> > > > > > > 512 KB */ +#define CONFIG_SYS_ICACHE_OFF
> > > > > > > +#define CONFIG_SYS_DCACHE_OFF
> > > > > > > +
> > > > > > > +#define CONFIG_MALLOC_F_ADDR 0x912000 /*
> > > > > > > malloc f used before GD_FLG_FULL_MALLOC_INIT set */ +
> > > > > > > +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image
> > > > gives a
> > > > > > error
> > > > > > > info not panic */ +
> > > > > > > +#undef CONFIG_DM_MMC
> > > > > > > +#undef CONFIG_DM_PMIC
> > > > > > > +#undef CONFIG_DM_PMIC_PFUZE100
> > > > > >
> > > > > > Why do you need to undef those config options?
> > > > > >
> > > > > > > +
> > > > > > > +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> > > > > > > +
> > > > > > > +#endif
> > > > > > > +
> > > > > > > +#define CONFIG_REMAKE_ELF
> > > > > > > +
> > > > > > > +#define CONFIG_BOARD_EARLY_INIT_F
> > > > > > > +#define CONFIG_BOARD_POSTCLK_INIT
> > > > > > > +#define CONFIG_BOARD_LATE_INIT
> > > > > > > +
> > > > > > > +/* Flat Device Tree Definitions */
> > > > > > > +#define CONFIG_OF_BOARD_SETUP
> > > > > > > +
> > > > > > > +#undef CONFIG_CMD_EXPORTENV
> > > > > > > +#undef CONFIG_CMD_IMPORTENV
> > > > > > > +#undef CONFIG_CMD_IMLS
> > > > > > > +
> > > > > > > +#undef CONFIG_CMD_CRC32
> > > > > > > +#undef CONFIG_BOOTM_NETBSD
> > > > > >
> > > > > > There seems to be some issue with inheritance, as you need
> > > > > > to undef those values manually.
> > > > > >
> > > > > > Why is it needed?
> > > > > >
> > > > > > > +
> > > > > > > +/* ENET Config */
> > > > > > > +/* ENET1 */
> > > > > > > +#if defined(CONFIG_CMD_NET)
> > > > > > > +#define CONFIG_CMD_PING
> > > > > > > +#define CONFIG_CMD_DHCP
> > > > > > > +#define CONFIG_CMD_MII
> > > > > > > +#define CONFIG_MII
> > > > > > > +#define CONFIG_ETHPRIME "FEC"
> > > > > > > +
> > > > > > > +#define CONFIG_FEC_MXC
> > > > > > > +#define CONFIG_FEC_XCV_TYPE RGMII
> > > > > > > +#define CONFIG_FEC_MXC_PHYADDR 0
> > > > > > > +#define FEC_QUIRK_ENET_MAC
> > > > > > > +
> > > > > > > +#define CONFIG_PHY_GIGE
> > > > > > > +#define IMX_FEC_BASE 0x30BE0000
> > > > > > > +
> > > > > > > +#define CONFIG_PHYLIB
> > > > > > > +#define CONFIG_PHY_ATHEROS
> > > > > > > +#endif
> > > > > > > +
> > > > > > > +/* Initial environment variables */
> > > > > > > +#define CONFIG_EXTRA_ENV_SETTINGS \
> > > > > > > + "script=boot.scr\0" \
> > > > > > > + "image=Image\0" \
> > > > > > > + "console=ttymxc1,115200
> > > > > > > earlycon=ec_imx6q,0x30890000,115200\0" \
> > > > > > > + "fdt_addr=0x43000000\0" \
> > > > > > > + "fdt_high=0xffffffffffffffff\0" \
> > > > > > > + "boot_fdt=try\0" \
> > > > > > > + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
> > > > > > > + "initrd_addr=0x43800000\0" \
> > > > > > > + "initrd_high=0xffffffffffffffff\0" \
> > > > > > > + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0"
> > > > > > > \
> > > > > > > + "mmcpart="
> > > > > > > __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
> > > > > > > + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
> > > > > > > + "mmcautodetect=yes\0" \
> > > > > > > + "mmcargs=setenv bootargs ${jh_clk}
> > > > > > > console=${console} root=${mmcroot}\0 " \
> > > > > > > + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart}
> > > > > > > ${loadaddr} ${script};\0" \
> > > > > > > + "bootscript=echo Running bootscript from
> > > > > > > mmc ...; " \
> > > > > > > + "source\0" \
> > > > > > > + "loadimage=fatload mmc ${mmcdev}:${mmcpart}
> > > > > > > ${loadaddr} ${image}\0" \
> > > > > > > + "loadfdt=fatload mmc ${mmcdev}:${mmcpart}
> > > > > > > ${fdt_addr} ${fdt_file}\0" \
> > > > > > > + "mmcboot=echo Booting from mmc ...; " \
> > > > > > > + "run mmcargs; " \
> > > > > > > + "if test ${boot_fdt} = yes || test
> > > > > > > ${boot_fdt} = try; then " \
> > > > > > > + "if run loadfdt; then " \
> > > > > > > + "booti ${loadaddr} -
> > > > > > > ${fdt_addr}; " \
> > > > > > > + "else " \
> > > > > > > + "echo WARN: Cannot load
> > > > > > > the DT; " \
> > > > > > > + "fi; " \
> > > > > > > + "else " \
> > > > > > > + "echo wait for boot; " \
> > > > > > > + "fi;\0" \
> > > > > > > + "netargs=setenv bootargs ${jh_clk}
> > > > > > > console=${console} " \
> > > > > > > + "root=/dev/nfs " \
> > > > > > > + "ip=dhcp
> > > > > > > nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
> > > > > > > + "netboot=echo Booting from net ...; " \
> > > > > > > + "run netargs; " \
> > > > > > > + "if test ${ip_dyn} = yes; then " \
> > > > > > > + "setenv get_cmd dhcp; " \
> > > > > > > + "else " \
> > > > > > > + "setenv get_cmd tftp; " \
> > > > > > > + "fi; " \
> > > > > > > + "${get_cmd} ${loadaddr} ${image}; " \
> > > > > > > + "if test ${boot_fdt} = yes || test
> > > > > > > ${boot_fdt} = try; then " \
> > > > > > > + "if ${get_cmd} ${fdt_addr}
> > > > > > > ${fdt_file}; then " \
> > > > > > > + "booti ${loadaddr} -
> > > > > > > ${fdt_addr}; " \
> > > > > > > + "else " \
> > > > > > > + "echo WARN: Cannot load
> > > > > > > the DT; " \
> > > > > > > + "fi; " \
> > > > > > > + "else " \
> > > > > > > + "booti; " \
> > > > > > > + "fi;\0"
> > > > > > > +
> > > > > > > +#define CONFIG_BOOTCOMMAND \
> > > > > > > + "mmc dev ${mmcdev}; if mmc rescan; then " \
> > > > > > > + "if run loadbootscript; then " \
> > > > > > > + "run bootscript; " \
> > > > > > > + "else " \
> > > > > > > + "if run loadimage; then " \
> > > > > > > + "run mmcboot; " \
> > > > > > > + "else run netboot; " \
> > > > > > > + "fi; " \
> > > > > > > + "fi; " \
> > > > > > > + "else booti ${loadaddr} - ${fdt_addr}; fi"
> > > > > > > +
> > > > > > > +/* Link Definitions */
> > > > > > > +#define CONFIG_LOADADDR 0x40480000
> > > > > > > +
> > > > > > > +#define CONFIG_SYS_LOAD_ADDR
> > CONFIG_LOADADDR
> > > > > > > +
> > > > > > > +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
> > > > > > > +#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
> > > > > > > +#define CONFIG_SYS_INIT_SP_OFFSET \
> > > > > > > + (CONFIG_SYS_INIT_RAM_SIZE -
> > > > > > > GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR
> > > > > > > \
> > > > > > > + (CONFIG_SYS_INIT_RAM_ADDR +
> > > > > > > CONFIG_SYS_INIT_SP_OFFSET) +
> > > > > > > +#define CONFIG_ENV_OVERWRITE
> > > > > > > +#if defined(CONFIG_ENV_IS_IN_MMC)
> > > > > > > +#define CONFIG_ENV_OFFSET (64 * SZ_64K)
> > > > > > > +#endif
> > > > > > > +#define CONFIG_ENV_SIZE 0x1000
> > > > > > > +#define CONFIG_SYS_MMC_ENV_DEV 0 /*
> > > > > > > USDHC2 */ +#define
> > > > > > > CONFIG_MMCROOT "/dev/mmcblk1p2" /*
> > > > > > > USDHC2 */ + +/* Size of malloc() pool */
> > > > > > > +#define CONFIG_SYS_MALLOC_LEN SZ_32M
> > > > > > > +
> > > > > > > +#define CONFIG_SYS_SDRAM_BASE 0x40000000
> > > > > > > +#define PHYS_SDRAM 0x40000000
> > > > > > > +#define PHYS_SDRAM_SIZE
> > > > > > > 0x80000000 /* 2GB DDR */ +
> > > > > > > +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
> > > > > > > +#define CONFIG_SYS_MEMTEST_END
> > > > > > (CONFIG_SYS_MEMTEST_START +
> > > > > > > (PHYS_SDRAM_SIZE >> 1)) +
> > > > > > > +#define CONFIG_BAUDRATE 115200
> > > > > > > +
> > > > > > > +#define CONFIG_MXC_UART_BASE
> > > > > > > UART2_BASE_ADDR +
> > > > > > > +/* Monitor Command Prompt */
> > > > > > > +#undef CONFIG_SYS_PROMPT
> > > > > > > +#define CONFIG_SYS_PROMPT "u-boot=> "
> > > > > > > +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
> > > > > > > +#define CONFIG_SYS_CBSIZE 2048
> > > > > > > +#define CONFIG_SYS_MAXARGS 64
> > > > > > > +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
> > > > > > > +#define CONFIG_SYS_PBSIZE
> > > > > > > (CONFIG_SYS_CBSIZE
> > > > > > > + \ +
> > > > > > > sizeof(CONFIG_SYS_PROMPT) + 16) +
> > > > > > > +#define CONFIG_IMX_BOOTAUX
> > > > > > > +
> > > > > > > +/* USDHC */
> > > > > > > +#define CONFIG_CMD_MMC
> > > > > > > +#define CONFIG_FSL_ESDHC
> > > > > > > +#define CONFIG_FSL_USDHC
> > > > > > > +
> > > > > > > +#define CONFIG_SYS_FSL_USDHC_NUM 2
> > > > > > > +#define CONFIG_SYS_FSL_ESDHC_ADDR 0
> > > > > > > +
> > > > > > > +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific
> > > > > > > */ +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
> > > > > > > +
> > > > > > > +#define CONFIG_MXC_OCOTP
> > > > > > > +#define CONFIG_CMD_FUSE
> > > > > > > +
> > > > > > > +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable
> > > > > > > I2C bus 1 */ +#define
> > > > > > > CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus
> > > > > > > 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /*
> > > > > > > enable I2C bus 3 */ +#define CONFIG_SYS_I2C_SPEED 100000
> > > > > >
> > > > > > Some of those values are (SYS_I2C_*, MXC_OCOTP, FSL_*) are
> > > > > > already supported by Kconfig. Please use Kconfig instead.
> > > > > >
> > > > > > > +
> > > > > > > +#define CONFIG_OF_SYSTEM_SETUP
> > > > > > > +
> > > > > > > +#endif
> > > > > >
> > > > > >
> > > > > > Best regards,
> > > > > >
> > > > > > Lukasz Majewski
> > > > > >
> > > > > > --
> > > > > >
> > > > > > DENX Software Engineering GmbH, Managing Director:
> > Wolfgang
> > > > > > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194
> > > > > > Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax:
> > > > > > (+49)-8142-66989-80 Email: lukma at denx.de
> > > >
> > > >
> > > >
> > > >
> > > > Best regards,
> > > >
> > > > Lukasz Majewski
> > > >
> > > > --
> > > >
> > > > DENX Software Engineering GmbH, Managing Director: Wolfgang
> > > > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194
> > > > Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax:
> > > > (+49)-8142-66989-80 Email: lukma at denx.de
> >
> >
> >
> >
> > Best regards,
> >
> > Lukasz Majewski
> >
> > --
> >
> > DENX Software Engineering GmbH, Managing Director: Wolfgang
> > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell,
> > Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> > lukma at denx.de
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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