* [U-Boot] [PATCH v2 01/17] dm: Fix documentation entry as there is no UCLASS_CLOCK uclass
2019-01-31 9:03 [U-Boot] [PATCH v2 00/17] imx: dm: Update mccmon6 board to only use DM/DTS in u-boot proper Lukasz Majewski
@ 2019-01-31 9:03 ` Lukasz Majewski
2019-01-31 10:04 ` Simon Glass
2019-01-31 9:03 ` [U-Boot] [PATCH v2 02/17] cmd: Do not show frequency for clocks which .get_rate() return error Lukasz Majewski
` (15 subsequent siblings)
16 siblings, 1 reply; 24+ messages in thread
From: Lukasz Majewski @ 2019-01-31 9:03 UTC (permalink / raw)
To: u-boot
There is no UCLASS_CLOCK uclass defined. Instead we do use the UCLASS_CLK.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
---
Changes in v2: None
include/clk.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/clk.h b/include/clk.h
index 8e366163f9..f6fbcc6634 100644
--- a/include/clk.h
+++ b/include/clk.h
@@ -19,7 +19,7 @@
* clock provider. This API provides a standard means for drivers to enable and
* disable clocks, and to set the rate at which they oscillate.
*
- * A driver that implements UCLASS_CLOCK is a clock provider. A provider will
+ * A driver that implements UCLASS_CLK is a clock provider. A provider will
* often implement multiple separate clocks, since the hardware it manages
* often has this capability. clk-uclass.h describes the interface which
* clock providers must implement.
--
2.11.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [U-Boot] [PATCH v2 02/17] cmd: Do not show frequency for clocks which .get_rate() return error
2019-01-31 9:03 [U-Boot] [PATCH v2 00/17] imx: dm: Update mccmon6 board to only use DM/DTS in u-boot proper Lukasz Majewski
2019-01-31 9:03 ` [U-Boot] [PATCH v2 01/17] dm: Fix documentation entry as there is no UCLASS_CLOCK uclass Lukasz Majewski
@ 2019-01-31 9:03 ` Lukasz Majewski
2019-01-31 10:04 ` Simon Glass
2019-01-31 9:03 ` [U-Boot] [PATCH v2 03/17] dm: clk: Define clk_get_parent_rate() for clk operations Lukasz Majewski
` (14 subsequent siblings)
16 siblings, 1 reply; 24+ messages in thread
From: Lukasz Majewski @ 2019-01-31 9:03 UTC (permalink / raw)
To: u-boot
It may happen that some UCLASS_CLK clocks drivers work as a "managers",
to call other, proper clocks. This situation is present in the iMX{6|8}
clocks when supporting CONFIG_CLK (and CCF).
To avoid bogus output of "clk dump" we omit clocks which return error
value - allowing reusing default implementation of this command.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
---
Changes in v2: None
cmd/clk.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/cmd/clk.c b/cmd/clk.c
index fd4231589c..2ea82176aa 100644
--- a/cmd/clk.c
+++ b/cmd/clk.c
@@ -16,6 +16,7 @@ int __weak soc_clk_dump(void)
struct udevice *dev;
struct uclass *uc;
struct clk clk;
+ ulong rate;
int ret;
/* Device addresses start at 1 */
@@ -37,7 +38,9 @@ int __weak soc_clk_dump(void)
continue;
}
- printf("%-30.30s : %lu Hz\n", dev->name, clk_get_rate(&clk));
+ rate = clk_get_rate(&clk);
+ if (!IS_ERR_VALUE(rate))
+ printf("%-30.30s : %lu Hz\n", dev->name, rate);
clk_free(&clk);
}
--
2.11.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [U-Boot] [PATCH v2 02/17] cmd: Do not show frequency for clocks which .get_rate() return error
2019-01-31 9:03 ` [U-Boot] [PATCH v2 02/17] cmd: Do not show frequency for clocks which .get_rate() return error Lukasz Majewski
@ 2019-01-31 10:04 ` Simon Glass
0 siblings, 0 replies; 24+ messages in thread
From: Simon Glass @ 2019-01-31 10:04 UTC (permalink / raw)
To: u-boot
+Stephen
On Thu, 31 Jan 2019 at 02:04, Lukasz Majewski <lukma@denx.de> wrote:
>
> It may happen that some UCLASS_CLK clocks drivers work as a "managers",
> to call other, proper clocks. This situation is present in the iMX{6|8}
> clocks when supporting CONFIG_CLK (and CCF).
>
> To avoid bogus output of "clk dump" we omit clocks which return error
> value - allowing reusing default implementation of this command.
>
> Signed-off-by: Lukasz Majewski <lukma@denx.de>
> ---
>
> Changes in v2: None
>
> cmd/clk.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 24+ messages in thread
* [U-Boot] [PATCH v2 03/17] dm: clk: Define clk_get_parent_rate() for clk operations
2019-01-31 9:03 [U-Boot] [PATCH v2 00/17] imx: dm: Update mccmon6 board to only use DM/DTS in u-boot proper Lukasz Majewski
2019-01-31 9:03 ` [U-Boot] [PATCH v2 01/17] dm: Fix documentation entry as there is no UCLASS_CLOCK uclass Lukasz Majewski
2019-01-31 9:03 ` [U-Boot] [PATCH v2 02/17] cmd: Do not show frequency for clocks which .get_rate() return error Lukasz Majewski
@ 2019-01-31 9:03 ` Lukasz Majewski
2019-01-31 10:05 ` Simon Glass
2019-01-31 9:03 ` [U-Boot] [PATCH v2 04/17] dm: clk: Define clk_get_by_id() " Lukasz Majewski
` (13 subsequent siblings)
16 siblings, 1 reply; 24+ messages in thread
From: Lukasz Majewski @ 2019-01-31 9:03 UTC (permalink / raw)
To: u-boot
This commit adds the clk_get_parent_rate() function, which is responsible
for getting the rate of parent clock.
Unfortunately, u-boot's DM support for getting parent is different
(the parent relationship is in udevice) than the one in common clock
framework (CCF) in Linux.
To alleviate this problem - the clk_get_parent_rate() function has been
introduced to clk-uclass.c.
As written in the in-code comment - some clocks do not set clk->id (and
require it to be set to 0) and hence the standard ckl_{request|get_rate|
free} API is used.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
---
Changes in v2: None
drivers/clk/clk-uclass.c | 41 +++++++++++++++++++++++++++++++++++++++++
include/clk.h | 9 +++++++++
2 files changed, 50 insertions(+)
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index 6d7a514006..f1640dda67 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -340,6 +340,47 @@ ulong clk_get_rate(struct clk *clk)
return ops->get_rate(clk);
}
+ulong clk_get_parent_rate(struct clk *clk)
+{
+ const struct clk_ops *ops;
+ struct udevice *pdev;
+ struct clk pclk;
+ ulong rate;
+ int ret;
+
+ debug("%s(clk=%p)\n", __func__, clk);
+
+ pdev = clk->dev->parent;
+ if (!pdev)
+ return -ENODEV;
+
+ ops = clk_dev_ops(pdev);
+ if (!ops->get_rate)
+ return -ENOSYS;
+
+ /*
+ * We do use memset, clk_{request|get_rate|free}
+ * as there are clocks - like the "fixed" ones, which
+ * doesn't posses the clk wrapper struct (just added to
+ * UCLASS_CLK) and explicitly check if clk->id = 0.
+ *
+ * In fact the "clock" resources (like ops, description)
+ * are accessed via udevice structure (pdev - parent's one)
+ */
+
+ memset(&pclk, 0, sizeof(pclk));
+ ret = clk_request(pdev, &pclk);
+ if (ret) {
+ printf("%s: pclk: %s request failed!\n", __func__, pdev->name);
+ return ret;
+ }
+
+ rate = clk_get_rate(&pclk);
+ clk_free(&pclk);
+
+ return rate;
+}
+
ulong clk_set_rate(struct clk *clk, ulong rate)
{
const struct clk_ops *ops = clk_dev_ops(clk->dev);
diff --git a/include/clk.h b/include/clk.h
index f6fbcc6634..8224295ec3 100644
--- a/include/clk.h
+++ b/include/clk.h
@@ -238,6 +238,15 @@ int clk_free(struct clk *clk);
ulong clk_get_rate(struct clk *clk);
/**
+ * clk_get_parent_rate() - Get parent of current clock rate.
+ *
+ * @clk: A clock struct that was previously successfully requested by
+ * clk_request/get_by_*().
+ * @return clock rate in Hz, or -ve error code.
+ */
+ulong clk_get_parent_rate(struct clk *clk);
+
+/**
* clk_set_rate() - Set current clock rate.
*
* @clk: A clock struct that was previously successfully requested by
--
2.11.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [U-Boot] [PATCH v2 03/17] dm: clk: Define clk_get_parent_rate() for clk operations
2019-01-31 9:03 ` [U-Boot] [PATCH v2 03/17] dm: clk: Define clk_get_parent_rate() for clk operations Lukasz Majewski
@ 2019-01-31 10:05 ` Simon Glass
2019-01-31 11:14 ` Lukasz Majewski
0 siblings, 1 reply; 24+ messages in thread
From: Simon Glass @ 2019-01-31 10:05 UTC (permalink / raw)
To: u-boot
+Stephen
Hi Lukasz,
On Thu, 31 Jan 2019 at 02:04, Lukasz Majewski <lukma@denx.de> wrote:
>
> This commit adds the clk_get_parent_rate() function, which is responsible
> for getting the rate of parent clock.
> Unfortunately, u-boot's DM support for getting parent is different
> (the parent relationship is in udevice) than the one in common clock
> framework (CCF) in Linux.
>
> To alleviate this problem - the clk_get_parent_rate() function has been
> introduced to clk-uclass.c.
>
> As written in the in-code comment - some clocks do not set clk->id (and
> require it to be set to 0) and hence the standard ckl_{request|get_rate|
> free} API is used.
>
> Signed-off-by: Lukasz Majewski <lukma@denx.de>
> ---
>
> Changes in v2: None
>
> drivers/clk/clk-uclass.c | 41 +++++++++++++++++++++++++++++++++++++++++
> include/clk.h | 9 +++++++++
> 2 files changed, 50 insertions(+)
Can we please call this from test/dm/clk.c?
>
> diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
> index 6d7a514006..f1640dda67 100644
> --- a/drivers/clk/clk-uclass.c
> +++ b/drivers/clk/clk-uclass.c
> @@ -340,6 +340,47 @@ ulong clk_get_rate(struct clk *clk)
> return ops->get_rate(clk);
> }
>
> +ulong clk_get_parent_rate(struct clk *clk)
> +{
> + const struct clk_ops *ops;
> + struct udevice *pdev;
> + struct clk pclk;
> + ulong rate;
> + int ret;
> +
> + debug("%s(clk=%p)\n", __func__, clk);
> +
> + pdev = clk->dev->parent;
dev_get_parent(clk->dev)
> + if (!pdev)
> + return -ENODEV;
Not needed, all devices have parents except the root, which is not in UCLASS_CLK
> +
> + ops = clk_dev_ops(pdev);
> + if (!ops->get_rate)
> + return -ENOSYS;
> +
> + /*
> + * We do use memset, clk_{request|get_rate|free}
> + * as there are clocks - like the "fixed" ones, which
> + * doesn't posses the clk wrapper struct (just added to
> + * UCLASS_CLK) and explicitly check if clk->id = 0.
> + *
> + * In fact the "clock" resources (like ops, description)
> + * are accessed via udevice structure (pdev - parent's one)
> + */
> +
drop blank line. Also is that comment wrapped to use the full number of columns?
Also, this seems like a bug that should be fixed?
> + memset(&pclk, 0, sizeof(pclk));
> + ret = clk_request(pdev, &pclk);
> + if (ret) {
> + printf("%s: pclk: %s request failed!\n", __func__, pdev->name);
> + return ret;
> + }
> +
> + rate = clk_get_rate(&pclk);
> + clk_free(&pclk);
> +
> + return rate;
> +}
> +
> ulong clk_set_rate(struct clk *clk, ulong rate)
> {
> const struct clk_ops *ops = clk_dev_ops(clk->dev);
> diff --git a/include/clk.h b/include/clk.h
> index f6fbcc6634..8224295ec3 100644
> --- a/include/clk.h
> +++ b/include/clk.h
> @@ -238,6 +238,15 @@ int clk_free(struct clk *clk);
> ulong clk_get_rate(struct clk *clk);
>
> /**
> + * clk_get_parent_rate() - Get parent of current clock rate.
> + *
> + * @clk: A clock struct that was previously successfully requested by
> + * clk_request/get_by_*().
> + * @return clock rate in Hz, or -ve error code.
> + */
> +ulong clk_get_parent_rate(struct clk *clk);
> +
> +/**
> * clk_set_rate() - Set current clock rate.
> *
> * @clk: A clock struct that was previously successfully requested by
> --
> 2.11.0
>
Regards,
Simon
^ permalink raw reply [flat|nested] 24+ messages in thread* [U-Boot] [PATCH v2 03/17] dm: clk: Define clk_get_parent_rate() for clk operations
2019-01-31 10:05 ` Simon Glass
@ 2019-01-31 11:14 ` Lukasz Majewski
0 siblings, 0 replies; 24+ messages in thread
From: Lukasz Majewski @ 2019-01-31 11:14 UTC (permalink / raw)
To: u-boot
Hi Simon,
> +Stephen
>
> Hi Lukasz,
>
> On Thu, 31 Jan 2019 at 02:04, Lukasz Majewski <lukma@denx.de> wrote:
> >
> > This commit adds the clk_get_parent_rate() function, which is
> > responsible for getting the rate of parent clock.
> > Unfortunately, u-boot's DM support for getting parent is different
> > (the parent relationship is in udevice) than the one in common clock
> > framework (CCF) in Linux.
> >
> > To alleviate this problem - the clk_get_parent_rate() function has
> > been introduced to clk-uclass.c.
> >
> > As written in the in-code comment - some clocks do not set clk->id
> > (and require it to be set to 0) and hence the standard
> > ckl_{request|get_rate| free} API is used.
> >
> > Signed-off-by: Lukasz Majewski <lukma@denx.de>
> > ---
> >
> > Changes in v2: None
> >
> > drivers/clk/clk-uclass.c | 41
> > +++++++++++++++++++++++++++++++++++++++++ include/clk.h
> > | 9 +++++++++ 2 files changed, 50 insertions(+)
>
> Can we please call this from test/dm/clk.c?
Ok.
>
> >
> > diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
> > index 6d7a514006..f1640dda67 100644
> > --- a/drivers/clk/clk-uclass.c
> > +++ b/drivers/clk/clk-uclass.c
> > @@ -340,6 +340,47 @@ ulong clk_get_rate(struct clk *clk)
> > return ops->get_rate(clk);
> > }
> >
> > +ulong clk_get_parent_rate(struct clk *clk)
> > +{
> > + const struct clk_ops *ops;
> > + struct udevice *pdev;
> > + struct clk pclk;
> > + ulong rate;
> > + int ret;
> > +
> > + debug("%s(clk=%p)\n", __func__, clk);
> > +
> > + pdev = clk->dev->parent;
>
> dev_get_parent(clk->dev)
Yes, correct.
>
> > + if (!pdev)
> > + return -ENODEV;
>
> Not needed, all devices have parents except the root, which is not in
> UCLASS_CLK
Ok.
>
> > +
> > + ops = clk_dev_ops(pdev);
> > + if (!ops->get_rate)
> > + return -ENOSYS;
> > +
> > + /*
> > + * We do use memset, clk_{request|get_rate|free}
> > + * as there are clocks - like the "fixed" ones, which
> > + * doesn't posses the clk wrapper struct (just added to
> > + * UCLASS_CLK) and explicitly check if clk->id = 0.
> > + *
> > + * In fact the "clock" resources (like ops, description)
> > + * are accessed via udevice structure (pdev - parent's one)
> > + */
> > +
>
> drop blank line. Also is that comment wrapped to use the full number
> of columns?
I will refactor the comment.
>
> Also, this seems like a bug that should be fixed?
Yes, this seems strange to me:
The main structure passed in the clock API in U-boot is struct clk *clk
pointer.
However, the fixed clocks (clk_fixed_rate.c) require the clk->id to be
set to 0. This is strange as imposes in practice passing new, memset'ed
to 0 clk structure pointer. Moreover, they doesn't have corresponding
struct clk definition and exists only linked in UCLASS_CLK.
The pattern to get clock rate:
memset(clk, 0, sizeof(clk);
clk_request(pdev, clk) --> clk->dev = pdev [*]; (this is _the_ defacto
clock assignment)
clk_get_rate(clk)
clk_free(clk)
is also used in socfpga [1] and 'clk dump' command and IMHO is wrong
(but I cannot understand why it was done in that way - we _shall_ pass
pointer to struct clk, not rely on udevices - like in [*]).
Such approach causes the passed clk pointer to be useless as it is NULL
when we call clk_get_rate() recursively.
And for this reason the struct clk *clk pointer is stored in
driver_data for udevice.
[1] - arch/arm/mach-socfpga/clock_manager_arria10.c
>
> > + memset(&pclk, 0, sizeof(pclk));
> > + ret = clk_request(pdev, &pclk);
> > + if (ret) {
> > + printf("%s: pclk: %s request failed!\n", __func__,
> > pdev->name);
> > + return ret;
> > + }
> > +
> > + rate = clk_get_rate(&pclk);
> > + clk_free(&pclk);
> > +
> > + return rate;
> > +}
> > +
> > ulong clk_set_rate(struct clk *clk, ulong rate)
> > {
> > const struct clk_ops *ops = clk_dev_ops(clk->dev);
> > diff --git a/include/clk.h b/include/clk.h
> > index f6fbcc6634..8224295ec3 100644
> > --- a/include/clk.h
> > +++ b/include/clk.h
> > @@ -238,6 +238,15 @@ int clk_free(struct clk *clk);
> > ulong clk_get_rate(struct clk *clk);
> >
> > /**
> > + * clk_get_parent_rate() - Get parent of current clock rate.
> > + *
> > + * @clk: A clock struct that was previously successfully
> > requested by
> > + * clk_request/get_by_*().
> > + * @return clock rate in Hz, or -ve error code.
> > + */
> > +ulong clk_get_parent_rate(struct clk *clk);
> > +
> > +/**
> > * clk_set_rate() - Set current clock rate.
> > *
> > * @clk: A clock struct that was previously successfully
> > requested by --
> > 2.11.0
> >
>
> Regards,
> Simon
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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^ permalink raw reply [flat|nested] 24+ messages in thread
* [U-Boot] [PATCH v2 04/17] dm: clk: Define clk_get_by_id() for clk operations
2019-01-31 9:03 [U-Boot] [PATCH v2 00/17] imx: dm: Update mccmon6 board to only use DM/DTS in u-boot proper Lukasz Majewski
` (2 preceding siblings ...)
2019-01-31 9:03 ` [U-Boot] [PATCH v2 03/17] dm: clk: Define clk_get_parent_rate() for clk operations Lukasz Majewski
@ 2019-01-31 9:03 ` Lukasz Majewski
2019-01-31 10:05 ` Simon Glass
2019-01-31 9:03 ` [U-Boot] [PATCH v2 05/17] clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: 5.0-rc3) Lukasz Majewski
` (12 subsequent siblings)
16 siblings, 1 reply; 24+ messages in thread
From: Lukasz Majewski @ 2019-01-31 9:03 UTC (permalink / raw)
To: u-boot
This commit adds the clk_get_by_id() function, which is responsible
for getting the udevice with matching clk->id. Such approach allows
re-usage of inherit DM list relationship for the same class (UCLASS_CLK).
As a result - we don't need any other external list - it is just enough
to look for UCLASS_CLK related udevices.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
---
Changes in v2: None
drivers/clk/clk-uclass.c | 22 ++++++++++++++++++++++
include/clk.h | 11 +++++++++++
2 files changed, 33 insertions(+)
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index f1640dda67..12ec0baa74 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -455,6 +455,28 @@ int clk_disable_bulk(struct clk_bulk *bulk)
return 0;
}
+int clk_get_by_id(ulong id, struct clk **c)
+{
+ struct udevice *dev;
+ struct uclass *uc;
+ int ret;
+
+ ret = uclass_get(UCLASS_CLK, &uc);
+ if (ret)
+ return ret;
+
+ uclass_foreach_dev(dev, uc) {
+ struct clk *clk = (struct clk *)dev_get_driver_data(dev);
+
+ if (clk->id == id) {
+ *c = clk;
+ return 0;
+ }
+ }
+
+ return -ENODEV;
+}
+
UCLASS_DRIVER(clk) = {
.id = UCLASS_CLK,
.name = "clk",
diff --git a/include/clk.h b/include/clk.h
index 8224295ec3..045e60357d 100644
--- a/include/clk.h
+++ b/include/clk.h
@@ -315,4 +315,15 @@ static inline bool clk_valid(struct clk *clk)
{
return !!clk->dev;
}
+
+/**
+ * clk_get_by_id() - Get the clock by knowing its ID
+ *
+ * @id: The clock ID to search for
+ *
+ * @c: A pointer to clock struct that has been found among added clocks
+ * to UCLASS_CLK
+ * @return zero on success, or -ve error code.
+ */
+int clk_get_by_id(ulong id, struct clk **c);
#endif
--
2.11.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [U-Boot] [PATCH v2 04/17] dm: clk: Define clk_get_by_id() for clk operations
2019-01-31 9:03 ` [U-Boot] [PATCH v2 04/17] dm: clk: Define clk_get_by_id() " Lukasz Majewski
@ 2019-01-31 10:05 ` Simon Glass
2019-01-31 10:51 ` Lukasz Majewski
0 siblings, 1 reply; 24+ messages in thread
From: Simon Glass @ 2019-01-31 10:05 UTC (permalink / raw)
To: u-boot
On Thu, 31 Jan 2019 at 02:04, Lukasz Majewski <lukma@denx.de> wrote:
>
> This commit adds the clk_get_by_id() function, which is responsible
> for getting the udevice with matching clk->id. Such approach allows
> re-usage of inherit DM list relationship for the same class (UCLASS_CLK).
> As a result - we don't need any other external list - it is just enough
> to look for UCLASS_CLK related udevices.
>
> Signed-off-by: Lukasz Majewski <lukma@denx.de>
> ---
>
> Changes in v2: None
>
> drivers/clk/clk-uclass.c | 22 ++++++++++++++++++++++
> include/clk.h | 11 +++++++++++
> 2 files changed, 33 insertions(+)
>
Please add a test that calls this.
> diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
> index f1640dda67..12ec0baa74 100644
> --- a/drivers/clk/clk-uclass.c
> +++ b/drivers/clk/clk-uclass.c
> @@ -455,6 +455,28 @@ int clk_disable_bulk(struct clk_bulk *bulk)
> return 0;
> }
>
> +int clk_get_by_id(ulong id, struct clk **c)
Can you use clkp instead of c?
> +{
> + struct udevice *dev;
> + struct uclass *uc;
> + int ret;
> +
> + ret = uclass_get(UCLASS_CLK, &uc);
> + if (ret)
> + return ret;
> +
> + uclass_foreach_dev(dev, uc) {
> + struct clk *clk = (struct clk *)dev_get_driver_data(dev);
> +
> + if (clk->id == id) {
> + *c = clk;
> + return 0;
> + }
> + }
> +
> + return -ENODEV;
I wonder if -ENOENT would be better?
> +}
> +
> UCLASS_DRIVER(clk) = {
> .id = UCLASS_CLK,
> .name = "clk",
> diff --git a/include/clk.h b/include/clk.h
> index 8224295ec3..045e60357d 100644
> --- a/include/clk.h
> +++ b/include/clk.h
> @@ -315,4 +315,15 @@ static inline bool clk_valid(struct clk *clk)
> {
> return !!clk->dev;
> }
> +
> +/**
> + * clk_get_by_id() - Get the clock by knowing its ID
> + *
> + * @id: The clock ID to search for
> + *
> + * @c: A pointer to clock struct that has been found among added clocks
> + * to UCLASS_CLK
> + * @return zero on success, or -ve error code.
-NOENT on error? I think you can be specific here
> + */
> +int clk_get_by_id(ulong id, struct clk **c);
> #endif
> --
> 2.11.0
>
Regards,
Simon
^ permalink raw reply [flat|nested] 24+ messages in thread* [U-Boot] [PATCH v2 04/17] dm: clk: Define clk_get_by_id() for clk operations
2019-01-31 10:05 ` Simon Glass
@ 2019-01-31 10:51 ` Lukasz Majewski
0 siblings, 0 replies; 24+ messages in thread
From: Lukasz Majewski @ 2019-01-31 10:51 UTC (permalink / raw)
To: u-boot
Hi Simon,
> On Thu, 31 Jan 2019 at 02:04, Lukasz Majewski <lukma@denx.de> wrote:
> >
> > This commit adds the clk_get_by_id() function, which is responsible
> > for getting the udevice with matching clk->id. Such approach allows
> > re-usage of inherit DM list relationship for the same class
> > (UCLASS_CLK). As a result - we don't need any other external list -
> > it is just enough to look for UCLASS_CLK related udevices.
> >
> > Signed-off-by: Lukasz Majewski <lukma@denx.de>
> > ---
> >
> > Changes in v2: None
> >
> > drivers/clk/clk-uclass.c | 22 ++++++++++++++++++++++
> > include/clk.h | 11 +++++++++++
> > 2 files changed, 33 insertions(+)
> >
>
> Please add a test that calls this.
Ok.
>
> > diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
> > index f1640dda67..12ec0baa74 100644
> > --- a/drivers/clk/clk-uclass.c
> > +++ b/drivers/clk/clk-uclass.c
> > @@ -455,6 +455,28 @@ int clk_disable_bulk(struct clk_bulk *bulk)
> > return 0;
> > }
> >
> > +int clk_get_by_id(ulong id, struct clk **c)
>
> Can you use clkp instead of c?
Ok.
>
> > +{
> > + struct udevice *dev;
> > + struct uclass *uc;
> > + int ret;
> > +
> > + ret = uclass_get(UCLASS_CLK, &uc);
> > + if (ret)
> > + return ret;
> > +
> > + uclass_foreach_dev(dev, uc) {
> > + struct clk *clk = (struct clk
> > *)dev_get_driver_data(dev); +
> > + if (clk->id == id) {
> > + *c = clk;
> > + return 0;
> > + }
> > + }
> > +
> > + return -ENODEV;
>
> I wonder if -ENOENT would be better?
Yes, it would better describe the situation.
>
> > +}
> > +
> > UCLASS_DRIVER(clk) = {
> > .id = UCLASS_CLK,
> > .name = "clk",
> > diff --git a/include/clk.h b/include/clk.h
> > index 8224295ec3..045e60357d 100644
> > --- a/include/clk.h
> > +++ b/include/clk.h
> > @@ -315,4 +315,15 @@ static inline bool clk_valid(struct clk *clk)
> > {
> > return !!clk->dev;
> > }
> > +
> > +/**
> > + * clk_get_by_id() - Get the clock by knowing its ID
> > + *
> > + * @id: The clock ID to search for
> > + *
> > + * @c: A pointer to clock struct that has been found among added
> > clocks
> > + * to UCLASS_CLK
> > + * @return zero on success, or -ve error code.
>
> -NOENT on error? I think you can be specific here
Ok.
>
> > + */
> > +int clk_get_by_id(ulong id, struct clk **c);
> > #endif
> > --
> > 2.11.0
> >
>
> Regards,
> Simon
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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^ permalink raw reply [flat|nested] 24+ messages in thread
* [U-Boot] [PATCH v2 05/17] clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: 5.0-rc3)
2019-01-31 9:03 [U-Boot] [PATCH v2 00/17] imx: dm: Update mccmon6 board to only use DM/DTS in u-boot proper Lukasz Majewski
` (3 preceding siblings ...)
2019-01-31 9:03 ` [U-Boot] [PATCH v2 04/17] dm: clk: Define clk_get_by_id() " Lukasz Majewski
@ 2019-01-31 9:03 ` Lukasz Majewski
2019-01-31 9:03 ` [U-Boot] [PATCH v2 06/17] ARM: imx: cosmetic: Remove not needed comment from the mccmon6.h file Lukasz Majewski
` (11 subsequent siblings)
16 siblings, 0 replies; 24+ messages in thread
From: Lukasz Majewski @ 2019-01-31 9:03 UTC (permalink / raw)
To: u-boot
This commit brings the files from Linux kernel to provide clocks support
as it is used on the Linux kernel with common clock framework [CCF] setup.
The directory structure has been preserved. The ported code only supports
reading information from PLL, MUX, Divider, etc and enabling/disabling
the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic
to the alias numbering as the information about the clock is read from
device tree.
One needs to pay attention to the comments indicating necessary for U-boot's
DM changes.
If needed the code can be extended to support the "set" part of the clock
management.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
---
Changes in v2: None
Design decisions/issues:
- U-boot's DM for clk differs from Linux CCF. The most notably difference
is the lack of support for hierarchical clocks and "clock as a manager
driver" (single clock DTS node acts as a starting point for all other
clocks).
- The "central" structure of this patch series is struct udevice and its
driver_data field contains the struct clk pointer (to the originally created
one).
- Clocks access (rate reading) is by following API: clk_request(..,clk),
clk_get_rate(clk), clk_free(clk).
Now U-boot only relies on udevice's dev pointer in struct clk and passes
cleared clk (memset(clk,0,sizeof(clk)). This is necessary for e.g.
clk_fixed_rate.c clocks (and checked explicitly).
- The clk_get_rate() is recursive now (we go up till "osc" clock). This
could be improved if necessary
- On purpose the "manager" clk driver (clk-imx6q.c) is not using large
table to store pointers to clocks - e.g. clk[IMX6QDL_CLK_USDHC2_SEL] = ....
Instead we use udevice's linked list for the same class (UCLASS_CLK).
The rationale - when porting the code as is from Linux, one would need
~1KiB of RAM to store it. This is way too much if we do plan to use this
driver in SPL.
---
drivers/clk/Kconfig | 7 ++
drivers/clk/Makefile | 2 +
drivers/clk/clk-divider.c | 148 ++++++++++++++++++++++++++++++++++
drivers/clk/clk-fixed-factor.c | 87 ++++++++++++++++++++
drivers/clk/clk-mux.c | 164 +++++++++++++++++++++++++++++++++++++
drivers/clk/clk.c | 56 +++++++++++++
drivers/clk/imx/Kconfig | 8 ++
drivers/clk/imx/Makefile | 2 +
drivers/clk/imx/clk-gate2.c | 113 ++++++++++++++++++++++++++
drivers/clk/imx/clk-imx6q.c | 179 +++++++++++++++++++++++++++++++++++++++++
drivers/clk/imx/clk-pfd.c | 91 +++++++++++++++++++++
drivers/clk/imx/clk-pllv3.c | 83 +++++++++++++++++++
drivers/clk/imx/clk.h | 75 +++++++++++++++++
include/linux/clk-provider.h | 94 ++++++++++++++++++++++
14 files changed, 1109 insertions(+)
create mode 100644 drivers/clk/clk-divider.c
create mode 100644 drivers/clk/clk-fixed-factor.c
create mode 100644 drivers/clk/clk-mux.c
create mode 100644 drivers/clk/clk.c
create mode 100644 drivers/clk/imx/clk-gate2.c
create mode 100644 drivers/clk/imx/clk-imx6q.c
create mode 100644 drivers/clk/imx/clk-pfd.c
create mode 100644 drivers/clk/imx/clk-pllv3.c
create mode 100644 drivers/clk/imx/clk.h
create mode 100644 include/linux/clk-provider.h
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 51c931b906..d37c0e86b5 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -46,6 +46,13 @@ config CLK_BOSTON
help
Enable this to support the clocks
+config CLK_CCF
+ bool "Common Clock Framework [CCF] support "
+ depends on CLK
+ help
+ Enable this option if you want to (re-)use the Linux kernel's Common
+ Clock Framework [CCF] code in U-Boot's clock driver.
+
config CLK_STM32F
bool "Enable clock driver support for STM32F family"
depends on CLK && (STM32F7 || STM32F4)
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 6a4ff9143b..d426414ca6 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -5,6 +5,8 @@
#
obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o clk_fixed_rate.o
+obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk-fixed-factor.o clk.o clk-divider.o \
+ clk-mux.o
obj-y += imx/
obj-y += tegra/
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
new file mode 100644
index 0000000000..fa013dd9db
--- /dev/null
+++ b/drivers/clk/clk-divider.c
@@ -0,0 +1,148 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 DENX Software Engineering
+ * Lukasz Majewski, DENX Software Engineering, lukma at denx.de
+ *
+ * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
+ * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
+ * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <clk-uclass.h>
+#include <dm/device.h>
+#include <dm/uclass.h>
+#include <dm/lists.h>
+#include <dm/device-internal.h>
+#include <linux/clk-provider.h>
+#include <div64.h>
+#include <clk.h>
+#include "clk.h"
+
+#define UBOOT_DM_CLK_IMX_DIVIDER "imx_clk_divider"
+
+static unsigned int _get_table_div(const struct clk_div_table *table,
+ unsigned int val)
+{
+ const struct clk_div_table *clkt;
+
+ for (clkt = table; clkt->div; clkt++)
+ if (clkt->val == val)
+ return clkt->div;
+ return 0;
+}
+
+static unsigned int _get_div(const struct clk_div_table *table,
+ unsigned int val, unsigned long flags, u8 width)
+{
+ if (flags & CLK_DIVIDER_ONE_BASED)
+ return val;
+ if (flags & CLK_DIVIDER_POWER_OF_TWO)
+ return 1 << val;
+ if (flags & CLK_DIVIDER_MAX_AT_ZERO)
+ return val ? val : clk_div_mask(width) + 1;
+ if (table)
+ return _get_table_div(table, val);
+ return val + 1;
+}
+
+unsigned long divider_recalc_rate(struct clk *hw, unsigned long parent_rate,
+ unsigned int val,
+ const struct clk_div_table *table,
+ unsigned long flags, unsigned long width)
+{
+ unsigned int div;
+
+ div = _get_div(table, val, flags, width);
+ if (!div) {
+ WARN(!(flags & CLK_DIVIDER_ALLOW_ZERO),
+ "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
+ clk_hw_get_name(hw));
+ return parent_rate;
+ }
+
+ return DIV_ROUND_UP_ULL((u64)parent_rate, div);
+}
+
+static ulong clk_divider_recalc_rate(struct clk *clk)
+{
+ struct clk_divider *divider =
+ (struct clk_divider *)dev_get_driver_data(clk->dev);
+ unsigned long parent_rate = clk_get_parent_rate(clk);
+ unsigned int val;
+
+ val = readl(divider->reg) >> divider->shift;
+ val &= clk_div_mask(divider->width);
+
+ return divider_recalc_rate(clk, parent_rate, val, divider->table,
+ divider->flags, divider->width);
+}
+
+const struct clk_ops clk_divider_ops = {
+ .get_rate = clk_divider_recalc_rate,
+};
+
+static struct clk *_register_divider(struct device *dev, const char *name,
+ const char *parent_name, unsigned long flags,
+ void __iomem *reg, u8 shift, u8 width,
+ u8 clk_divider_flags, const struct clk_div_table *table)
+{
+ struct clk_divider *div;
+ struct clk *clk;
+ int ret;
+
+ if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
+ if (width + shift > 16) {
+ pr_warn("divider value exceeds LOWORD field\n");
+ return ERR_PTR(-EINVAL);
+ }
+ }
+
+ /* allocate the divider */
+ div = kzalloc(sizeof(*div), GFP_KERNEL);
+ if (!div)
+ return ERR_PTR(-ENOMEM);
+
+ /* struct clk_divider assignments */
+ div->reg = reg;
+ div->shift = shift;
+ div->width = width;
+ div->flags = clk_divider_flags;
+ div->table = table;
+
+ /* register the clock */
+ clk = &div->clk;
+
+ ret = clk_register(clk, UBOOT_DM_CLK_IMX_DIVIDER, (ulong)clk,
+ name, parent_name);
+ if (ret) {
+ kfree(div);
+ return ERR_PTR(ret);
+ }
+
+ return clk;
+}
+
+struct clk *clk_register_divider(struct device *dev, const char *name,
+ const char *parent_name, unsigned long flags,
+ void __iomem *reg, u8 shift, u8 width,
+ u8 clk_divider_flags)
+{
+ struct clk *clk;
+
+ clk = _register_divider(dev, name, parent_name, flags, reg, shift,
+ width, clk_divider_flags, NULL);
+ if (IS_ERR(clk))
+ return ERR_CAST(clk);
+ return clk;
+}
+
+U_BOOT_DRIVER(clk_divider) = {
+ .name = UBOOT_DM_CLK_IMX_DIVIDER,
+ .id = UCLASS_CLK,
+ .ops = &clk_divider_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c
new file mode 100644
index 0000000000..c21d773963
--- /dev/null
+++ b/drivers/clk/clk-fixed-factor.c
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 DENX Software Engineering
+ * Lukasz Majewski, DENX Software Engineering, lukma at denx.de
+ *
+ * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
+ */
+#include <common.h>
+#include <malloc.h>
+#include <clk-uclass.h>
+#include <dm/device.h>
+#include <linux/clk-provider.h>
+#include <div64.h>
+#include <clk.h>
+#include "clk.h"
+
+#define UBOOT_DM_CLK_IMX_FIXED_FACTOR "imx_clk_fixed_factor"
+
+static ulong clk_factor_recalc_rate(struct clk *clk)
+{
+ struct clk_fixed_factor *fix =
+ (struct clk_fixed_factor *)dev_get_driver_data(clk->dev);
+ unsigned long parent_rate = clk_get_parent_rate(clk);
+ unsigned long long int rate;
+
+ rate = (unsigned long long int)parent_rate * fix->mult;
+ do_div(rate, fix->div);
+ return (ulong)rate;
+}
+
+const struct clk_ops clk_fixed_factor_ops = {
+ .get_rate = clk_factor_recalc_rate,
+};
+
+struct clk *clk_hw_register_fixed_factor(struct device *dev,
+ const char *name, const char *parent_name, unsigned long flags,
+ unsigned int mult, unsigned int div)
+{
+ struct clk_fixed_factor *fix;
+ struct clk *clk;
+ int ret;
+
+ fix = kmalloc(sizeof(*fix), GFP_KERNEL);
+ if (!fix)
+ return ERR_PTR(-ENOMEM);
+
+ /* struct clk_fixed_factor assignments */
+ fix->mult = mult;
+ fix->div = div;
+ clk = &fix->clk;
+
+ /*
+ * We pass the struct clk *clk pointer (which is the same as
+ * clk_fixed_factor *fix - by the struct elements alignment) to DM as a
+ * driver_data, so it can be easily accessible from the udevice level.
+ * Moreover, the struct clk is only a wrapper on udevice which
+ * corresponds to the "real" clock device.
+ */
+ ret = clk_register(clk, UBOOT_DM_CLK_IMX_FIXED_FACTOR, (ulong)clk,
+ name, parent_name);
+ if (ret) {
+ kfree(fix);
+ return ERR_PTR(ret);
+ }
+
+ return clk;
+}
+
+struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
+ const char *parent_name, unsigned long flags,
+ unsigned int mult, unsigned int div)
+{
+ struct clk *clk;
+
+ clk = clk_hw_register_fixed_factor(dev, name, parent_name, flags, mult,
+ div);
+ if (IS_ERR(clk))
+ return ERR_CAST(clk);
+ return clk;
+}
+
+U_BOOT_DRIVER(clk_fixed_factor) = {
+ .name = UBOOT_DM_CLK_IMX_FIXED_FACTOR,
+ .id = UCLASS_CLK,
+ .ops = &clk_fixed_factor_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
new file mode 100644
index 0000000000..8db1d48946
--- /dev/null
+++ b/drivers/clk/clk-mux.c
@@ -0,0 +1,164 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 DENX Software Engineering
+ * Lukasz Majewski, DENX Software Engineering, lukma at denx.de
+ *
+ * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
+ * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
+ * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
+ *
+ * Simple multiplexer clock implementation
+ */
+
+/*
+ * U-Boot CCF porting node:
+ *
+ * The Linux kernel - as of tag: 5.0-rc3 is using also the imx_clk_fixup_mux()
+ * version of CCF mux. It is used on e.g. imx6q to provide fixes (like
+ * imx_cscmr1_fixup) for broken HW.
+ *
+ * At least for IMX6Q (but NOT IMX6QP) it is important when we set the parent
+ * clock.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <clk-uclass.h>
+#include <dm/device.h>
+#include <linux/clk-provider.h>
+#include <clk.h>
+#include "clk.h"
+
+#define UBOOT_DM_CLK_IMX_MUX "imx_clk_mux"
+
+int clk_mux_val_to_index(struct clk *clk, u32 *table, unsigned int flags,
+ unsigned int val)
+{
+ struct clk_mux *mux = to_clk_mux(clk);
+ int num_parents = mux->num_parents;
+
+ if (table) {
+ int i;
+
+ for (i = 0; i < num_parents; i++)
+ if (table[i] == val)
+ return i;
+ return -EINVAL;
+ }
+
+ if (val && (flags & CLK_MUX_INDEX_BIT))
+ val = ffs(val) - 1;
+
+ if (val && (flags & CLK_MUX_INDEX_ONE))
+ val--;
+
+ if (val >= num_parents)
+ return -EINVAL;
+
+ return val;
+}
+
+static u8 clk_mux_get_parent(struct clk *clk)
+{
+ struct clk_mux *mux = to_clk_mux(clk);
+ u32 val;
+
+ val = readl(mux->reg) >> mux->shift;
+ val &= mux->mask;
+
+ return clk_mux_val_to_index(clk, mux->table, mux->flags, val);
+}
+
+const struct clk_ops clk_mux_ops = {
+ .get_rate = clk_generic_get_rate,
+};
+
+struct clk *clk_hw_register_mux_table(struct device *dev, const char *name,
+ const char * const *parent_names, u8 num_parents,
+ unsigned long flags,
+ void __iomem *reg, u8 shift, u32 mask,
+ u8 clk_mux_flags, u32 *table)
+{
+ struct clk_mux *mux;
+ struct clk *clk;
+ u8 width = 0;
+ int ret;
+
+ if (clk_mux_flags & CLK_MUX_HIWORD_MASK) {
+ width = fls(mask) - ffs(mask) + 1;
+ if (width + shift > 16) {
+ pr_err("mux value exceeds LOWORD field\n");
+ return ERR_PTR(-EINVAL);
+ }
+ }
+
+ /* allocate the mux */
+ mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+ if (!mux)
+ return ERR_PTR(-ENOMEM);
+
+ /* U-boot specific assignments */
+ mux->parent_names = parent_names;
+ mux->num_parents = num_parents;
+
+ /* struct clk_mux assignments */
+ mux->reg = reg;
+ mux->shift = shift;
+ mux->mask = mask;
+ mux->flags = clk_mux_flags;
+ mux->table = table;
+
+ clk = &mux->clk;
+
+ /*
+ * Read the current mux setup - so we assign correct parent.
+ *
+ * Changing parent would require changing internals of udevice struct
+ * for the corresponding clock (to do that define .set_parent() method.
+ */
+ ret = clk_register(clk, UBOOT_DM_CLK_IMX_MUX, (ulong)clk, name,
+ parent_names[clk_mux_get_parent(clk)]);
+ if (ret) {
+ kfree(mux);
+ return ERR_PTR(ret);
+ }
+
+ return clk;
+}
+
+struct clk *clk_register_mux_table(struct device *dev, const char *name,
+ const char * const *parent_names, u8 num_parents,
+ unsigned long flags,
+ void __iomem *reg, u8 shift, u32 mask,
+ u8 clk_mux_flags, u32 *table)
+{
+ struct clk *clk;
+
+ clk = clk_hw_register_mux_table(dev, name, parent_names, num_parents,
+ flags, reg, shift, mask, clk_mux_flags,
+ table);
+ if (IS_ERR(clk))
+ return ERR_CAST(clk);
+ return clk;
+}
+
+struct clk *clk_register_mux(struct device *dev, const char *name,
+ const char * const *parent_names, u8 num_parents,
+ unsigned long flags,
+ void __iomem *reg, u8 shift, u8 width,
+ u8 clk_mux_flags)
+{
+ u32 mask = BIT(width) - 1;
+
+ return clk_register_mux_table(dev, name, parent_names, num_parents,
+ flags, reg, shift, mask, clk_mux_flags,
+ NULL);
+}
+
+U_BOOT_DRIVER(clk_mux) = {
+ .name = UBOOT_DM_CLK_IMX_MUX,
+ .id = UCLASS_CLK,
+ .ops = &clk_mux_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
new file mode 100644
index 0000000000..0a0fffb50b
--- /dev/null
+++ b/drivers/clk/clk.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 DENX Software Engineering
+ * Lukasz Majewski, DENX Software Engineering, lukma at denx.de
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm/device.h>
+#include <dm/uclass.h>
+#include <dm/lists.h>
+#include <dm/device-internal.h>
+#include <clk.h>
+
+int clk_register(struct clk *clk, const char *drv_name,
+ ulong drv_data, const char *name,
+ const char *parent_name)
+{
+ struct udevice *parent;
+ struct driver *drv;
+ int ret;
+
+ ret = uclass_get_device_by_name(UCLASS_CLK, parent_name, &parent);
+ if (ret)
+ printf("%s: UCLASS parent: 0x%p\n", __func__, parent);
+
+ debug("%s: name: %s parent: %s [0x%p]\n", __func__, name, parent->name,
+ parent);
+
+ drv = lists_driver_lookup_name(drv_name);
+ if (!drv) {
+ printf("%s: %s is not a valid driver name\n",
+ __func__, drv_name);
+ return -ENOENT;
+ }
+
+ ret = device_bind_with_driver_data(parent, drv, name, drv_data,
+ ofnode_null(), &clk->dev);
+ if (ret) {
+ printf("%s: CLK: %s driver bind error [%d]!\n", __func__, name,
+ ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+ulong clk_generic_get_rate(struct clk *clk)
+{
+ return clk_get_parent_rate(clk);
+}
+
+const char *clk_hw_get_name(const struct clk *hw)
+{
+ return hw->dev->name;
+}
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index a6fb58d6cf..ae7bdf1cb5 100644
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -1,3 +1,11 @@
+config CLK_IMX6Q
+ bool "Clock support for i.MX6Q"
+ depends on ARCH_MX6
+ select CLK
+ select CLK_CCF
+ help
+ This enables DM/DTS support for clock driver in i.MX6Q platforms.
+
config CLK_IMX8
bool "Clock support for i.MX8"
depends on ARCH_IMX8
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 5505ae52e2..beba3bff39 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -2,4 +2,6 @@
#
# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk-gate2.o clk-pllv3.o clk-pfd.o
+obj-$(CONFIG_CLK_IMX6Q) += clk-imx6q.o
obj-$(CONFIG_CLK_IMX8) += clk-imx8.o
diff --git a/drivers/clk/imx/clk-gate2.c b/drivers/clk/imx/clk-gate2.c
new file mode 100644
index 0000000000..1e53e4f9db
--- /dev/null
+++ b/drivers/clk/imx/clk-gate2.c
@@ -0,0 +1,113 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 DENX Software Engineering
+ * Lukasz Majewski, DENX Software Engineering, lukma at denx.de
+ *
+ * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
+ * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Gated clock implementation
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <clk-uclass.h>
+#include <dm/device.h>
+#include <linux/clk-provider.h>
+#include <clk.h>
+#include "clk.h"
+
+#define UBOOT_DM_CLK_IMX_GATE2 "imx_clk_gate2"
+
+struct clk_gate2 {
+ struct clk clk;
+ void __iomem *reg;
+ u8 bit_idx;
+ u8 cgr_val;
+ u8 flags;
+};
+
+#define to_clk_gate2(_clk) container_of(_clk, struct clk_gate2, clk)
+
+static int clk_gate2_enable(struct clk *clk)
+{
+ struct clk_gate2 *gate =
+ (struct clk_gate2 *)dev_get_driver_data(clk->dev);
+ u32 reg;
+
+ reg = readl(gate->reg);
+ reg &= ~(3 << gate->bit_idx);
+ reg |= gate->cgr_val << gate->bit_idx;
+ writel(reg, gate->reg);
+
+ return 0;
+}
+
+static int clk_gate2_disable(struct clk *clk)
+{
+ struct clk_gate2 *gate =
+ (struct clk_gate2 *)dev_get_driver_data(clk->dev);
+ u32 reg;
+
+ reg = readl(gate->reg);
+ reg &= ~(3 << gate->bit_idx);
+ writel(reg, gate->reg);
+
+ return 0;
+}
+
+static const struct clk_ops clk_gate2_ops = {
+ .enable = clk_gate2_enable,
+ .disable = clk_gate2_disable,
+ .get_rate = clk_generic_get_rate,
+};
+
+struct clk *clk_register_gate2(struct device *dev, const char *name,
+ const char *parent_name, unsigned long flags,
+ void __iomem *reg, u8 bit_idx, u8 cgr_val,
+ u8 clk_gate2_flags)
+{
+ struct clk_gate2 *gate;
+ struct clk *clk;
+ int ret;
+
+ gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+ if (!gate)
+ return ERR_PTR(-ENOMEM);
+
+ /* struct clk_gate2 assignments */
+ gate->reg = reg;
+ gate->bit_idx = bit_idx;
+ gate->cgr_val = cgr_val;
+ gate->flags = clk_gate2_flags;
+
+ /*
+ * U-boot DM adjustments:
+ *
+ * clk and gate reslove to the same address - lets pass clock
+ * for better readability.
+ */
+ clk = &gate->clk;
+
+ ret = clk_register(clk, UBOOT_DM_CLK_IMX_GATE2, (ulong)clk,
+ name, parent_name);
+ if (ret) {
+ kfree(gate);
+ return ERR_PTR(ret);
+ }
+
+ return clk;
+}
+
+U_BOOT_DRIVER(clk_gate2) = {
+ .name = UBOOT_DM_CLK_IMX_GATE2,
+ .id = UCLASS_CLK,
+ .ops = &clk_gate2_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
new file mode 100644
index 0000000000..92e9337d44
--- /dev/null
+++ b/drivers/clk/imx/clk-imx6q.c
@@ -0,0 +1,179 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 DENX Software Engineering
+ * Lukasz Majewski, DENX Software Engineering, lukma at denx.de
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <dt-bindings/clock/imx6qdl-clock.h>
+
+#include "clk.h"
+
+static int imx6q_check_id(ulong id)
+{
+ if (id < IMX6QDL_CLK_DUMMY || id >= IMX6QDL_CLK_END) {
+ printf("%s: Invalid clk ID #%lu\n", __func__, id);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static ulong imx6q_clk_get_rate(struct clk *clk)
+{
+ struct clk *c;
+ int ret;
+
+ debug("%s(#%lu)\n", __func__, clk->id);
+
+ ret = imx6q_check_id(clk->id);
+ if (ret)
+ return ret;
+
+ ret = clk_get_by_id(clk->id, &c);
+ if (ret)
+ return ret;
+
+ return clk_get_rate(c);
+}
+
+static ulong imx6q_clk_set_rate(struct clk *clk, unsigned long rate)
+{
+ debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
+
+ return rate;
+}
+
+static int __imx6q_clk_enable(struct clk *clk, bool enable)
+{
+ struct clk *c;
+ int ret = 0;
+
+ debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
+
+ ret = imx6q_check_id(clk->id);
+ if (ret)
+ return ret;
+
+ ret = clk_get_by_id(clk->id, &c);
+ if (ret)
+ return ret;
+
+ if (enable)
+ ret = clk_enable(c);
+ else
+ ret = clk_disable(c);
+
+ return ret;
+}
+
+static int imx6q_clk_disable(struct clk *clk)
+{
+ return __imx6q_clk_enable(clk, 0);
+}
+
+static int imx6q_clk_enable(struct clk *clk)
+{
+ return __imx6q_clk_enable(clk, 1);
+}
+
+static struct clk_ops imx6q_clk_ops = {
+ .set_rate = imx6q_clk_set_rate,
+ .get_rate = imx6q_clk_get_rate,
+ .enable = imx6q_clk_enable,
+ .disable = imx6q_clk_disable,
+};
+
+static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
+
+static int imx6q_clk_probe(struct udevice *dev)
+{
+ void *base;
+
+ /* Anatop clocks */
+ base = (void *)ANATOP_BASE_ADDR;
+
+ clk_dm(IMX6QDL_CLK_PLL2,
+ imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc",
+ base + 0x30, 0x1));
+ clk_dm(IMX6QDL_CLK_PLL3_USB_OTG,
+ imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc",
+ base + 0x10, 0x3));
+ clk_dm(IMX6QDL_CLK_PLL3_60M,
+ imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8));
+ clk_dm(IMX6QDL_CLK_PLL2_PFD0_352M,
+ imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0));
+ clk_dm(IMX6QDL_CLK_PLL2_PFD2_396M,
+ imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2));
+
+ /* CCM clocks */
+ base = dev_read_addr_ptr(dev);
+ if (base == (void *)FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ clk_dm(IMX6QDL_CLK_USDHC1_SEL,
+ imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1,
+ usdhc_sels, ARRAY_SIZE(usdhc_sels)));
+ clk_dm(IMX6QDL_CLK_USDHC2_SEL,
+ imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1,
+ usdhc_sels, ARRAY_SIZE(usdhc_sels)));
+ clk_dm(IMX6QDL_CLK_USDHC3_SEL,
+ imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1,
+ usdhc_sels, ARRAY_SIZE(usdhc_sels)));
+ clk_dm(IMX6QDL_CLK_USDHC4_SEL,
+ imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1,
+ usdhc_sels, ARRAY_SIZE(usdhc_sels)));
+
+ clk_dm(IMX6QDL_CLK_USDHC1_PODF,
+ imx_clk_divider("usdhc1_podf", "usdhc1_sel",
+ base + 0x24, 11, 3));
+ clk_dm(IMX6QDL_CLK_USDHC2_PODF,
+ imx_clk_divider("usdhc2_podf", "usdhc2_sel",
+ base + 0x24, 16, 3));
+ clk_dm(IMX6QDL_CLK_USDHC3_PODF,
+ imx_clk_divider("usdhc3_podf", "usdhc3_sel",
+ base + 0x24, 19, 3));
+ clk_dm(IMX6QDL_CLK_USDHC4_PODF,
+ imx_clk_divider("usdhc4_podf", "usdhc4_sel",
+ base + 0x24, 22, 3));
+
+ clk_dm(IMX6QDL_CLK_ECSPI_ROOT,
+ imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6));
+
+ clk_dm(IMX6QDL_CLK_ECSPI1,
+ imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0));
+ clk_dm(IMX6QDL_CLK_ECSPI2,
+ imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2));
+ clk_dm(IMX6QDL_CLK_ECSPI3,
+ imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4));
+ clk_dm(IMX6QDL_CLK_ECSPI4,
+ imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6));
+ clk_dm(IMX6QDL_CLK_USDHC1,
+ imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2));
+ clk_dm(IMX6QDL_CLK_USDHC2,
+ imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4));
+ clk_dm(IMX6QDL_CLK_USDHC3,
+ imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6));
+ clk_dm(IMX6QDL_CLK_USDHC4,
+ imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8));
+
+ return 0;
+}
+
+static const struct udevice_id imx6q_clk_ids[] = {
+ { .compatible = "fsl,imx6q-ccm" },
+ { },
+};
+
+U_BOOT_DRIVER(imx6q_clk) = {
+ .name = "clk_imx6q",
+ .id = UCLASS_CLK,
+ .of_match = imx6q_clk_ids,
+ .ops = &imx6q_clk_ops,
+ .probe = imx6q_clk_probe,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/imx/clk-pfd.c b/drivers/clk/imx/clk-pfd.c
new file mode 100644
index 0000000000..2293d481d4
--- /dev/null
+++ b/drivers/clk/imx/clk-pfd.c
@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 DENX Software Engineering
+ * Lukasz Majewski, DENX Software Engineering, lukma at denx.de
+ *
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2012 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <clk-uclass.h>
+#include <dm/device.h>
+#include <linux/clk-provider.h>
+#include <div64.h>
+#include <clk.h>
+#include "clk.h"
+
+#define UBOOT_DM_CLK_IMX_PFD "imx_clk_pfd"
+
+struct clk_pfd {
+ struct clk clk;
+ void __iomem *reg;
+ u8 idx;
+};
+
+#define to_clk_pfd(_clk) container_of(_clk, struct clk_pfd, clk)
+
+#define SET 0x4
+#define CLR 0x8
+#define OTG 0xc
+
+static unsigned long clk_pfd_recalc_rate(struct clk *clk)
+{
+ struct clk_pfd *pfd =
+ (struct clk_pfd *)dev_get_driver_data(clk->dev);
+ unsigned long parent_rate = clk_get_parent_rate(clk);
+ u64 tmp = parent_rate;
+ u8 frac = (readl(pfd->reg) >> (pfd->idx * 8)) & 0x3f;
+
+ tmp *= 18;
+ do_div(tmp, frac);
+
+ return tmp;
+}
+
+static const struct clk_ops clk_pfd_ops = {
+ .get_rate = clk_pfd_recalc_rate,
+};
+
+struct clk *imx_clk_pfd(const char *name, const char *parent_name,
+ void __iomem *reg, u8 idx)
+{
+ struct clk_pfd *pfd;
+ struct clk *clk;
+ int ret;
+
+ pfd = kzalloc(sizeof(*pfd), GFP_KERNEL);
+ if (!pfd)
+ return ERR_PTR(-ENOMEM);
+
+ pfd->reg = reg;
+ pfd->idx = idx;
+
+ /* register the clock */
+ clk = &pfd->clk;
+
+ ret = clk_register(clk, UBOOT_DM_CLK_IMX_PFD, (ulong)clk,
+ name, parent_name);
+ if (ret) {
+ kfree(pfd);
+ return ERR_PTR(ret);
+ }
+
+ return clk;
+}
+
+U_BOOT_DRIVER(clk_pfd) = {
+ .name = UBOOT_DM_CLK_IMX_PFD,
+ .id = UCLASS_CLK,
+ .ops = &clk_pfd_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
new file mode 100644
index 0000000000..3fe9b7c03d
--- /dev/null
+++ b/drivers/clk/imx/clk-pllv3.c
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 DENX Software Engineering
+ * Lukasz Majewski, DENX Software Engineering, lukma at denx.de
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <clk-uclass.h>
+#include <dm/device.h>
+#include <dm/uclass.h>
+#include <clk.h>
+#include "clk.h"
+
+#define UBOOT_DM_CLK_IMX_PLLV3 "imx_clk_pllv3"
+
+struct clk_pllv3 {
+ struct clk clk;
+ void __iomem *base;
+ u32 div_mask;
+ u32 div_shift;
+};
+
+#define to_clk_pllv3(_clk) container_of(_clk, struct clk_pllv3, clk)
+
+static ulong clk_pllv3_get_rate(struct clk *clk)
+{
+ struct clk_pllv3 *pll =
+ (struct clk_pllv3 *)dev_get_driver_data(clk->dev);
+ unsigned long parent_rate = clk_get_parent_rate(clk);
+
+ u32 div = (readl(pll->base) >> pll->div_shift) & pll->div_mask;
+
+ return (div == 1) ? parent_rate * 22 : parent_rate * 20;
+}
+
+static const struct clk_ops clk_pllv3_generic_ops = {
+ .get_rate = clk_pllv3_get_rate,
+};
+
+struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
+ const char *parent_name, void __iomem *base,
+ u32 div_mask)
+{
+ struct clk_pllv3 *pll;
+ struct clk *clk;
+ char *drv_name;
+ int ret;
+
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+ if (!pll)
+ return ERR_PTR(-ENOMEM);
+
+ switch (type) {
+ case IMX_PLLV3_GENERIC:
+ case IMX_PLLV3_USB:
+ drv_name = UBOOT_DM_CLK_IMX_PLLV3;
+ break;
+ default:
+ kfree(pll);
+ return ERR_PTR(-ENOTSUPP);
+ }
+
+ pll->base = base;
+ pll->div_mask = div_mask;
+ clk = &pll->clk;
+
+ ret = clk_register(clk, drv_name, (ulong)clk, name, parent_name);
+ if (ret) {
+ kfree(pll);
+ return ERR_PTR(ret);
+ }
+
+ return clk;
+}
+
+U_BOOT_DRIVER(clk_pllv3_generic) = {
+ .name = UBOOT_DM_CLK_IMX_PLLV3,
+ .id = UCLASS_CLK,
+ .ops = &clk_pllv3_generic_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
new file mode 100644
index 0000000000..864a215a22
--- /dev/null
+++ b/drivers/clk/imx/clk.h
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 DENX Software Engineering
+ * Lukasz Majewski, DENX Software Engineering, lukma at denx.de
+ */
+#ifndef __MACH_IMX_CLK_H
+#define __MACH_IMX_CLK_H
+
+#include <linux/clk-provider.h>
+
+static inline void clk_dm(ulong id, struct clk *clk)
+{
+ if (!IS_ERR(clk))
+ clk->id = id;
+}
+
+enum imx_pllv3_type {
+ IMX_PLLV3_GENERIC,
+ IMX_PLLV3_SYS,
+ IMX_PLLV3_USB,
+ IMX_PLLV3_USB_VF610,
+ IMX_PLLV3_AV,
+ IMX_PLLV3_ENET,
+ IMX_PLLV3_ENET_IMX7,
+ IMX_PLLV3_SYS_VF610,
+ IMX_PLLV3_DDR_IMX7,
+};
+
+struct clk *clk_register_gate2(struct device *dev, const char *name,
+ const char *parent_name, unsigned long flags,
+ void __iomem *reg, u8 bit_idx, u8 cgr_val,
+ u8 clk_gate_flags);
+
+struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
+ const char *parent_name, void __iomem *base,
+ u32 div_mask);
+
+static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
+ void __iomem *reg, u8 shift)
+{
+ return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
+ shift, 0x3, 0);
+}
+
+static inline struct clk *imx_clk_fixed_factor(const char *name,
+ const char *parent, unsigned int mult, unsigned int div)
+{
+ return clk_register_fixed_factor(NULL, name, parent,
+ CLK_SET_RATE_PARENT, mult, div);
+}
+
+static inline struct clk *imx_clk_divider(const char *name, const char *parent,
+ void __iomem *reg, u8 shift, u8 width)
+{
+ return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
+ reg, shift, width, 0);
+}
+
+struct clk *imx_clk_pfd(const char *name, const char *parent_name,
+ void __iomem *reg, u8 idx);
+
+struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg,
+ u8 shift, u8 width, const char * const *parents,
+ int num_parents, void (*fixup)(u32 *val));
+
+static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
+ u8 shift, u8 width, const char * const *parents,
+ int num_parents)
+{
+ return clk_register_mux(NULL, name, parents, num_parents,
+ CLK_SET_RATE_NO_REPARENT, reg, shift,
+ width, 0);
+}
+
+#endif /* __MACH_IMX_CLK_H */
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
new file mode 100644
index 0000000000..eac045c5f8
--- /dev/null
+++ b/include/linux/clk-provider.h
@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 DENX Software Engineering
+ * Lukasz Majewski, DENX Software Engineering, lukma at denx.de
+ *
+ * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
+ * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
+ */
+#ifndef __LINUX_CLK_PROVIDER_H
+#define __LINUX_CLK_PROVIDER_H
+
+#define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
+#define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
+
+#define CLK_MUX_INDEX_ONE BIT(0)
+#define CLK_MUX_INDEX_BIT BIT(1)
+#define CLK_MUX_HIWORD_MASK BIT(2)
+#define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */
+#define CLK_MUX_ROUND_CLOSEST BIT(4)
+
+struct clk_mux {
+ struct clk clk;
+ void __iomem *reg;
+ u32 *table;
+ u32 mask;
+ u8 shift;
+ u8 flags;
+
+ /*
+ * Fields from struct clk_init_data - this struct has been
+ * omitted to avoid too deep level of CCF for bootloader
+ */
+ const char * const *parent_names;
+ u8 num_parents;
+};
+
+#define to_clk_mux(_clk) container_of(_clk, struct clk_mux, clk)
+
+struct clk_div_table {
+ unsigned int val;
+ unsigned int div;
+};
+
+struct clk_divider {
+ struct clk clk;
+ void __iomem *reg;
+ u8 shift;
+ u8 width;
+ u8 flags;
+ const struct clk_div_table *table;
+};
+
+#define clk_div_mask(width) ((1 << (width)) - 1)
+#define to_clk_divider(_clk) container_of(_clk, struct clk_divider, clk)
+
+#define CLK_DIVIDER_ONE_BASED BIT(0)
+#define CLK_DIVIDER_POWER_OF_TWO BIT(1)
+#define CLK_DIVIDER_ALLOW_ZERO BIT(2)
+#define CLK_DIVIDER_HIWORD_MASK BIT(3)
+#define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
+#define CLK_DIVIDER_READ_ONLY BIT(5)
+#define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
+
+struct clk_fixed_factor {
+ struct clk clk;
+ unsigned int mult;
+ unsigned int div;
+};
+
+#define to_clk_fixed_factor(_clk) container_of(_clk, struct clk_fixed_factor,\
+ clk)
+
+int clk_register(struct clk *clk, const char *drv_name,
+ ulong drv_data, const char *name,
+ const char *parent_name);
+
+struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
+ const char *parent_name, unsigned long flags,
+ unsigned int mult, unsigned int div);
+
+struct clk *clk_register_divider(struct device *dev, const char *name,
+ const char *parent_name, unsigned long flags,
+ void __iomem *reg, u8 shift, u8 width,
+ u8 clk_divider_flags);
+
+struct clk *clk_register_mux(struct device *dev, const char *name,
+ const char * const *parent_names, u8 num_parents,
+ unsigned long flags,
+ void __iomem *reg, u8 shift, u8 width,
+ u8 clk_mux_flags);
+
+const char *clk_hw_get_name(const struct clk *hw);
+ulong clk_generic_get_rate(struct clk *clk);
+#endif /* __LINUX_CLK_PROVIDER_H */
--
2.11.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [U-Boot] [PATCH v2 06/17] ARM: imx: cosmetic: Remove not needed comment from the mccmon6.h file
2019-01-31 9:03 [U-Boot] [PATCH v2 00/17] imx: dm: Update mccmon6 board to only use DM/DTS in u-boot proper Lukasz Majewski
` (4 preceding siblings ...)
2019-01-31 9:03 ` [U-Boot] [PATCH v2 05/17] clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: 5.0-rc3) Lukasz Majewski
@ 2019-01-31 9:03 ` Lukasz Majewski
2019-01-31 9:03 ` [U-Boot] [PATCH v2 07/17] ARM: imx: config: Disable support for USB on MCCMON6 Lukasz Majewski
` (10 subsequent siblings)
16 siblings, 0 replies; 24+ messages in thread
From: Lukasz Majewski @ 2019-01-31 9:03 UTC (permalink / raw)
To: u-boot
This comment is a leftover from the Kconfig CONFIG_*MTD* move.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
---
Changes in v2: None
include/configs/mccmon6.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h
index 644f339993..86ab66f3ab 100644
--- a/include/configs/mccmon6.h
+++ b/include/configs/mccmon6.h
@@ -70,8 +70,6 @@
#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) }
#define CONFIG_SYS_FLASH_BANKS_SIZES { (32 * SZ_1M) }
-/* MTD support */
-
/* USB Configs */
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
--
2.11.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [U-Boot] [PATCH v2 07/17] ARM: imx: config: Disable support for USB on MCCMON6
2019-01-31 9:03 [U-Boot] [PATCH v2 00/17] imx: dm: Update mccmon6 board to only use DM/DTS in u-boot proper Lukasz Majewski
` (5 preceding siblings ...)
2019-01-31 9:03 ` [U-Boot] [PATCH v2 06/17] ARM: imx: cosmetic: Remove not needed comment from the mccmon6.h file Lukasz Majewski
@ 2019-01-31 9:03 ` Lukasz Majewski
2019-01-31 9:03 ` [U-Boot] [PATCH v2 08/17] net: imx: Add support for waiting some time after FEC gpio reset Lukasz Majewski
` (9 subsequent siblings)
16 siblings, 0 replies; 24+ messages in thread
From: Lukasz Majewski @ 2019-01-31 9:03 UTC (permalink / raw)
To: u-boot
The IMX6Q based MCCMON6 is not using USB for any purpose.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
---
Changes in v2: None
configs/mccmon6_nor_defconfig | 2 --
configs/mccmon6_sd_defconfig | 2 --
include/configs/mccmon6.h | 5 -----
3 files changed, 9 deletions(-)
diff --git a/configs/mccmon6_nor_defconfig b/configs/mccmon6_nor_defconfig
index 1ab29c1ca6..18070cd0b1 100644
--- a/configs/mccmon6_nor_defconfig
+++ b/configs/mccmon6_nor_defconfig
@@ -19,7 +19,6 @@ CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
@@ -46,5 +45,4 @@ CONFIG_MII=y
CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_DM_THERMAL=y
-CONFIG_USB=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/mccmon6_sd_defconfig b/configs/mccmon6_sd_defconfig
index 6d47db57ee..d1d1313e1e 100644
--- a/configs/mccmon6_sd_defconfig
+++ b/configs/mccmon6_sd_defconfig
@@ -20,7 +20,6 @@ CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
@@ -47,5 +46,4 @@ CONFIG_MII=y
CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_DM_THERMAL=y
-CONFIG_USB=y
CONFIG_OF_LIBFDT=y
diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h
index 86ab66f3ab..5ca9bc6848 100644
--- a/include/configs/mccmon6.h
+++ b/include/configs/mccmon6.h
@@ -70,11 +70,6 @@
#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) }
#define CONFIG_SYS_FLASH_BANKS_SIZES { (32 * SZ_1M) }
-/* USB Configs */
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CONFIG_MXC_USB_FLAGS 0
-
/* Ethernet Configuration */
#define CONFIG_FEC_MXC
#define IMX_FEC_BASE ENET_BASE_ADDR
--
2.11.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [U-Boot] [PATCH v2 08/17] net: imx: Add support for waiting some time after FEC gpio reset
2019-01-31 9:03 [U-Boot] [PATCH v2 00/17] imx: dm: Update mccmon6 board to only use DM/DTS in u-boot proper Lukasz Majewski
` (6 preceding siblings ...)
2019-01-31 9:03 ` [U-Boot] [PATCH v2 07/17] ARM: imx: config: Disable support for USB on MCCMON6 Lukasz Majewski
@ 2019-01-31 9:03 ` Lukasz Majewski
2019-01-31 9:03 ` [U-Boot] [PATCH v2 09/17] spi: imx: Add support for 'per' clock enabling via driver model Lukasz Majewski
` (8 subsequent siblings)
16 siblings, 0 replies; 24+ messages in thread
From: Lukasz Majewski @ 2019-01-31 9:03 UTC (permalink / raw)
To: u-boot
The support for in-kernel (v4.20) "phy-reset-post-delay" property has
been implemented in u-boot's FEC IMX driver. It has the same range (1 to
1000ms) as in Linux.
Some PHYs require waiting some time after the reset to be accessible
via MII bus. This problem has been observed on mccmon6 board with KSZ9031
PHY IC, when DM_ETH was enabled (as DM slightly changes time between
PHY initialization and first access).
Signed-off-by: Lukasz Majewski <lukma@denx.de>
---
Changes in v2: None
drivers/net/fec_mxc.c | 11 +++++++++++
drivers/net/fec_mxc.h | 1 +
2 files changed, 12 insertions(+)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 1a59026a62..6305aa5c05 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -1315,6 +1315,8 @@ static void fec_gpio_reset(struct fec_priv *priv)
dm_gpio_set_value(&priv->phy_reset_gpio, 1);
mdelay(priv->reset_delay);
dm_gpio_set_value(&priv->phy_reset_gpio, 0);
+ if (priv->post_reset_delay)
+ mdelay(priv->post_reset_delay);
}
}
#endif
@@ -1474,6 +1476,15 @@ static int fecmxc_ofdata_to_platdata(struct udevice *dev)
/* property value wrong, use default value */
priv->reset_delay = 1;
}
+
+ priv->post_reset_delay = dev_read_u32_default(dev,
+ "phy-reset-post-delay",
+ 0);
+ if (priv->post_reset_delay > 1000) {
+ printf("FEC MXC: phy reset post delay should be <= 1000ms\n");
+ /* property value wrong, use default value */
+ priv->post_reset_delay = 0;
+ }
#endif
return 0;
diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h
index e9a661f0a1..d069af533a 100644
--- a/drivers/net/fec_mxc.h
+++ b/drivers/net/fec_mxc.h
@@ -258,6 +258,7 @@ struct fec_priv {
#ifdef CONFIG_DM_GPIO
struct gpio_desc phy_reset_gpio;
uint32_t reset_delay;
+ u32 post_reset_delay;
#endif
#ifdef CONFIG_DM_ETH
u32 interface;
--
2.11.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [U-Boot] [PATCH v2 09/17] spi: imx: Add support for 'per' clock enabling via driver model
2019-01-31 9:03 [U-Boot] [PATCH v2 00/17] imx: dm: Update mccmon6 board to only use DM/DTS in u-boot proper Lukasz Majewski
` (7 preceding siblings ...)
2019-01-31 9:03 ` [U-Boot] [PATCH v2 08/17] net: imx: Add support for waiting some time after FEC gpio reset Lukasz Majewski
@ 2019-01-31 9:03 ` Lukasz Majewski
2019-01-31 9:03 ` [U-Boot] [PATCH v2 10/17] ARM: imx: Covnert mccmon6 to use DM/DTS in the u-boot proper Lukasz Majewski
` (7 subsequent siblings)
16 siblings, 0 replies; 24+ messages in thread
From: Lukasz Majewski @ 2019-01-31 9:03 UTC (permalink / raw)
To: u-boot
With this commit one can enable ECSPI clock on imx6q without the need to
define direct call to it in the board file (as it is done up to now).
The information regarding proper clocks is provided via DTS description.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
---
Changes in v2: None
drivers/spi/mxc_spi.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index 6846762719..f34506099e 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -7,6 +7,7 @@
#include <dm.h>
#include <malloc.h>
#include <spi.h>
+#include <clk.h>
#include <linux/errno.h>
#include <asm/io.h>
#include <asm/gpio.h>
@@ -50,6 +51,9 @@ struct mxc_spi_slave {
unsigned int max_hz;
unsigned int mode;
struct gpio_desc ss;
+#if CONFIG_IS_ENABLED(CLK)
+ struct clk per_clk;
+#endif
};
static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
@@ -494,6 +498,19 @@ static int mxc_spi_probe(struct udevice *bus)
const void *blob = gd->fdt_blob;
int ret;
+#if CONFIG_IS_ENABLED(CLK)
+ ret = clk_get_by_name(bus, "per", &mxcs->per_clk);
+ if (ret) {
+ printf("%s: Failed to get per_clk\n", __func__);
+ return ret;
+ }
+
+ ret = clk_enable(&mxcs->per_clk);
+ if (ret) {
+ printf("%s: Failed to enable per_clk\n", __func__);
+ return ret;
+ }
+#endif
if (gpio_request_by_name(bus, "cs-gpios", 0, &plat->ss,
GPIOD_IS_OUT)) {
dev_err(bus, "No cs-gpios property\n");
--
2.11.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [U-Boot] [PATCH v2 10/17] ARM: imx: Covnert mccmon6 to use DM/DTS in the u-boot proper
2019-01-31 9:03 [U-Boot] [PATCH v2 00/17] imx: dm: Update mccmon6 board to only use DM/DTS in u-boot proper Lukasz Majewski
` (8 preceding siblings ...)
2019-01-31 9:03 ` [U-Boot] [PATCH v2 09/17] spi: imx: Add support for 'per' clock enabling via driver model Lukasz Majewski
@ 2019-01-31 9:03 ` Lukasz Majewski
2019-01-31 9:03 ` [U-Boot] [PATCH v2 11/17] ARM: imx: Decouple mccmon6's SPL and u-boot proper code Lukasz Majewski
` (6 subsequent siblings)
16 siblings, 0 replies; 24+ messages in thread
From: Lukasz Majewski @ 2019-01-31 9:03 UTC (permalink / raw)
To: u-boot
This commit converts mccmon6's u-boot proper (in a single commit to avoid
build breaks) to use solely DM/DTS.
The DTS description of the mccmon6 has been ported from Linux kernel
(v4.20, SHA1: 8fe28cb58bcb235034b64cbbb7550a8a43fd88be)
Signed-off-by: Lukasz Majewski <lukma@denx.de>
---
Changes in v2: None
arch/arm/dts/imx6q-mccmon6.dts | 382 +++++++++++++++++++++++++++++++++++++++
arch/arm/mach-imx/mx6/Kconfig | 7 +
board/liebherr/mccmon6/mccmon6.c | 161 -----------------
configs/mccmon6_nor_defconfig | 30 ++-
configs/mccmon6_sd_defconfig | 29 ++-
include/configs/mccmon6.h | 18 --
6 files changed, 444 insertions(+), 183 deletions(-)
create mode 100644 arch/arm/dts/imx6q-mccmon6.dts
diff --git a/arch/arm/dts/imx6q-mccmon6.dts b/arch/arm/dts/imx6q-mccmon6.dts
new file mode 100644
index 0000000000..27cde56115
--- /dev/null
+++ b/arch/arm/dts/imx6q-mccmon6.dts
@@ -0,0 +1,382 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019
+ * Lukasz Majewski, DENX Software Engineering, lukma at denx.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+ or X11
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include "imx6q.dtsi"
+
+/ {
+ model = "Liebherr Nenzig (LWN) iMX6Q";
+ compatible = "lwn,imx6-mccmon6", "fsl,imx6";
+
+ aliases {
+ mmc0 = &usdhc3;
+ mmc1 = &usdhc2;
+ spi0 = &ecspi3;
+ };
+
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ memory at 10000000 {
+ reg = <0x10000000 0x80000000>;
+ };
+};
+
+&ecspi3 {
+ cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs &pinctrl_ecspi3_flwp>;
+ spi-max-frequency = <25000000>;
+ status = "okay";
+
+ s25sl032p: flash at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <40000000>;
+ reg = <0>;
+ };
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rgmii";
+ phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <10>;
+ phy-reset-post-delay = <1>;
+ /* KSZ9031 PHY SKEW setup - old values * 60 ps */
+ rxc-skew-ps = <1860>;
+ txc-skew-ps = <1860>;
+ txen-skew-ps = <900>;
+ rxdv-skew-ps = <900>;
+ rxd0-skew-ps = <180>;
+ rxd1-skew-ps = <180>;
+ rxd2-skew-ps = <180>;
+ rxd3-skew-ps = <180>;
+ txd0-skew-ps = <120>;
+ txd1-skew-ps = <300>;
+ txd2-skew-ps = <0>;
+ txd3-skew-ps = <120>;
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ pfuze100: pmic at 8 {
+ compatible = "fsl,pfuze100";
+ reg = <0x08>;
+
+ regulators {
+ sw1a_reg: sw1ab {
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw1c_reg: sw1c {
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw2_reg: sw2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3950000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw3a_reg: sw3a {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw3b_reg: sw3b {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw4_reg: sw4 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ swbst_reg: swbst {
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5150000>;
+ };
+
+ snvs_reg: vsnvs {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vref_reg: vrefddr {
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vgen1_reg: vgen1 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ };
+
+ vgen2_reg: vgen2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ };
+
+ vgen3_reg: vgen3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vgen4_reg: vgen4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen5_reg: vgen5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen6_reg: vgen6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&weim {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
+ ranges = <0 0 0x08000000 0x08000000>;
+ status = "okay";
+
+ nor at 0,0 {
+ compatible = "cfi-flash";
+ reg = <0 0 0x02000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ bank-width = <2>;
+ use-advanced-sector-protection;
+ fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
+ 0x0000c000 0x1404a38e 0x00000000>;
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_ecspi3: ecspi3grp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
+ MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
+ MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
+ >;
+ };
+
+ pinctrl_ecspi3_cs: ecspi3csgrp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000
+ >;
+ };
+
+ pinctrl_ecspi3_flwp: ecspi3flwpgrp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x80000000
+ >;
+ };
+
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
+ MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
+ MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0
+ >;
+ };
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
+ MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
+ MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b1
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
+ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
+ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
+ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
+ MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059
+ >;
+ };
+
+ pinctrl_weim_cs0: weimcs0grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
+ >;
+ };
+
+ pinctrl_weim_nor: weimnorgrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
+ MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
+ MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
+ MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
+ MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
+ MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
+ MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
+ MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
+ MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
+ MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
+ MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
+ MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
+ MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
+ MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
+ MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
+ MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
+ MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
+ MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
+ MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
+ MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
+ MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
+ MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
+ MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
+ MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
+ MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
+ MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
+ MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
+ MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
+ MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
+ MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
+ MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
+ MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
+ MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
+ MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
+ MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
+ MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
+ MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
+ MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
+ MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
+ MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
+ MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
+ MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
+ MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
+ >;
+ };
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ bus-width = <4>;
+ cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&usdhc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ bus-width = <8>;
+ non-removable;
+ no-1-8-v;
+ keep-power-in-suspend;
+ status = "okay";
+};
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index d0cee514a2..b81ba79f46 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -205,6 +205,13 @@ config TARGET_MCCMON6
bool "mccmon6"
select MX6QDL
select SUPPORT_SPL
+ select DM
+ select DM_GPIO
+ select DM_ETH
+ select DM_SERIAL
+ select DM_I2C
+ select DM_SPI
+ imply CMD_DM
config TARGET_MX6CUBOXI
bool "Solid-run mx6 boards"
diff --git a/board/liebherr/mccmon6/mccmon6.c b/board/liebherr/mccmon6/mccmon6.c
index 946b91f3a1..497095572e 100644
--- a/board/liebherr/mccmon6/mccmon6.c
+++ b/board/liebherr/mccmon6/mccmon6.c
@@ -12,17 +12,13 @@
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/mxc_i2c.h>
-#include <asm/mach-imx/spi.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/io.h>
#include <fsl_esdhc.h>
#include <mmc.h>
#include <netdev.h>
-#include <micrel.h>
#include <phy.h>
#include <input.h>
-#include <i2c.h>
#include <spl.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -35,24 +31,11 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
-
-#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
- PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-
#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
-#define ETH_PHY_RESET IMX_GPIO_NR(1, 27)
-#define ECSPI3_CS0 IMX_GPIO_NR(4, 24)
-#define ECSPI3_FLWP IMX_GPIO_NR(4, 27)
#define NOR_WP IMX_GPIO_NR(1, 1)
#define DISPLAY_EN IMX_GPIO_NR(1, 2)
@@ -93,45 +76,11 @@ static iomux_v3_cfg_t const usdhc3_pads[] = {
IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
};
-static iomux_v3_cfg_t const enet_pads[] = {
- IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL
- | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK
- | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL
- | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- /* KSZ9031 PHY Reset */
- IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
static void setup_iomux_uart(void)
{
SETUP_IOMUX_PADS(uart1_pads);
}
-static void setup_iomux_enet(void)
-{
- SETUP_IOMUX_PADS(enet_pads);
-
- /* Reset KSZ9031 PHY */
- gpio_direction_output(ETH_PHY_RESET, 0);
- mdelay(10);
- gpio_set_value(ETH_PHY_RESET, 1);
- udelay(100);
-}
-
static struct fsl_esdhc_cfg usdhc_cfg[2] = {
{USDHC3_BASE_ADDR},
{USDHC2_BASE_ADDR},
@@ -273,74 +222,6 @@ static void setup_eimnor(void)
eimnor_cs_setup();
}
-/* mccmon6 board has SPI Flash is connected to SPI3 */
-int board_spi_cs_gpio(unsigned bus, unsigned cs)
-{
- return (bus == 2 && cs == 0) ? ECSPI3_CS0 : -1;
-}
-
-static iomux_v3_cfg_t const ecspi3_pads[] = {
- /* SPI3 */
- IOMUX_PADS(PAD_DISP0_DAT3__GPIO4_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
- IOMUX_PADS(PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
- IOMUX_PADS(PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
-};
-
-void setup_spi(void)
-{
- SETUP_IOMUX_PADS(ecspi3_pads);
-
- enable_spi_clk(true, 2);
-
- /* set cs0 to high */
- gpio_direction_output(ECSPI3_CS0, 1);
-
- /* set flwp to high */
- gpio_direction_output(ECSPI3_FLWP, 1);
-}
-
-struct i2c_pads_info mx6q_i2c1_pad_info = {
- .scl = {
- .i2c_mode = MX6Q_PAD_CSI0_DAT9__I2C1_SCL
- | MUX_PAD_CTRL(I2C_PAD_CTRL),
- .gpio_mode = MX6Q_PAD_CSI0_DAT9__GPIO5_IO27
- | MUX_PAD_CTRL(I2C_PAD_CTRL),
- .gp = IMX_GPIO_NR(5, 27)
- },
- .sda = {
- .i2c_mode = MX6Q_PAD_CSI0_DAT8__I2C1_SDA
- | MUX_PAD_CTRL(I2C_PAD_CTRL),
- .gpio_mode = MX6Q_PAD_CSI0_DAT8__GPIO5_IO26
- | MUX_PAD_CTRL(I2C_PAD_CTRL),
- .gp = IMX_GPIO_NR(5, 26)
- }
-};
-
-struct i2c_pads_info mx6q_i2c2_pad_info = {
- .scl = {
- .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL
- | MUX_PAD_CTRL(I2C_PAD_CTRL),
- .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12
- | MUX_PAD_CTRL(I2C_PAD_CTRL),
- .gp = IMX_GPIO_NR(4, 12)
- },
- .sda = {
- .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA
- | MUX_PAD_CTRL(I2C_PAD_CTRL),
- .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13
- | MUX_PAD_CTRL(I2C_PAD_CTRL),
- .gp = IMX_GPIO_NR(4, 13)
- }
-};
-
-int board_eth_init(bd_t *bis)
-{
- setup_iomux_enet();
-
- return cpu_eth_init(bis);
-}
-
int board_early_init_f(void)
{
setup_iomux_uart();
@@ -356,10 +237,6 @@ int board_init(void)
gpio_direction_output(DISPLAY_EN, 1);
setup_eimnor();
- setup_spi();
-
- setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c1_pad_info);
- setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info);
return 0;
}
@@ -378,44 +255,6 @@ int checkboard(void)
return 0;
}
-int board_phy_config(struct phy_device *phydev)
-{
- /*
- * Default setting for GMII Clock Pad Skew Register 0x1EF:
- * MMD Address 0x2h, Register 0x8h
- *
- * GTX_CLK Pad Skew 0xF -> 0.9 nsec skew
- * RX_CLK Pad Skew 0xF -> 0.9 nsec skew
- *
- * Adjustment -> write 0x3FF:
- * GTX_CLK Pad Skew 0x1F -> 1.8 nsec skew
- * RX_CLK Pad Skew 0x1F -> 1.8 nsec skew
- *
- */
- ksz9031_phy_extended_write(phydev, 0x2,
- MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
- MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x3FF);
-
- ksz9031_phy_extended_write(phydev, 0x02,
- MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
- MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x00FF);
-
- ksz9031_phy_extended_write(phydev, 0x2,
- MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
- MII_KSZ9031_MOD_DATA_NO_POST_INC,
- 0x3333);
-
- ksz9031_phy_extended_write(phydev, 0x2,
- MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
- MII_KSZ9031_MOD_DATA_NO_POST_INC,
- 0x2052);
-
- if (phydev->drv->config)
- phydev->drv->config(phydev);
-
- return 0;
-}
-
#ifdef CONFIG_SPL_BOARD_INIT
void spl_board_init(void)
{
diff --git a/configs/mccmon6_nor_defconfig b/configs/mccmon6_nor_defconfig
index 18070cd0b1..93290fcbaf 100644
--- a/configs/mccmon6_nor_defconfig
+++ b/configs/mccmon6_nor_defconfig
@@ -9,24 +9,36 @@ CONFIG_SPL=y
# CONFIG_CMD_BMODE is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=1
+CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/liebherr/mccmon6/mon6_imximage_nor.cfg"
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_BOUNCE_BUFFER=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_NOR_SUPPORT=y
+CONFIG_CMD_CLK=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+# CONFIG_CMD_PINMUX is not set
CONFIG_CMD_SF=y
CONFIG_CMD_CACHE=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=8000000.nor"
CONFIG_MTDPARTS_DEFAULT="mtdparts=8000000.nor:32m at 0x0(mccmon6-image.nor),256k at 0x40000(u-boot-env.nor),1m at 0x80000(u-boot.nor),8m at 0x180000(kernel.nor),8m at 0x980000(swupdate-kernel.nor),8m at 0x1180000(swupdate-rootfs.nor),128k at 0x1980000(kernel-dtb.nor),128k at 0x19C0000(swupdate-kernel-dtb.nor)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6q-mccmon6"
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_DM=y
+CONFIG_CLK_IMX6Q=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
@@ -36,13 +48,27 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+# CONFIG_SPL_PMIC_CHILDREN is not set
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
+# CONFIG_SPECIFY_CONSOLE_INDEX is not set
+# CONFIG_SPL_SERIAL_PRESENT is not set
+# CONFIG_TPL_SERIAL_PRESENT is not set
+CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_DM_THERMAL=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/mccmon6_sd_defconfig b/configs/mccmon6_sd_defconfig
index d1d1313e1e..caa8ec70f9 100644
--- a/configs/mccmon6_sd_defconfig
+++ b/configs/mccmon6_sd_defconfig
@@ -10,24 +10,36 @@ CONFIG_SPL=y
# CONFIG_CMD_BMODE is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=1
+CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/liebherr/mccmon6/mon6_imximage_sd.cfg"
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_BOUNCE_BUFFER=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_NOR_SUPPORT=y
+CONFIG_CMD_CLK=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+# CONFIG_CMD_PINMUX is not set
CONFIG_CMD_SF=y
CONFIG_CMD_CACHE=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=8000000.nor"
CONFIG_MTDPARTS_DEFAULT="mtdparts=8000000.nor:32m at 0x0(mccmon6-image.nor),256k at 0x40000(u-boot-env.nor),1m at 0x80000(u-boot.nor),8m at 0x180000(kernel.nor),8m at 0x980000(swupdate-kernel.nor),8m at 0x1180000(swupdate-rootfs.nor),128k at 0x1980000(kernel-dtb.nor),128k at 0x19C0000(swupdate-kernel-dtb.nor)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6q-mccmon6"
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_DM=y
+CONFIG_CLK_IMX6Q=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
@@ -37,13 +49,26 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+# CONFIG_SPL_PMIC_CHILDREN is not set
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
+# CONFIG_SPL_SERIAL_PRESENT is not set
+# CONFIG_TPL_SERIAL_PRESENT is not set
+CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_DM_THERMAL=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h
index 5ca9bc6848..f72d8cba2b 100644
--- a/include/configs/mccmon6.h
+++ b/include/configs/mccmon6.h
@@ -34,27 +34,12 @@
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
-#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT
-
-#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE
#define CONFIG_SYS_MEMTEST_START 0x10000000
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 500 * SZ_1M)
-#define CONFIG_SF_DEFAULT_BUS 2
-#define CONFIG_SF_DEFAULT_CS 0
-#define CONFIG_SF_DEFAULT_SPEED 25000000
-#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
-
-/* I2C Configs */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_SPEED 100000
-
/* MMC Configuration */
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
@@ -71,10 +56,7 @@
#define CONFIG_SYS_FLASH_BANKS_SIZES { (32 * SZ_1M) }
/* Ethernet Configuration */
-#define CONFIG_FEC_MXC
#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RGMII
-#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 1
#define CONFIG_EXTRA_ENV_SETTINGS \
--
2.11.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [U-Boot] [PATCH v2 11/17] ARM: imx: Decouple mccmon6's SPL and u-boot proper code
2019-01-31 9:03 [U-Boot] [PATCH v2 00/17] imx: dm: Update mccmon6 board to only use DM/DTS in u-boot proper Lukasz Majewski
` (9 preceding siblings ...)
2019-01-31 9:03 ` [U-Boot] [PATCH v2 10/17] ARM: imx: Covnert mccmon6 to use DM/DTS in the u-boot proper Lukasz Majewski
@ 2019-01-31 9:03 ` Lukasz Majewski
2019-01-31 9:03 ` [U-Boot] [PATCH v2 12/17] ARM: imx: Disable 1Gbps support on MCCMON6's KSZ9031 PHY Lukasz Majewski
` (5 subsequent siblings)
16 siblings, 0 replies; 24+ messages in thread
From: Lukasz Majewski @ 2019-01-31 9:03 UTC (permalink / raw)
To: u-boot
The mccmon6 has been used a "mixed" approach between SPL and u-boot
proper sources.
This commit decoupes SPL and u-boot proper, which allows clear
distinction between those two code bases and facilitates conversion
to DM/DTS on this particular board.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
---
Changes in v2: None
board/liebherr/mccmon6/Makefile | 7 +-
board/liebherr/mccmon6/mccmon6.c | 285 ---------------------------------------
board/liebherr/mccmon6/spl.c | 266 +++++++++++++++++++++++++++++++++++-
3 files changed, 268 insertions(+), 290 deletions(-)
diff --git a/board/liebherr/mccmon6/Makefile b/board/liebherr/mccmon6/Makefile
index ead6750ebf..3c9786c6b7 100644
--- a/board/liebherr/mccmon6/Makefile
+++ b/board/liebherr/mccmon6/Makefile
@@ -2,5 +2,8 @@
#
# (C) Copyright 2016-2017
# Lukasz Majewski, DENX Software Engineering, lukma at denx.de
-
-obj-y := mccmon6.o spl.o
+ifdef CONFIG_SPL_BUILD
+obj-y := spl.o
+else
+obj-y := mccmon6.o
+endif
diff --git a/board/liebherr/mccmon6/mccmon6.c b/board/liebherr/mccmon6/mccmon6.c
index 497095572e..33b28aca11 100644
--- a/board/liebherr/mccmon6/mccmon6.c
+++ b/board/liebherr/mccmon6/mccmon6.c
@@ -8,37 +8,11 @@
#include <asm/arch/clock.h>
#include <asm/arch/iomux.h>
#include <asm/arch/imx-regs.h>
-#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/boot_mode.h>
-#include <asm/io.h>
-#include <fsl_esdhc.h>
-#include <mmc.h>
-#include <netdev.h>
-#include <phy.h>
-#include <input.h>
-#include <spl.h>
DECLARE_GLOBAL_DATA_PTR;
-#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
- PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
- PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
- PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
-
-#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
-#define NOR_WP IMX_GPIO_NR(1, 1)
-#define DISPLAY_EN IMX_GPIO_NR(1, 2)
-
int dram_init(void)
{
gd->ram_size = imx_ddr_size();
@@ -46,198 +20,11 @@ int dram_init(void)
return 0;
}
-static iomux_v3_cfg_t const uart1_pads[] = {
- IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
- IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
-};
-
-static iomux_v3_cfg_t const usdhc2_pads[] = {
- IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- /* Carrier MicroSD Card Detect */
- IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-static iomux_v3_cfg_t const usdhc3_pads[] = {
- IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-};
-
-static void setup_iomux_uart(void)
-{
- SETUP_IOMUX_PADS(uart1_pads);
-}
-
-static struct fsl_esdhc_cfg usdhc_cfg[2] = {
- {USDHC3_BASE_ADDR},
- {USDHC2_BASE_ADDR},
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- int ret = 0;
-
- switch (cfg->esdhc_base) {
- case USDHC2_BASE_ADDR:
- ret = !gpio_get_value(USDHC2_CD_GPIO);
- break;
- case USDHC3_BASE_ADDR:
- /*
- * eMMC don't have card detect pin - since it is soldered to the
- * PCB board
- */
- ret = 1;
- break;
- }
- return ret;
-}
-
-int board_mmc_init(bd_t *bis)
-{
- int ret;
- u32 index = 0;
-
- /*
- * MMC MAP
- * (U-Boot device node) (Physical Port)
- * mmc0 Soldered on board eMMC device
- * mmc1 MicroSD card
- */
- for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
- switch (index) {
- case 0:
- SETUP_IOMUX_PADS(usdhc3_pads);
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
- usdhc_cfg[0].max_bus_width = 8;
- break;
- case 1:
- SETUP_IOMUX_PADS(usdhc2_pads);
- usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
- usdhc_cfg[1].max_bus_width = 4;
- gpio_direction_input(USDHC2_CD_GPIO);
- break;
- default:
- printf("Warning: More USDHC controllers (%d) than supported (%d)\n",
- index + 1, CONFIG_SYS_FSL_USDHC_NUM);
- return -EINVAL;
- }
-
- ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
- if (ret)
- return ret;
- }
-
- return 0;
-}
-
-static iomux_v3_cfg_t const eimnor_pads[] = {
- IOMUX_PADS(PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D18__EIM_DATA18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D19__EIM_DATA19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D20__EIM_DATA20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D21__EIM_DATA21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D22__EIM_DATA22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D23__EIM_DATA23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D24__EIM_DATA24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D25__EIM_DATA25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D26__EIM_DATA26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D27__EIM_DATA27 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D28__EIM_DATA28 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D29__EIM_DATA29 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D30__EIM_DATA30 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D31__EIM_DATA31 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_DA0__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_DA1__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_DA2__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_DA3__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_DA4__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_DA5__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_DA6__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_DA7__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_DA8__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_DA9__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_DA10__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_DA11__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_DA12__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_DA13__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_DA14__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_DA15__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_A16__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_A17__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_A18__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_A19__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_A20__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_A21__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_A22__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_A23__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_A24__EIM_ADDR24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_A25__EIM_ADDR25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_OE__EIM_OE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_RW__EIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_CS0__EIM_CS0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-static void eimnor_cs_setup(void)
-{
- struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
-
-
- /* NOR configuration */
- writel(0x00620181, &weim_regs->cs0gcr1);
- writel(0x00000001, &weim_regs->cs0gcr2);
- writel(0x0b020000, &weim_regs->cs0rcr1);
- writel(0x0000b000, &weim_regs->cs0rcr2);
- writel(0x0804a240, &weim_regs->cs0wcr1);
- writel(0x00000000, &weim_regs->cs0wcr2);
-
- writel(0x00000120, &weim_regs->wcr);
- writel(0x00000010, &weim_regs->wiar);
- writel(0x00000000, &weim_regs->ear);
-
- set_chipselect_size(CS0_128);
-}
-
-static void setup_eimnor(void)
-{
- SETUP_IOMUX_PADS(eimnor_pads);
- gpio_direction_output(NOR_WP, 1);
-
- enable_eim_clk(1);
- eimnor_cs_setup();
-}
-
-int board_early_init_f(void)
-{
- setup_iomux_uart();
-
- return 0;
-}
-
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
- gpio_direction_output(DISPLAY_EN, 1);
-
- setup_eimnor();
-
return 0;
}
@@ -254,75 +41,3 @@ int checkboard(void)
return 0;
}
-
-#ifdef CONFIG_SPL_BOARD_INIT
-void spl_board_init(void)
-{
- setup_eimnor();
-
- gpio_direction_output(DISPLAY_EN, 1);
-}
-#endif /* CONFIG_SPL_BOARD_INIT */
-
-#ifdef CONFIG_SPL_BUILD
-void board_boot_order(u32 *spl_boot_list)
-{
- switch (spl_boot_device()) {
- case BOOT_DEVICE_MMC2:
- case BOOT_DEVICE_MMC1:
- spl_boot_list[0] = BOOT_DEVICE_MMC2;
- spl_boot_list[1] = BOOT_DEVICE_MMC1;
- break;
-
- case BOOT_DEVICE_NOR:
- spl_boot_list[0] = BOOT_DEVICE_NOR;
- break;
- }
-}
-#endif /* CONFIG_SPL_BUILD */
-
-#ifdef CONFIG_SPL_OS_BOOT
-int spl_start_uboot(void)
-{
- char s[16];
- int ret;
- /*
- * We use BOOT_DEVICE_MMC1, but SD card is connected
- * to MMC2
- *
- * Correct "mapping" is delivered in board defined
- * board_boot_order() function.
- *
- * SD card boot is regarded as a "development" one,
- * hence we _always_ go through the u-boot.
- *
- */
- if (spl_boot_device() == BOOT_DEVICE_MMC1)
- return 1;
-
- /* break into full u-boot on 'c' */
- if (serial_tstc() && serial_getc() == 'c')
- return 1;
-
- env_init();
- ret = env_get_f("boot_os", s, sizeof(s));
- if ((ret != -1) && (strcmp(s, "no") == 0))
- return 1;
-
- /*
- * Check if SWUpdate recovery needs to be started
- *
- * recovery_status = NULL (not set - ret == -1) -> normal operation
- *
- * recovery_status = progress or
- * recovery_status = failed or
- * recovery_status = <any value> -> start SWUpdate
- *
- */
- ret = env_get_f("recovery_status", s, sizeof(s));
- if (ret != -1)
- return 1;
-
- return 0;
-}
-#endif /* CONFIG_SPL_OS_BOOT */
diff --git a/board/liebherr/mccmon6/spl.c b/board/liebherr/mccmon6/spl.c
index acfc4902c1..afd080fe26 100644
--- a/board/liebherr/mccmon6/spl.c
+++ b/board/liebherr/mccmon6/spl.c
@@ -20,7 +20,6 @@
#include <asm/arch/sys_proto.h>
#include <spl.h>
-#if defined(CONFIG_SPL_BUILD)
#include <asm/arch/mx6-ddr.h>
/*
* Driving strength:
@@ -274,6 +273,20 @@ static void spl_dram_init(void)
udelay(100);
}
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+ IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+ IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
+static void setup_iomux_uart(void)
+{
+ SETUP_IOMUX_PADS(uart1_pads);
+}
+
void board_init_f(ulong dummy)
{
ccgr_init();
@@ -284,7 +297,7 @@ void board_init_f(ulong dummy)
gpr_init();
/* iomux */
- board_early_init_f();
+ setup_iomux_uart();
/* setup GP timer */
timer_init();
@@ -295,4 +308,251 @@ void board_init_f(ulong dummy)
/* DDR initialization */
spl_dram_init();
}
-#endif
+
+void board_boot_order(u32 *spl_boot_list)
+{
+ switch (spl_boot_device()) {
+ case BOOT_DEVICE_MMC2:
+ case BOOT_DEVICE_MMC1:
+ spl_boot_list[0] = BOOT_DEVICE_MMC2;
+ spl_boot_list[1] = BOOT_DEVICE_MMC1;
+ break;
+
+ case BOOT_DEVICE_NOR:
+ spl_boot_list[0] = BOOT_DEVICE_NOR;
+ break;
+ }
+}
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+ char s[16];
+ int ret;
+ /*
+ * We use BOOT_DEVICE_MMC1, but SD card is connected
+ * to MMC2
+ *
+ * Correct "mapping" is delivered in board defined
+ * board_boot_order() function.
+ *
+ * SD card boot is regarded as a "development" one,
+ * hence we _always_ go through the u-boot.
+ *
+ */
+ if (spl_boot_device() == BOOT_DEVICE_MMC1)
+ return 1;
+
+ /* break into full u-boot on 'c' */
+ if (serial_tstc() && serial_getc() == 'c')
+ return 1;
+
+ env_init();
+ ret = env_get_f("boot_os", s, sizeof(s));
+ if ((ret != -1) && (strcmp(s, "no") == 0))
+ return 1;
+
+ /*
+ * Check if SWUpdate recovery needs to be started
+ *
+ * recovery_status = NULL (not set - ret == -1) -> normal operation
+ *
+ * recovery_status = progress or
+ * recovery_status = failed or
+ * recovery_status = <any value> -> start SWUpdate
+ *
+ */
+ ret = env_get_f("recovery_status", s, sizeof(s));
+ if (ret != -1)
+ return 1;
+
+ return 0;
+}
+#endif /* CONFIG_SPL_OS_BOOT */
+
+#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define NOR_WP IMX_GPIO_NR(1, 1)
+
+static iomux_v3_cfg_t const eimnor_pads[] = {
+ IOMUX_PADS(PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D18__EIM_DATA18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D19__EIM_DATA19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D20__EIM_DATA20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D21__EIM_DATA21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D22__EIM_DATA22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D23__EIM_DATA23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D24__EIM_DATA24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D25__EIM_DATA25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D26__EIM_DATA26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D27__EIM_DATA27 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D28__EIM_DATA28 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D29__EIM_DATA29 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D30__EIM_DATA30 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D31__EIM_DATA31 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA0__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA1__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA2__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA3__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA4__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA5__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA6__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA7__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA8__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA9__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA10__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA11__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA12__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA13__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA14__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA15__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A16__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A17__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A18__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A19__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A20__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A21__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A22__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A23__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A24__EIM_ADDR24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A25__EIM_ADDR25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_OE__EIM_OE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_RW__EIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_CS0__EIM_CS0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static void eimnor_cs_setup(void)
+{
+ struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
+
+ /* NOR configuration */
+ writel(0x00620181, &weim_regs->cs0gcr1);
+ writel(0x00000001, &weim_regs->cs0gcr2);
+ writel(0x0b020000, &weim_regs->cs0rcr1);
+ writel(0x0000b000, &weim_regs->cs0rcr2);
+ writel(0x0804a240, &weim_regs->cs0wcr1);
+ writel(0x00000000, &weim_regs->cs0wcr2);
+
+ writel(0x00000120, &weim_regs->wcr);
+ writel(0x00000010, &weim_regs->wiar);
+ writel(0x00000000, &weim_regs->ear);
+
+ set_chipselect_size(CS0_128);
+}
+
+static void setup_eimnor(void)
+{
+ SETUP_IOMUX_PADS(eimnor_pads);
+ gpio_direction_output(NOR_WP, 1);
+
+ enable_eim_clk(1);
+ eimnor_cs_setup();
+}
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+ IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ /* Carrier MicroSD Card Detect */
+ IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+ IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+};
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+ {USDHC3_BASE_ADDR},
+ {USDHC2_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ case USDHC2_BASE_ADDR:
+ ret = !gpio_get_value(USDHC2_CD_GPIO);
+ break;
+ case USDHC3_BASE_ADDR:
+ /*
+ * eMMC don't have card detect pin - since it is soldered to the
+ * PCB board
+ */
+ ret = 1;
+ break;
+ }
+ return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ int ret;
+ u32 index = 0;
+
+ /*
+ * MMC MAP
+ * (U-Boot device node) (Physical Port)
+ * mmc0 Soldered on board eMMC device
+ * mmc1 MicroSD card
+ */
+ for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
+ switch (index) {
+ case 0:
+ SETUP_IOMUX_PADS(usdhc3_pads);
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ usdhc_cfg[0].max_bus_width = 8;
+ break;
+ case 1:
+ SETUP_IOMUX_PADS(usdhc2_pads);
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ usdhc_cfg[1].max_bus_width = 4;
+ gpio_direction_input(USDHC2_CD_GPIO);
+ break;
+ default:
+ printf("Warning: More USDHC controllers (%d) than supported (%d)\n",
+ index + 1, CONFIG_SYS_FSL_USDHC_NUM);
+ return -EINVAL;
+ }
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_SPL_BOARD_INIT
+#define DISPLAY_EN IMX_GPIO_NR(1, 2)
+void spl_board_init(void)
+{
+ setup_eimnor();
+
+ gpio_direction_output(DISPLAY_EN, 1);
+}
+#endif /* CONFIG_SPL_BOARD_INIT */
--
2.11.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [U-Boot] [PATCH v2 12/17] ARM: imx: Disable 1Gbps support on MCCMON6's KSZ9031 PHY
2019-01-31 9:03 [U-Boot] [PATCH v2 00/17] imx: dm: Update mccmon6 board to only use DM/DTS in u-boot proper Lukasz Majewski
` (10 preceding siblings ...)
2019-01-31 9:03 ` [U-Boot] [PATCH v2 11/17] ARM: imx: Decouple mccmon6's SPL and u-boot proper code Lukasz Majewski
@ 2019-01-31 9:03 ` Lukasz Majewski
2019-01-31 9:03 ` [U-Boot] [PATCH v2 13/17] Kconfig: Make CMD_SPL_NAND_OFS only available when proper memory is used Lukasz Majewski
` (4 subsequent siblings)
16 siblings, 0 replies; 24+ messages in thread
From: Lukasz Majewski @ 2019-01-31 9:03 UTC (permalink / raw)
To: u-boot
mccmon6 works in 10/100 MiB Ethernet environment, so disabling 1GiB support
improves robustness of the network after power up (as one don't need to
wait for autoneg).
Signed-off-by: Lukasz Majewski <lukma@denx.de>
---
Changes in v2:
- Port the Common Clock Framework from Linux to U-boot (tag: 5.0-rc3)
include/configs/mccmon6.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h
index f72d8cba2b..b25aacbf41 100644
--- a/include/configs/mccmon6.h
+++ b/include/configs/mccmon6.h
@@ -65,6 +65,7 @@
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"boot_os=yes\0" \
+ "disable_giga=yes\0" \
"download_kernel=" \
"tftpboot ${kernel_addr} ${kernel_file};" \
"tftpboot ${fdt_addr} ${fdtfile};\0" \
--
2.11.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [U-Boot] [PATCH v2 13/17] Kconfig: Make CMD_SPL_NAND_OFS only available when proper memory is used
2019-01-31 9:03 [U-Boot] [PATCH v2 00/17] imx: dm: Update mccmon6 board to only use DM/DTS in u-boot proper Lukasz Majewski
` (11 preceding siblings ...)
2019-01-31 9:03 ` [U-Boot] [PATCH v2 12/17] ARM: imx: Disable 1Gbps support on MCCMON6's KSZ9031 PHY Lukasz Majewski
@ 2019-01-31 9:03 ` Lukasz Majewski
2019-01-31 9:03 ` [U-Boot] [PATCH v2 14/17] Kconfig: cosmetic: Update description of CMD_SPL_NAND_OFS Lukasz Majewski
` (3 subsequent siblings)
16 siblings, 0 replies; 24+ messages in thread
From: Lukasz Majewski @ 2019-01-31 9:03 UTC (permalink / raw)
To: u-boot
This commit makes the CMD_SPL_NAND_OFS only visible when we use NAND
memory.
Before this change it was present when only CMD_SPL was enabled (and
would stay when board with other falcon boot medium is used).
Signed-off-by: Lukasz Majewski <lukma@denx.de>
---
Changes in v2: None
cmd/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/cmd/Kconfig b/cmd/Kconfig
index ea1a325eb3..bc08b935a5 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -316,6 +316,7 @@ config CMD_SPL
config CMD_SPL_NAND_OFS
hex "Offset of OS command line args for Falcon-mode NAND boot"
depends on CMD_SPL
+ depends on CMD_SPL && (TPL_NAND_SUPPORT || SPL_NAND_SUPPORT)
default 0
help
This provides the offset of the command line arguments for Linux
--
2.11.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [U-Boot] [PATCH v2 14/17] Kconfig: cosmetic: Update description of CMD_SPL_NAND_OFS
2019-01-31 9:03 [U-Boot] [PATCH v2 00/17] imx: dm: Update mccmon6 board to only use DM/DTS in u-boot proper Lukasz Majewski
` (12 preceding siblings ...)
2019-01-31 9:03 ` [U-Boot] [PATCH v2 13/17] Kconfig: Make CMD_SPL_NAND_OFS only available when proper memory is used Lukasz Majewski
@ 2019-01-31 9:03 ` Lukasz Majewski
2019-01-31 9:03 ` [U-Boot] [PATCH v2 15/17] Kconfig: Add CMD_SPL_NOR_OFS config for falcon boot argument offset Lukasz Majewski
` (2 subsequent siblings)
16 siblings, 0 replies; 24+ messages in thread
From: Lukasz Majewski @ 2019-01-31 9:03 UTC (permalink / raw)
To: u-boot
The CMD_SPL_NAND_OFS description was a bit misleading, has
been updated.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
---
Changes in v2: None
cmd/Kconfig | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/cmd/Kconfig b/cmd/Kconfig
index bc08b935a5..f9a668b80f 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -314,8 +314,7 @@ config CMD_SPL
command.
config CMD_SPL_NAND_OFS
- hex "Offset of OS command line args for Falcon-mode NAND boot"
- depends on CMD_SPL
+ hex "Offset of OS args or dtb for Falcon-mode NAND boot"
depends on CMD_SPL && (TPL_NAND_SUPPORT || SPL_NAND_SUPPORT)
default 0
help
--
2.11.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [U-Boot] [PATCH v2 15/17] Kconfig: Add CMD_SPL_NOR_OFS config for falcon boot argument offset
2019-01-31 9:03 [U-Boot] [PATCH v2 00/17] imx: dm: Update mccmon6 board to only use DM/DTS in u-boot proper Lukasz Majewski
` (13 preceding siblings ...)
2019-01-31 9:03 ` [U-Boot] [PATCH v2 14/17] Kconfig: cosmetic: Update description of CMD_SPL_NAND_OFS Lukasz Majewski
@ 2019-01-31 9:03 ` Lukasz Majewski
2019-01-31 9:03 ` [U-Boot] [PATCH v2 16/17] doc: Update parallel NOR flash related information in README.falcon Lukasz Majewski
2019-01-31 9:03 ` [U-Boot] [PATCH v2 17/17] imx: Convert mccmon6 to use fitImage instead of uImage+DTB Lukasz Majewski
16 siblings, 0 replies; 24+ messages in thread
From: Lukasz Majewski @ 2019-01-31 9:03 UTC (permalink / raw)
To: u-boot
This option will provide the offset in the parallel NOR flash memory to,
which the falcon boot data is stored.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
---
Changes in v2: None
cmd/Kconfig | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/cmd/Kconfig b/cmd/Kconfig
index f9a668b80f..e37d28e86a 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -323,6 +323,14 @@ config CMD_SPL_NAND_OFS
for full information about how to use this option (and also see
board/gateworks/gw_ventana/README for an example).
+config CMD_SPL_NOR_OFS
+ hex "Offset of OS args or dtb for Falcon-mode NOR boot"
+ depends on CMD_SPL && SPL_NOR_SUPPORT
+ default 0
+ help
+ This provides the offset of the command line arguments or dtb for
+ Linux when booting from NOR in Falcon mode.
+
config CMD_SPL_WRITE_SIZE
hex "Size of argument area"
depends on CMD_SPL
--
2.11.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [U-Boot] [PATCH v2 16/17] doc: Update parallel NOR flash related information in README.falcon
2019-01-31 9:03 [U-Boot] [PATCH v2 00/17] imx: dm: Update mccmon6 board to only use DM/DTS in u-boot proper Lukasz Majewski
` (14 preceding siblings ...)
2019-01-31 9:03 ` [U-Boot] [PATCH v2 15/17] Kconfig: Add CMD_SPL_NOR_OFS config for falcon boot argument offset Lukasz Majewski
@ 2019-01-31 9:03 ` Lukasz Majewski
2019-01-31 9:03 ` [U-Boot] [PATCH v2 17/17] imx: Convert mccmon6 to use fitImage instead of uImage+DTB Lukasz Majewski
16 siblings, 0 replies; 24+ messages in thread
From: Lukasz Majewski @ 2019-01-31 9:03 UTC (permalink / raw)
To: u-boot
This commit updates the doc/README.falcon regarding Falcon boot on
NOR flash memories.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
---
Changes in v2: None
doc/README.falcon | 3 +++
1 file changed, 3 insertions(+)
diff --git a/doc/README.falcon b/doc/README.falcon
index 9a7f0bc235..204f4b12b6 100644
--- a/doc/README.falcon
+++ b/doc/README.falcon
@@ -67,6 +67,9 @@ CONFIG_SYS_NAND_SPL_KERNEL_OFFS Offset in NAND where the kernel is stored
CONFIG_CMD_SPL_NAND_OFS Offset in NAND where the parameters area was saved.
+CONFIG_CMD_SPL_NOR_OFS Offset in NOR where the parameters area was saved.
+ (Please refer to MCCMON6 board's configuraiton)
+
CONFIG_CMD_SPL_WRITE_SIZE Size of the parameters area to be copied
CONFIG_SPL_OS_BOOT Activate Falcon Mode.
--
2.11.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [U-Boot] [PATCH v2 17/17] imx: Convert mccmon6 to use fitImage instead of uImage+DTB
2019-01-31 9:03 [U-Boot] [PATCH v2 00/17] imx: dm: Update mccmon6 board to only use DM/DTS in u-boot proper Lukasz Majewski
` (15 preceding siblings ...)
2019-01-31 9:03 ` [U-Boot] [PATCH v2 16/17] doc: Update parallel NOR flash related information in README.falcon Lukasz Majewski
@ 2019-01-31 9:03 ` Lukasz Majewski
16 siblings, 0 replies; 24+ messages in thread
From: Lukasz Majewski @ 2019-01-31 9:03 UTC (permalink / raw)
To: u-boot
This commit enabled support for fitImage on mccmon6 when we
switch to DT/DTS.
Moreover, it provides Falcon boot functionality to parallel
NOR flash memories (spl_nor.c).
Signed-off-by: Lukasz Majewski <lukma@denx.de>
---
Changes in v2: None
board/liebherr/mccmon6/spl.c | 7 ++++++
common/spl/spl_nor.c | 5 ++++
configs/mccmon6_nor_defconfig | 8 +++++-
configs/mccmon6_sd_defconfig | 6 ++++-
include/configs/mccmon6.h | 57 +++++++++++++++++--------------------------
5 files changed, 47 insertions(+), 36 deletions(-)
diff --git a/board/liebherr/mccmon6/spl.c b/board/liebherr/mccmon6/spl.c
index afd080fe26..c5cfea2a55 100644
--- a/board/liebherr/mccmon6/spl.c
+++ b/board/liebherr/mccmon6/spl.c
@@ -324,6 +324,13 @@ void board_boot_order(u32 *spl_boot_list)
}
}
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ return 0;
+}
+#endif
+
#ifdef CONFIG_SPL_OS_BOOT
int spl_start_uboot(void)
{
diff --git a/common/spl/spl_nor.c b/common/spl/spl_nor.c
index 969e319de0..c9364072f3 100644
--- a/common/spl/spl_nor.c
+++ b/common/spl/spl_nor.c
@@ -48,6 +48,11 @@ static int spl_nor_load_image(struct spl_image_info *spl_image,
CONFIG_SYS_OS_BASE,
(void *)header);
+#ifdef CONFIG_SYS_SPL_ARGS_ADDR
+ memcpy((void *)CONFIG_SYS_SPL_ARGS_ADDR,
+ (void *)CONFIG_CMD_SPL_NOR_OFS,
+ CONFIG_CMD_SPL_WRITE_SIZE);
+#endif
return ret;
}
#endif
diff --git a/configs/mccmon6_nor_defconfig b/configs/mccmon6_nor_defconfig
index 93290fcbaf..c69e482eef 100644
--- a/configs/mccmon6_nor_defconfig
+++ b/configs/mccmon6_nor_defconfig
@@ -10,12 +10,18 @@ CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/liebherr/mccmon6/mon6_imximage_nor.cfg"
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_BOUNCE_BUFFER=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_NOR_SUPPORT=y
+CONFIG_SPL_OS_BOOT=y
+CONFIG_SYS_OS_BASE=0x8180000
+CONFIG_CMD_SPL=y
+CONFIG_CMD_SPL_NOR_OFS=0x09600000
+CONFIG_CMD_SPL_WRITE_SIZE=0x20000
CONFIG_CMD_CLK=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
@@ -28,7 +34,7 @@ CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=8000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=8000000.nor:32m at 0x0(mccmon6-image.nor),256k at 0x40000(u-boot-env.nor),1m at 0x80000(u-boot.nor),8m at 0x180000(kernel.nor),8m at 0x980000(swupdate-kernel.nor),8m at 0x1180000(swupdate-rootfs.nor),128k at 0x1980000(kernel-dtb.nor),128k at 0x19C0000(swupdate-kernel-dtb.nor)"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=8000000.nor:32m at 0x0(mccmon6-image.nor),256k at 0x40000(u-boot-env.nor),1m at 0x80000(u-boot.nor),8m at 0x180000(kernel.nor),8m at 0x980000(swupdate-kernel.nor),8m at 0x1180000(swupdate-rootfs.nor)"
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-mccmon6"
CONFIG_ENV_IS_IN_FLASH=y
diff --git a/configs/mccmon6_sd_defconfig b/configs/mccmon6_sd_defconfig
index caa8ec70f9..cb0f5698b1 100644
--- a/configs/mccmon6_sd_defconfig
+++ b/configs/mccmon6_sd_defconfig
@@ -11,12 +11,16 @@ CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/liebherr/mccmon6/mon6_imximage_sd.cfg"
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_BOUNCE_BUFFER=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_NOR_SUPPORT=y
+CONFIG_CMD_SPL=y
+CONFIG_CMD_SPL_NOR_OFS=0x09600000
+CONFIG_CMD_SPL_WRITE_SIZE=0x20000
CONFIG_CMD_CLK=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
@@ -29,7 +33,7 @@ CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=8000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=8000000.nor:32m at 0x0(mccmon6-image.nor),256k at 0x40000(u-boot-env.nor),1m at 0x80000(u-boot.nor),8m at 0x180000(kernel.nor),8m at 0x980000(swupdate-kernel.nor),8m at 0x1180000(swupdate-rootfs.nor),128k at 0x1980000(kernel-dtb.nor),128k at 0x19C0000(swupdate-kernel-dtb.nor)"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=8000000.nor:32m at 0x0(mccmon6-image.nor),256k at 0x40000(u-boot-env.nor),1m at 0x80000(u-boot.nor),8m at 0x180000(kernel.nor),8m at 0x980000(swupdate-kernel.nor),8m at 0x1180000(swupdate-rootfs.nor)"
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-mccmon6"
CONFIG_ENV_IS_IN_FLASH=y
diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h
index b25aacbf41..c685de6551 100644
--- a/include/configs/mccmon6.h
+++ b/include/configs/mccmon6.h
@@ -14,10 +14,6 @@
#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + 0x80000)
-#define CONFIG_SPL_OS_BOOT
-#define CONFIG_SYS_OS_BASE (CONFIG_SYS_FLASH_BASE + 0x180000)
-#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + 0x1980000)
-#define CONFIG_SYS_FDT_SIZE (48 * SZ_1K)
#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000
/*
@@ -28,8 +24,7 @@
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR (0x800)
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (0x80)
#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR (0x1000)
-#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
-#define CONFIG_SPL_FS_LOAD_ARGS_NAME "imx6q-mccmon.dtb"
+#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "fitImage"
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
@@ -61,14 +56,13 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"console=ttymxc0,115200 quiet\0" \
- "fdtfile=imx6q-mccmon6.dtb\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"boot_os=yes\0" \
+ "kernelsize=0x300000\0" \
"disable_giga=yes\0" \
"download_kernel=" \
- "tftpboot ${kernel_addr} ${kernel_file};" \
- "tftpboot ${fdt_addr} ${fdtfile};\0" \
+ "tftpboot ${loadaddr} ${kernel_file};\0" \
"get_boot_medium=" \
"setenv boot_medium nor;" \
"setexpr.l _src_sbmr1 *0x020d8004;" \
@@ -76,10 +70,7 @@
"if test ${_b_medium} = 40; then " \
"setenv boot_medium sdcard;" \
"fi\0" \
- "kernel_file=uImage\0" \
- "load_kernel=" \
- "load mmc ${bootdev}:${bootpart} ${kernel_addr} uImage;" \
- "load mmc ${bootdev}:${bootpart} ${fdt_addr} ${fdtfile};\0" \
+ "kernel_file=fitImage\0" \
"boot_sd=" \
"echo '#######################';" \
"echo '# Factory SDcard Boot #';" \
@@ -90,12 +81,11 @@
"run factory_flash_img;\0" \
"boot_nor=" \
"setenv kernelnor 0x08180000;" \
- "setenv dtbnor 0x09980000;" \
"setenv bootargs console=${console} " \
CONFIG_MTDPARTS_DEFAULT " " \
"root=/dev/mmcblk1 rootfstype=ext4 rw rootwait noinitrd;" \
- "cp.l ${dtbnor} ${dtbloadaddr} 0x8000;" \
- "bootm ${kernelnor} - ${dtbloadaddr};\0" \
+ "cp.l ${kernelnor} ${loadaddr} ${kernelsize};" \
+ "bootm ${loadaddr};reset;\0" \
"boot_recovery=" \
"echo '#######################';" \
"echo '# RECOVERY SWU Boot #';" \
@@ -103,14 +93,13 @@
"setenv rootfsloadaddr 0x13000000;" \
"setenv swukernelnor 0x08980000;" \
"setenv swurootfsnor 0x09180000;" \
- "setenv swudtbnor 0x099A0000;" \
"setenv bootargs console=${console} " \
CONFIG_MTDPARTS_DEFAULT " " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}::off root=/dev/ram rw;" \
"cp.l ${swurootfsnor} ${rootfsloadaddr} 0x200000;" \
- "cp.l ${swudtbnor} ${dtbloadaddr} 0x8000;" \
- "bootm ${swukernelnor} ${rootfsloadaddr} ${dtbloadaddr};\0" \
+ "cp.l ${swukernelnor} ${loadaddr} ${kernelsize};" \
+ "bootm ${loadaddr} ${rootfsloadaddr};reset;\0" \
"boot_tftp=" \
"echo '#######################';" \
"echo '# TFTP Boot #';" \
@@ -118,7 +107,7 @@
"if run download_kernel; then " \
"setenv bootargs console=${console} " \
"root=/dev/mmcblk0p2 rootwait;" \
- "bootm ${kernel_addr} - ${fdt_addr};" \
+ "bootm $loadaddr};reset;" \
"fi\0" \
"bootcmd=" \
"if test -n ${recovery_status}; then " \
@@ -138,13 +127,10 @@
"fi;" \
"fi\0" \
"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
- "fdt_addr=0x18000000\0" \
"bootdev=1\0" \
"bootpart=1\0" \
- "kernel_addr=" __stringify(CONFIG_LOADADDR) "\0" \
"netdev=eth0\0" \
"load_addr=0x11000000\0" \
- "dtbloadaddr=0x12000000\0" \
"uboot_file=u-boot.img\0" \
"SPL_file=SPL\0" \
"load_uboot=tftp ${load_addr} ${uboot_file}\0" \
@@ -171,6 +157,7 @@
"device ${mmcdev};" \
"run factory_nor_img;" \
"run factory_eMMC_img;" \
+ "run factory_SPL_falcon_setup;" \
"fi\0" \
"factory_eMMC_img="\
"echo 'Update mccmon6 eMMC image'; " \
@@ -192,6 +179,16 @@
"erase ${nor_bank_start} +${nor_img_size};" \
"setexpr nor_img_size ${nor_img_size} / 4; " \
"cp.l ${nor_img_addr} ${nor_bank_start} ${nor_img_size}\0" \
+ "factory_SPL_falcon_setup="\
+ "echo 'Write Falcon boot data'; " \
+ "setenv kernelnor 0x08180000;" \
+ "cp.l ${kernelnor} ${loadaddr} ${kernelsize};" \
+ "spl export fdt ${loadaddr};" \
+ "setenv nor_img_addr ${fdtargsaddr};" \
+ "setenv nor_img_size 0x20000;" \
+ "setenv nor_bank_start " \
+ __stringify(CONFIG_CMD_SPL_NOR_OFS)";" \
+ "run nor_update\0" \
"tftp_nor_uboot="\
"echo 'Update mccmon6 NOR U-BOOT via TFTP'; " \
"setenv nor_img_file u-boot.img; " \
@@ -200,22 +197,14 @@
"if tftpboot ${nor_img_addr} ${nor_img_file}; then " \
"run nor_update;" \
"fi\0" \
- "tftp_nor_uImg="\
- "echo 'Update mccmon6 NOR uImage via TFTP'; " \
- "setenv nor_img_file uImage; " \
+ "tftp_nor_fitImg="\
+ "echo 'Update mccmon6 NOR fitImage via TFTP'; " \
+ "setenv nor_img_file fitImage; " \
"setenv nor_img_size 0x500000; " \
"setenv nor_bank_start 0x08180000; " \
"if tftpboot ${nor_img_addr} ${nor_img_file}; then " \
"run nor_update;" \
"fi\0" \
- "tftp_nor_dtb="\
- "echo 'Update mccmon6 NOR DTB via TFTP'; " \
- "setenv nor_img_file imx6q-mccmon6.dtb; " \
- "setenv nor_img_size 0x20000; " \
- "setenv nor_bank_start 0x09980000; " \
- "if tftpboot ${nor_img_addr} ${nor_img_file}; then " \
- "run nor_update;" \
- "fi\0" \
"tftp_nor_img="\
"echo 'Update mccmon6 NOR image via TFTP'; " \
"if tftpboot ${nor_img_addr} ${nor_img_file}; then " \
--
2.11.0
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