From: Michael Trimarchi <michael@amarulasolutions.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [RFC PATCH 3/3] sunxi: Fix A33 memory initialization
Date: Tue, 12 Feb 2019 17:57:08 +0100 [thread overview]
Message-ID: <20190212165708.23040-3-michael@amarulasolutions.com> (raw)
In-Reply-To: <20190212165708.23040-1-michael@amarulasolutions.com>
Set two rank timing and exit self-refresh timing seems not done
properly. We know use the same write that we are using
on H5 silicon.
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
---
arch/arm/mach-sunxi/dram_sun8i_a33.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-sunxi/dram_sun8i_a33.c b/arch/arm/mach-sunxi/dram_sun8i_a33.c
index d73a93a132..355fe30aba 100644
--- a/arch/arm/mach-sunxi/dram_sun8i_a33.c
+++ b/arch/arm/mach-sunxi/dram_sun8i_a33.c
@@ -146,7 +146,7 @@ static void auto_set_timing_para(struct dram_para *para)
writel(reg_val, &mctl_ctl->dramtmg5);
/* Set two rank timing and exit self-refresh timing */
clrsetbits_le32(&mctl_ctl->dramtmg8, (0xff << 8) | (0xff << 0),
- 0x33 << 8 | (0x8 << 0));
+ 0x33 << 8 | (0x10 << 0));
/* Set phy interface time */
reg_val = (0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8)
| (wr_latency << 0);
--
2.17.1
next prev parent reply other threads:[~2019-02-12 16:57 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-12 16:57 [U-Boot] [RFC PATCH 1/3] sunxi: Use clrsetbits_le32 instead of multiple instruction Michael Trimarchi
2019-02-12 16:57 ` [U-Boot] [RFC PATCH 2/3] sunxi: Don't change the rank in dram size detection in A33 Michael Trimarchi
2019-02-13 8:44 ` Maxime Ripard
2019-02-13 8:49 ` Michael Nazzareno Trimarchi
2019-02-13 11:10 ` Michael Nazzareno Trimarchi
2019-02-12 16:57 ` Michael Trimarchi [this message]
2019-02-13 8:45 ` [U-Boot] [RFC PATCH 3/3] sunxi: Fix A33 memory initialization Maxime Ripard
2019-02-13 8:50 ` Michael Nazzareno Trimarchi
2019-02-13 15:54 ` Maxime Ripard
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