From: Marek Vasut <marex@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH] ARM: socfpga: Configure PL310 latencies
Date: Tue, 19 Feb 2019 01:44:00 +0100 [thread overview]
Message-ID: <20190219004400.841-1-marex@denx.de> (raw)
Configure the PL310 tag and data latency registers, which slightly
improves performance and aligns the behavior with Linux.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
---
arch/arm/mach-socfpga/misc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 78fbe28724..1ea4e32c11 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -62,6 +62,9 @@ void v7_outer_cache_enable(void)
/* Disable the L2 cache */
clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+ writel(0x111, &pl310->pl310_tag_latency_ctrl);
+ writel(0x121, &pl310->pl310_data_latency_ctrl);
+
/* enable BRESP, instruction and data prefetch, full line of zeroes */
setbits_le32(&pl310->pl310_aux_ctrl,
L310_AUX_CTRL_DATA_PREFETCH_MASK |
--
2.19.2
next reply other threads:[~2019-02-19 0:44 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-19 0:44 Marek Vasut [this message]
2019-02-19 10:01 ` [U-Boot] [PATCH] ARM: socfpga: Configure PL310 latencies Simon Goldschmidt
2019-02-28 23:59 ` Dinh Nguyen
2019-03-01 9:40 ` Marek Vasut
2019-03-01 15:19 ` Dinh Nguyen
2019-03-01 16:09 ` Marek Vasut
2019-03-01 16:10 ` Dinh Nguyen
2019-02-19 20:09 ` Dinh Nguyen
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