From: Faiz Abbas <faiz_abbas@ti.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v2 1/4] board: ti: dra71: Add pinmux settings for NAND on DRA71x EVM
Date: Wed, 27 Feb 2019 13:29:35 +0530 [thread overview]
Message-ID: <20190227075938.7180-2-faiz_abbas@ti.com> (raw)
In-Reply-To: <20190227075938.7180-1-faiz_abbas@ti.com>
From: Franklin S Cooper Jr <fcooper@ti.com>
By default VOUT3 occupies the pins required for NAND. Therefore, create
a seperate entry that can be use to reconfigure these pins to work for
NAND.
On the EVM SWITCH 8 pins 0 and 1 will be used to determine if NAND is
enabled or not. For NAND to be selected pin 0 should be on and pin 1
should be off. Any other combination will assume NAND shouldn't be
enabled.
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
---
board/ti/dra7xx/mux_data.h | 60 ++++++++++++++++++++++++++++----------
1 file changed, 44 insertions(+), 16 deletions(-)
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
index f1f6bd5316..75da5cb608 100644
--- a/board/ti/dra7xx/mux_data.h
+++ b/board/ti/dra7xx/mux_data.h
@@ -220,22 +220,6 @@ const struct pad_conf_entry dra72x_rgmii_padconf_array_revc[] = {
};
const struct pad_conf_entry dra71x_core_padconf_array[] = {
- {GPMC_AD0, (M3 | PIN_INPUT)}, /* gpmc_ad0.vout3_d0 */
- {GPMC_AD1, (M3 | PIN_INPUT)}, /* gpmc_ad1.vout3_d1 */
- {GPMC_AD2, (M3 | PIN_INPUT)}, /* gpmc_ad2.vout3_d2 */
- {GPMC_AD3, (M3 | PIN_INPUT)}, /* gpmc_ad3.vout3_d3 */
- {GPMC_AD4, (M3 | PIN_INPUT)}, /* gpmc_ad4.vout3_d4 */
- {GPMC_AD5, (M3 | PIN_INPUT)}, /* gpmc_ad5.vout3_d5 */
- {GPMC_AD6, (M3 | PIN_INPUT)}, /* gpmc_ad6.vout3_d6 */
- {GPMC_AD7, (M3 | PIN_INPUT)}, /* gpmc_ad7.vout3_d7 */
- {GPMC_AD8, (M3 | PIN_INPUT)}, /* gpmc_ad8.vout3_d8 */
- {GPMC_AD9, (M3 | PIN_INPUT)}, /* gpmc_ad9.vout3_d9 */
- {GPMC_AD10, (M3 | PIN_INPUT)}, /* gpmc_ad10.vout3_d10 */
- {GPMC_AD11, (M3 | PIN_INPUT)}, /* gpmc_ad11.vout3_d11 */
- {GPMC_AD12, (M3 | PIN_INPUT)}, /* gpmc_ad12.vout3_d12 */
- {GPMC_AD13, (M3 | PIN_INPUT)}, /* gpmc_ad13.vout3_d13 */
- {GPMC_AD14, (M3 | PIN_INPUT)}, /* gpmc_ad14.vout3_d14 */
- {GPMC_AD15, (M3 | PIN_INPUT)}, /* gpmc_ad15.vout3_d15 */
{GPMC_A0, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a0.vout3_d16 */
{GPMC_A1, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a1.vout3_d17 */
{GPMC_A2, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a2.vout3_d18 */
@@ -370,6 +354,50 @@ const struct pad_conf_entry dra71x_core_padconf_array[] = {
{WAKEUP3, (M1 | PULL_ENA | PULL_UP)}, /* Wakeup3.sys_nirq1 */
};
+const struct pad_conf_entry dra71x_vout3_padconf_array[] = {
+ {GPMC_AD0, (M3 | PIN_INPUT)}, /* gpmc_ad0.vout3_d0 */
+ {GPMC_AD1, (M3 | PIN_INPUT)}, /* gpmc_ad1.vout3_d1 */
+ {GPMC_AD2, (M3 | PIN_INPUT)}, /* gpmc_ad2.vout3_d2 */
+ {GPMC_AD3, (M3 | PIN_INPUT)}, /* gpmc_ad3.vout3_d3 */
+ {GPMC_AD4, (M3 | PIN_INPUT)}, /* gpmc_ad4.vout3_d4 */
+ {GPMC_AD5, (M3 | PIN_INPUT)}, /* gpmc_ad5.vout3_d5 */
+ {GPMC_AD6, (M3 | PIN_INPUT)}, /* gpmc_ad6.vout3_d6 */
+ {GPMC_AD7, (M3 | PIN_INPUT)}, /* gpmc_ad7.vout3_d7 */
+ {GPMC_AD8, (M3 | PIN_INPUT)}, /* gpmc_ad8.vout3_d8 */
+ {GPMC_AD9, (M3 | PIN_INPUT)}, /* gpmc_ad9.vout3_d9 */
+ {GPMC_AD10, (M3 | PIN_INPUT)}, /* gpmc_ad10.vout3_d10 */
+ {GPMC_AD11, (M3 | PIN_INPUT)}, /* gpmc_ad11.vout3_d11 */
+ {GPMC_AD12, (M3 | PIN_INPUT)}, /* gpmc_ad12.vout3_d12 */
+ {GPMC_AD13, (M3 | PIN_INPUT)}, /* gpmc_ad13.vout3_d13 */
+ {GPMC_AD14, (M3 | PIN_INPUT)}, /* gpmc_ad14.vout3_d14 */
+ {GPMC_AD15, (M3 | PIN_INPUT)}, /* gpmc_ad15.vout3_d15 */
+};
+
+const struct pad_conf_entry dra71x_nand_padconf_array[] = {
+ {GPMC_AD0, (M0 | PIN_INPUT)}, /* gpmc_ad0.gpmc_ad0 */
+ {GPMC_AD1, (M0 | PIN_INPUT)}, /* gpmc_ad1.gpmc_ad1 */
+ {GPMC_AD2, (M0 | PIN_INPUT)}, /* gpmc_ad2.gpmc_ad2 */
+ {GPMC_AD3, (M0 | PIN_INPUT)}, /* gpmc_ad3.gpmc_ad3 */
+ {GPMC_AD4, (M0 | PIN_INPUT)}, /* gpmc_ad4.gpmc_ad4 */
+ {GPMC_AD5, (M0 | PIN_INPUT)}, /* gpmc_ad5.gpmc_ad5 */
+ {GPMC_AD6, (M0 | PIN_INPUT)}, /* gpmc_ad6.gpmc_ad6 */
+ {GPMC_AD7, (M0 | PIN_INPUT)}, /* gpmc_ad7.gpmc_ad7 */
+ {GPMC_AD8, (M0 | PIN_INPUT)}, /* gpmc_ad8.gpmc_ad8 */
+ {GPMC_AD9, (M0 | PIN_INPUT)}, /* gpmc_ad9.gpmc_ad9 */
+ {GPMC_AD10, (M0 | PIN_INPUT)}, /* gpmc_ad10.gpmc_ad10 */
+ {GPMC_AD11, (M0 | PIN_INPUT)}, /* gpmc_ad11.gpmc_ad11 */
+ {GPMC_AD12, (M0 | PIN_INPUT)}, /* gpmc_ad12.gpmc_ad12 */
+ {GPMC_AD13, (M0 | PIN_INPUT)}, /* gpmc_ad13.gpmc_ad13 */
+ {GPMC_AD14, (M0 | PIN_INPUT)}, /* gpmc_ad14.gpmc_ad14 */
+ {GPMC_AD15, (M0 | PIN_INPUT)}, /* gpmc_ad15.gpmc_ad15 */
+ {GPMC_CS0, (M0 | PIN_INPUT_PULLUP)}, /* gpmc_cs0.gpmc_cs0 */
+ {GPMC_ADVN_ALE, (M0 | PIN_INPUT_PULLDOWN)}, /* gpmc_advn_ale.gpmc_advn_ale */
+ {GPMC_OEN_REN, (M0 | PIN_INPUT_PULLUP)}, /* gpmc_oen_ren.gpmc_oen_ren */
+ {GPMC_WEN, (M0 | PIN_INPUT_PULLUP)}, /* gpmc_wen.gpmc_wen */
+ {GPMC_BEN0, (M0 | PIN_INPUT_PULLDOWN)}, /* gpmc_ben0.gpmc_ben0 */
+ {GPMC_WAIT0, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* gpmc_wait0.gpmc_wait0 */
+};
+
const struct pad_conf_entry early_padconf[] = {
{UART1_RXD, (PIN_INPUT_SLEW | M0)}, /* UART1_RXD */
{UART1_TXD, (PIN_INPUT_SLEW | M0)}, /* UART1_TXD */
--
2.19.2
next prev parent reply other threads:[~2019-02-27 7:59 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-27 7:59 [U-Boot] [PATCH v2 0/4] Add Support for NAND in dra71x-evm Faiz Abbas
2019-02-27 7:59 ` Faiz Abbas [this message]
2019-04-12 16:30 ` [U-Boot] [U-Boot, v2, 1/4] board: ti: dra71: Add pinmux settings for NAND on DRA71x EVM Tom Rini
2019-02-27 7:59 ` [U-Boot] [PATCH v2 2/4] arm: dra7: Allow NAND to be enabled " Faiz Abbas
2019-04-12 16:30 ` [U-Boot] [U-Boot, v2, " Tom Rini
2019-02-27 7:59 ` [U-Boot] [PATCH v2 3/4] configs: dra71x-evm: Add Support for NAND Faiz Abbas
2019-04-12 16:30 ` [U-Boot] [U-Boot, v2, " Tom Rini
2019-02-27 7:59 ` [U-Boot] [PATCH v2 4/4] configs: ti_omap5_common: Add NAND environment settings Faiz Abbas
2019-02-27 18:55 ` Tom Rini
2019-04-12 16:30 ` [U-Boot] [U-Boot, v2, " Tom Rini
2019-03-13 15:05 ` [U-Boot] [PATCH v2 0/4] Add Support for NAND in dra71x-evm Faiz Abbas
2019-03-13 16:01 ` Tom Rini
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