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From: Jagan Teki <jagan@amarulasolutions.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v3 3/9] spi: sun4i: Simplify reg writes using set/clrbits_le32
Date: Wed, 27 Feb 2019 20:02:07 +0530	[thread overview]
Message-ID: <20190227143213.8963-4-jagan@amarulasolutions.com> (raw)
In-Reply-To: <20190227143213.8963-1-jagan@amarulasolutions.com>

Update the existing register writes using setbits_le32 and
clrbits_le32 in required places.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/spi/sun4i_spi.c | 21 ++++++++-------------
 1 file changed, 8 insertions(+), 13 deletions(-)

diff --git a/drivers/spi/sun4i_spi.c b/drivers/spi/sun4i_spi.c
index f5f2d5635a..0b1663038c 100644
--- a/drivers/spi/sun4i_spi.c
+++ b/drivers/spi/sun4i_spi.c
@@ -283,20 +283,18 @@ static int sun4i_spi_claim_bus(struct udevice *dev)
 {
 	struct sun4i_spi_priv *priv = dev_get_priv(dev->parent);
 
-	writel(SUN4I_CTL_ENABLE | SUN4I_CTL_MASTER | SUN4I_CTL_TP |
-	       SUN4I_CTL_CS_MANUAL | SUN4I_CTL_CS_ACTIVE_LOW,
-	       &priv->regs->ctl);
+	setbits_le32(&priv->regs->ctl, SUN4I_CTL_ENABLE |
+		     SUN4I_CTL_MASTER | SUN4I_CTL_TP |
+		     SUN4I_CTL_CS_MANUAL | SUN4I_CTL_CS_ACTIVE_LOW);
+
 	return 0;
 }
 
 static int sun4i_spi_release_bus(struct udevice *dev)
 {
 	struct sun4i_spi_priv *priv = dev_get_priv(dev->parent);
-	u32 reg;
 
-	reg = readl(&priv->regs->ctl);
-	reg &= ~SUN4I_CTL_ENABLE;
-	writel(reg, &priv->regs->ctl);
+	clrbits_le32(&priv->regs->ctl, SUN4I_CTL_ENABLE);
 
 	return 0;
 }
@@ -309,7 +307,7 @@ static int sun4i_spi_xfer(struct udevice *dev, unsigned int bitlen,
 	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
 
 	u32 len = bitlen / 8;
-	u32 reg, rx_fifocnt;
+	u32 rx_fifocnt;
 	u8 nbytes;
 	int ret;
 
@@ -324,10 +322,8 @@ static int sun4i_spi_xfer(struct udevice *dev, unsigned int bitlen,
 	if (flags & SPI_XFER_BEGIN)
 		sun4i_spi_set_cs(bus, slave_plat->cs, true);
 
-	reg = readl(&priv->regs->ctl);
-
 	/* Reset FIFOs */
-	writel(reg | SUN4I_CTL_RF_RST | SUN4I_CTL_TF_RST, &priv->regs->ctl);
+	setbits_le32(&priv->regs->ctl, SUN4I_CTL_RF_RST | SUN4I_CTL_TF_RST);
 
 	while (len) {
 		/* Setup the transfer now... */
@@ -341,8 +337,7 @@ static int sun4i_spi_xfer(struct udevice *dev, unsigned int bitlen,
 		sun4i_spi_fill_fifo(priv, nbytes);
 
 		/* Start the transfer */
-		reg = readl(&priv->regs->ctl);
-		writel(reg | SUN4I_CTL_XCH, &priv->regs->ctl);
+		setbits_le32(&priv->regs->ctl, SUN4I_CTL_XCH);
 
 		/* Wait till RX FIFO to be empty */
 		ret = readl_poll_timeout(&priv->regs->fifo_sta, rx_fifocnt,
-- 
2.18.0.321.gffc6fa0e3

  parent reply	other threads:[~2019-02-27 14:32 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-02-27 14:32 [U-Boot] [PATCH v3 0/9] spi: Add Allwinner A31 SPI driver Jagan Teki
2019-02-27 14:32 ` [U-Boot] [PATCH v3 1/9] spi: sun4i: Poll for rxfifo to be filled up Jagan Teki
2019-02-27 14:32 ` [U-Boot] [PATCH v3 2/9] clk: sunxi: Implement SPI clocks, resets Jagan Teki
2019-02-27 14:32 ` Jagan Teki [this message]
2019-02-27 14:32 ` [U-Boot] [PATCH v3 4/9] spi: sun4i: Access registers and bits via enum offsets Jagan Teki
2019-02-27 14:32 ` [U-Boot] [PATCH v3 5/9] spi: sun4i: Support fifo_depth via drvdata Jagan Teki
2019-02-27 14:32 ` [U-Boot] [PATCH v3 6/9] spi: sun4i: Add CLK support Jagan Teki
2019-02-27 14:32 ` [U-Boot] [PATCH v3 7/9] spi: sun4: Add A31 spi controller support Jagan Teki
2019-02-27 14:32 ` [U-Boot] [PATCH v3 8/9] spi: sun4i: Driver cleanup Jagan Teki
2019-02-27 14:32 ` [U-Boot] [PATCH v3 9/9] spi: Rename sun4i_spi.c into spi-sunxi.c Jagan Teki
2019-03-06 16:24 ` [U-Boot] [PATCH v3 0/9] spi: Add Allwinner A31 SPI driver Jagan Teki

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