[U-Boot] [PATCH v2 1/2] x86: TunnelCreek: switch P state to the highest freq

[Andy Shevchenko <andriy.shevchenko@linux.intel.com>]

On Thu, Feb 28, 2019 at 11:29:50AM +0800, Bin Meng wrote:
> On Thu, May 24, 2018 at 12:00 PM Bin Meng <bmeng.cn@gmail.com> wrote:
> > On Thu, Apr 12, 2018 at 4:07 PM, Christian Gmeiner
> > <christian.gmeiner@gmail.com> wrote:

> So to me this seems to match my understanding about EIST. If this is
> true, then I can't explain why Christian's patch is needed since the
> EIST is disabled on TunnelCreek by default and the processor should
> already run at the highest performance.

The some internal documents I found suggesting that first what one needs to do
is to be sure that EIST is enabled / disabled by reading a bit from CPUID.

(There is no mention of the exact bit, I'm guessing it might be X86_FEATURE_EST)

It also refers to IA32_MISC_ENABLE MSR, i.e. bit 20
(MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT) and bit 16
(MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT), that firmware can set up
accordingly.

Hope this helps.

P.S. All names are implying Linux kernel source code.

-- 
With Best Regards,
Andy Shevchenko