From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andy Shevchenko Date: Wed, 6 Mar 2019 13:09:51 +0200 Subject: [U-Boot] [PATCH v2 1/2] x86: TunnelCreek: switch P state to the highest freq In-Reply-To: References: <20180412080743.24614-1-christian.gmeiner@gmail.com> Message-ID: <20190306110951.GA9224@smile.fi.intel.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Thu, Feb 28, 2019 at 11:29:50AM +0800, Bin Meng wrote: > On Thu, May 24, 2018 at 12:00 PM Bin Meng wrote: > > On Thu, Apr 12, 2018 at 4:07 PM, Christian Gmeiner > > wrote: > So to me this seems to match my understanding about EIST. If this is > true, then I can't explain why Christian's patch is needed since the > EIST is disabled on TunnelCreek by default and the processor should > already run at the highest performance. The some internal documents I found suggesting that first what one needs to do is to be sure that EIST is enabled / disabled by reading a bit from CPUID. (There is no mention of the exact bit, I'm guessing it might be X86_FEATURE_EST) It also refers to IA32_MISC_ENABLE MSR, i.e. bit 20 (MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT) and bit 16 (MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT), that firmware can set up accordingly. Hope this helps. P.S. All names are implying Linux kernel source code. -- With Best Regards, Andy Shevchenko