From: Marek Vasut <marex@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 3/4] ARM: socfpga: Fix Arria10 SPI and NAND U-Boot offset
Date: Wed, 6 Mar 2019 22:05:33 +0100 [thread overview]
Message-ID: <20190306210534.9365-3-marex@denx.de> (raw)
In-Reply-To: <20190306210534.9365-1-marex@denx.de>
The SPL size on Gen5 is 4*64kiB, but on A10 it is 4*256kiB.
Handle the difference.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
---
include/configs/socfpga_common.h | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index f182e9e71b..181af9b646 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -275,12 +275,20 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
/* SPL QSPI boot support */
#ifdef CONFIG_SPL_SPI_SUPPORT
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x100000
+#endif
#endif
/* SPL NAND boot support */
#ifdef CONFIG_SPL_NAND_SUPPORT
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x100000
+#endif
#endif
/*
--
2.20.1
next prev parent reply other threads:[~2019-03-06 21:05 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-06 21:05 [U-Boot] [PATCH 1/4] ARM: socfpga: Disable D cache in SPL Marek Vasut
2019-03-06 21:05 ` [U-Boot] [PATCH 2/4] ARM: socfpga: Drop CONFIG_SYS_NAND_BAD_BLOCK_POS Marek Vasut
2019-03-08 3:54 ` Chee, Tien Fong
2019-03-06 21:05 ` Marek Vasut [this message]
2019-03-07 8:15 ` [U-Boot] [PATCH 3/4] ARM: socfpga: Fix Arria10 SPI and NAND U-Boot offset Simon Goldschmidt
2019-03-06 21:05 ` [U-Boot] [PATCH 4/4] ARM: socfpga: Fix A10 SoCDK Kconfig Marek Vasut
2019-03-08 4:33 ` Chee, Tien Fong
2019-03-08 3:43 ` [U-Boot] [PATCH 1/4] ARM: socfpga: Disable D cache in SPL Chee, Tien Fong
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