[U-Boot] [PATCH 0/9] AE350 SMP support RISC-V

[Andes <uboot@andestech.com>]

From: Rick Chen <rick@andestech.com>

This patch series was based on Lukas's patchsets of SMP support for RISC-V.
Add Andestech's PLIC for IPI handling and PLMT to replace Soc timer.
It has been verified on AE350 SMP platform in M-mode and boot SMP kernel ok.

Verification in S-mode is still on-going.

Rick Chen (9):
  riscv: ax25: Create a simple-bus driver for the soc node
  riscv: Add a SYSCON driver for Andestech's PLIC
  riscv: Add a SYSCON driver for Andestech's PLMT
  riscv: ae350: initialize PLIC
  riscv: ae350: disable ATCPIT100 timer
  riscv: ax25: Add platform-specific Kconfig options
  riscv: ax25: Andes specific cache shall only support in M-mode.
  riscv: dts: ae350 support SMP.
  riscv: ae350: enable SMP

 arch/riscv/Kconfig                      | 18 +++++++
 arch/riscv/cpu/ax25/Kconfig             |  7 +++
 arch/riscv/cpu/ax25/cpu.c               | 16 +++++++
 arch/riscv/dts/ae350_32.dts             | 81 ++++++++++++++++++++++---------
 arch/riscv/dts/ae350_64.dts             | 47 ++++++++++++++++--
 arch/riscv/include/asm/global_data.h    |  6 +++
 arch/riscv/include/asm/syscon.h         |  3 +-
 arch/riscv/lib/Makefile                 |  2 +
 arch/riscv/lib/nds_plic.c               | 84 +++++++++++++++++++++++++++++++++
 arch/riscv/lib/nds_plmt.c               | 53 +++++++++++++++++++++
 board/AndesTech/ax25-ae350/Kconfig      |  1 +
 board/AndesTech/ax25-ae350/ax25-ae350.c | 30 ++++++++++++
 configs/ae350_rv32_defconfig            |  1 -
 configs/ae350_rv64_defconfig            |  1 -
 14 files changed, 320 insertions(+), 30 deletions(-)
 create mode 100644 arch/riscv/lib/nds_plic.c
 create mode 100644 arch/riscv/lib/nds_plmt.c

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2.7.4