From mboxrd@z Thu Jan 1 00:00:00 1970 From: Fabien Parent Date: Sun, 24 Mar 2019 16:46:35 +0100 Subject: [U-Boot] [PATCH v3 4/7] clk: mediatek: add support for SETCLR_INV and NO_SETCLR flags In-Reply-To: <20190324154638.29800-1-fparent@baylibre.com> References: <20190324154638.29800-1-fparent@baylibre.com> Message-ID: <20190324154638.29800-5-fparent@baylibre.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Add the implementation for the CLK_GATE_SETCLR_INV and CLK_GATE_NO_SETCLR flags. Signed-off-by: Fabien Parent Acked-by: Ryder Lee --- v3: * No changes --- drivers/clk/mediatek/clk-mtk.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index 870b14ed8b..6c6b500d9b 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -390,6 +390,12 @@ static int mtk_clk_gate_enable(struct clk *clk) case CLK_GATE_SETCLR: writel(bit, priv->base + gate->regs->clr_ofs); break; + case CLK_GATE_SETCLR_INV: + writel(bit, priv->base + gate->regs->set_ofs); + break; + case CLK_GATE_NO_SETCLR: + clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, 0); + break; case CLK_GATE_NO_SETCLR_INV: clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, bit); break; @@ -411,6 +417,12 @@ static int mtk_clk_gate_disable(struct clk *clk) case CLK_GATE_SETCLR: writel(bit, priv->base + gate->regs->set_ofs); break; + case CLK_GATE_SETCLR_INV: + writel(bit, priv->base + gate->regs->clr_ofs); + break; + case CLK_GATE_NO_SETCLR: + clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, bit); + break; case CLK_GATE_NO_SETCLR_INV: clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, 0); break; -- 2.20.1