From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andes Date: Mon, 25 Mar 2019 15:35:18 +0800 Subject: [U-Boot] [PATCH v2 5/7] riscv: ax25: Andes specific cache shall only support in M-mode In-Reply-To: <20190325073520.452-1-uboot@andestech.com> References: <20190325073520.452-1-uboot@andestech.com> Message-ID: <20190325073520.452-6-uboot@andestech.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de From: Rick Chen Limit the cache configuration only can be supported in M mode. It can not be manipulated in S mode. Signed-off-by: Rick Chen Cc: Greentime Hu Reviewed-by: Bin Meng --- arch/riscv/cpu/ax25/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig index 68bd4e9..6b4b92e 100644 --- a/arch/riscv/cpu/ax25/Kconfig +++ b/arch/riscv/cpu/ax25/Kconfig @@ -14,6 +14,7 @@ if RISCV_NDS config RISCV_NDS_CACHE bool "AndeStar V5 families specific cache support" + depends on RISCV_MMODE help Provide Andes Technology AndeStar V5 families specific cache support. -- 2.7.4