[U-Boot] [PATCH v2 6/7] riscv: dts: ae350 support SMP

Bin Meng
2019-03-29T09:24:33Z

Hi Rick,

On Mon, Mar 25, 2019 at 3:40 PM Andes <uboot@andestech.com> wrote:
>
> From: Rick Chen <rick@andestech.com>
>
> Signed-off-by: Rick Chen <rick@andestech.com>
> Cc: Greentime Hu <greentime@andestech.com>
> ---
> arch/riscv/dts/ae350_32.dts | 81 +++++++++++++++++++++++++++++++++------------
> arch/riscv/dts/ae350_64.dts | 47 +++++++++++++++++++++++---
> 2 files changed, 101 insertions(+), 27 deletions(-)
>
> diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
> index 0679827..7cff312 100644
> --- a/arch/riscv/dts/ae350_32.dts
> +++ b/arch/riscv/dts/ae350_32.dts
> @@ -26,16 +26,49 @@
> status = "okay";
> compatible = "riscv";
> riscv,isa = "rv32imafdc";
> + riscv,priv-major = <1>;
> + riscv,priv-minor = <10>;
> mmu-type = "riscv,sv32";
> clock-frequency = <60000000>;
> + i-cache-size = <0x8000>;
> + i-cache-line-size = <32>;
> d-cache-size = <0x8000>;
> d-cache-line-size = <32>;
> + next-level-cache = <&L2>;
> CPU0_intc: interrupt-controller {
> #interrupt-cells = <1>;
> interrupt-controller;
> compatible = "riscv,cpu-intc";
> };
> };
> + CPU1: cpu at 1 {
> + device_type = "cpu";

the indention looks wrong

> + reg = <1>;
> + status = "okay";
> + compatible = "riscv";
> + riscv,isa = "rv32i2p0m2p0a2p0f2p0d2p0c2p0xv5-0p0";

the isa string is not recovered, like cpu0

> + riscv,priv-major = <1>;
> + riscv,priv-minor = <10>;
> + mmu-type = "riscv,sv32";
> + clock-frequency = <60000000>;
> + i-cache-size = <0x8000>;
> + i-cache-line-size = <32>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <32>;
> + next-level-cache = <&L2>;
> + CPU1_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + compatible = "riscv,cpu-intc";
> + };
> + };

[snip]

Regards,
Bin