[U-Boot] [PATCH v2 03/10] clk: imx: Add i.MX6UL clock driver

[Jagan Teki <jagan@amarulasolutions.com>]

i.MX6 clock control module comprise of parent clocks, gates, multiplexers,
dividers, PODF, PLL, fixed rate and etc.

This patch add i.MX6UL USDHC clocks via gate clock which would eventually
handle enable/disable operations via imx6_clock_gate.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/clk/imx/Kconfig      |  7 +++++++
 drivers/clk/imx/Makefile     |  1 +
 drivers/clk/imx/clk-imx6ul.c | 37 ++++++++++++++++++++++++++++++++++++
 3 files changed, 45 insertions(+)
 create mode 100644 drivers/clk/imx/clk-imx6ul.c

diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index f81903dcf4..952cec8bff 100644
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -15,6 +15,13 @@ config CLK_IMX6Q
 	  This enables common clock driver support for platforms based
 	  on i.MX6 QDL SoC.
 
+config CLK_IMX6UL
+	bool "Clock driver for i.MX6UL"
+	default MX6UL
+	help
+	 This enables common clock driver support for platforms based
+	 on i.MX6 UL SoC.
+
 config CLK_IMX8
 	bool "Clock support for i.MX8"
 	default ARCH_IMX8
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index a4cb2bbf3b..999de1dd6f 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -7,4 +7,5 @@ obj-$(CONFIG_CLK_IMX) += clk-imx6-common.o
 endif
 
 obj-$(CONFIG_CLK_IMX6Q) += clk-imx6q.o
+obj-$(CONFIG_CLK_IMX6UL) += clk-imx6ul.o
 obj-$(CONFIG_CLK_IMX8) += clk-imx8.o
diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c
new file mode 100644
index 0000000000..f5250e8b72
--- /dev/null
+++ b/drivers/clk/imx/clk-imx6ul.c
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Amarula Solutions.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <asm/arch/clock.h>
+#include <dt-bindings/clock/imx6ul-clock.h>
+
+static const struct imx6_clk_gate imx6ul_gates[] = {
+	[IMX6UL_CLK_USDHC1]		= GATE(0x080, GENMASK(3, 2)),
+	[IMX6UL_CLK_USDHC2]		= GATE(0x080, GENMASK(5, 4)),
+};
+
+static const struct imx6_clk_desc imx6ul_clk_desc = {
+	.gates = imx6ul_gates,
+};
+
+static const struct udevice_id clk_imx6ul_ids[] = {
+	{
+	  .compatible = "fsl,imx6ul-ccm",
+	  .data = (ulong)&imx6ul_clk_desc
+	},
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(clk_imx6ul) = {
+	.name		= "clk_imx6ul",
+	.id		= UCLASS_CLK,
+	.of_match	= clk_imx6ul_ids,
+	.priv_auto_alloc_size	= sizeof(struct imx6_clk_priv),
+	.ops		= &imx6_clk_ops,
+	.probe		= imx6_clk_probe,
+};
-- 
2.18.0.321.gffc6fa0e3