From mboxrd@z Thu Jan 1 00:00:00 1970 From: Keerthy Date: Fri, 12 Apr 2019 12:08:16 +0530 Subject: [U-Boot] [PATCH 2/6] arm: mach-omap2: am33xx: ddr: Add 1ms delay to avoid L3 error In-Reply-To: <20190412063820.25924-1-j-keerthy@ti.com> References: <20190412063820.25924-1-j-keerthy@ti.com> Message-ID: <20190412063820.25924-3-j-keerthy@ti.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de From: Brad Griffis Add 1ms delay to avoid L3 timeout error during suspend resume. Signed-off-by: Brad Griffis Signed-off-by: Keerthy --- arch/arm/mach-omap2/am33xx/ddr.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-omap2/am33xx/ddr.c b/arch/arm/mach-omap2/am33xx/ddr.c index 816d4e8e05..5d947a68c3 100644 --- a/arch/arm/mach-omap2/am33xx/ddr.c +++ b/arch/arm/mach-omap2/am33xx/ddr.c @@ -138,6 +138,9 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr) /* Enable read leveling */ writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_ctl); + /* Wait 1ms because of L3 timeout error */ + udelay(1000); + /* * Enable full read and write leveling. Wait for read and write * leveling bit to clear RDWRLVLFULL_START bit 31 -- 2.17.1