From mboxrd@z Thu Jan 1 00:00:00 1970 From: Keerthy Date: Fri, 12 Apr 2019 12:08:19 +0530 Subject: [U-Boot] [PATCH 5/6] arm: mach-omap2: am33xx: ddr: update value for ext_phy_ctrl_36 In-Reply-To: <20190412063820.25924-1-j-keerthy@ti.com> References: <20190412063820.25924-1-j-keerthy@ti.com> Message-ID: <20190412063820.25924-6-j-keerthy@ti.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de From: Brad Griffis for suspend/resume robustness update value for ext_phy_ctrl_36 for suspend/resume robustness with hardware leveling enabled. Match recommended values from EMIF Tools app note: http://www.ti.com/lit/an/sprac70/sprac70.pdf Signed-off-by: Brad Griffis Signed-off-by: Keerthy --- arch/arm/mach-omap2/am33xx/ddr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/am33xx/ddr.c b/arch/arm/mach-omap2/am33xx/ddr.c index e6e6ef8e9a..13fac2d3cd 100644 --- a/arch/arm/mach-omap2/am33xx/ddr.c +++ b/arch/arm/mach-omap2/am33xx/ddr.c @@ -307,8 +307,8 @@ static void ext_phy_settings_hwlvl(const struct emif_regs *regs, int nr) writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34_shdw); writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35); writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35_shdw); - writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36); - writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw); + writel(0x00000077, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36); + writel(0x00000077, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw); /* * Sequence to ensure that the PHY is again in a known state after -- 2.17.1