From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thierry Reding Date: Mon, 15 Apr 2019 11:32:16 +0200 Subject: [U-Boot] [PATCH v5 04/27] ARM: tegra: Remove disp1 clock initialization on Tegra210 In-Reply-To: <20190415093239.27509-1-thierry.reding@gmail.com> References: <20190415093239.27509-1-thierry.reding@gmail.com> Message-ID: <20190415093239.27509-5-thierry.reding@gmail.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de From: Thierry Reding pll_c is not a valid parent for the disp1 clock, so trying to set it will fail. Given that display is not used in U-Boot, remove the init table entry so that disp1 will keep its default parent (clk_m). Signed-off-by: Thierry Reding --- arch/arm/mach-tegra/tegra210/clock.c | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/mach-tegra/tegra210/clock.c b/arch/arm/mach-tegra/tegra210/clock.c index 0d7cafea2017..b240860f08cf 100644 --- a/arch/arm/mach-tegra/tegra210/clock.c +++ b/arch/arm/mach-tegra/tegra210/clock.c @@ -1265,7 +1265,6 @@ struct periph_clk_init periph_clk_init_table[] = { { PERIPH_ID_SBC5, CLOCK_ID_PERIPH }, { PERIPH_ID_SBC6, CLOCK_ID_PERIPH }, { PERIPH_ID_HOST1X, CLOCK_ID_PERIPH }, - { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL }, { PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH }, { PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH }, { PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH }, -- 2.21.0