From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dinh Nguyen Date: Tue, 23 Apr 2019 16:55:05 -0500 Subject: [U-Boot] [PATCHv5 5/6] ARM: socfpga: use the pl310 driver to configure the cache In-Reply-To: <20190423215506.7515-1-dinguyen@kernel.org> References: <20190423215506.7515-1-dinguyen@kernel.org> Message-ID: <20190423215506.7515-6-dinguyen@kernel.org> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Find the UCLASS_CACHE driver to configure the cache controller's settings. Reviewed-by: Marek Vasut Reviewed-by: Simon Glass Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/misc.c | 16 +++------------- 1 file changed, 3 insertions(+), 13 deletions(-) diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index ec8339e045..34d8c4c51b 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -59,20 +59,10 @@ void enable_caches(void) #ifdef CONFIG_SYS_L2_PL310 void v7_outer_cache_enable(void) { - /* Disable the L2 cache */ - clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); - - writel(0x0, &pl310->pl310_tag_latency_ctrl); - writel(0x10, &pl310->pl310_data_latency_ctrl); - - /* enable BRESP, instruction and data prefetch, full line of zeroes */ - setbits_le32(&pl310->pl310_aux_ctrl, - L310_AUX_CTRL_DATA_PREFETCH_MASK | - L310_AUX_CTRL_INST_PREFETCH_MASK | - L310_SHARED_ATT_OVERRIDE_ENABLE); + struct udevice *dev; - /* Enable the L2 cache */ - setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); + if (uclass_get_device(UCLASS_CACHE, 0, &dev)) + pr_err("cache controller driver NOT found!\n"); } void v7_outer_cache_disable(void) -- 2.20.0