From: Jagan Teki <jagan@amarulasolutions.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v2 38/99] ram: rockchip: rk3399: Add cap_info structure
Date: Mon, 17 Jun 2019 13:01:51 +0530 [thread overview]
Message-ID: <20190617073252.27810-39-jagan@amarulasolutions.com> (raw)
In-Reply-To: <20190617073252.27810-1-jagan@amarulasolutions.com>
Group common ddr attributes like
- rank
- col
- bk
- bw
- dbw
- row_3_4
- cs0_row
- cs1_row
- ddrconfig
into a common cap_info structure for more code readability and extend
if possible based on the new features.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
.../include/asm/arch-rockchip/sdram_rk3399.h | 6 +-
drivers/ram/rockchip/sdram_rk3399.c | 71 ++++++++++---------
2 files changed, 41 insertions(+), 36 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
index a191d242f8..67044f53e5 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
@@ -96,7 +96,7 @@ struct rk3399_ddr_cic_regs {
/* DENALI_CTL_274 */
#define MEM_RST_VALID 1
-struct rk3399_sdram_channel {
+struct sdram_cap_info {
unsigned int rank;
/* dram column number, 0 means this channel is invalid */
unsigned int col;
@@ -114,6 +114,10 @@ struct rk3399_sdram_channel {
unsigned int cs0_row;
unsigned int cs1_row;
unsigned int ddrconfig;
+};
+
+struct rk3399_sdram_channel {
+ struct sdram_cap_info cap_info;
struct rk3399_msch_timings noc_timings;
};
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 6c3a2b5453..231f69b173 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -155,35 +155,36 @@ static void set_memory_map(const struct chan_info *chan, u32 channel,
u32 row;
/* Get row number from ddrconfig setting */
- if (sdram_ch->ddrconfig < 2 || sdram_ch->ddrconfig == 4)
+ if (sdram_ch->cap_info.ddrconfig < 2 ||
+ sdram_ch->cap_info.ddrconfig == 4)
row = 16;
- else if (sdram_ch->ddrconfig == 3)
+ else if (sdram_ch->cap_info.ddrconfig == 3)
row = 14;
else
row = 15;
- cs_map = (sdram_ch->rank > 1) ? 3 : 1;
- reduc = (sdram_ch->bw == 2) ? 0 : 1;
+ cs_map = (sdram_ch->cap_info.rank > 1) ? 3 : 1;
+ reduc = (sdram_ch->cap_info.bw == 2) ? 0 : 1;
/* Set the dram configuration to ctrl */
- clrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->col));
+ clrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->cap_info.col));
clrsetbits_le32(&denali_ctl[190], (0x3 << 16) | (0x7 << 24),
- ((3 - sdram_ch->bk) << 16) |
+ ((3 - sdram_ch->cap_info.bk) << 16) |
((16 - row) << 24));
clrsetbits_le32(&denali_ctl[196], 0x3 | (1 << 16),
cs_map | (reduc << 16));
/* PI_199 PI_COL_DIFF:RW:0:4 */
- clrsetbits_le32(&denali_pi[199], 0xF, (12 - sdram_ch->col));
+ clrsetbits_le32(&denali_pi[199], 0xF, (12 - sdram_ch->cap_info.col));
/* PI_155 PI_ROW_DIFF:RW:24:3 PI_BANK_DIFF:RW:16:2 */
clrsetbits_le32(&denali_pi[155], (0x3 << 16) | (0x7 << 24),
- ((3 - sdram_ch->bk) << 16) |
+ ((3 - sdram_ch->cap_info.bk) << 16) |
((16 - row) << 24));
/* PI_41 PI_CS_MAP:RW:24:4 */
clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24);
- if (sdram_ch->rank == 1 && params->base.dramtype == DDR3)
+ if (sdram_ch->cap_info.rank == 1 && params->base.dramtype == DDR3)
writel(0x2EC7FFFF, &denali_pi[34]);
}
@@ -681,7 +682,7 @@ static int data_training_ca(const struct chan_info *chan, u32 channel,
u32 *denali_phy = chan->publ->denali_phy;
u32 i, tmp;
u32 obs_0, obs_1, obs_2, obs_err = 0;
- u32 rank = params->ch[channel].rank;
+ u32 rank = params->ch[channel].cap_info.rank;
u32 rank_mask;
/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
@@ -744,7 +745,7 @@ static int data_training_wl(const struct chan_info *chan, u32 channel,
u32 *denali_phy = chan->publ->denali_phy;
u32 i, tmp;
u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
- u32 rank = params->ch[channel].rank;
+ u32 rank = params->ch[channel].cap_info.rank;
/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
writel(0x00003f7c, (&denali_pi[175]));
@@ -806,7 +807,7 @@ static int data_training_rg(const struct chan_info *chan, u32 channel,
u32 *denali_phy = chan->publ->denali_phy;
u32 i, tmp;
u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
- u32 rank = params->ch[channel].rank;
+ u32 rank = params->ch[channel].cap_info.rank;
/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
writel(0x00003f7c, (&denali_pi[175]));
@@ -868,7 +869,7 @@ static int data_training_rl(const struct chan_info *chan, u32 channel,
{
u32 *denali_pi = chan->pi->denali_pi;
u32 i, tmp;
- u32 rank = params->ch[channel].rank;
+ u32 rank = params->ch[channel].cap_info.rank;
/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
writel(0x00003f7c, (&denali_pi[175]));
@@ -916,7 +917,7 @@ static int data_training_wdql(const struct chan_info *chan, u32 channel,
{
u32 *denali_pi = chan->pi->denali_pi;
u32 i, tmp;
- u32 rank = params->ch[channel].rank;
+ u32 rank = params->ch[channel].cap_info.rank;
u32 rank_mask;
/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
@@ -1050,14 +1051,14 @@ static void set_ddrconfig(const struct chan_info *chan,
unsigned int cs0_cap = 0;
unsigned int cs1_cap = 0;
- cs0_cap = (1 << (params->ch[channel].cs0_row
- + params->ch[channel].col
- + params->ch[channel].bk
- + params->ch[channel].bw - 20));
- if (params->ch[channel].rank > 1)
- cs1_cap = cs0_cap >> (params->ch[channel].cs0_row
- - params->ch[channel].cs1_row);
- if (params->ch[channel].row_3_4) {
+ cs0_cap = (1 << (params->ch[channel].cap_info.cs0_row
+ + params->ch[channel].cap_info.col
+ + params->ch[channel].cap_info.bk
+ + params->ch[channel].cap_info.bw - 20));
+ if (params->ch[channel].cap_info.rank > 1)
+ cs1_cap = cs0_cap >> (params->ch[channel].cap_info.cs0_row
+ - params->ch[channel].cap_info.cs1_row);
+ if (params->ch[channel].cap_info.row_3_4) {
cs0_cap = cs0_cap * 3 / 4;
cs1_cap = cs1_cap * 3 / 4;
}
@@ -1084,22 +1085,22 @@ static void dram_all_config(struct dram_info *dram,
struct rk3399_msch_regs *ddr_msch_regs;
const struct rk3399_msch_timings *noc_timing;
- if (params->ch[channel].col == 0)
+ if (params->ch[channel].cap_info.col == 0)
continue;
idx++;
- sys_reg2 |= SYS_REG_ENC_ROW_3_4(info->row_3_4, channel);
+ sys_reg2 |= SYS_REG_ENC_ROW_3_4(info->cap_info.row_3_4, channel);
sys_reg2 |= SYS_REG_ENC_CHINFO(channel);
- sys_reg2 |= SYS_REG_ENC_RANK(info->rank, channel);
- sys_reg2 |= SYS_REG_ENC_COL(info->col, channel);
- sys_reg2 |= SYS_REG_ENC_BK(info->bk, channel);
- sys_reg2 |= SYS_REG_ENC_BW(info->bw, channel);
- sys_reg2 |= SYS_REG_ENC_DBW(info->dbw, channel);
- SYS_REG_ENC_CS0_ROW(info->cs0_row, sys_reg2, sys_reg3, channel);
- if (info->cs1_row)
- SYS_REG_ENC_CS1_ROW(info->cs1_row, sys_reg2,
+ sys_reg2 |= SYS_REG_ENC_RANK(info->cap_info.rank, channel);
+ sys_reg2 |= SYS_REG_ENC_COL(info->cap_info.col, channel);
+ sys_reg2 |= SYS_REG_ENC_BK(info->cap_info.bk, channel);
+ sys_reg2 |= SYS_REG_ENC_BW(info->cap_info.bw, channel);
+ sys_reg2 |= SYS_REG_ENC_DBW(info->cap_info.dbw, channel);
+ SYS_REG_ENC_CS0_ROW(info->cap_info.cs0_row, sys_reg2, sys_reg3, channel);
+ if (info->cap_info.cs1_row)
+ SYS_REG_ENC_CS1_ROW(info->cap_info.cs1_row, sys_reg2,
sys_reg3, channel);
- sys_reg3 |= SYS_REG_ENC_CS1_COL(info->col, channel);
+ sys_reg3 |= SYS_REG_ENC_CS1_COL(info->cap_info.col, channel);
sys_reg3 |= SYS_REG_ENC_VERSION(DDR_SYS_REG_VERSION);
ddr_msch_regs = dram->chan[channel].msch;
@@ -1116,7 +1117,7 @@ static void dram_all_config(struct dram_info *dram,
&ddr_msch_regs->ddrmode);
/* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */
- if (params->ch[channel].rank == 1)
+ if (params->ch[channel].cap_info.rank == 1)
setbits_le32(&dram->chan[channel].pctl->denali_ctl[276],
1 << 17);
}
@@ -1226,7 +1227,7 @@ static int sdram_init(struct dram_info *dram,
}
set_ddrconfig(chan, params, channel,
- params->ch[channel].ddrconfig);
+ params->ch[channel].cap_info.ddrconfig);
}
dram_all_config(dram, params);
switch_to_phy_index1(dram, params);
--
2.18.0.321.gffc6fa0e3
next prev parent reply other threads:[~2019-06-17 7:31 UTC|newest]
Thread overview: 112+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-17 7:31 [U-Boot] [PATCH v2 00/99] ram: rk3399: Add LPDDR4 support Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 01/99] ram: rk3399: Fix code warnings Jagan Teki
2019-07-15 12:31 ` Kever Yang
2019-06-17 7:31 ` [U-Boot] [PATCH v2 02/99] ram: rk3399: Add space between string with format specifier Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 03/99] ram: rk3399: Add proper spaces in code Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 04/99] ram: rk3399: s/sdram_params/params Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 05/99] ram: rk3399: Handle data training return types Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 06/99] ram: rk3399: Order include files Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 07/99] ram: rk3399: Move macro after " Jagan Teki
2019-07-15 12:39 ` Kever Yang
2019-06-17 7:31 ` [U-Boot] [PATCH v2 08/99] ram: rk3399: Clear PI_175 interrupts in data training Jagan Teki
2019-07-15 12:39 ` Kever Yang
2019-06-17 7:31 ` [U-Boot] [PATCH v2 09/99] ram: rk3399: Use rank mask in ca " Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 10/99] ram: rk3399: Use rank mask in wdql " Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 11/99] ram: rk3399: Add ddrtype enc macro Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 12/99] ram: rk3399: Add channel number encoder macro Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 13/99] ram: rk3399: Add row_3_4 enc macro Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 14/99] ram: rk3399: Add chipinfo macro Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 15/99] ram: rk3399: Add rank enc macro Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 16/99] ram: rk3399: Add column " Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 17/99] ram: rk3399: Add bk " Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 18/99] ram: rk3399: Add dbw " Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 19/99] ram: rk3399: Add cs0_rw macro Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 20/99] ram: rk3399: Add cs1_rw macro Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 21/99] ram: rk3399: Add bw enc macro Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 22/99] ram: rk3399: Rename sys_reg with sys_reg2 Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 23/99] ram: rk3399: Update cs0_row to use sys_reg3 Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 24/99] ram: rk3399: Update cs1_row " Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 25/99] ram: rk3399: Add cs1_col enc macro Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 26/99] ram: rk3399: Add ddr version " Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 27/99] ram: rk3399: Add ddrtimingC0 Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 28/99] ram: rk3399: Add DdrMode Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 29/99] ram: rk3399: Handle pctl_cfg return type Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 30/99] ram: rk3399: s/tsel_wr_select_n/tsel_wr_select_dq_n Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 31/99] ram: rk3399: s/tsel_wr_select_p/tsel_wr_select_dq_p Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 32/99] ram: rk3399: s/ca_tsel_wr_select_n/tsel_wr_select_ca_n Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 33/99] ram: rk3399: s/ca_tsel_wr_select_p/tsel_wr_select_ca_p Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 34/99] ram: rk3399: Order tsel variables Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 35/99] ram: rk3399: Add phy pctrl reset support Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 36/99] ram: rk3399: Move pwrup_srefresh_exit to dram_info Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 37/99] ram: rk3399: Add pctl start support Jagan Teki
2019-06-17 7:31 ` Jagan Teki [this message]
2019-06-17 7:31 ` [U-Boot] [PATCH v2 39/99] ram: rk3399: s/rk3399_base_params/sdram_base_params Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 40/99] ram: rk3399: Move common sdram structures in common header Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 41/99] arm: include: rockchip: Move dramtypes to " Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 42/99] arm: include: rockchip: Add DDR4 enum Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 43/99] ram: rockchip: Add initial Kconfig Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 44/99] debug_uart: Add printdec Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 45/99] ram: rockchip: Add debug sdram driver Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 46/99] ram: rockchip: debug: Add sdram_print_ddr_info Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 47/99] ram: rockchip: debug: Get the cs capacity Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 48/99] ram: rk3399: debug: Add sdram_print_stride Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 49/99] ram: rk3399: Compute stride for 2 channels Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 50/99] ram: rk3399: Compute stride for 1 channel a Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 51/99] ram: rk3399: Add rank detection support Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 52/99] ram: rk3399: Enable sdram debug functions Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 53/99] rockchip: dts: rk3399: nanopi-neo4: Use DDR3-1866 dtsi Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 54/99] clk: rockchip: rk3399: Fix check patch warnings and checks Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 55/99] clk: rockchip: rk3399: Set 50MHz ddr clock Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 56/99] clk: rockchip: rk3399: Set 400MHz " Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 57/99] ram: rk3399: Add spaces in pctl_cfg Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 58/99] ram: rk3399: Configure phy IO in ds odt Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 59/99] ram: rockchip: Kconfig: Add RK3399 LPDDR4 entry Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 60/99] ram: rk3399: Add lpddr4 rank mask for ca training Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 61/99] ram: rk3399: Add lpddr4 rank mask for wdql training Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 62/99] ram: rk3399: Move mode_sel assignment Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 63/99] ram: rk3399: Don't wait for PLL lock in lpddr4 Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 64/99] ram: rk3399: Avoid two channel ZQ Cal Start at the same time Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 65/99] ram: rk3399: Configure PHY_898, PHY_919 for lpddr4 Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 66/99] ram: rk3399: Configure BOOSTP_EN, BOOSTN_EN " Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 67/99] ram: rk3399: Configure SLEWP_EN, SLEWN_EN " Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 68/99] ram: rk3399: Configure PHY RX_CM_INPUT " Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 69/99] ram: rk3399: Map chipselect " Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 70/99] ram: rk3399: Configure tsel write ca " Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 71/99] ram: rk3399: Don't disable dfi dram clk for lpddr4, rank 1 Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 72/99] ram: rk3399: Add IO settings Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 73/99] ram: sdram: Configure lpddr4 tsel rd, wr based on " Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 74/99] ram: rk3399: Add tsel control clock drive Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 75/99] ram: rk3399: Configure soc odt support Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 76/99] ram: rk3399: Get lpddr4 tsel_rd_en from io settings Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 77/99] ram: rk3399: Update lpddr4 vref based on " Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 78/99] ram: rk3399: Update lpddr4 mode_sel " Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 79/99] ram: rk3399: Update lpddr4 vref_mode_ac Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 80/99] ram: rk3399: Simplify data training first argument Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 81/99] ram: rk3399: Handle data training via ops Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 82/99] ram: rk3399: Add LPPDR4 mr detection Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 83/99] arm: include: rockchip: Add rk3399 pmu file Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 84/99] rockchip: rk3399: syscon: Add pmu support Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 85/99] rockchip: dts: rk3399: Add u-boot, dm-pre-reloc for pmu Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 86/99] ram: rk3399: Add LPPDDR4-400 timings inc Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 87/99] ram: rk3399: Add LPPDDR4-800 " Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 88/99] ram: rk3399: Add set_rate sdram rk3399 ops Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 89/99] ram: rk3399: Add lpddr4 set rate support Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 90/99] ram: rk3399: Set lpddr4 dq odt Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 91/99] ram: rk3399: Set lpddr4 ca odt Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 92/99] ram: rk3399: Set lpddr4 MR3 Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 93/99] ram: rk3399: Set lpddr4 MR12 Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 94/99] ram: rk3399: Set lpddr4 MR14 Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 95/99] configs: rockpro64: Enable LPDDR4 support Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 96/99] configs: rock-pi-4: " Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 97/99] rockchip: dts: rk3399: Add LPDDR4-100 timings Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 98/99] rockchip: dts: rk3399: rockpro64: Use LPDDR4-100 dtsi Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 99/99] rockchip: dts: rk3399: rock-pi-4: " Jagan Teki
2019-06-21 0:28 ` [U-Boot] [PATCH v2 00/99] ram: rk3399: Add LPDDR4 support Vasily Khoruzhick
2019-06-25 15:46 ` Jagan Teki
2019-06-25 18:42 ` Ezequiel Garcia
2019-06-26 10:22 ` Jagan Teki
2019-07-04 10:27 ` Kever Yang
2019-07-04 10:54 ` Jagan Teki
2019-07-05 7:38 ` Kever Yang
2019-06-25 8:43 ` Mark Kettenis
2019-07-07 13:17 ` Chris Webb
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190617073252.27810-39-jagan@amarulasolutions.com \
--to=jagan@amarulasolutions.com \
--cc=u-boot@lists.denx.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox