From: Jagan Teki <jagan@amarulasolutions.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v2 58/99] ram: rk3399: Configure phy IO in ds odt
Date: Mon, 17 Jun 2019 13:02:11 +0530 [thread overview]
Message-ID: <20190617073252.27810-59-jagan@amarulasolutions.com> (raw)
In-Reply-To: <20190617073252.27810-1-jagan@amarulasolutions.com>
Some dramtypes like lpddr4 initialization would required to
configure phy IO even after pctl_cfg and after set_ds_odt.
For those cases the set_ds_odt would be an initial call to
setup the phy.
To satisfy all the cases, trigger phy IO from set_ds_odt.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 327 ++++++++++++++--------------
1 file changed, 162 insertions(+), 165 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index d5ff17ad4f..7f01681a01 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -188,6 +188,166 @@ static void set_memory_map(const struct chan_info *chan, u32 channel,
writel(0x2EC7FFFF, &denali_pi[34]);
}
+static int phy_io_config(const struct chan_info *chan,
+ const struct rk3399_sdram_params *params)
+{
+ u32 *denali_phy = chan->publ->denali_phy;
+ u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac;
+ u32 mode_sel;
+ u32 reg_value;
+ u32 drv_value, odt_value;
+ u32 speed;
+
+ /* vref setting */
+ if (params->base.dramtype == LPDDR4) {
+ /* LPDDR4 */
+ vref_mode_dq = 0x6;
+ vref_value_dq = 0x1f;
+ vref_mode_ac = 0x6;
+ vref_value_ac = 0x1f;
+ } else if (params->base.dramtype == LPDDR3) {
+ if (params->base.odt == 1) {
+ vref_mode_dq = 0x5; /* LPDDR3 ODT */
+ drv_value = (readl(&denali_phy[6]) >> 12) & 0xf;
+ odt_value = (readl(&denali_phy[6]) >> 4) & 0xf;
+ if (drv_value == PHY_DRV_ODT_48) {
+ switch (odt_value) {
+ case PHY_DRV_ODT_240:
+ vref_value_dq = 0x16;
+ break;
+ case PHY_DRV_ODT_120:
+ vref_value_dq = 0x26;
+ break;
+ case PHY_DRV_ODT_60:
+ vref_value_dq = 0x36;
+ break;
+ default:
+ debug("Invalid ODT value.\n");
+ return -EINVAL;
+ }
+ } else if (drv_value == PHY_DRV_ODT_40) {
+ switch (odt_value) {
+ case PHY_DRV_ODT_240:
+ vref_value_dq = 0x19;
+ break;
+ case PHY_DRV_ODT_120:
+ vref_value_dq = 0x23;
+ break;
+ case PHY_DRV_ODT_60:
+ vref_value_dq = 0x31;
+ break;
+ default:
+ debug("Invalid ODT value.\n");
+ return -EINVAL;
+ }
+ } else if (drv_value == PHY_DRV_ODT_34_3) {
+ switch (odt_value) {
+ case PHY_DRV_ODT_240:
+ vref_value_dq = 0x17;
+ break;
+ case PHY_DRV_ODT_120:
+ vref_value_dq = 0x20;
+ break;
+ case PHY_DRV_ODT_60:
+ vref_value_dq = 0x2e;
+ break;
+ default:
+ debug("Invalid ODT value.\n");
+ return -EINVAL;
+ }
+ } else {
+ debug("Invalid DRV value.\n");
+ return -EINVAL;
+ }
+ } else {
+ vref_mode_dq = 0x2; /* LPDDR3 */
+ vref_value_dq = 0x1f;
+ }
+ vref_mode_ac = 0x2;
+ vref_value_ac = 0x1f;
+ } else if (params->base.dramtype == DDR3) {
+ /* DDR3L */
+ vref_mode_dq = 0x1;
+ vref_value_dq = 0x1f;
+ vref_mode_ac = 0x1;
+ vref_value_ac = 0x1f;
+ } else {
+ debug("Unknown DRAM type.\n");
+ return -EINVAL;
+ }
+
+ reg_value = (vref_mode_dq << 9) | (0x1 << 8) | vref_value_dq;
+
+ /* PHY_913 PHY_PAD_VREF_CTRL_DQ_0 12bits offset_8 */
+ clrsetbits_le32(&denali_phy[913], 0xfff << 8, reg_value << 8);
+ /* PHY_914 PHY_PAD_VREF_CTRL_DQ_1 12bits offset_0 */
+ clrsetbits_le32(&denali_phy[914], 0xfff, reg_value);
+ /* PHY_914 PHY_PAD_VREF_CTRL_DQ_2 12bits offset_16 */
+ clrsetbits_le32(&denali_phy[914], 0xfff << 16, reg_value << 16);
+ /* PHY_915 PHY_PAD_VREF_CTRL_DQ_3 12bits offset_0 */
+ clrsetbits_le32(&denali_phy[915], 0xfff, reg_value);
+
+ reg_value = (vref_mode_ac << 9) | (0x1 << 8) | vref_value_ac;
+
+ /* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */
+ clrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16);
+
+ if (params->base.dramtype == LPDDR4)
+ mode_sel = 0x6;
+ else if (params->base.dramtype == LPDDR3)
+ mode_sel = 0x0;
+ else if (params->base.dramtype == DDR3)
+ mode_sel = 0x1;
+ else
+ return -EINVAL;
+
+ /* PHY_924 PHY_PAD_FDBK_DRIVE */
+ clrsetbits_le32(&denali_phy[924], 0x7 << 15, mode_sel << 15);
+ /* PHY_926 PHY_PAD_DATA_DRIVE */
+ clrsetbits_le32(&denali_phy[926], 0x7 << 6, mode_sel << 6);
+ /* PHY_927 PHY_PAD_DQS_DRIVE */
+ clrsetbits_le32(&denali_phy[927], 0x7 << 6, mode_sel << 6);
+ /* PHY_928 PHY_PAD_ADDR_DRIVE */
+ clrsetbits_le32(&denali_phy[928], 0x7 << 14, mode_sel << 14);
+ /* PHY_929 PHY_PAD_CLK_DRIVE */
+ clrsetbits_le32(&denali_phy[929], 0x7 << 14, mode_sel << 14);
+ /* PHY_935 PHY_PAD_CKE_DRIVE */
+ clrsetbits_le32(&denali_phy[935], 0x7 << 14, mode_sel << 14);
+ /* PHY_937 PHY_PAD_RST_DRIVE */
+ clrsetbits_le32(&denali_phy[937], 0x7 << 14, mode_sel << 14);
+ /* PHY_939 PHY_PAD_CS_DRIVE */
+ clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14);
+
+ /* speed setting */
+ if (params->base.ddr_freq < 400)
+ speed = 0x0;
+ else if (params->base.ddr_freq < 800)
+ speed = 0x1;
+ else if (params->base.ddr_freq < 1200)
+ speed = 0x2;
+ else
+ speed = 0x3;
+
+ /* PHY_924 PHY_PAD_FDBK_DRIVE */
+ clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21);
+ /* PHY_926 PHY_PAD_DATA_DRIVE */
+ clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9);
+ /* PHY_927 PHY_PAD_DQS_DRIVE */
+ clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9);
+ /* PHY_928 PHY_PAD_ADDR_DRIVE */
+ clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17);
+ /* PHY_929 PHY_PAD_CLK_DRIVE */
+ clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17);
+ /* PHY_935 PHY_PAD_CKE_DRIVE */
+ clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17);
+ /* PHY_937 PHY_PAD_RST_DRIVE */
+ clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17);
+ /* PHY_939 PHY_PAD_CS_DRIVE */
+ clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17);
+
+ return 0;
+}
+
static void set_ds_odt(const struct chan_info *chan,
const struct rk3399_sdram_params *params)
{
@@ -332,6 +492,8 @@ static void set_ds_odt(const struct chan_info *chan,
/* phy_pad_fdbk_term 1bit DENALI_PHY_930 offset_17 */
clrsetbits_le32(&denali_phy[930], 0x1 << 17, reg_value);
+
+ phy_io_config(chan, params);
}
static void pctl_start(struct dram_info *dram, u8 channel)
@@ -376,166 +538,6 @@ static void pctl_start(struct dram_info *dram, u8 channel)
dram->pwrup_srefresh_exit[channel]);
}
-static int phy_io_config(const struct chan_info *chan,
- const struct rk3399_sdram_params *params)
-{
- u32 *denali_phy = chan->publ->denali_phy;
- u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac;
- u32 mode_sel;
- u32 reg_value;
- u32 drv_value, odt_value;
- u32 speed;
-
- /* vref setting */
- if (params->base.dramtype == LPDDR4) {
- /* LPDDR4 */
- vref_mode_dq = 0x6;
- vref_value_dq = 0x1f;
- vref_mode_ac = 0x6;
- vref_value_ac = 0x1f;
- } else if (params->base.dramtype == LPDDR3) {
- if (params->base.odt == 1) {
- vref_mode_dq = 0x5; /* LPDDR3 ODT */
- drv_value = (readl(&denali_phy[6]) >> 12) & 0xf;
- odt_value = (readl(&denali_phy[6]) >> 4) & 0xf;
- if (drv_value == PHY_DRV_ODT_48) {
- switch (odt_value) {
- case PHY_DRV_ODT_240:
- vref_value_dq = 0x16;
- break;
- case PHY_DRV_ODT_120:
- vref_value_dq = 0x26;
- break;
- case PHY_DRV_ODT_60:
- vref_value_dq = 0x36;
- break;
- default:
- debug("Invalid ODT value.\n");
- return -EINVAL;
- }
- } else if (drv_value == PHY_DRV_ODT_40) {
- switch (odt_value) {
- case PHY_DRV_ODT_240:
- vref_value_dq = 0x19;
- break;
- case PHY_DRV_ODT_120:
- vref_value_dq = 0x23;
- break;
- case PHY_DRV_ODT_60:
- vref_value_dq = 0x31;
- break;
- default:
- debug("Invalid ODT value.\n");
- return -EINVAL;
- }
- } else if (drv_value == PHY_DRV_ODT_34_3) {
- switch (odt_value) {
- case PHY_DRV_ODT_240:
- vref_value_dq = 0x17;
- break;
- case PHY_DRV_ODT_120:
- vref_value_dq = 0x20;
- break;
- case PHY_DRV_ODT_60:
- vref_value_dq = 0x2e;
- break;
- default:
- debug("Invalid ODT value.\n");
- return -EINVAL;
- }
- } else {
- debug("Invalid DRV value.\n");
- return -EINVAL;
- }
- } else {
- vref_mode_dq = 0x2; /* LPDDR3 */
- vref_value_dq = 0x1f;
- }
- vref_mode_ac = 0x2;
- vref_value_ac = 0x1f;
- } else if (params->base.dramtype == DDR3) {
- /* DDR3L */
- vref_mode_dq = 0x1;
- vref_value_dq = 0x1f;
- vref_mode_ac = 0x1;
- vref_value_ac = 0x1f;
- } else {
- debug("Unknown DRAM type.\n");
- return -EINVAL;
- }
-
- reg_value = (vref_mode_dq << 9) | (0x1 << 8) | vref_value_dq;
-
- /* PHY_913 PHY_PAD_VREF_CTRL_DQ_0 12bits offset_8 */
- clrsetbits_le32(&denali_phy[913], 0xfff << 8, reg_value << 8);
- /* PHY_914 PHY_PAD_VREF_CTRL_DQ_1 12bits offset_0 */
- clrsetbits_le32(&denali_phy[914], 0xfff, reg_value);
- /* PHY_914 PHY_PAD_VREF_CTRL_DQ_2 12bits offset_16 */
- clrsetbits_le32(&denali_phy[914], 0xfff << 16, reg_value << 16);
- /* PHY_915 PHY_PAD_VREF_CTRL_DQ_3 12bits offset_0 */
- clrsetbits_le32(&denali_phy[915], 0xfff, reg_value);
-
- reg_value = (vref_mode_ac << 9) | (0x1 << 8) | vref_value_ac;
-
- /* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */
- clrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16);
-
- if (params->base.dramtype == LPDDR4)
- mode_sel = 0x6;
- else if (params->base.dramtype == LPDDR3)
- mode_sel = 0x0;
- else if (params->base.dramtype == DDR3)
- mode_sel = 0x1;
- else
- return -EINVAL;
-
- /* PHY_924 PHY_PAD_FDBK_DRIVE */
- clrsetbits_le32(&denali_phy[924], 0x7 << 15, mode_sel << 15);
- /* PHY_926 PHY_PAD_DATA_DRIVE */
- clrsetbits_le32(&denali_phy[926], 0x7 << 6, mode_sel << 6);
- /* PHY_927 PHY_PAD_DQS_DRIVE */
- clrsetbits_le32(&denali_phy[927], 0x7 << 6, mode_sel << 6);
- /* PHY_928 PHY_PAD_ADDR_DRIVE */
- clrsetbits_le32(&denali_phy[928], 0x7 << 14, mode_sel << 14);
- /* PHY_929 PHY_PAD_CLK_DRIVE */
- clrsetbits_le32(&denali_phy[929], 0x7 << 14, mode_sel << 14);
- /* PHY_935 PHY_PAD_CKE_DRIVE */
- clrsetbits_le32(&denali_phy[935], 0x7 << 14, mode_sel << 14);
- /* PHY_937 PHY_PAD_RST_DRIVE */
- clrsetbits_le32(&denali_phy[937], 0x7 << 14, mode_sel << 14);
- /* PHY_939 PHY_PAD_CS_DRIVE */
- clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14);
-
- /* speed setting */
- if (params->base.ddr_freq < 400)
- speed = 0x0;
- else if (params->base.ddr_freq < 800)
- speed = 0x1;
- else if (params->base.ddr_freq < 1200)
- speed = 0x2;
- else
- speed = 0x3;
-
- /* PHY_924 PHY_PAD_FDBK_DRIVE */
- clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21);
- /* PHY_926 PHY_PAD_DATA_DRIVE */
- clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9);
- /* PHY_927 PHY_PAD_DQS_DRIVE */
- clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9);
- /* PHY_928 PHY_PAD_ADDR_DRIVE */
- clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17);
- /* PHY_929 PHY_PAD_CLK_DRIVE */
- clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17);
- /* PHY_935 PHY_PAD_CKE_DRIVE */
- clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17);
- /* PHY_937 PHY_PAD_RST_DRIVE */
- clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17);
- /* PHY_939 PHY_PAD_CS_DRIVE */
- clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17);
-
- return 0;
-}
-
static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
u32 channel, const struct rk3399_sdram_params *params)
{
@@ -545,7 +547,6 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
const u32 *params_ctl = params->pctl_regs.denali_ctl;
const u32 *params_phy = params->phy_regs.denali_phy;
u32 tmp, tmp1, tmp2;
- int ret;
/*
* work around controller bug:
@@ -623,10 +624,6 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
tmp = (readl(&denali_phy[467]) >> 16) & 0xff;
clrsetbits_le32(&denali_phy[467], 0xff << 16, (tmp + 0x10) << 16);
- ret = phy_io_config(chan, params);
- if (ret)
- return ret;
-
return 0;
}
--
2.18.0.321.gffc6fa0e3
next prev parent reply other threads:[~2019-06-17 7:32 UTC|newest]
Thread overview: 112+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-17 7:31 [U-Boot] [PATCH v2 00/99] ram: rk3399: Add LPDDR4 support Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 01/99] ram: rk3399: Fix code warnings Jagan Teki
2019-07-15 12:31 ` Kever Yang
2019-06-17 7:31 ` [U-Boot] [PATCH v2 02/99] ram: rk3399: Add space between string with format specifier Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 03/99] ram: rk3399: Add proper spaces in code Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 04/99] ram: rk3399: s/sdram_params/params Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 05/99] ram: rk3399: Handle data training return types Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 06/99] ram: rk3399: Order include files Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 07/99] ram: rk3399: Move macro after " Jagan Teki
2019-07-15 12:39 ` Kever Yang
2019-06-17 7:31 ` [U-Boot] [PATCH v2 08/99] ram: rk3399: Clear PI_175 interrupts in data training Jagan Teki
2019-07-15 12:39 ` Kever Yang
2019-06-17 7:31 ` [U-Boot] [PATCH v2 09/99] ram: rk3399: Use rank mask in ca " Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 10/99] ram: rk3399: Use rank mask in wdql " Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 11/99] ram: rk3399: Add ddrtype enc macro Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 12/99] ram: rk3399: Add channel number encoder macro Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 13/99] ram: rk3399: Add row_3_4 enc macro Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 14/99] ram: rk3399: Add chipinfo macro Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 15/99] ram: rk3399: Add rank enc macro Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 16/99] ram: rk3399: Add column " Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 17/99] ram: rk3399: Add bk " Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 18/99] ram: rk3399: Add dbw " Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 19/99] ram: rk3399: Add cs0_rw macro Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 20/99] ram: rk3399: Add cs1_rw macro Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 21/99] ram: rk3399: Add bw enc macro Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 22/99] ram: rk3399: Rename sys_reg with sys_reg2 Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 23/99] ram: rk3399: Update cs0_row to use sys_reg3 Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 24/99] ram: rk3399: Update cs1_row " Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 25/99] ram: rk3399: Add cs1_col enc macro Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 26/99] ram: rk3399: Add ddr version " Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 27/99] ram: rk3399: Add ddrtimingC0 Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 28/99] ram: rk3399: Add DdrMode Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 29/99] ram: rk3399: Handle pctl_cfg return type Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 30/99] ram: rk3399: s/tsel_wr_select_n/tsel_wr_select_dq_n Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 31/99] ram: rk3399: s/tsel_wr_select_p/tsel_wr_select_dq_p Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 32/99] ram: rk3399: s/ca_tsel_wr_select_n/tsel_wr_select_ca_n Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 33/99] ram: rk3399: s/ca_tsel_wr_select_p/tsel_wr_select_ca_p Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 34/99] ram: rk3399: Order tsel variables Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 35/99] ram: rk3399: Add phy pctrl reset support Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 36/99] ram: rk3399: Move pwrup_srefresh_exit to dram_info Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 37/99] ram: rk3399: Add pctl start support Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 38/99] ram: rockchip: rk3399: Add cap_info structure Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 39/99] ram: rk3399: s/rk3399_base_params/sdram_base_params Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 40/99] ram: rk3399: Move common sdram structures in common header Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 41/99] arm: include: rockchip: Move dramtypes to " Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 42/99] arm: include: rockchip: Add DDR4 enum Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 43/99] ram: rockchip: Add initial Kconfig Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 44/99] debug_uart: Add printdec Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 45/99] ram: rockchip: Add debug sdram driver Jagan Teki
2019-06-17 7:31 ` [U-Boot] [PATCH v2 46/99] ram: rockchip: debug: Add sdram_print_ddr_info Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 47/99] ram: rockchip: debug: Get the cs capacity Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 48/99] ram: rk3399: debug: Add sdram_print_stride Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 49/99] ram: rk3399: Compute stride for 2 channels Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 50/99] ram: rk3399: Compute stride for 1 channel a Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 51/99] ram: rk3399: Add rank detection support Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 52/99] ram: rk3399: Enable sdram debug functions Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 53/99] rockchip: dts: rk3399: nanopi-neo4: Use DDR3-1866 dtsi Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 54/99] clk: rockchip: rk3399: Fix check patch warnings and checks Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 55/99] clk: rockchip: rk3399: Set 50MHz ddr clock Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 56/99] clk: rockchip: rk3399: Set 400MHz " Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 57/99] ram: rk3399: Add spaces in pctl_cfg Jagan Teki
2019-06-17 7:32 ` Jagan Teki [this message]
2019-06-17 7:32 ` [U-Boot] [PATCH v2 59/99] ram: rockchip: Kconfig: Add RK3399 LPDDR4 entry Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 60/99] ram: rk3399: Add lpddr4 rank mask for ca training Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 61/99] ram: rk3399: Add lpddr4 rank mask for wdql training Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 62/99] ram: rk3399: Move mode_sel assignment Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 63/99] ram: rk3399: Don't wait for PLL lock in lpddr4 Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 64/99] ram: rk3399: Avoid two channel ZQ Cal Start at the same time Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 65/99] ram: rk3399: Configure PHY_898, PHY_919 for lpddr4 Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 66/99] ram: rk3399: Configure BOOSTP_EN, BOOSTN_EN " Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 67/99] ram: rk3399: Configure SLEWP_EN, SLEWN_EN " Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 68/99] ram: rk3399: Configure PHY RX_CM_INPUT " Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 69/99] ram: rk3399: Map chipselect " Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 70/99] ram: rk3399: Configure tsel write ca " Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 71/99] ram: rk3399: Don't disable dfi dram clk for lpddr4, rank 1 Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 72/99] ram: rk3399: Add IO settings Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 73/99] ram: sdram: Configure lpddr4 tsel rd, wr based on " Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 74/99] ram: rk3399: Add tsel control clock drive Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 75/99] ram: rk3399: Configure soc odt support Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 76/99] ram: rk3399: Get lpddr4 tsel_rd_en from io settings Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 77/99] ram: rk3399: Update lpddr4 vref based on " Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 78/99] ram: rk3399: Update lpddr4 mode_sel " Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 79/99] ram: rk3399: Update lpddr4 vref_mode_ac Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 80/99] ram: rk3399: Simplify data training first argument Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 81/99] ram: rk3399: Handle data training via ops Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 82/99] ram: rk3399: Add LPPDR4 mr detection Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 83/99] arm: include: rockchip: Add rk3399 pmu file Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 84/99] rockchip: rk3399: syscon: Add pmu support Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 85/99] rockchip: dts: rk3399: Add u-boot, dm-pre-reloc for pmu Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 86/99] ram: rk3399: Add LPPDDR4-400 timings inc Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 87/99] ram: rk3399: Add LPPDDR4-800 " Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 88/99] ram: rk3399: Add set_rate sdram rk3399 ops Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 89/99] ram: rk3399: Add lpddr4 set rate support Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 90/99] ram: rk3399: Set lpddr4 dq odt Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 91/99] ram: rk3399: Set lpddr4 ca odt Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 92/99] ram: rk3399: Set lpddr4 MR3 Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 93/99] ram: rk3399: Set lpddr4 MR12 Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 94/99] ram: rk3399: Set lpddr4 MR14 Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 95/99] configs: rockpro64: Enable LPDDR4 support Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 96/99] configs: rock-pi-4: " Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 97/99] rockchip: dts: rk3399: Add LPDDR4-100 timings Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 98/99] rockchip: dts: rk3399: rockpro64: Use LPDDR4-100 dtsi Jagan Teki
2019-06-17 7:32 ` [U-Boot] [PATCH v2 99/99] rockchip: dts: rk3399: rock-pi-4: " Jagan Teki
2019-06-21 0:28 ` [U-Boot] [PATCH v2 00/99] ram: rk3399: Add LPDDR4 support Vasily Khoruzhick
2019-06-25 15:46 ` Jagan Teki
2019-06-25 18:42 ` Ezequiel Garcia
2019-06-26 10:22 ` Jagan Teki
2019-07-04 10:27 ` Kever Yang
2019-07-04 10:54 ` Jagan Teki
2019-07-05 7:38 ` Kever Yang
2019-06-25 8:43 ` Mark Kettenis
2019-07-07 13:17 ` Chris Webb
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