[U-Boot] [PATCH 06/12] arm: spear: Purely cosmetic changes in start.S

Miquel Raynal
2019-05-07T12:18:48Z

Before cleaning a bit further the spear/start.S file, apply a few
cosmetic changes: capital letters, comment indentation and small
rewriting.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
arch/arm/cpu/arm926ejs/spear/start.S | 17 ++++++++---------
1 file changed, 8 insertions(+), 9 deletions(-)

diff --git a/arch/arm/cpu/arm926ejs/spear/start.S b/arch/arm/cpu/arm926ejs/spear/start.S
index c3bb58c55b..566cf668b7 100644
--- a/arch/arm/cpu/arm926ejs/spear/start.S
+++ b/arch/arm/cpu/arm926ejs/spear/start.S
@@ -31,11 +31,10 @@
.globl reset

reset:
-/*
- * SPL has to return back to BootROM in a few cases.
- * eg. Ethernet boot, UART boot, USB boot
- * Saving registers for returning back
- */
+ /*
+ * SPL has to return back to BootROM in a few cases (eg. Ethernet boot,
+ * UART boot, USB boot): save registers in BootROM's stack.
+ */
stmdb sp!, {r0-r12,r14}
bl cpu_init_crit
ldmia sp!, {r0-r12,pc}
@@ -52,14 +51,14 @@ reset:
*/
cpu_init_crit:
/*
- * flush v4 I/D caches
+ * Flush v4 I/D caches
*/
mov r0, #0
- mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
- mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
+ mcr p15, 0, r0, c7, c7, 0 /* Flush v3/v4 cache */
+ mcr p15, 0, r0, c8, c7, 0 /* Flush v4 TLB */

/*
- * enable instruction cache
+ * Enable instruction cache
*/
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
--
2.19.1