From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jagan Teki Date: Tue, 16 Jul 2019 17:27:12 +0530 Subject: [U-Boot] [PATCH v3 24/57] ram: rk3399: Don't wait for PLL lock in lpddr4 In-Reply-To: <20190716115745.12585-1-jagan@amarulasolutions.com> References: <20190716115745.12585-1-jagan@amarulasolutions.com> Message-ID: <20190716115745.12585-25-jagan@amarulasolutions.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de lpddr4 has PLL bypass mode during phy initialization phase, which does all pll configurations. So no need to wait explicitly during pctl config. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen --- drivers/ram/rockchip/sdram_rk3399.c | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 88fbfa440d..023838a301 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -570,16 +570,22 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan, setbits_le32(&denali_pi[0], START); setbits_le32(&denali_ctl[0], START); - /* Waiting for phy DLL lock */ - while (1) { - tmp = readl(&denali_phy[920]); - tmp1 = readl(&denali_phy[921]); - tmp2 = readl(&denali_phy[922]); - if ((((tmp >> 16) & 0x1) == 0x1) && - (((tmp1 >> 16) & 0x1) == 0x1) && - (((tmp1 >> 0) & 0x1) == 0x1) && - (((tmp2 >> 0) & 0x1) == 0x1)) - break; + /** + * LPDDR4 use PLL bypass mode for init + * not need to wait for the PLL to lock + */ + if (params->base.dramtype != LPDDR4) { + /* Waiting for phy DLL lock */ + while (1) { + tmp = readl(&denali_phy[920]); + tmp1 = readl(&denali_phy[921]); + tmp2 = readl(&denali_phy[922]); + if ((((tmp >> 16) & 0x1) == 0x1) && + (((tmp1 >> 16) & 0x1) == 0x1) && + (((tmp1 >> 0) & 0x1) == 0x1) && + (((tmp2 >> 0) & 0x1) == 0x1)) + break; + } } copy_to_reg(&denali_phy[896], ¶ms_phy[896], (958 - 895) * 4); -- 2.18.0.321.gffc6fa0e3