* [U-Boot] [PATCH 4/5] mx7ulp: Select the SCG1 APLL PFD as a system clock source
2019-05-15 9:56 [U-Boot] [PATCH 0/5] i.MX7ULP EVK: update ddr script to make board boot Peng Fan
@ 2019-05-15 9:56 ` Peng Fan
0 siblings, 0 replies; 2+ messages in thread
From: Peng Fan @ 2019-05-15 9:56 UTC (permalink / raw)
To: u-boot
From: Ye Li <ye.li@nxp.com>
Due to the APLL out glitch issue, the APLLCFG PLLS bit must
be set to select SCG1 APLL PFD for generating system clock to align
with the design.
Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
---
board/freescale/mx7ulp_evk/imximage.cfg | 2 +-
board/freescale/mx7ulp_evk/plugin.S | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/freescale/mx7ulp_evk/imximage.cfg b/board/freescale/mx7ulp_evk/imximage.cfg
index d4f6c3c62d..6bc7c199f5 100644
--- a/board/freescale/mx7ulp_evk/imximage.cfg
+++ b/board/freescale/mx7ulp_evk/imximage.cfg
@@ -45,7 +45,7 @@ DATA 4 0x403f00dc 0x00000000
DATA 4 0x403e0040 0x01000020
DATA 4 0x403e0500 0x01000000
DATA 4 0x403e050c 0x80808080
-DATA 4 0x403e0508 0x00160000
+DATA 4 0x403e0508 0x00160002
DATA 4 0x403E0510 0x00000002
DATA 4 0x403E0514 0x00000005
DATA 4 0x403e0500 0x00000001
diff --git a/board/freescale/mx7ulp_evk/plugin.S b/board/freescale/mx7ulp_evk/plugin.S
index ccd2fc03a4..55dfecc751 100644
--- a/board/freescale/mx7ulp_evk/plugin.S
+++ b/board/freescale/mx7ulp_evk/plugin.S
@@ -18,7 +18,7 @@
ldr r3, =0x80808080
str r3, [r2, #0x50c]
- ldr r3, =0x00160000
+ ldr r3, =0x00160002
str r3, [r2, #0x508]
ldr r3, =0x00000002
str r3, [r2, #0x510]
--
2.16.4
^ permalink raw reply related [flat|nested] 2+ messages in thread
* [U-Boot] [PATCH 4/5] mx7ulp: Select the SCG1 APLL PFD as a system clock source
@ 2019-07-20 8:46 sbabic at denx.de
0 siblings, 0 replies; 2+ messages in thread
From: sbabic at denx.de @ 2019-07-20 8:46 UTC (permalink / raw)
To: u-boot
> From: Ye Li <ye.li@nxp.com>
> Due to the APLL out glitch issue, the APLLCFG PLLS bit must
> be set to select SCG1 APLL PFD for generating system clock to align
> with the design.
> Signed-off-by: Ye Li <ye.li@nxp.com>
> Acked-by: Peng Fan <peng.fan@nxp.com>
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2019-07-20 8:46 UTC | newest]
Thread overview: 2+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2019-07-20 8:46 [U-Boot] [PATCH 4/5] mx7ulp: Select the SCG1 APLL PFD as a system clock source sbabic at denx.de
-- strict thread matches above, loose matches on Subject: below --
2019-05-15 9:56 [U-Boot] [PATCH 0/5] i.MX7ULP EVK: update ddr script to make board boot Peng Fan
2019-05-15 9:56 ` [U-Boot] [PATCH 4/5] mx7ulp: Select the SCG1 APLL PFD as a system clock source Peng Fan
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox