[U-Boot] [PATCH 13/22] imx8m: Fix MMU table issue for OPTEE memory

[Lukasz Majewski <lukma@denx.de>]

On Fri, 9 Aug 2019 04:15:21 +0000
Peng Fan <peng.fan@nxp.com> wrote:

> When running with OPTEE, the MMU table in u-boot does not remove the
> OPTEE memory from its settings. So ARM speculative prefetch in u-boot
> may access that OPTEE memory. Due to trust zone is enabled by OPTEE
> and that memory is set to secure access, then the speculative
> prefetch will fail and cause various memory issue in u-boot.
> The fail address register and int_status register in trustzone has
> logged that speculative access from u-boot.
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  arch/arm/mach-imx/imx8m/soc.c | 20 ++++++++++++++++++--
>  1 file changed, 18 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mach-imx/imx8m/soc.c
> b/arch/arm/mach-imx/imx8m/soc.c index 5115471eff..dd393b581b 100644
> --- a/arch/arm/mach-imx/imx8m/soc.c
> +++ b/arch/arm/mach-imx/imx8m/soc.c
> @@ -112,16 +112,18 @@ static struct mm_region imx8m_mem_map[] = {
>  		/* DRAM1 */
>  		.virt = 0x40000000UL,
>  		.phys = 0x40000000UL,
> -		.size = 0xC0000000UL,
> +		.size = PHYS_SDRAM_SIZE,

Wouldn't this change break other imx8m boards?

>  		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
>  			 PTE_BLOCK_OUTER_SHARE
> +#ifdef PHYS_SDRAM_2_SIZE
>  	}, {
>  		/* DRAM2 */
>  		.virt = 0x100000000UL,
>  		.phys = 0x100000000UL,
> -		.size = 0x040000000UL,
> +		.size = PHYS_SDRAM_2_SIZE,

The same here.

>  		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
>  			 PTE_BLOCK_OUTER_SHARE
> +#endif
>  	}, {
>  		/* List terminator */
>  		0,
> @@ -130,6 +132,20 @@ static struct mm_region imx8m_mem_map[] = {
>  
>  struct mm_region *mem_map = imx8m_mem_map;
>  
> +void enable_caches(void)
> +{
> +	/*
> +	 * If OPTEE runs, remove OPTEE memory from MMU table to
> +	 * avoid speculative prefetch. OPTEE runs at the top of
> +	 * the first memory bank
> +	 */
> +	if (rom_pointer[1])
> +		imx8m_mem_map[5].size -= rom_pointer[1];
> +
> +	icache_enable();
> +	dcache_enable();

In the other patch (which adds board based on imx8mm - in this series
22/22) the D and I caches were disabled. Why you add code to enable
them and those are not enabled on imx8mm EVK board?

> +}
> +
>  static u32 get_cpu_variant_type(u32 type)
>  {
>  	struct ocotp_regs *ocotp = (struct ocotp_regs
> *)OCOTP_BASE_ADDR;



Best regards,

Lukasz Majewski

--

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