From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andy Shevchenko Date: Thu, 29 Aug 2019 17:04:20 +0300 Subject: [U-Boot] [PATCH v1 3/4] x86: tangier: Fix off-by-one error when preparing CSRT In-Reply-To: <20190829140421.2830-1-andriy.shevchenko@linux.intel.com> References: <20190829140421.2830-1-andriy.shevchenko@linux.intel.com> Message-ID: <20190829140421.2830-3-andriy.shevchenko@linux.intel.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Intel iDMA 32-bit controller has 17 bits for the maximum block size value. Due to nature of the binary number representation the maximum value is 2^17 - 1. The original code misses the latter part in equation. Fixes: 5e99fde34a77 ("x86: tangier: Populate CSRT for shared DMA controller") Signed-off-by: Andy Shevchenko --- arch/x86/cpu/tangier/acpi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/cpu/tangier/acpi.c b/arch/x86/cpu/tangier/acpi.c index 362e133cf1..8b128138b0 100644 --- a/arch/x86/cpu/tangier/acpi.c +++ b/arch/x86/cpu/tangier/acpi.c @@ -95,7 +95,7 @@ static u32 acpi_fill_csrt_dma(struct acpi_csrt_group *grp) si->dma_address_width = 32; si->base_request_line = 0; si->num_handshake_signals = 16; - si->max_block_size = 0x20000; + si->max_block_size = 0x1ffff; return grp->length; } -- 2.23.0.rc1