* [U-Boot] [PATCH 1/5] ARM: MediaTek: Add support for MediaTek MT8518 SoC [not found] <20190911064818.1723-1-mingming.lee@mediatek.com> @ 2019-09-11 6:48 ` mingming lee 0 siblings, 0 replies; 6+ messages in thread From: mingming lee @ 2019-09-11 6:48 UTC (permalink / raw) To: u-boot Add support for MediaTek MT8518 SoC. This include the file that will initialize the SoC after boot and its device tree. Signed-off-by: mingming lee <mingming.lee@mediatek.com> --- arch/arm/dts/mt8518.dtsi | 201 ++++++++++++++++++ arch/arm/mach-mediatek/Kconfig | 9 + arch/arm/mach-mediatek/Makefile | 1 + arch/arm/mach-mediatek/mt8518/Makefile | 4 + arch/arm/mach-mediatek/mt8518/init.c | 116 ++++++++++ arch/arm/mach-mediatek/mt8518/lowlevel_init.S | 59 +++++ 6 files changed, 390 insertions(+) create mode 100644 arch/arm/dts/mt8518.dtsi create mode 100644 arch/arm/mach-mediatek/mt8518/Makefile create mode 100644 arch/arm/mach-mediatek/mt8518/init.c create mode 100644 arch/arm/mach-mediatek/mt8518/lowlevel_init.S diff --git a/arch/arm/dts/mt8518.dtsi b/arch/arm/dts/mt8518.dtsi new file mode 100644 index 0000000000..39d001884f --- /dev/null +++ b/arch/arm/dts/mt8518.dtsi @@ -0,0 +1,201 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2019 MediaTek Inc. + * Author: Mingming Lee <mingming.lee@mediatek.com> + * + */ + +#include <dt-bindings/clock/mt8518-clk.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "mediatek,mt8518"; + interrupt-parent = <&sysirq>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "mediatek,mt8518-smp"; + + cpu0: cpu at 0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + clock-frequency = <1300000000>; + }; + + cpu1: cpu at 1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + clock-frequency = <1300000000>; + }; + + cpu2: cpu at 2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + clock-frequency = <1300000000>; + }; + + cpu3: cpu at 3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + clock-frequency = <1300000000>; + }; + }; + + chipid: chipid at 08000000 { + compatible = "mediatek,chipid"; + reg = <0x08000000 0x0004>, + <0x08000004 0x0004>, + <0x08000008 0x0004>, + <0x0800000c 0x0004>; + }; + + topckgen: clock-controller at 10000000 { + compatible = "mediatek,mt8518-topckgen"; + reg = <0x10000000 0x1000>; + #clock-cells = <1>; + }; + + topckgen_cg: clock-controller-cg at 10000000 { + compatible = "mediatek,mt8518-topckgen-cg"; + reg = <0x10000000 0x1000>; + #clock-cells = <1>; + }; + + apmixedsys: clock-controller at 10018000 { + compatible = "mediatek,mt8518-apmixedsys"; + reg = <0x10018000 0x1000>; + #clock-cells = <1>; + }; + + gic: interrupt-controller at 0c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0xc000000 0x40000>, /* GICD */ + <0xc100000 0x200000>; /* GICR */ + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + sysirq: interrupt-controller at 10200a80 { + compatible = "mediatek,sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0x10200a80 0x50>; + }; + + apdma: dma-controller at 11000480 { + compatible = "mediatek,mt8518-uart-dma", + "mediatek,mt6577-uart-dma"; + reg = <0x11000480 0x80>, + <0x11000500 0x80>, + <0x11000580 0x80>, + <0x11000600 0x80>, + <0x11000980 0x80>, + <0x11000a00 0x80>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_APDMA>; + clock-names = "apdma"; + #dma-cells = <1>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + clock-frequency = <13000000>; + }; + + timer0: apxgpt at 10008000 { + compatible = "mediatek,timer", + "mediatek,mt8518-timer", + "mediatek,mt6577-timer"; + reg = <0x10008000 0x1000>; + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_CLK26M_D2>, + <&topckgen CLK_TOP_CLK32K>, + <&topckgen CLK_TOP_APXGPT>; + clock-names = "clk13m", + "clk32k", + "bus"; + }; + + watchdog: watchdog at 10007000 { + compatible = "mediatek,wdt"; + reg = <0x10007000 0x1000>; + interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_FALLING>; + #reset-cells = <1>; + status = "disabled"; + }; + + mmc0: mmc at 11120000 { + compatible = "mediatek,mt8516-mmc"; + reg = <0x11120000 0x1000>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_MSDC0>, + <&topckgen CLK_TOP_MSDC0>, + <&topckgen CLK_TOP_MSDC0_B>; + clock-names = "source", "hclk", "source_cg"; + status = "disabled"; + }; + + uart0: serial at 11005000 { + compatible = "mediatek,hsuart"; + reg = <0x11005000 0x1000>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_UART0_SEL>, + <&topckgen CLK_TOP_UART0>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart1: serial at 11001A000 { + compatible = "mediatek,hsuart"; + reg = <0x1001A000 0x1000>; + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_UART1_SEL>, + <&topckgen CLK_TOP_UART1>; + clock-names = "baud", "bus"; + dmas = <&apdma 2 + &apdma 3>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart2: serial at 11007000 { + compatible = "mediatek,hsuart"; + reg = <0x11007000 0x1000>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_UART2_SEL>, + <&topckgen CLK_TOP_UART2>; + clock-names = "baud", "bus"; + dmas = <&apdma 4 + &apdma 5>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + +}; diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig index 25ef7651f0..8e343c3182 100644 --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig @@ -38,6 +38,15 @@ config TARGET_MT8516 Ethernet, IR TX/RX, I2C, I2S, S/PDIF, and built-in Wi-Fi / Bluetooth combo chip and several DDR3 and DDR4 options. +config TARGET_MT8518 + bool "MediaTek MT8518 SoC" + select ARM64 + help + The MediaTek MT8518 is a ARM64-based SoC with a quad-core Cortex-A53. + including UART, SPI, USB2.0 and OTG, SD and MMC cards, NAND, PWM, + Ethernet, IR TX/RX, I2C, I2S, S/PDIF, and built-in Wi-Fi / Bluetooth combo + chip and several DDR3 and DDR4 options. + endchoice source "board/mediatek/mt7623/Kconfig" diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile index ea414dc407..b9b2355e03 100644 --- a/arch/arm/mach-mediatek/Makefile +++ b/arch/arm/mach-mediatek/Makefile @@ -6,3 +6,4 @@ obj-$(CONFIG_SPL_BUILD) += spl.o obj-$(CONFIG_TARGET_MT7623) += mt7623/ obj-$(CONFIG_TARGET_MT7629) += mt7629/ obj-$(CONFIG_TARGET_MT8516) += mt8516/ +obj-$(CONFIG_TARGET_MT8518) += mt8518/ diff --git a/arch/arm/mach-mediatek/mt8518/Makefile b/arch/arm/mach-mediatek/mt8518/Makefile new file mode 100644 index 0000000000..007eb4a367 --- /dev/null +++ b/arch/arm/mach-mediatek/mt8518/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y += init.o +obj-y += lowlevel_init.o diff --git a/arch/arm/mach-mediatek/mt8518/init.c b/arch/arm/mach-mediatek/mt8518/init.c new file mode 100644 index 0000000000..419454f794 --- /dev/null +++ b/arch/arm/mach-mediatek/mt8518/init.c @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Configuration for MediaTek MT8518 SoC + * + * Copyright (C) 2019 MediaTek Inc. + * Author: Mingming Lee <mingming.lee@mediatek.com> + */ + +#include <clk.h> +#include <common.h> +#include <dm.h> +#include <fdtdec.h> +#include <ram.h> +#include <asm/arch/misc.h> +#include <asm/armv8/mmu.h> +#include <asm/sections.h> +#include <dm/uclass.h> +#include <dt-bindings/clock/mt8518-clk.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + int ret; + + ret = fdtdec_setup_memory_banksize(); + if (ret) + return ret; + + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = gd->ram_base; + gd->bd->bi_dram[0].size = gd->ram_size; + + return 0; +} + +int mtk_pll_early_init(void) +{ + unsigned long pll_rates[] = { + [CLK_APMIXED_ARMPLL] = 1300000000, + [CLK_APMIXED_MAINPLL] = 1501000000, + [CLK_APMIXED_UNIVPLL] = 1248000000, + [CLK_APMIXED_MMPLL] = 380000000, + }; + struct udevice *dev; + int ret, i; + + ret = uclass_get_device_by_driver(UCLASS_CLK, + DM_GET_DRIVER(mtk_clk_apmixedsys), + &dev); + if (ret) + return ret; + + /* configure default rate then enable apmixedsys */ + for (i = 0; i < ARRAY_SIZE(pll_rates); i++) { + struct clk clk = { .id = i, .dev = dev }; + + ret = clk_set_rate(&clk, pll_rates[i]); + if (ret) + return ret; + + ret = clk_enable(&clk); + if (ret) + return ret; + } + + return 0; +} + +int mtk_soc_early_init(void) +{ + int ret; + + /* initialize early clocks */ + ret = mtk_pll_early_init(); + if (ret) + return ret; + + return 0; +} + +void reset_cpu(ulong addr) +{ + psci_system_reset(); +} + +int print_cpuinfo(void) +{ + printf("CPU: MediaTek MT8518\n"); + return 0; +} + +static struct mm_region mt8518_mem_map[] = { + { + /* DDR */ + .virt = 0x40000000UL, + .phys = 0x40000000UL, + .size = 0x20000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, + }, { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x20000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + 0, + } +}; + +struct mm_region *mem_map = mt8518_mem_map; diff --git a/arch/arm/mach-mediatek/mt8518/lowlevel_init.S b/arch/arm/mach-mediatek/mt8518/lowlevel_init.S new file mode 100644 index 0000000000..3db4ee5b85 --- /dev/null +++ b/arch/arm/mach-mediatek/mt8518/lowlevel_init.S @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 MediaTek Inc. + * Author: Mingming Lee <mingming.lee@mediatek.com> + */ + +/*pre-loader LK to uboot argument Location*/ +.global BOOT_ARGUMENT_DRAM_SIZE +BOOT_ARGUMENT_DRAM_SIZE: + .word 0x00000000 + +.global BOOT_ARGUMENT_LINUX_ID +BOOT_ARGUMENT_LINUX_ID: + .word 0x00000000 + +.global BOOT_ARGUMENT_LOCATION +BOOT_ARGUMENT_LOCATION: + .word 0x00000000 + +/****************To instead what defined in start.S************************** + *void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) __attribute__((weak)) + ****************************************************************************/ + +.globl save_boot_params +save_boot_params: + ldr x6, =BOOT_ARGUMENT_DRAM_SIZE + str x0, [x6] + ldr x6, =BOOT_ARGUMENT_LINUX_ID + str x1, [x6] + ldr x6, =BOOT_ARGUMENT_LOCATION + str x2, [x6] + b save_boot_params_ret + +/* + * Switch from AArch64 EL2 to AArch32 EL2 + * @param inputs: + * x0: argument, zero + * x1: machine nr + * x2: fdt address + * x3: input argument + * x4: kernel entry point + * @param outputs for secure firmware: + * x0: function id + * x1: kernel entry point + * x2: machine nr + * x3: fdt address +*/ +.global armv8_el2_to_aarch32 +armv8_el2_to_aarch32: + mov x3, x2 + mov x2, x1 + mov x1, x4 + mov x4, #0 + /* Define in src\bsp\trustzone\atf\v1.2\ */ + /* mt8xxx\plat\mediatek\common\sip_svc.h */ + /* MTK_SIP_KERNEL_BOOT_AARCH64 for U-BOOT-64 to KERNEL*/ + ldr x0, =0xC2000200 + SMC #0 + ret -- 2.23.0 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 0/5] Add support for MediaTek MT8518 Soc @ 2019-09-11 11:14 mingming lee 2019-09-11 11:14 ` [U-Boot] [PATCH 1/5] ARM: MediaTek: Add support for MediaTek MT8518 SoC mingming lee 0 siblings, 1 reply; 6+ messages in thread From: mingming lee @ 2019-09-11 11:14 UTC (permalink / raw) To: u-boot This patch series adds basic boot support on eMMC for the MediaTek MT8518 SoC based boards. This series add the clock, pinctrl drivers and the SoC initializaton code. mingming lee (5): ARM: MediaTek: Add support for MediaTek MT8518 SoC clk: mediatek: add driver for MT8518 mmc: mtk-sd: add HS200 support pinctrl: add driver for MT8518 ARM: MediaTek: add basic support for MT8518 boards arch/arm/dts/Makefile | 3 +- arch/arm/dts/mt8518-ap1-emmc.dts | 104 ++ arch/arm/dts/mt8518.dtsi | 210 +++ arch/arm/mach-mediatek/Kconfig | 10 + arch/arm/mach-mediatek/Makefile | 1 + arch/arm/mach-mediatek/mt8518/Makefile | 4 + arch/arm/mach-mediatek/mt8518/init.c | 116 ++ arch/arm/mach-mediatek/mt8518/lowlevel_init.S | 59 + board/mediatek/mt8518/Kconfig | 14 + board/mediatek/mt8518/MAINTAINERS | 6 + board/mediatek/mt8518/Makefile | 3 + board/mediatek/mt8518/mt8518_ap1.c | 27 + configs/mt8518_ap1_emmc_defconfig | 54 + drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8518.c | 1558 +++++++++++++++++ drivers/mmc/mtk-sd.c | 30 +- drivers/pinctrl/mediatek/Kconfig | 4 + drivers/pinctrl/mediatek/Makefile | 1 + drivers/pinctrl/mediatek/pinctrl-mt8518.c | 411 +++++ include/configs/mt8518.h | 73 + include/dt-bindings/clock/mt8518-clk.h | 249 +++ 21 files changed, 2931 insertions(+), 7 deletions(-) create mode 100644 arch/arm/dts/mt8518-ap1-emmc.dts create mode 100644 arch/arm/dts/mt8518.dtsi create mode 100644 arch/arm/mach-mediatek/mt8518/Makefile create mode 100644 arch/arm/mach-mediatek/mt8518/init.c create mode 100644 arch/arm/mach-mediatek/mt8518/lowlevel_init.S create mode 100644 board/mediatek/mt8518/Kconfig create mode 100644 board/mediatek/mt8518/MAINTAINERS create mode 100644 board/mediatek/mt8518/Makefile create mode 100644 board/mediatek/mt8518/mt8518_ap1.c create mode 100644 configs/mt8518_ap1_emmc_defconfig create mode 100644 drivers/clk/mediatek/clk-mt8518.c create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8518.c create mode 100644 include/configs/mt8518.h create mode 100644 include/dt-bindings/clock/mt8518-clk.h -- 2.18.0 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 1/5] ARM: MediaTek: Add support for MediaTek MT8518 SoC 2019-09-11 11:14 [U-Boot] [PATCH 0/5] Add support for MediaTek MT8518 Soc mingming lee @ 2019-09-11 11:14 ` mingming lee 2019-10-13 10:55 ` Matthias Brugger 0 siblings, 1 reply; 6+ messages in thread From: mingming lee @ 2019-09-11 11:14 UTC (permalink / raw) To: u-boot Add support for MediaTek MT8518 SoC. This include the file that will initialize the SoC after boot and its device tree. Signed-off-by: mingming lee <mingming.lee@mediatek.com> --- arch/arm/dts/mt8518.dtsi | 201 ++++++++++++++++++ arch/arm/mach-mediatek/Kconfig | 9 + arch/arm/mach-mediatek/Makefile | 1 + arch/arm/mach-mediatek/mt8518/Makefile | 4 + arch/arm/mach-mediatek/mt8518/init.c | 116 ++++++++++ arch/arm/mach-mediatek/mt8518/lowlevel_init.S | 59 +++++ 6 files changed, 390 insertions(+) create mode 100644 arch/arm/dts/mt8518.dtsi create mode 100644 arch/arm/mach-mediatek/mt8518/Makefile create mode 100644 arch/arm/mach-mediatek/mt8518/init.c create mode 100644 arch/arm/mach-mediatek/mt8518/lowlevel_init.S diff --git a/arch/arm/dts/mt8518.dtsi b/arch/arm/dts/mt8518.dtsi new file mode 100644 index 0000000000..39d001884f --- /dev/null +++ b/arch/arm/dts/mt8518.dtsi @@ -0,0 +1,201 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2019 MediaTek Inc. + * Author: Mingming Lee <mingming.lee@mediatek.com> + * + */ + +#include <dt-bindings/clock/mt8518-clk.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "mediatek,mt8518"; + interrupt-parent = <&sysirq>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "mediatek,mt8518-smp"; + + cpu0: cpu at 0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + clock-frequency = <1300000000>; + }; + + cpu1: cpu at 1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + clock-frequency = <1300000000>; + }; + + cpu2: cpu at 2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + clock-frequency = <1300000000>; + }; + + cpu3: cpu at 3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + clock-frequency = <1300000000>; + }; + }; + + chipid: chipid at 08000000 { + compatible = "mediatek,chipid"; + reg = <0x08000000 0x0004>, + <0x08000004 0x0004>, + <0x08000008 0x0004>, + <0x0800000c 0x0004>; + }; + + topckgen: clock-controller at 10000000 { + compatible = "mediatek,mt8518-topckgen"; + reg = <0x10000000 0x1000>; + #clock-cells = <1>; + }; + + topckgen_cg: clock-controller-cg at 10000000 { + compatible = "mediatek,mt8518-topckgen-cg"; + reg = <0x10000000 0x1000>; + #clock-cells = <1>; + }; + + apmixedsys: clock-controller at 10018000 { + compatible = "mediatek,mt8518-apmixedsys"; + reg = <0x10018000 0x1000>; + #clock-cells = <1>; + }; + + gic: interrupt-controller at 0c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0xc000000 0x40000>, /* GICD */ + <0xc100000 0x200000>; /* GICR */ + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + sysirq: interrupt-controller at 10200a80 { + compatible = "mediatek,sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0x10200a80 0x50>; + }; + + apdma: dma-controller at 11000480 { + compatible = "mediatek,mt8518-uart-dma", + "mediatek,mt6577-uart-dma"; + reg = <0x11000480 0x80>, + <0x11000500 0x80>, + <0x11000580 0x80>, + <0x11000600 0x80>, + <0x11000980 0x80>, + <0x11000a00 0x80>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_APDMA>; + clock-names = "apdma"; + #dma-cells = <1>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + clock-frequency = <13000000>; + }; + + timer0: apxgpt at 10008000 { + compatible = "mediatek,timer", + "mediatek,mt8518-timer", + "mediatek,mt6577-timer"; + reg = <0x10008000 0x1000>; + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_CLK26M_D2>, + <&topckgen CLK_TOP_CLK32K>, + <&topckgen CLK_TOP_APXGPT>; + clock-names = "clk13m", + "clk32k", + "bus"; + }; + + watchdog: watchdog at 10007000 { + compatible = "mediatek,wdt"; + reg = <0x10007000 0x1000>; + interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_FALLING>; + #reset-cells = <1>; + status = "disabled"; + }; + + mmc0: mmc at 11120000 { + compatible = "mediatek,mt8516-mmc"; + reg = <0x11120000 0x1000>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_MSDC0>, + <&topckgen CLK_TOP_MSDC0>, + <&topckgen CLK_TOP_MSDC0_B>; + clock-names = "source", "hclk", "source_cg"; + status = "disabled"; + }; + + uart0: serial at 11005000 { + compatible = "mediatek,hsuart"; + reg = <0x11005000 0x1000>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_UART0_SEL>, + <&topckgen CLK_TOP_UART0>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart1: serial at 11001A000 { + compatible = "mediatek,hsuart"; + reg = <0x1001A000 0x1000>; + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_UART1_SEL>, + <&topckgen CLK_TOP_UART1>; + clock-names = "baud", "bus"; + dmas = <&apdma 2 + &apdma 3>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart2: serial at 11007000 { + compatible = "mediatek,hsuart"; + reg = <0x11007000 0x1000>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_UART2_SEL>, + <&topckgen CLK_TOP_UART2>; + clock-names = "baud", "bus"; + dmas = <&apdma 4 + &apdma 5>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + +}; diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig index 25ef7651f0..8e343c3182 100644 --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig @@ -38,6 +38,15 @@ config TARGET_MT8516 Ethernet, IR TX/RX, I2C, I2S, S/PDIF, and built-in Wi-Fi / Bluetooth combo chip and several DDR3 and DDR4 options. +config TARGET_MT8518 + bool "MediaTek MT8518 SoC" + select ARM64 + help + The MediaTek MT8518 is a ARM64-based SoC with a quad-core Cortex-A53. + including UART, SPI, USB2.0 and OTG, SD and MMC cards, NAND, PWM, + Ethernet, IR TX/RX, I2C, I2S, S/PDIF, and built-in Wi-Fi / Bluetooth combo + chip and several DDR3 and DDR4 options. + endchoice source "board/mediatek/mt7623/Kconfig" diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile index ea414dc407..b9b2355e03 100644 --- a/arch/arm/mach-mediatek/Makefile +++ b/arch/arm/mach-mediatek/Makefile @@ -6,3 +6,4 @@ obj-$(CONFIG_SPL_BUILD) += spl.o obj-$(CONFIG_TARGET_MT7623) += mt7623/ obj-$(CONFIG_TARGET_MT7629) += mt7629/ obj-$(CONFIG_TARGET_MT8516) += mt8516/ +obj-$(CONFIG_TARGET_MT8518) += mt8518/ diff --git a/arch/arm/mach-mediatek/mt8518/Makefile b/arch/arm/mach-mediatek/mt8518/Makefile new file mode 100644 index 0000000000..007eb4a367 --- /dev/null +++ b/arch/arm/mach-mediatek/mt8518/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y += init.o +obj-y += lowlevel_init.o diff --git a/arch/arm/mach-mediatek/mt8518/init.c b/arch/arm/mach-mediatek/mt8518/init.c new file mode 100644 index 0000000000..419454f794 --- /dev/null +++ b/arch/arm/mach-mediatek/mt8518/init.c @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Configuration for MediaTek MT8518 SoC + * + * Copyright (C) 2019 MediaTek Inc. + * Author: Mingming Lee <mingming.lee@mediatek.com> + */ + +#include <clk.h> +#include <common.h> +#include <dm.h> +#include <fdtdec.h> +#include <ram.h> +#include <asm/arch/misc.h> +#include <asm/armv8/mmu.h> +#include <asm/sections.h> +#include <dm/uclass.h> +#include <dt-bindings/clock/mt8518-clk.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + int ret; + + ret = fdtdec_setup_memory_banksize(); + if (ret) + return ret; + + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = gd->ram_base; + gd->bd->bi_dram[0].size = gd->ram_size; + + return 0; +} + +int mtk_pll_early_init(void) +{ + unsigned long pll_rates[] = { + [CLK_APMIXED_ARMPLL] = 1300000000, + [CLK_APMIXED_MAINPLL] = 1501000000, + [CLK_APMIXED_UNIVPLL] = 1248000000, + [CLK_APMIXED_MMPLL] = 380000000, + }; + struct udevice *dev; + int ret, i; + + ret = uclass_get_device_by_driver(UCLASS_CLK, + DM_GET_DRIVER(mtk_clk_apmixedsys), + &dev); + if (ret) + return ret; + + /* configure default rate then enable apmixedsys */ + for (i = 0; i < ARRAY_SIZE(pll_rates); i++) { + struct clk clk = { .id = i, .dev = dev }; + + ret = clk_set_rate(&clk, pll_rates[i]); + if (ret) + return ret; + + ret = clk_enable(&clk); + if (ret) + return ret; + } + + return 0; +} + +int mtk_soc_early_init(void) +{ + int ret; + + /* initialize early clocks */ + ret = mtk_pll_early_init(); + if (ret) + return ret; + + return 0; +} + +void reset_cpu(ulong addr) +{ + psci_system_reset(); +} + +int print_cpuinfo(void) +{ + printf("CPU: MediaTek MT8518\n"); + return 0; +} + +static struct mm_region mt8518_mem_map[] = { + { + /* DDR */ + .virt = 0x40000000UL, + .phys = 0x40000000UL, + .size = 0x20000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, + }, { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x20000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + 0, + } +}; + +struct mm_region *mem_map = mt8518_mem_map; diff --git a/arch/arm/mach-mediatek/mt8518/lowlevel_init.S b/arch/arm/mach-mediatek/mt8518/lowlevel_init.S new file mode 100644 index 0000000000..3db4ee5b85 --- /dev/null +++ b/arch/arm/mach-mediatek/mt8518/lowlevel_init.S @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 MediaTek Inc. + * Author: Mingming Lee <mingming.lee@mediatek.com> + */ + +/*pre-loader LK to uboot argument Location*/ +.global BOOT_ARGUMENT_DRAM_SIZE +BOOT_ARGUMENT_DRAM_SIZE: + .word 0x00000000 + +.global BOOT_ARGUMENT_LINUX_ID +BOOT_ARGUMENT_LINUX_ID: + .word 0x00000000 + +.global BOOT_ARGUMENT_LOCATION +BOOT_ARGUMENT_LOCATION: + .word 0x00000000 + +/****************To instead what defined in start.S************************** + *void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) __attribute__((weak)) + ****************************************************************************/ + +.globl save_boot_params +save_boot_params: + ldr x6, =BOOT_ARGUMENT_DRAM_SIZE + str x0, [x6] + ldr x6, =BOOT_ARGUMENT_LINUX_ID + str x1, [x6] + ldr x6, =BOOT_ARGUMENT_LOCATION + str x2, [x6] + b save_boot_params_ret + +/* + * Switch from AArch64 EL2 to AArch32 EL2 + * @param inputs: + * x0: argument, zero + * x1: machine nr + * x2: fdt address + * x3: input argument + * x4: kernel entry point + * @param outputs for secure firmware: + * x0: function id + * x1: kernel entry point + * x2: machine nr + * x3: fdt address +*/ +.global armv8_el2_to_aarch32 +armv8_el2_to_aarch32: + mov x3, x2 + mov x2, x1 + mov x1, x4 + mov x4, #0 + /* Define in src\bsp\trustzone\atf\v1.2\ */ + /* mt8xxx\plat\mediatek\common\sip_svc.h */ + /* MTK_SIP_KERNEL_BOOT_AARCH64 for U-BOOT-64 to KERNEL*/ + ldr x0, =0xC2000200 + SMC #0 + ret -- 2.18.0 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 1/5] ARM: MediaTek: Add support for MediaTek MT8518 SoC 2019-09-11 11:14 ` [U-Boot] [PATCH 1/5] ARM: MediaTek: Add support for MediaTek MT8518 SoC mingming lee @ 2019-10-13 10:55 ` Matthias Brugger 2019-10-15 6:25 ` Mingming Lee ` (2 more replies) 0 siblings, 3 replies; 6+ messages in thread From: Matthias Brugger @ 2019-10-13 10:55 UTC (permalink / raw) To: u-boot On 11/09/2019 13:14, mingming lee wrote: > Add support for MediaTek MT8518 SoC. This include the file > that will initialize the SoC after boot and its device tree. > > Signed-off-by: mingming lee <mingming.lee@mediatek.com> > --- > arch/arm/dts/mt8518.dtsi | 201 ++++++++++++++++++ > arch/arm/mach-mediatek/Kconfig | 9 + > arch/arm/mach-mediatek/Makefile | 1 + > arch/arm/mach-mediatek/mt8518/Makefile | 4 + > arch/arm/mach-mediatek/mt8518/init.c | 116 ++++++++++ > arch/arm/mach-mediatek/mt8518/lowlevel_init.S | 59 +++++ > 6 files changed, 390 insertions(+) > create mode 100644 arch/arm/dts/mt8518.dtsi > create mode 100644 arch/arm/mach-mediatek/mt8518/Makefile > create mode 100644 arch/arm/mach-mediatek/mt8518/init.c > create mode 100644 arch/arm/mach-mediatek/mt8518/lowlevel_init.S > > diff --git a/arch/arm/dts/mt8518.dtsi b/arch/arm/dts/mt8518.dtsi > new file mode 100644 > index 0000000000..39d001884f > --- /dev/null > +++ b/arch/arm/dts/mt8518.dtsi > @@ -0,0 +1,201 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* > + * Copyright (C) 2019 MediaTek Inc. > + * Author: Mingming Lee <mingming.lee@mediatek.com> > + * > + */ > + > +#include <dt-bindings/clock/mt8518-clk.h> > +#include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/interrupt-controller/irq.h> > +#include <dt-bindings/interrupt-controller/arm-gic.h> > + > +/ { > + compatible = "mediatek,mt8518"; > + interrupt-parent = <&sysirq>; > + #address-cells = <1>; > + #size-cells = <1>; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + enable-method = "mediatek,mt8518-smp"; > + > + cpu0: cpu at 0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x0>; > + clock-frequency = <1300000000>; > + }; > + > + cpu1: cpu at 1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x1>; > + clock-frequency = <1300000000>; > + }; > + > + cpu2: cpu at 2 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x2>; > + clock-frequency = <1300000000>; > + }; > + > + cpu3: cpu at 3 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x3>; > + clock-frequency = <1300000000>; > + }; > + }; > + > + chipid: chipid at 08000000 { > + compatible = "mediatek,chipid"; > + reg = <0x08000000 0x0004>, > + <0x08000004 0x0004>, > + <0x08000008 0x0004>, > + <0x0800000c 0x0004>; > + }; I couldn't find any driver using this compatible. You may want to drop this 'device'. Regards, Matthias ^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 1/5] ARM: MediaTek: Add support for MediaTek MT8518 SoC 2019-10-13 10:55 ` Matthias Brugger @ 2019-10-15 6:25 ` Mingming Lee 2019-10-15 6:42 ` Mingming Lee 2019-10-15 6:56 ` Mingming Lee 2 siblings, 0 replies; 6+ messages in thread From: Mingming Lee @ 2019-10-15 6:25 UTC (permalink / raw) To: u-boot On Sun, 2019-10-13 at 18:55 +0800, Matthias Brugger wrote: > > On 11/09/2019 13:14, mingming lee wrote: > > Add support for MediaTek MT8518 SoC. This include the file > > that will initialize the SoC after boot and its device tree. > > > > Signed-off-by: mingming lee <mingming.lee@mediatek.com> > > --- > > arch/arm/dts/mt8518.dtsi | 201 ++++++++++++++++++ > > arch/arm/mach-mediatek/Kconfig | 9 + > > arch/arm/mach-mediatek/Makefile | 1 + > > arch/arm/mach-mediatek/mt8518/Makefile | 4 + > > arch/arm/mach-mediatek/mt8518/init.c | 116 ++++++++++ > > arch/arm/mach-mediatek/mt8518/lowlevel_init.S | 59 +++++ > > 6 files changed, 390 insertions(+) > > create mode 100644 arch/arm/dts/mt8518.dtsi > > create mode 100644 arch/arm/mach-mediatek/mt8518/Makefile > > create mode 100644 arch/arm/mach-mediatek/mt8518/init.c > > create mode 100644 arch/arm/mach-mediatek/mt8518/lowlevel_init.S > > > > diff --git a/arch/arm/dts/mt8518.dtsi b/arch/arm/dts/mt8518.dtsi > > new file mode 100644 > > index 0000000000..39d001884f > > --- /dev/null > > +++ b/arch/arm/dts/mt8518.dtsi > > @@ -0,0 +1,201 @@ > > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > > +/* > > + * Copyright (C) 2019 MediaTek Inc. > > + * Author: Mingming Lee <mingming.lee@mediatek.com> > > + * > > + */ > > + > > +#include <dt-bindings/clock/mt8518-clk.h> > > +#include <dt-bindings/gpio/gpio.h> > > +#include <dt-bindings/interrupt-controller/irq.h> > > +#include <dt-bindings/interrupt-controller/arm-gic.h> > > + > > +/ { > > + compatible = "mediatek,mt8518"; > > + interrupt-parent = <&sysirq>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + > > + cpus { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + enable-method = "mediatek,mt8518-smp"; > > + > > + cpu0: cpu at 0 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a53"; > > + reg = <0x0>; > > + clock-frequency = <1300000000>; > > + }; > > + > > + cpu1: cpu at 1 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a53"; > > + reg = <0x1>; > > + clock-frequency = <1300000000>; > > + }; > > + > > + cpu2: cpu at 2 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a53"; > > + reg = <0x2>; > > + clock-frequency = <1300000000>; > > + }; > > + > > + cpu3: cpu at 3 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a53"; > > + reg = <0x3>; > > + clock-frequency = <1300000000>; > > + }; > > + }; > > + > > + chipid: chipid at 08000000 { > > + compatible = "mediatek,chipid"; > > + reg = <0x08000000 0x0004>, > > + <0x08000004 0x0004>, > > + <0x08000008 0x0004>, > > + <0x0800000c 0x0004>; > > + }; > > I couldn't find any driver using this compatible. > You may want to drop this 'device'. > > Regards, > Matthias Thank you for review. I will drop it and also drop other unused 'device'. ^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 1/5] ARM: MediaTek: Add support for MediaTek MT8518 SoC 2019-10-13 10:55 ` Matthias Brugger 2019-10-15 6:25 ` Mingming Lee @ 2019-10-15 6:42 ` Mingming Lee 2019-10-15 6:56 ` Mingming Lee 2 siblings, 0 replies; 6+ messages in thread From: Mingming Lee @ 2019-10-15 6:42 UTC (permalink / raw) To: u-boot On Sun, 2019-10-13 at 18:55 +0800, Matthias Brugger wrote: > > On 11/09/2019 13:14, mingming lee wrote: > > Add support for MediaTek MT8518 SoC. This include the file > > that will initialize the SoC after boot and its device tree. > > > > Signed-off-by: mingming lee <mingming.lee@mediatek.com> > > --- > > arch/arm/dts/mt8518.dtsi | 201 ++++++++++++++++++ > > arch/arm/mach-mediatek/Kconfig | 9 + > > arch/arm/mach-mediatek/Makefile | 1 + > > arch/arm/mach-mediatek/mt8518/Makefile | 4 + > > arch/arm/mach-mediatek/mt8518/init.c | 116 ++++++++++ > > arch/arm/mach-mediatek/mt8518/lowlevel_init.S | 59 +++++ > > 6 files changed, 390 insertions(+) > > create mode 100644 arch/arm/dts/mt8518.dtsi > > create mode 100644 arch/arm/mach-mediatek/mt8518/Makefile > > create mode 100644 arch/arm/mach-mediatek/mt8518/init.c > > create mode 100644 arch/arm/mach-mediatek/mt8518/lowlevel_init.S > > > > diff --git a/arch/arm/dts/mt8518.dtsi b/arch/arm/dts/mt8518.dtsi > > new file mode 100644 > > index 0000000000..39d001884f > > --- /dev/null > > +++ b/arch/arm/dts/mt8518.dtsi > > @@ -0,0 +1,201 @@ > > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > > +/* > > + * Copyright (C) 2019 MediaTek Inc. > > + * Author: Mingming Lee <mingming.lee@mediatek.com> > > + * > > + */ > > + > > +#include <dt-bindings/clock/mt8518-clk.h> > > +#include <dt-bindings/gpio/gpio.h> > > +#include <dt-bindings/interrupt-controller/irq.h> > > +#include <dt-bindings/interrupt-controller/arm-gic.h> > > + > > +/ { > > + compatible = "mediatek,mt8518"; > > + interrupt-parent = <&sysirq>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + > > + cpus { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + enable-method = "mediatek,mt8518-smp"; > > + > > + cpu0: cpu at 0 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a53"; > > + reg = <0x0>; > > + clock-frequency = <1300000000>; > > + }; > > + > > + cpu1: cpu at 1 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a53"; > > + reg = <0x1>; > > + clock-frequency = <1300000000>; > > + }; > > + > > + cpu2: cpu at 2 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a53"; > > + reg = <0x2>; > > + clock-frequency = <1300000000>; > > + }; > > + > > + cpu3: cpu at 3 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a53"; > > + reg = <0x3>; > > + clock-frequency = <1300000000>; > > + }; > > + }; > > + > > + chipid: chipid at 08000000 { > > + compatible = "mediatek,chipid"; > > + reg = <0x08000000 0x0004>, > > + <0x08000004 0x0004>, > > + <0x08000008 0x0004>, > > + <0x0800000c 0x0004>; > > + }; > > I couldn't find any driver using this compatible. > You may want to drop this 'device'. > > Regards, > Matthias Thank you for review. I will drop this 'device' and also drop other unused 'device'. ^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 1/5] ARM: MediaTek: Add support for MediaTek MT8518 SoC 2019-10-13 10:55 ` Matthias Brugger 2019-10-15 6:25 ` Mingming Lee 2019-10-15 6:42 ` Mingming Lee @ 2019-10-15 6:56 ` Mingming Lee 2 siblings, 0 replies; 6+ messages in thread From: Mingming Lee @ 2019-10-15 6:56 UTC (permalink / raw) To: u-boot On Sun, 2019-10-13 at 18:55 +0800, Matthias Brugger wrote: > > On 11/09/2019 13:14, mingming lee wrote: > > Add support for MediaTek MT8518 SoC. This include the file > > that will initialize the SoC after boot and its device tree. > > > > Signed-off-by: mingming lee <mingming.lee@mediatek.com> > > --- > > arch/arm/dts/mt8518.dtsi | 201 ++++++++++++++++++ > > arch/arm/mach-mediatek/Kconfig | 9 + > > arch/arm/mach-mediatek/Makefile | 1 + > > arch/arm/mach-mediatek/mt8518/Makefile | 4 + > > arch/arm/mach-mediatek/mt8518/init.c | 116 ++++++++++ > > arch/arm/mach-mediatek/mt8518/lowlevel_init.S | 59 +++++ > > 6 files changed, 390 insertions(+) > > create mode 100644 arch/arm/dts/mt8518.dtsi > > create mode 100644 arch/arm/mach-mediatek/mt8518/Makefile > > create mode 100644 arch/arm/mach-mediatek/mt8518/init.c > > create mode 100644 arch/arm/mach-mediatek/mt8518/lowlevel_init.S > > > > diff --git a/arch/arm/dts/mt8518.dtsi b/arch/arm/dts/mt8518.dtsi > > new file mode 100644 > > index 0000000000..39d001884f > > --- /dev/null > > +++ b/arch/arm/dts/mt8518.dtsi > > @@ -0,0 +1,201 @@ > > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > > +/* > > + * Copyright (C) 2019 MediaTek Inc. > > + * Author: Mingming Lee <mingming.lee@mediatek.com> > > + * > > + */ > > + > > +#include <dt-bindings/clock/mt8518-clk.h> > > +#include <dt-bindings/gpio/gpio.h> > > +#include <dt-bindings/interrupt-controller/irq.h> > > +#include <dt-bindings/interrupt-controller/arm-gic.h> > > + > > +/ { > > + compatible = "mediatek,mt8518"; > > + interrupt-parent = <&sysirq>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + > > + cpus { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + enable-method = "mediatek,mt8518-smp"; > > + > > + cpu0: cpu at 0 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a53"; > > + reg = <0x0>; > > + clock-frequency = <1300000000>; > > + }; > > + > > + cpu1: cpu at 1 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a53"; > > + reg = <0x1>; > > + clock-frequency = <1300000000>; > > + }; > > + > > + cpu2: cpu at 2 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a53"; > > + reg = <0x2>; > > + clock-frequency = <1300000000>; > > + }; > > + > > + cpu3: cpu at 3 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a53"; > > + reg = <0x3>; > > + clock-frequency = <1300000000>; > > + }; > > + }; > > + > > + chipid: chipid at 08000000 { > > + compatible = "mediatek,chipid"; > > + reg = <0x08000000 0x0004>, > > + <0x08000004 0x0004>, > > + <0x08000008 0x0004>, > > + <0x0800000c 0x0004>; > > + }; > > I couldn't find any driver using this compatible. > You may want to drop this 'device'. > > Regards, > Matthias Thank you for review. I will drop it and also drop other unused 'device'. ^ permalink raw reply [flat|nested] 6+ messages in thread
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Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
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2019-09-11 6:48 ` [U-Boot] [PATCH 1/5] ARM: MediaTek: Add support for MediaTek MT8518 SoC mingming lee
2019-09-11 11:14 [U-Boot] [PATCH 0/5] Add support for MediaTek MT8518 Soc mingming lee
2019-09-11 11:14 ` [U-Boot] [PATCH 1/5] ARM: MediaTek: Add support for MediaTek MT8518 SoC mingming lee
2019-10-13 10:55 ` Matthias Brugger
2019-10-15 6:25 ` Mingming Lee
2019-10-15 6:42 ` Mingming Lee
2019-10-15 6:56 ` Mingming Lee
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