[U-Boot] [PATCH 0/5] Add support for MediaTek MT8518 Soc

[U-Boot] [PATCH 0/5] Add support for MediaTek MT8518 Soc

[mingming lee]

This patch series adds basic boot support on eMMC for the MediaTek
MT8518 SoC based boards. This series add the clock, pinctrl drivers
and the SoC initializaton code.

mingming lee (5):
  ARM: MediaTek: Add support for MediaTek MT8518 SoC
  clk: mediatek: add driver for MT8518
  mmc: mtk-sd: add HS200 support
  pinctrl: add driver for MT8518
  ARM: MediaTek: add basic support for MT8518 boards

 arch/arm/dts/Makefile                         |    3 +-
 arch/arm/dts/mt8518-ap1-emmc.dts              |  104 ++
 arch/arm/dts/mt8518.dtsi                      |  210 +++
 arch/arm/mach-mediatek/Kconfig                |   10 +
 arch/arm/mach-mediatek/Makefile               |    1 +
 arch/arm/mach-mediatek/mt8518/Makefile        |    4 +
 arch/arm/mach-mediatek/mt8518/init.c          |  116 ++
 arch/arm/mach-mediatek/mt8518/lowlevel_init.S |   59 +
 board/mediatek/mt8518/Kconfig                 |   14 +
 board/mediatek/mt8518/MAINTAINERS             |    6 +
 board/mediatek/mt8518/Makefile                |    3 +
 board/mediatek/mt8518/mt8518_ap1.c            |   27 +
 configs/mt8518_ap1_emmc_defconfig             |   54 +
 drivers/clk/mediatek/Makefile                 |    1 +
 drivers/clk/mediatek/clk-mt8518.c             | 1558 +++++++++++++++++
 drivers/mmc/mtk-sd.c                          |   30 +-
 drivers/pinctrl/mediatek/Kconfig              |    4 +
 drivers/pinctrl/mediatek/Makefile             |    1 +
 drivers/pinctrl/mediatek/pinctrl-mt8518.c     |  411 +++++
 include/configs/mt8518.h                      |   73 +
 include/dt-bindings/clock/mt8518-clk.h        |  249 +++
 21 files changed, 2931 insertions(+), 7 deletions(-)
 create mode 100644 arch/arm/dts/mt8518-ap1-emmc.dts
 create mode 100644 arch/arm/dts/mt8518.dtsi
 create mode 100644 arch/arm/mach-mediatek/mt8518/Makefile
 create mode 100644 arch/arm/mach-mediatek/mt8518/init.c
 create mode 100644 arch/arm/mach-mediatek/mt8518/lowlevel_init.S
 create mode 100644 board/mediatek/mt8518/Kconfig
 create mode 100644 board/mediatek/mt8518/MAINTAINERS
 create mode 100644 board/mediatek/mt8518/Makefile
 create mode 100644 board/mediatek/mt8518/mt8518_ap1.c
 create mode 100644 configs/mt8518_ap1_emmc_defconfig
 create mode 100644 drivers/clk/mediatek/clk-mt8518.c
 create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8518.c
 create mode 100644 include/configs/mt8518.h
 create mode 100644 include/dt-bindings/clock/mt8518-clk.h

-- 
2.18.0

[U-Boot] [PATCH 1/5] ARM: MediaTek: Add support for MediaTek MT8518 SoC

[mingming lee]

Add support for MediaTek MT8518 SoC. This include the file
that will initialize the SoC after boot and its device tree.

Signed-off-by: mingming lee <mingming.lee@mediatek.com>
---
 arch/arm/dts/mt8518.dtsi                      | 201 ++++++++++++++++++
 arch/arm/mach-mediatek/Kconfig                |   9 +
 arch/arm/mach-mediatek/Makefile               |   1 +
 arch/arm/mach-mediatek/mt8518/Makefile        |   4 +
 arch/arm/mach-mediatek/mt8518/init.c          | 116 ++++++++++
 arch/arm/mach-mediatek/mt8518/lowlevel_init.S |  59 +++++
 6 files changed, 390 insertions(+)
 create mode 100644 arch/arm/dts/mt8518.dtsi
 create mode 100644 arch/arm/mach-mediatek/mt8518/Makefile
 create mode 100644 arch/arm/mach-mediatek/mt8518/init.c
 create mode 100644 arch/arm/mach-mediatek/mt8518/lowlevel_init.S

diff --git a/arch/arm/dts/mt8518.dtsi b/arch/arm/dts/mt8518.dtsi
new file mode 100644
index 0000000000..39d001884f
--- /dev/null
+++ b/arch/arm/dts/mt8518.dtsi
@@ -0,0 +1,201 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Mingming Lee <mingming.lee@mediatek.com>
+ *
+ */
+
+#include <dt-bindings/clock/mt8518-clk.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "mediatek,mt8518";
+	interrupt-parent = <&sysirq>;
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		enable-method = "mediatek,mt8518-smp";
+
+		cpu0: cpu at 0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0>;
+			clock-frequency = <1300000000>;
+		};
+
+		cpu1: cpu at 1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x1>;
+			clock-frequency = <1300000000>;
+		};
+
+		cpu2: cpu at 2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x2>;
+			clock-frequency = <1300000000>;
+		};
+
+		cpu3: cpu at 3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x3>;
+			clock-frequency = <1300000000>;
+		};
+	};
+
+	chipid: chipid at 08000000 {
+		compatible = "mediatek,chipid";
+		reg = <0x08000000 0x0004>,
+		      <0x08000004 0x0004>,
+		      <0x08000008 0x0004>,
+		      <0x0800000c 0x0004>;
+	};
+
+	topckgen: clock-controller at 10000000 {
+		compatible = "mediatek,mt8518-topckgen";
+		reg = <0x10000000 0x1000>;
+		#clock-cells = <1>;
+	};
+
+	topckgen_cg: clock-controller-cg at 10000000 {
+		compatible = "mediatek,mt8518-topckgen-cg";
+		reg = <0x10000000 0x1000>;
+		#clock-cells = <1>;
+	};
+
+	apmixedsys: clock-controller at 10018000 {
+		compatible = "mediatek,mt8518-apmixedsys";
+		reg = <0x10018000 0x1000>;
+		#clock-cells = <1>;
+	};
+
+	gic: interrupt-controller at 0c000000 {
+		 compatible = "arm,gic-v3";
+		#interrupt-cells = <3>;
+		interrupt-parent = <&gic>;
+		interrupt-controller;
+		reg = <0xc000000 0x40000>,	/* GICD */
+			  <0xc100000 0x200000>; /* GICR */
+		interrupts = <GIC_PPI 9
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+	};
+
+	sysirq: interrupt-controller at 10200a80 {
+		compatible = "mediatek,sysirq";
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		interrupt-parent = <&gic>;
+		reg = <0x10200a80 0x50>;
+	};
+
+	apdma: dma-controller at 11000480 {
+		compatible = "mediatek,mt8518-uart-dma",
+			"mediatek,mt6577-uart-dma";
+		reg = <0x11000480 0x80>,
+			  <0x11000500 0x80>,
+			  <0x11000580 0x80>,
+			  <0x11000600 0x80>,
+			  <0x11000980 0x80>,
+			  <0x11000a00 0x80>;
+		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>,
+			<GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>,
+			<GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>,
+			<GIC_SPI 99 IRQ_TYPE_LEVEL_LOW>,
+			<GIC_SPI 100 IRQ_TYPE_LEVEL_LOW>,
+			<GIC_SPI 101 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&topckgen CLK_TOP_APDMA>;
+		clock-names = "apdma";
+		#dma-cells = <1>;
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_PPI 13
+				 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+				 <GIC_PPI 14
+				 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+				 <GIC_PPI 11
+				 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+				 <GIC_PPI 10
+				 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+		clock-frequency = <13000000>;
+	};
+
+	timer0: apxgpt at 10008000 {
+		compatible = "mediatek,timer",
+			   "mediatek,mt8518-timer",
+			   "mediatek,mt6577-timer";
+		reg = <0x10008000 0x1000>;
+		interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&topckgen CLK_TOP_CLK26M_D2>,
+			 <&topckgen CLK_TOP_CLK32K>,
+			 <&topckgen CLK_TOP_APXGPT>;
+		clock-names = "clk13m",
+			 "clk32k",
+			 "bus";
+	};
+
+	watchdog: watchdog at 10007000 {
+		compatible = "mediatek,wdt";
+		reg = <0x10007000 0x1000>;
+		interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_FALLING>;
+		#reset-cells = <1>;
+		status = "disabled";
+	};
+
+	mmc0: mmc at 11120000 {
+		compatible = "mediatek,mt8516-mmc";
+		reg = <0x11120000 0x1000>;
+		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&topckgen CLK_TOP_MSDC0>,
+			<&topckgen CLK_TOP_MSDC0>,
+			<&topckgen CLK_TOP_MSDC0_B>;
+		clock-names = "source", "hclk", "source_cg";
+		status = "disabled";
+	};
+
+	uart0: serial at 11005000 {
+		compatible = "mediatek,hsuart";
+		reg = <0x11005000 0x1000>;
+		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&topckgen CLK_TOP_UART0_SEL>,
+			<&topckgen CLK_TOP_UART0>;
+		clock-names = "baud", "bus";
+		status = "disabled";
+	};
+
+	uart1: serial at 11001A000 {
+		compatible = "mediatek,hsuart";
+		reg = <0x1001A000 0x1000>;
+		interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&topckgen CLK_TOP_UART1_SEL>,
+			<&topckgen CLK_TOP_UART1>;
+		clock-names = "baud", "bus";
+		dmas = <&apdma 2
+			&apdma 3>;
+		dma-names = "tx", "rx";
+		status = "disabled";
+	};
+
+	uart2: serial at 11007000 {
+		compatible = "mediatek,hsuart";
+		reg = <0x11007000 0x1000>;
+		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&topckgen CLK_TOP_UART2_SEL>,
+			<&topckgen CLK_TOP_UART2>;
+		clock-names = "baud", "bus";
+		dmas = <&apdma 4
+			&apdma 5>;
+		dma-names = "tx", "rx";
+		status = "disabled";
+	};
+
+};
diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
index 25ef7651f0..8e343c3182 100644
--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -38,6 +38,15 @@ config TARGET_MT8516
 	  Ethernet, IR TX/RX, I2C, I2S, S/PDIF, and built-in Wi-Fi / Bluetooth combo
 	  chip and several DDR3 and DDR4 options.
 
+config TARGET_MT8518
+	bool "MediaTek MT8518 SoC"
+	select ARM64
+	help
+	  The MediaTek MT8518 is a ARM64-based SoC with a quad-core Cortex-A53.
+	  including UART, SPI, USB2.0 and OTG, SD and MMC cards, NAND, PWM,
+	  Ethernet, IR TX/RX, I2C, I2S, S/PDIF, and built-in Wi-Fi / Bluetooth combo
+	  chip and several DDR3 and DDR4 options.
+
 endchoice
 
 source "board/mediatek/mt7623/Kconfig"
diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile
index ea414dc407..b9b2355e03 100644
--- a/arch/arm/mach-mediatek/Makefile
+++ b/arch/arm/mach-mediatek/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_SPL_BUILD)	+= spl.o
 obj-$(CONFIG_TARGET_MT7623) += mt7623/
 obj-$(CONFIG_TARGET_MT7629) += mt7629/
 obj-$(CONFIG_TARGET_MT8516) += mt8516/
+obj-$(CONFIG_TARGET_MT8518) += mt8518/
diff --git a/arch/arm/mach-mediatek/mt8518/Makefile b/arch/arm/mach-mediatek/mt8518/Makefile
new file mode 100644
index 0000000000..007eb4a367
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt8518/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier:	GPL-2.0
+
+obj-y += init.o
+obj-y += lowlevel_init.o
diff --git a/arch/arm/mach-mediatek/mt8518/init.c b/arch/arm/mach-mediatek/mt8518/init.c
new file mode 100644
index 0000000000..419454f794
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt8518/init.c
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Configuration for MediaTek MT8518 SoC
+ *
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Mingming Lee <mingming.lee@mediatek.com>
+ */
+
+#include <clk.h>
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <ram.h>
+#include <asm/arch/misc.h>
+#include <asm/armv8/mmu.h>
+#include <asm/sections.h>
+#include <dm/uclass.h>
+#include <dt-bindings/clock/mt8518-clk.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	int ret;
+
+	ret = fdtdec_setup_memory_banksize();
+	if (ret)
+		return ret;
+
+	return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = gd->ram_base;
+	gd->bd->bi_dram[0].size = gd->ram_size;
+
+	return 0;
+}
+
+int mtk_pll_early_init(void)
+{
+	unsigned long pll_rates[] = {
+		[CLK_APMIXED_ARMPLL] =   1300000000,
+		[CLK_APMIXED_MAINPLL] =  1501000000,
+		[CLK_APMIXED_UNIVPLL] =  1248000000,
+		[CLK_APMIXED_MMPLL] =     380000000,
+	};
+	struct udevice *dev;
+	int ret, i;
+
+	ret = uclass_get_device_by_driver(UCLASS_CLK,
+					  DM_GET_DRIVER(mtk_clk_apmixedsys),
+					  &dev);
+	if (ret)
+		return ret;
+
+	/* configure default rate then enable apmixedsys */
+	for (i = 0; i < ARRAY_SIZE(pll_rates); i++) {
+		struct clk clk = { .id = i, .dev = dev };
+
+		ret = clk_set_rate(&clk, pll_rates[i]);
+		if (ret)
+			return ret;
+
+		ret = clk_enable(&clk);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+int mtk_soc_early_init(void)
+{
+	int ret;
+
+	/* initialize early clocks */
+	ret = mtk_pll_early_init();
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+	psci_system_reset();
+}
+
+int print_cpuinfo(void)
+{
+	printf("CPU:   MediaTek MT8518\n");
+	return 0;
+}
+
+static struct mm_region mt8518_mem_map[] = {
+	{
+		/* DDR */
+		.virt = 0x40000000UL,
+		.phys = 0x40000000UL,
+		.size = 0x20000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
+	}, {
+		.virt = 0x00000000UL,
+		.phys = 0x00000000UL,
+		.size = 0x20000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		0,
+	}
+};
+
+struct mm_region *mem_map = mt8518_mem_map;
diff --git a/arch/arm/mach-mediatek/mt8518/lowlevel_init.S b/arch/arm/mach-mediatek/mt8518/lowlevel_init.S
new file mode 100644
index 0000000000..3db4ee5b85
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt8518/lowlevel_init.S
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Mingming Lee <mingming.lee@mediatek.com>
+ */
+
+/*pre-loader LK to uboot argument Location*/
+.global BOOT_ARGUMENT_DRAM_SIZE
+BOOT_ARGUMENT_DRAM_SIZE:
+	.word 0x00000000
+
+.global BOOT_ARGUMENT_LINUX_ID
+BOOT_ARGUMENT_LINUX_ID:
+	.word 0x00000000
+
+.global BOOT_ARGUMENT_LOCATION
+BOOT_ARGUMENT_LOCATION:
+	.word 0x00000000
+
+/****************To instead what defined in start.S**************************
+ *void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) __attribute__((weak))
+ ****************************************************************************/
+
+.globl save_boot_params
+save_boot_params:
+	ldr     x6, =BOOT_ARGUMENT_DRAM_SIZE
+	str     x0, [x6]
+	ldr     x6, =BOOT_ARGUMENT_LINUX_ID
+	str     x1, [x6]
+	ldr     x6, =BOOT_ARGUMENT_LOCATION
+	str     x2, [x6]
+	b       save_boot_params_ret
+
+/*
+ * Switch from AArch64 EL2 to AArch32 EL2
+ * @param inputs:
+ * x0: argument, zero
+ * x1: machine nr
+ * x2: fdt address
+ * x3: input argument
+ * x4: kernel entry point
+ * @param outputs for secure firmware:
+ * x0: function id
+ * x1: kernel entry point
+ * x2: machine nr
+ * x3: fdt address
+*/
+.global armv8_el2_to_aarch32
+armv8_el2_to_aarch32:
+	mov     x3, x2
+	mov     x2, x1
+	mov     x1, x4
+	mov	x4, #0
+	/* Define in src\bsp\trustzone\atf\v1.2\ */
+	/* mt8xxx\plat\mediatek\common\sip_svc.h */
+	/* MTK_SIP_KERNEL_BOOT_AARCH64 for U-BOOT-64 to KERNEL*/
+	ldr x0, =0xC2000200
+	SMC #0
+	ret
-- 
2.18.0

[U-Boot] [PATCH 1/5] ARM: MediaTek: Add support for MediaTek MT8518 SoC

[Matthias Brugger]

On 11/09/2019 13:14, mingming lee wrote:
> Add support for MediaTek MT8518 SoC. This include the file
> that will initialize the SoC after boot and its device tree.
> 
> Signed-off-by: mingming lee <mingming.lee@mediatek.com>
> ---
>  arch/arm/dts/mt8518.dtsi                      | 201 ++++++++++++++++++
>  arch/arm/mach-mediatek/Kconfig                |   9 +
>  arch/arm/mach-mediatek/Makefile               |   1 +
>  arch/arm/mach-mediatek/mt8518/Makefile        |   4 +
>  arch/arm/mach-mediatek/mt8518/init.c          | 116 ++++++++++
>  arch/arm/mach-mediatek/mt8518/lowlevel_init.S |  59 +++++
>  6 files changed, 390 insertions(+)
>  create mode 100644 arch/arm/dts/mt8518.dtsi
>  create mode 100644 arch/arm/mach-mediatek/mt8518/Makefile
>  create mode 100644 arch/arm/mach-mediatek/mt8518/init.c
>  create mode 100644 arch/arm/mach-mediatek/mt8518/lowlevel_init.S
> 
> diff --git a/arch/arm/dts/mt8518.dtsi b/arch/arm/dts/mt8518.dtsi
> new file mode 100644
> index 0000000000..39d001884f
> --- /dev/null
> +++ b/arch/arm/dts/mt8518.dtsi
> @@ -0,0 +1,201 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2019 MediaTek Inc.
> + * Author: Mingming Lee <mingming.lee@mediatek.com>
> + *
> + */
> +
> +#include <dt-bindings/clock/mt8518-clk.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> +	compatible = "mediatek,mt8518";
> +	interrupt-parent = <&sysirq>;
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		enable-method = "mediatek,mt8518-smp";
> +
> +		cpu0: cpu at 0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a53";
> +			reg = <0x0>;
> +			clock-frequency = <1300000000>;
> +		};
> +
> +		cpu1: cpu at 1 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a53";
> +			reg = <0x1>;
> +			clock-frequency = <1300000000>;
> +		};
> +
> +		cpu2: cpu at 2 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a53";
> +			reg = <0x2>;
> +			clock-frequency = <1300000000>;
> +		};
> +
> +		cpu3: cpu at 3 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a53";
> +			reg = <0x3>;
> +			clock-frequency = <1300000000>;
> +		};
> +	};
> +
> +	chipid: chipid at 08000000 {
> +		compatible = "mediatek,chipid";
> +		reg = <0x08000000 0x0004>,
> +		      <0x08000004 0x0004>,
> +		      <0x08000008 0x0004>,
> +		      <0x0800000c 0x0004>;
> +	};

I couldn't find any driver using this compatible.
You may want to drop this 'device'.

Regards,
Matthias

[U-Boot] [PATCH 1/5] ARM: MediaTek: Add support for MediaTek MT8518 SoC

[Mingming Lee]

On Sun, 2019-10-13 at 18:55 +0800, Matthias Brugger wrote:
> 
> On 11/09/2019 13:14, mingming lee wrote:
> > Add support for MediaTek MT8518 SoC. This include the file
> > that will initialize the SoC after boot and its device tree.
> > 
> > Signed-off-by: mingming lee <mingming.lee@mediatek.com>
> > ---
> >  arch/arm/dts/mt8518.dtsi                      | 201 ++++++++++++++++++
> >  arch/arm/mach-mediatek/Kconfig                |   9 +
> >  arch/arm/mach-mediatek/Makefile               |   1 +
> >  arch/arm/mach-mediatek/mt8518/Makefile        |   4 +
> >  arch/arm/mach-mediatek/mt8518/init.c          | 116 ++++++++++
> >  arch/arm/mach-mediatek/mt8518/lowlevel_init.S |  59 +++++
> >  6 files changed, 390 insertions(+)
> >  create mode 100644 arch/arm/dts/mt8518.dtsi
> >  create mode 100644 arch/arm/mach-mediatek/mt8518/Makefile
> >  create mode 100644 arch/arm/mach-mediatek/mt8518/init.c
> >  create mode 100644 arch/arm/mach-mediatek/mt8518/lowlevel_init.S
> > 
> > diff --git a/arch/arm/dts/mt8518.dtsi b/arch/arm/dts/mt8518.dtsi
> > new file mode 100644
> > index 0000000000..39d001884f
> > --- /dev/null
> > +++ b/arch/arm/dts/mt8518.dtsi
> > @@ -0,0 +1,201 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/*
> > + * Copyright (C) 2019 MediaTek Inc.
> > + * Author: Mingming Lee <mingming.lee@mediatek.com>
> > + *
> > + */
> > +
> > +#include <dt-bindings/clock/mt8518-clk.h>
> > +#include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > +/ {
> > +	compatible = "mediatek,mt8518";
> > +	interrupt-parent = <&sysirq>;
> > +	#address-cells = <1>;
> > +	#size-cells = <1>;
> > +
> > +	cpus {
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +		enable-method = "mediatek,mt8518-smp";
> > +
> > +		cpu0: cpu at 0 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a53";
> > +			reg = <0x0>;
> > +			clock-frequency = <1300000000>;
> > +		};
> > +
> > +		cpu1: cpu at 1 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a53";
> > +			reg = <0x1>;
> > +			clock-frequency = <1300000000>;
> > +		};
> > +
> > +		cpu2: cpu at 2 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a53";
> > +			reg = <0x2>;
> > +			clock-frequency = <1300000000>;
> > +		};
> > +
> > +		cpu3: cpu at 3 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a53";
> > +			reg = <0x3>;
> > +			clock-frequency = <1300000000>;
> > +		};
> > +	};
> > +
> > +	chipid: chipid at 08000000 {
> > +		compatible = "mediatek,chipid";
> > +		reg = <0x08000000 0x0004>,
> > +		      <0x08000004 0x0004>,
> > +		      <0x08000008 0x0004>,
> > +		      <0x0800000c 0x0004>;
> > +	};
> 
> I couldn't find any driver using this compatible.
> You may want to drop this 'device'.
> 
> Regards,
> Matthias

Thank you for review.
I will drop it and also drop other unused 'device'.

[U-Boot] [PATCH 1/5] ARM: MediaTek: Add support for MediaTek MT8518 SoC

[Mingming Lee]

On Sun, 2019-10-13 at 18:55 +0800, Matthias Brugger wrote:
> 
> On 11/09/2019 13:14, mingming lee wrote:
> > Add support for MediaTek MT8518 SoC. This include the file
> > that will initialize the SoC after boot and its device tree.
> > 
> > Signed-off-by: mingming lee <mingming.lee@mediatek.com>
> > ---
> >  arch/arm/dts/mt8518.dtsi                      | 201 ++++++++++++++++++
> >  arch/arm/mach-mediatek/Kconfig                |   9 +
> >  arch/arm/mach-mediatek/Makefile               |   1 +
> >  arch/arm/mach-mediatek/mt8518/Makefile        |   4 +
> >  arch/arm/mach-mediatek/mt8518/init.c          | 116 ++++++++++
> >  arch/arm/mach-mediatek/mt8518/lowlevel_init.S |  59 +++++
> >  6 files changed, 390 insertions(+)
> >  create mode 100644 arch/arm/dts/mt8518.dtsi
> >  create mode 100644 arch/arm/mach-mediatek/mt8518/Makefile
> >  create mode 100644 arch/arm/mach-mediatek/mt8518/init.c
> >  create mode 100644 arch/arm/mach-mediatek/mt8518/lowlevel_init.S
> > 
> > diff --git a/arch/arm/dts/mt8518.dtsi b/arch/arm/dts/mt8518.dtsi
> > new file mode 100644
> > index 0000000000..39d001884f
> > --- /dev/null
> > +++ b/arch/arm/dts/mt8518.dtsi
> > @@ -0,0 +1,201 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/*
> > + * Copyright (C) 2019 MediaTek Inc.
> > + * Author: Mingming Lee <mingming.lee@mediatek.com>
> > + *
> > + */
> > +
> > +#include <dt-bindings/clock/mt8518-clk.h>
> > +#include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > +/ {
> > +	compatible = "mediatek,mt8518";
> > +	interrupt-parent = <&sysirq>;
> > +	#address-cells = <1>;
> > +	#size-cells = <1>;
> > +
> > +	cpus {
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +		enable-method = "mediatek,mt8518-smp";
> > +
> > +		cpu0: cpu at 0 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a53";
> > +			reg = <0x0>;
> > +			clock-frequency = <1300000000>;
> > +		};
> > +
> > +		cpu1: cpu at 1 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a53";
> > +			reg = <0x1>;
> > +			clock-frequency = <1300000000>;
> > +		};
> > +
> > +		cpu2: cpu at 2 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a53";
> > +			reg = <0x2>;
> > +			clock-frequency = <1300000000>;
> > +		};
> > +
> > +		cpu3: cpu at 3 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a53";
> > +			reg = <0x3>;
> > +			clock-frequency = <1300000000>;
> > +		};
> > +	};
> > +
> > +	chipid: chipid at 08000000 {
> > +		compatible = "mediatek,chipid";
> > +		reg = <0x08000000 0x0004>,
> > +		      <0x08000004 0x0004>,
> > +		      <0x08000008 0x0004>,
> > +		      <0x0800000c 0x0004>;
> > +	};
> 
> I couldn't find any driver using this compatible.
> You may want to drop this 'device'.
> 
> Regards,
> Matthias

Thank you for review.
I will drop this 'device' and also drop other unused 'device'.

[U-Boot] [PATCH 1/5] ARM: MediaTek: Add support for MediaTek MT8518 SoC

[Mingming Lee]

On Sun, 2019-10-13 at 18:55 +0800, Matthias Brugger wrote:
> 
> On 11/09/2019 13:14, mingming lee wrote:
> > Add support for MediaTek MT8518 SoC. This include the file
> > that will initialize the SoC after boot and its device tree.
> > 
> > Signed-off-by: mingming lee <mingming.lee@mediatek.com>
> > ---
> >  arch/arm/dts/mt8518.dtsi                      | 201 ++++++++++++++++++
> >  arch/arm/mach-mediatek/Kconfig                |   9 +
> >  arch/arm/mach-mediatek/Makefile               |   1 +
> >  arch/arm/mach-mediatek/mt8518/Makefile        |   4 +
> >  arch/arm/mach-mediatek/mt8518/init.c          | 116 ++++++++++
> >  arch/arm/mach-mediatek/mt8518/lowlevel_init.S |  59 +++++
> >  6 files changed, 390 insertions(+)
> >  create mode 100644 arch/arm/dts/mt8518.dtsi
> >  create mode 100644 arch/arm/mach-mediatek/mt8518/Makefile
> >  create mode 100644 arch/arm/mach-mediatek/mt8518/init.c
> >  create mode 100644 arch/arm/mach-mediatek/mt8518/lowlevel_init.S
> > 
> > diff --git a/arch/arm/dts/mt8518.dtsi b/arch/arm/dts/mt8518.dtsi
> > new file mode 100644
> > index 0000000000..39d001884f
> > --- /dev/null
> > +++ b/arch/arm/dts/mt8518.dtsi
> > @@ -0,0 +1,201 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/*
> > + * Copyright (C) 2019 MediaTek Inc.
> > + * Author: Mingming Lee <mingming.lee@mediatek.com>
> > + *
> > + */
> > +
> > +#include <dt-bindings/clock/mt8518-clk.h>
> > +#include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > +/ {
> > +	compatible = "mediatek,mt8518";
> > +	interrupt-parent = <&sysirq>;
> > +	#address-cells = <1>;
> > +	#size-cells = <1>;
> > +
> > +	cpus {
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +		enable-method = "mediatek,mt8518-smp";
> > +
> > +		cpu0: cpu at 0 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a53";
> > +			reg = <0x0>;
> > +			clock-frequency = <1300000000>;
> > +		};
> > +
> > +		cpu1: cpu at 1 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a53";
> > +			reg = <0x1>;
> > +			clock-frequency = <1300000000>;
> > +		};
> > +
> > +		cpu2: cpu at 2 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a53";
> > +			reg = <0x2>;
> > +			clock-frequency = <1300000000>;
> > +		};
> > +
> > +		cpu3: cpu at 3 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a53";
> > +			reg = <0x3>;
> > +			clock-frequency = <1300000000>;
> > +		};
> > +	};
> > +
> > +	chipid: chipid at 08000000 {
> > +		compatible = "mediatek,chipid";
> > +		reg = <0x08000000 0x0004>,
> > +		      <0x08000004 0x0004>,
> > +		      <0x08000008 0x0004>,
> > +		      <0x0800000c 0x0004>;
> > +	};
> 
> I couldn't find any driver using this compatible.
> You may want to drop this 'device'.
> 
> Regards,
> Matthias

Thank you for review.
I will drop it and also drop other unused 'device'.

[U-Boot] [PATCH 2/5] clk: mediatek: add driver for MT8518

[mingming lee]

Add clock driver for MediaTek MT8518 SoC.

Signed-off-by: mingming lee <mingming.lee@mediatek.com>
---
 drivers/clk/mediatek/Makefile          |    1 +
 drivers/clk/mediatek/clk-mt8518.c      | 1558 ++++++++++++++++++++++++
 include/dt-bindings/clock/mt8518-clk.h |  249 ++++
 3 files changed, 1808 insertions(+)
 create mode 100644 drivers/clk/mediatek/clk-mt8518.c
 create mode 100644 include/dt-bindings/clock/mt8518-clk.h

diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index a47a5bdbc2..e92bcd4efe 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_ARCH_MEDIATEK) += clk-mtk.o
 obj-$(CONFIG_TARGET_MT7623) += clk-mt7623.o
 obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o
 obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o
+obj-$(CONFIG_TARGET_MT8518) += clk-mt8518.o
diff --git a/drivers/clk/mediatek/clk-mt8518.c b/drivers/clk/mediatek/clk-mt8518.c
new file mode 100644
index 0000000000..35b3db28e6
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8518.c
@@ -0,0 +1,1558 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek clock driver for MT8518 SoC
+ *
+ * Copyright (C) 2019 BayLibre, SAS
+ * Author: Chen Zhong <chen.zhong@mediatek.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <dt-bindings/clock/mt8518-clk.h>
+
+#include "clk-mtk.h"
+
+#define MT8518_PLL_FMAX		(3000UL * MHZ)
+#define MT8518_CON0_RST_BAR	BIT(27)
+
+/* apmixedsys */
+#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg,	\
+	    _pd_shift, _pcw_reg, _pcw_shift) {				\
+		.id = _id,						\
+		.reg = _reg,						\
+		.pwr_reg = _pwr_reg,					\
+		.en_mask = _en_mask,					\
+		.rst_bar_mask = MT8518_CON0_RST_BAR,			\
+		.fmax = MT8518_PLL_FMAX,				\
+		.flags = _flags,					\
+		.pcwbits = _pcwbits,					\
+		.pd_reg = _pd_reg,					\
+		.pd_shift = _pd_shift,					\
+		.pcw_reg = _pcw_reg,					\
+		.pcw_shift = _pcw_shift,				\
+	}
+
+static const struct mtk_pll_data apmixed_plls[] = {
+	PLL(CLK_APMIXED_ARMPLL, 0x0100, 0x0110, 0x00000001,
+	    0, 21, 0x0104, 24, 0x0104, 0),
+	PLL(CLK_APMIXED_MAINPLL, 0x0120, 0x0130, 0x00000001,
+	    HAVE_RST_BAR, 21, 0x0124, 24, 0x0124, 0),
+	PLL(CLK_APMIXED_UNIVPLL, 0x0140, 0x0150, 0x30000001,
+	    HAVE_RST_BAR, 7, 0x0144, 24, 0x0144, 0),
+	PLL(CLK_APMIXED_MMPLL, 0x0160, 0x0170, 0x00000001,
+	    0, 21, 0x0164, 24, 0x0164, 0),
+	PLL(CLK_APMIXED_APLL1, 0x0180, 0x0190, 0x00000001,
+	    0, 31, 0x0180, 1, 0x0184, 0),
+	PLL(CLK_APMIXED_APLL2, 0x01A0, 0x01B0, 0x00000001,
+	    0, 31, 0x01A0, 1, 0x01A4, 0),
+	PLL(CLK_APMIXED_TVDPLL, 0x01C0, 0x01D0, 0x00000001,
+	    0, 21, 0x01C4, 24, 0x01C4, 0),
+};
+
+/* topckgen */
+#define FACTOR0(_id, _parent, _mult, _div)	\
+	FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
+
+#define FACTOR1(_id, _parent, _mult, _div)	\
+	FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
+
+#define FACTOR2(_id, _parent, _mult, _div)	\
+	FACTOR(_id, _parent, _mult, _div, 0)
+
+static const struct mtk_fixed_clk top_fixed_clks[] = {
+	FIXED_CLK(CLK_TOP_CLK_NULL, CLK_XTAL, 26000000),
+	FIXED_CLK(CLK_TOP_FQ_TRNG_OUT0, CLK_TOP_CLK_NULL, 500000000),
+	FIXED_CLK(CLK_TOP_FQ_TRNG_OUT1, CLK_TOP_CLK_NULL, 500000000),
+	FIXED_CLK(CLK_TOP_CLK32K, CLK_XTAL, 32000),
+};
+
+static const struct mtk_fixed_factor top_fixed_divs[] = {
+	FACTOR2(CLK_TOP_DMPLL, CLK_XTAL, 1, 1),
+	FACTOR0(CLK_TOP_MAINPLL_D4, CLK_APMIXED_MAINPLL, 1, 4),
+	FACTOR0(CLK_TOP_MAINPLL_D8, CLK_APMIXED_MAINPLL, 1, 8),
+	FACTOR0(CLK_TOP_MAINPLL_D16, CLK_APMIXED_MAINPLL, 1, 16),
+	FACTOR0(CLK_TOP_MAINPLL_D11, CLK_APMIXED_MAINPLL, 1, 11),
+	FACTOR0(CLK_TOP_MAINPLL_D22, CLK_APMIXED_MAINPLL, 1, 22),
+	FACTOR0(CLK_TOP_MAINPLL_D3, CLK_APMIXED_MAINPLL, 1, 3),
+	FACTOR0(CLK_TOP_MAINPLL_D6, CLK_APMIXED_MAINPLL, 1, 6),
+	FACTOR0(CLK_TOP_MAINPLL_D12, CLK_APMIXED_MAINPLL, 1, 12),
+	FACTOR0(CLK_TOP_MAINPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
+	FACTOR0(CLK_TOP_MAINPLL_D10, CLK_APMIXED_MAINPLL, 1, 10),
+	FACTOR0(CLK_TOP_MAINPLL_D20, CLK_APMIXED_MAINPLL, 1, 20),
+	FACTOR0(CLK_TOP_MAINPLL_D40, CLK_APMIXED_MAINPLL, 1, 40),
+	FACTOR0(CLK_TOP_MAINPLL_D7, CLK_APMIXED_MAINPLL, 1, 7),
+	FACTOR0(CLK_TOP_MAINPLL_D14, CLK_APMIXED_MAINPLL, 1, 14),
+	FACTOR0(CLK_TOP_UNIVPLL_D2, CLK_APMIXED_UNIVPLL, 1, 2),
+	FACTOR0(CLK_TOP_UNIVPLL_D4, CLK_APMIXED_UNIVPLL, 1, 4),
+	FACTOR0(CLK_TOP_UNIVPLL_D8, CLK_APMIXED_UNIVPLL, 1, 8),
+	FACTOR0(CLK_TOP_UNIVPLL_D16, CLK_APMIXED_UNIVPLL, 1, 16),
+	FACTOR0(CLK_TOP_UNIVPLL_D3, CLK_APMIXED_UNIVPLL, 1, 3),
+	FACTOR0(CLK_TOP_UNIVPLL_D6, CLK_APMIXED_UNIVPLL, 1, 6),
+	FACTOR0(CLK_TOP_UNIVPLL_D12, CLK_APMIXED_UNIVPLL, 1, 12),
+	FACTOR0(CLK_TOP_UNIVPLL_D24, CLK_APMIXED_UNIVPLL, 1, 24),
+	FACTOR0(CLK_TOP_UNIVPLL_D5, CLK_APMIXED_UNIVPLL, 1, 5),
+	FACTOR0(CLK_TOP_UNIVPLL_D20, CLK_APMIXED_UNIVPLL, 1, 20),
+	FACTOR0(CLK_TOP_UNIVPLL_D10, CLK_APMIXED_UNIVPLL, 1, 10),
+	FACTOR0(CLK_TOP_MMPLL_D2, CLK_APMIXED_MMPLL, 1, 2),
+	FACTOR0(CLK_TOP_USB20_48M, CLK_APMIXED_UNIVPLL, 1, 26),
+	FACTOR0(CLK_TOP_APLL1, CLK_APMIXED_APLL1, 1, 1),
+	FACTOR1(CLK_TOP_APLL1_D4, CLK_TOP_APLL1, 1, 4),
+	FACTOR0(CLK_TOP_APLL2, CLK_APMIXED_APLL2, 1, 1),
+	FACTOR1(CLK_TOP_APLL2_D2, CLK_TOP_APLL2, 1, 2),
+	FACTOR1(CLK_TOP_APLL2_D3, CLK_TOP_APLL2, 1, 3),
+	FACTOR1(CLK_TOP_APLL2_D4, CLK_TOP_APLL2, 1, 4),
+	FACTOR1(CLK_TOP_APLL2_D8, CLK_TOP_APLL2, 1, 8),
+	FACTOR2(CLK_TOP_CLK26M, CLK_XTAL, 1, 1),
+	FACTOR2(CLK_TOP_CLK26M_D2, CLK_XTAL, 1, 2),
+	FACTOR2(CLK_TOP_CLK26M_D4, CLK_XTAL, 1, 4),
+	FACTOR2(CLK_TOP_CLK26M_D8, CLK_XTAL, 1, 8),
+	FACTOR2(CLK_TOP_CLK26M_D793, CLK_XTAL, 1, 793),
+	FACTOR0(CLK_TOP_TVDPLL, CLK_APMIXED_TVDPLL, 1, 1),
+	FACTOR1(CLK_TOP_TVDPLL_D2, CLK_TOP_TVDPLL, 1, 2),
+	FACTOR1(CLK_TOP_TVDPLL_D4, CLK_TOP_TVDPLL, 1, 4),
+	FACTOR1(CLK_TOP_TVDPLL_D8, CLK_TOP_TVDPLL, 1, 8),
+	FACTOR1(CLK_TOP_TVDPLL_D16, CLK_TOP_TVDPLL, 1, 16),
+	FACTOR1(CLK_TOP_USB20_CLK480M, CLK_TOP_CLK_NULL, 1, 1),
+	FACTOR1(CLK_TOP_RG_APLL1_D2, CLK_TOP_APLL1_SRC_SEL, 1, 2),
+	FACTOR1(CLK_TOP_RG_APLL1_D4, CLK_TOP_APLL1_SRC_SEL, 1, 4),
+	FACTOR1(CLK_TOP_RG_APLL1_D8, CLK_TOP_APLL1_SRC_SEL, 1, 8),
+	FACTOR1(CLK_TOP_RG_APLL1_D16, CLK_TOP_APLL1_SRC_SEL, 1, 16),
+	FACTOR1(CLK_TOP_RG_APLL1_D3, CLK_TOP_APLL1_SRC_SEL, 1, 3),
+	FACTOR1(CLK_TOP_RG_APLL2_D2, CLK_TOP_APLL2_SRC_SEL, 1, 2),
+	FACTOR1(CLK_TOP_RG_APLL2_D4, CLK_TOP_APLL2_SRC_SEL, 1, 4),
+	FACTOR1(CLK_TOP_RG_APLL2_D8, CLK_TOP_APLL2_SRC_SEL, 1, 8),
+	FACTOR1(CLK_TOP_RG_APLL2_D16, CLK_TOP_APLL2_SRC_SEL, 1, 16),
+	FACTOR1(CLK_TOP_RG_APLL2_D3, CLK_TOP_APLL2_SRC_SEL, 1, 3),
+	FACTOR1(CLK_TOP_NFI1X_INFRA_BCLK, CLK_TOP_NFI2X_SEL, 1, 2),
+	FACTOR1(CLK_TOP_AHB_INFRA_D2, CLK_TOP_AXIBUS_SEL, 1, 2),
+};
+
+static const int uart0_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D24
+};
+
+static const int emi1x_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_DMPLL
+};
+
+static const int emi_ddrphy_parents[] = {
+	CLK_TOP_EMI1X_SEL,
+	CLK_TOP_EMI1X_SEL
+};
+
+static const int msdc1_parents[] = {
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D6,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D8,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_UNIVPLL_D8,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D16,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MMPLL_D2,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D12
+};
+
+static const int pwm_mm_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D12
+};
+
+static const int pmicspi_parents[] = {
+	CLK_TOP_UNIVPLL_D20,
+	CLK_TOP_USB20_48M,
+	CLK_TOP_UNIVPLL_D16,
+	CLK_TOP_CLK26M,
+	CLK_TOP_CLK26M_D2
+};
+
+static const int nfi2x_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_MAINPLL_D4,
+	CLK_TOP_MAINPLL_D5,
+	CLK_TOP_MAINPLL_D6,
+	CLK_TOP_MAINPLL_D7,
+	CLK_TOP_MAINPLL_D8,
+	CLK_TOP_MAINPLL_D10,
+	CLK_TOP_MAINPLL_D12
+};
+
+static const int ddrphycfg_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_MAINPLL_D16
+};
+
+static const int smi_parents[] = {
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK26M,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_UNIVPLL_D4,
+	CLK_TOP_MAINPLL_D7,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D14
+};
+
+static const int usb_parents[] = {
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D16,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D20
+};
+
+static const int spinor_parents[] = {
+	CLK_TOP_CLK26M_D2,
+	CLK_TOP_CLK26M,
+	CLK_TOP_MAINPLL_D40,
+	CLK_TOP_UNIVPLL_D24,
+	CLK_TOP_UNIVPLL_D20,
+	CLK_TOP_MAINPLL_D20,
+	CLK_TOP_MAINPLL_D16,
+	CLK_TOP_UNIVPLL_D12
+};
+
+static const int eth_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_MAINPLL_D40,
+	CLK_TOP_UNIVPLL_D24,
+	CLK_TOP_UNIVPLL_D20,
+	CLK_TOP_MAINPLL_D20
+};
+
+static const int aud1_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_APLL1_SRC_SEL
+};
+
+static const int aud2_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_APLL2_SRC_SEL
+};
+
+static const int i2c_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_USB20_48M,
+	CLK_TOP_UNIVPLL_D12,
+	CLK_TOP_UNIVPLL_D10,
+	CLK_TOP_UNIVPLL_D8
+};
+
+static const int aud_i2s0_m_parents[] = {
+	CLK_TOP_AUD1,
+	CLK_TOP_AUD2
+};
+
+static const int aud_spdifin_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D2,
+	CLK_TOP_TVDPLL
+};
+
+static const int dbg_atclk_parents[] = {
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK26M,
+	CLK_TOP_MAINPLL_D5,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_UNIVPLL_D5
+};
+
+static const int png_sys_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D8,
+	CLK_TOP_MAINPLL_D7,
+	CLK_TOP_MAINPLL_D6,
+	CLK_TOP_MAINPLL_D5,
+	CLK_TOP_UNIVPLL_D3
+};
+
+static const int sej_13m_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_CLK26M_D2
+};
+
+static const int imgrz_sys_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_MAINPLL_D6,
+	CLK_TOP_MAINPLL_D7,
+	CLK_TOP_MAINPLL_D5,
+	CLK_TOP_UNIVPLL_D4,
+	CLK_TOP_UNIVPLL_D10,
+	CLK_TOP_UNIVPLL_D5,
+	CLK_TOP_UNIVPLL_D6
+};
+
+static const int graph_eclk_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_MAINPLL_D6,
+	CLK_TOP_UNIVPLL_D8,
+	CLK_TOP_UNIVPLL_D16,
+	CLK_TOP_MAINPLL_D7,
+	CLK_TOP_UNIVPLL_D4,
+	CLK_TOP_UNIVPLL_D10,
+	CLK_TOP_UNIVPLL_D24,
+	CLK_TOP_MAINPLL_D8
+};
+
+static const int fdbi_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_MAINPLL_D12,
+	CLK_TOP_MAINPLL_D14,
+	CLK_TOP_MAINPLL_D16,
+	CLK_TOP_UNIVPLL_D10,
+	CLK_TOP_UNIVPLL_D12,
+	CLK_TOP_UNIVPLL_D16,
+	CLK_TOP_UNIVPLL_D24,
+	CLK_TOP_TVDPLL_D2,
+	CLK_TOP_TVDPLL_D4,
+	CLK_TOP_TVDPLL_D8,
+	CLK_TOP_TVDPLL_D16
+};
+
+static const int faudio_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D24,
+	CLK_TOP_APLL1_D4,
+	CLK_TOP_APLL2_D4
+};
+
+static const int fa2sys_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_APLL1_SRC_SEL,
+	CLK_TOP_RG_APLL1_D2,
+	CLK_TOP_RG_APLL1_D4,
+	CLK_TOP_RG_APLL1_D8,
+	CLK_TOP_RG_APLL1_D16,
+	CLK_TOP_CLK26M_D2,
+	CLK_TOP_RG_APLL1_D3
+};
+
+static const int fa1sys_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_APLL2_SRC_SEL,
+	CLK_TOP_RG_APLL2_D2,
+	CLK_TOP_RG_APLL2_D4,
+	CLK_TOP_RG_APLL2_D8,
+	CLK_TOP_RG_APLL2_D16,
+	CLK_TOP_CLK26M_D2,
+	CLK_TOP_RG_APLL2_D3
+};
+
+static const int fasm_m_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D12,
+	CLK_TOP_UNIVPLL_D6,
+	CLK_TOP_MAINPLL_D7
+};
+
+static const int fecc_ck_parents[] = {
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D6,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_UNIVPLL_D4,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_UNIVPLL_D3,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D3
+};
+
+static const int pe2_mac_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_MAINPLL_D11,
+	CLK_TOP_MAINPLL_D16,
+	CLK_TOP_UNIVPLL_D12,
+	CLK_TOP_UNIVPLL_D10
+};
+
+static const int cmsys_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D5,
+	CLK_TOP_UNIVPLL_D6,
+	CLK_TOP_MAINPLL_D5,
+	CLK_TOP_APLL2,
+	CLK_TOP_APLL2_D2,
+	CLK_TOP_APLL2_D4,
+	CLK_TOP_APLL2_D3
+};
+
+static const int gcpu_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_MAINPLL_D4,
+	CLK_TOP_MAINPLL_D5,
+	CLK_TOP_MAINPLL_D6,
+	CLK_TOP_MAINPLL_D7,
+	CLK_TOP_UNIVPLL_D4,
+	CLK_TOP_UNIVPLL_D10,
+	CLK_TOP_UNIVPLL_D3
+};
+
+static const int spis_ck_parents[] = {
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D12,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_UNIVPLL_D8,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_UNIVPLL_D6,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_UNIVPLL_D5,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_UNIVPLL_D4,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D4,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_UNIVPLL_D3
+};
+
+static const int apll1_ref_parents[] = {
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL
+};
+
+static const int int_32k_parents[] = {
+	CLK_TOP_CLK32K,
+	CLK_TOP_CLK26M_D793
+};
+
+static const int apll1_src_parents[] = {
+	CLK_TOP_APLL1,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL
+};
+
+static const int apll2_src_parents[] = {
+	CLK_TOP_APLL2,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL
+};
+
+static const int faud_intbus_parents[] = {
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK26M,
+	CLK_TOP_MAINPLL_D11,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK26M,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_UNIVPLL_D10,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_RG_APLL2_D8,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK26M_D2,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_RG_APLL1_D8,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_UNIVPLL_D20
+};
+
+static const int axibus_parents[] = {
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK26M,
+	CLK_TOP_MAINPLL_D11,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D12,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_UNIVPLL_D10,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK26M_D2,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_APLL2_D8
+};
+
+static const int hapll1_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_APLL1_SRC_SEL,
+	CLK_TOP_RG_APLL1_D2,
+	CLK_TOP_RG_APLL1_D4,
+	CLK_TOP_RG_APLL1_D8,
+	CLK_TOP_RG_APLL1_D16,
+	CLK_TOP_CLK26M_D2,
+	CLK_TOP_CLK26M_D8,
+	CLK_TOP_RG_APLL1_D3
+};
+
+static const int hapll2_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_APLL2_SRC_SEL,
+	CLK_TOP_RG_APLL2_D2,
+	CLK_TOP_RG_APLL2_D4,
+	CLK_TOP_RG_APLL2_D8,
+	CLK_TOP_RG_APLL2_D16,
+	CLK_TOP_CLK26M_D2,
+	CLK_TOP_CLK26M_D4,
+	CLK_TOP_RG_APLL2_D3
+};
+
+static const int spinfi_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D24,
+	CLK_TOP_UNIVPLL_D20,
+	CLK_TOP_MAINPLL_D22,
+	CLK_TOP_UNIVPLL_D16,
+	CLK_TOP_MAINPLL_D16,
+	CLK_TOP_UNIVPLL_D12,
+	CLK_TOP_UNIVPLL_D10,
+	CLK_TOP_MAINPLL_D11
+};
+
+static const int msdc0_parents[] = {
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D6,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D8,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_UNIVPLL_D8,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D16,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D12,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_APMIXED_MMPLL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MMPLL_D2
+};
+
+static const int msdc0_clk50_parents[] = {
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D6,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D8,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_UNIVPLL_D8,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D6
+};
+
+static const int msdc2_parents[] = {
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D6,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D8,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_UNIVPLL_D8,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D16,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MMPLL_D2,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D12,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_APMIXED_MMPLL
+};
+
+static const int disp_dpi_ck_parents[] = {
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK26M,
+	CLK_TOP_TVDPLL_D2,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_TVDPLL_D4,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_TVDPLL_D8,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_TVDPLL_D16
+};
+
+static const struct mtk_composite top_muxes[] = {
+	/* CLK_MUX_SEL0 */
+	MUX(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1),
+	MUX(CLK_TOP_EMI1X_SEL, emi1x_parents, 0x000, 1, 1),
+	MUX(CLK_TOP_EMI_DDRPHY_SEL, emi_ddrphy_parents, 0x000, 2, 1),
+	MUX(CLK_TOP_MSDC1_SEL, msdc1_parents, 0x000, 4, 8),
+	MUX(CLK_TOP_PWM_MM_SEL, pwm_mm_parents, 0x000, 18, 1),
+	MUX(CLK_TOP_UART1_SEL, uart0_parents, 0x000, 19, 1),
+	MUX(CLK_TOP_SPM_52M_SEL, uart0_parents, 0x000, 22, 1),
+	MUX(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x000, 23, 3),
+	/* CLK_MUX_SEL1 */
+	MUX(CLK_TOP_NFI2X_SEL, nfi2x_parents, 0x004, 0, 3),
+	MUX(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x004, 15, 1),
+	MUX(CLK_TOP_SMI_SEL, smi_parents, 0x004, 16, 4),
+	MUX(CLK_TOP_USB_SEL, usb_parents, 0x004, 20, 3),
+	/* CLK_MUX_SEL8 */
+	MUX(CLK_TOP_SPINOR_SEL, spinor_parents, 0x040, 0, 3),
+	MUX(CLK_TOP_ETH_SEL, eth_parents, 0x040, 6, 3),
+	MUX(CLK_TOP_AUD1_SEL, aud1_parents, 0x040, 22, 1),
+	MUX(CLK_TOP_AUD2_SEL, aud2_parents, 0x040, 23, 1),
+	MUX(CLK_TOP_I2C_SEL, i2c_parents, 0x040, 28, 3),
+	/* CLK_SEL_9 */
+	MUX(CLK_TOP_AUD_I2S0_M_SEL, aud_i2s0_m_parents, 0x044, 12, 1),
+	MUX(CLK_TOP_AUD_I2S3_M_SEL, aud_i2s0_m_parents, 0x044, 15, 1),
+	MUX(CLK_TOP_AUD_I2S4_M_SEL, aud_i2s0_m_parents, 0x044, 16, 1),
+	MUX(CLK_TOP_AUD_I2S6_M_SEL, aud_i2s0_m_parents, 0x044, 18, 1),
+	/* CLK_MUX_SEL13 */
+	MUX(CLK_TOP_PWM_SEL, pwm_mm_parents, 0x07c, 0, 1),
+	MUX(CLK_TOP_AUD_SPDIFIN_SEL, aud_spdifin_parents, 0x07c, 2, 2),
+	MUX(CLK_TOP_UART2_SEL, uart0_parents, 0x07c, 4, 1),
+	MUX(CLK_TOP_DBG_ATCLK_SEL, dbg_atclk_parents, 0x07c, 7, 3),
+	MUX(CLK_TOP_PNG_SYS_SEL, png_sys_parents, 0x07c, 16, 3),
+	MUX(CLK_TOP_SEJ_13M_SEL, sej_13m_parents, 0x07c, 22, 1),
+	/* CLK_MUX_SEL14 */
+	MUX(CLK_TOP_IMGRZ_SYS_SEL, imgrz_sys_parents, 0xc0, 0, 3),
+	MUX(CLK_TOP_GRAPH_ECLK_SEL, graph_eclk_parents, 0xc0, 8, 4),
+	MUX(CLK_TOP_FDBI_SEL, fdbi_parents, 0xc0, 12, 4),
+	MUX(CLK_TOP_FAUDIO_SEL, faudio_parents, 0xc0, 16, 2),
+	MUX(CLK_TOP_FA2SYS_SEL, fa2sys_parents, 0xc0, 24, 3),
+	MUX(CLK_TOP_FA1SYS_SEL, fa1sys_parents, 0xc0, 27, 3),
+	MUX(CLK_TOP_FASM_M_SEL, fasm_m_parents, 0xc0, 30, 2),
+	/* CLK_MUX_SEL15 */
+	MUX(CLK_TOP_FASM_H_SEL, fasm_m_parents, 0xC4, 0, 2),
+	MUX(CLK_TOP_FASM_L_SEL, fasm_m_parents, 0xC4, 2, 2),
+	MUX(CLK_TOP_FECC_CK_SEL, fecc_ck_parents, 0xC4, 18, 6),
+	MUX(CLK_TOP_PE2_MAC_SEL, pe2_mac_parents, 0xC4, 24, 3),
+	MUX(CLK_TOP_CMSYS_SEL, cmsys_parents, 0xC4, 28, 3),
+	/* CLK_MUX_SEL16 */
+	MUX(CLK_TOP_GCPU_SEL, gcpu_parents, 0xC8, 0, 3),
+	MUX(CLK_TOP_SPIS_CK_SEL, spis_ck_parents, 0xC8, 4, 8),
+	/* CLK_MUX_SEL17 */
+	MUX(CLK_TOP_APLL1_REF_SEL, apll1_ref_parents, 0xCC, 6, 3),
+	MUX(CLK_TOP_APLL2_REF_SEL, apll1_ref_parents, 0xCC, 9, 3),
+	MUX(CLK_TOP_INT_32K_SEL, int_32k_parents, 0xCC, 12, 1),
+	MUX(CLK_TOP_APLL1_SRC_SEL, apll1_src_parents, 0xCC, 13, 2),
+	MUX(CLK_TOP_APLL2_SRC_SEL, apll2_src_parents, 0xCC, 15, 2),
+	/* CLK_MUX_SEL19 */
+	MUX(CLK_TOP_FAUD_INTBUS_SEL, faud_intbus_parents, 0xD4, 8, 8),
+	MUX(CLK_TOP_AXIBUS_SEL, axibus_parents, 0xD4, 24, 8),
+	/* CLK_MUX_SEL21 */
+	MUX(CLK_TOP_HAPLL1_SEL, hapll1_parents, 0xDC, 0, 4),
+	MUX(CLK_TOP_HAPLL2_SEL, hapll2_parents, 0xDC, 4, 4),
+	MUX(CLK_TOP_SPINFI_SEL, spinfi_parents, 0xDC, 8, 4),
+	/* CLK_MUX_SEL22 */
+	MUX(CLK_TOP_MSDC0_SEL, msdc0_parents, 0xF4, 0, 8),
+	MUX(CLK_TOP_MSDC0_CLK50_SEL, msdc0_clk50_parents, 0xF4, 8, 6),
+	MUX(CLK_TOP_MSDC2_SEL, msdc2_parents, 0xF4, 15, 8),
+	MUX(CLK_TOP_MSDC2_CLK50_SEL, msdc0_clk50_parents, 0xF4, 23, 6),
+	/* CLK_MUX_SEL23 */
+	MUX(CLK_TOP_DISP_DPI_CK_SEL, disp_dpi_ck_parents, 0xF8, 0, 6),
+	MUX(CLK_TOP_SPI1_SEL, spis_ck_parents, 0xF8, 6, 8),
+	MUX(CLK_TOP_SPI2_SEL, spis_ck_parents, 0xF8, 14, 8),
+	MUX(CLK_TOP_SPI3_SEL, spis_ck_parents, 0xF8, 22, 8),
+};
+
+static const struct mtk_gate_regs top0_cg_regs = {
+	.set_ofs = 0x50,
+	.clr_ofs = 0x80,
+	.sta_ofs = 0x20,
+};
+
+static const struct mtk_gate_regs top1_cg_regs = {
+	.set_ofs = 0x54,
+	.clr_ofs = 0x84,
+	.sta_ofs = 0x24,
+};
+
+static const struct mtk_gate_regs top2_cg_regs = {
+	.set_ofs = 0x6c,
+	.clr_ofs = 0x9c,
+	.sta_ofs = 0x3c,
+};
+
+static const struct mtk_gate_regs top3_cg_regs = {
+	.set_ofs = 0x44,
+	.clr_ofs = 0x44,
+	.sta_ofs = 0x44,
+};
+
+static const struct mtk_gate_regs top4_cg_regs = {
+	.set_ofs = 0xa0,
+	.clr_ofs = 0xb0,
+	.sta_ofs = 0x70,
+};
+
+static const struct mtk_gate_regs top5_cg_regs = {
+	.set_ofs = 0x120,
+	.clr_ofs = 0x140,
+	.sta_ofs = 0xe0,
+};
+
+static const struct mtk_gate_regs top6_cg_regs = {
+	.set_ofs = 0x128,
+	.clr_ofs = 0x148,
+	.sta_ofs = 0xe8,
+};
+
+static const struct mtk_gate_regs top7_cg_regs = {
+	.set_ofs = 0x12c,
+	.clr_ofs = 0x14c,
+	.sta_ofs = 0xec,
+};
+
+#define GATE_TOP0(_id, _parent, _shift) {			\
+		.id = _id,					\
+		.parent = _parent,				\
+		.regs = &top0_cg_regs,				\
+		.shift = _shift,				\
+		.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN,	\
+	}
+
+#define GATE_TOP1(_id, _parent, _shift) {			\
+		.id = _id,					\
+		.parent = _parent,				\
+		.regs = &top1_cg_regs,				\
+		.shift = _shift,				\
+		.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN,	\
+	}
+
+#define GATE_TOP2(_id, _parent, _shift) {			\
+		.id = _id,					\
+		.parent = _parent,				\
+		.regs = &top2_cg_regs,				\
+		.shift = _shift,				\
+		.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN,	\
+	}
+
+#define GATE_TOP2_I(_id, _parent, _shift) {				\
+		.id = _id,						\
+		.parent = _parent,					\
+		.regs = &top2_cg_regs,					\
+		.shift = _shift,					\
+		.flags = CLK_GATE_SETCLR_INV | CLK_PARENT_TOPCKGEN,	\
+	}
+
+#define GATE_TOP3(_id, _parent, _shift) {			\
+		.id = _id,					\
+		.parent = _parent,				\
+		.regs = &top3_cg_regs,				\
+		.shift = _shift,				\
+		.flags = CLK_GATE_NO_SETCLR | CLK_PARENT_TOPCKGEN,	\
+	}
+
+#define GATE_TOP4(_id, _parent, _shift) {				\
+		.id = _id,						\
+		.parent = _parent,					\
+		.regs = &top4_cg_regs,					\
+		.shift = _shift,					\
+		.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN,	\
+	}
+
+#define GATE_TOP5(_id, _parent, _shift) {				\
+		.id = _id,						\
+		.parent = _parent,					\
+		.regs = &top5_cg_regs,					\
+		.shift = _shift,					\
+		.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN,	\
+	}
+
+#define GATE_TOP5_I(_id, _parent, _shift) {				\
+		.id = _id,						\
+		.parent = _parent,					\
+		.regs = &top5_cg_regs,					\
+		.shift = _shift,					\
+		.flags = CLK_GATE_SETCLR_INV | CLK_PARENT_TOPCKGEN,	\
+	}
+
+#define GATE_TOP6(_id, _parent, _shift) {				\
+		.id = _id,						\
+		.parent = _parent,					\
+		.regs = &top5_cg_regs,					\
+		.shift = _shift,					\
+		.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN,	\
+	}
+
+#define GATE_TOP7(_id, _parent, _shift) {				\
+		.id = _id,						\
+		.parent = _parent,					\
+		.regs = &top5_cg_regs,					\
+		.shift = _shift,					\
+		.flags = CLK_GATE_SETCLR_INV | CLK_PARENT_TOPCKGEN,	\
+	}
+
+static const struct mtk_gate top_clks[] = {
+	/* TOP0 */
+	GATE_TOP0(CLK_TOP_PWM_MM, CLK_TOP_PWM_MM_SEL, 0),
+	GATE_TOP0(CLK_TOP_SMI, CLK_TOP_SMI_SEL, 9),
+	GATE_TOP0(CLK_TOP_SPI2, CLK_TOP_SPI2_SEL, 10),
+	GATE_TOP0(CLK_TOP_SPI3, CLK_TOP_SPI3_SEL, 11),
+	GATE_TOP0(CLK_TOP_SPINFI, CLK_TOP_SPINFI_SEL, 12),
+	GATE_TOP0(CLK_TOP_26M_DEBUG, CLK_TOP_CLK26M, 16),
+	GATE_TOP0(CLK_TOP_USB_48M_DEBUG, CLK_TOP_USB20_48M, 17),
+	GATE_TOP0(CLK_TOP_52M_DEBUG, CLK_TOP_UNIVPLL_D24, 18),
+	GATE_TOP0(CLK_TOP_32K_DEBUG, CLK_TOP_INT_32K_SEL, 19),
+	/* TOP1 */
+	GATE_TOP1(CLK_TOP_THERM, CLK_TOP_AXIBUS_SEL, 1),
+	GATE_TOP1(CLK_TOP_APDMA, CLK_TOP_AXIBUS_SEL, 2),
+	GATE_TOP1(CLK_TOP_I2C0, CLK_TOP_AHB_INFRA_D2, 3),
+	GATE_TOP1(CLK_TOP_I2C1, CLK_TOP_AHB_INFRA_D2, 4),
+	GATE_TOP1(CLK_TOP_AUXADC1, CLK_TOP_CLK26M, 5),
+	GATE_TOP1(CLK_TOP_NFI, CLK_TOP_NFI1X_INFRA_BCLK, 6),
+	GATE_TOP1(CLK_TOP_NFIECC, CLK_TOP_AXIBUS_SEL, 7),
+	GATE_TOP1(CLK_TOP_DEBUGSYS, CLK_TOP_DBG_ATCLK_SEL, 8),
+	GATE_TOP1(CLK_TOP_PWM, CLK_TOP_AXIBUS_SEL, 9),
+	GATE_TOP1(CLK_TOP_UART0, CLK_TOP_UART0_SEL, 10),
+	GATE_TOP1(CLK_TOP_UART1, CLK_TOP_UART1_SEL, 11),
+	GATE_TOP1(CLK_TOP_USB, CLK_TOP_USB_B, 13),
+	GATE_TOP1(CLK_TOP_FLASHIF_26M, CLK_TOP_CLK26M, 14),
+	GATE_TOP1(CLK_TOP_AUXADC2, CLK_TOP_CLK26M, 15),
+	GATE_TOP1(CLK_TOP_I2C2, CLK_TOP_AHB_INFRA_D2, 16),
+	GATE_TOP1(CLK_TOP_MSDC0, CLK_TOP_MSDC0_SEL, 17),
+	GATE_TOP1(CLK_TOP_MSDC1, CLK_TOP_MSDC1_SEL, 18),
+	GATE_TOP1(CLK_TOP_NFI2X, CLK_TOP_NFI2X_SEL, 19),
+	GATE_TOP1(CLK_TOP_MEMSLP_DLYER, CLK_TOP_CLK26M, 22),
+	GATE_TOP1(CLK_TOP_SPI, CLK_TOP_SPI1_SEL, 23),
+	GATE_TOP1(CLK_TOP_APXGPT, CLK_TOP_CLK26M, 24),
+	GATE_TOP1(CLK_TOP_PMICWRAP_MD, CLK_TOP_CLK26M, 27),
+	GATE_TOP1(CLK_TOP_PMICWRAP_CONN, CLK_TOP_PMICSPI_SEL, 28),
+	GATE_TOP1(CLK_TOP_PMIC_SYSCK, CLK_TOP_CLK26M, 29),
+	GATE_TOP1(CLK_TOP_AUX_ADC, CLK_TOP_CLK26M, 30),
+	GATE_TOP1(CLK_TOP_AUX_TP, CLK_TOP_CLK26M, 31),
+	/* TOP2 */
+	GATE_TOP2(CLK_TOP_RBIST, CLK_TOP_UNIVPLL_D12, 1),
+	GATE_TOP2(CLK_TOP_NFI_BUS, CLK_TOP_AXIBUS_SEL, 2),
+	GATE_TOP2(CLK_TOP_GCE, CLK_TOP_AXIBUS_SEL, 4),
+	GATE_TOP2(CLK_TOP_TRNG, CLK_TOP_AXIBUS_SEL, 5),
+	GATE_TOP2(CLK_TOP_PWM_B, CLK_TOP_PWM_SEL, 8),
+	GATE_TOP2(CLK_TOP_PWM1_FB, CLK_TOP_PWM_SEL, 9),
+	GATE_TOP2(CLK_TOP_PWM2_FB, CLK_TOP_PWM_SEL, 10),
+	GATE_TOP2(CLK_TOP_PWM3_FB, CLK_TOP_PWM_SEL, 11),
+	GATE_TOP2(CLK_TOP_PWM4_FB, CLK_TOP_PWM_SEL, 12),
+	GATE_TOP2(CLK_TOP_PWM5_FB, CLK_TOP_PWM_SEL, 13),
+	GATE_TOP2(CLK_TOP_FLASHIF_FREERUN, CLK_TOP_AXIBUS_SEL, 15),
+	GATE_TOP2(CLK_TOP_CQDMA, CLK_TOP_AXIBUS_SEL, 17),
+	GATE_TOP2(CLK_TOP_66M_ETH, CLK_TOP_AXIBUS_SEL, 19),
+	GATE_TOP2(CLK_TOP_133M_ETH, CLK_TOP_AXIBUS_SEL, 20),
+	GATE_TOP2(CLK_TOP_FLASHIF_AXI, CLK_TOP_SPI1_SEL, 23),
+	GATE_TOP2(CLK_TOP_USBIF, CLK_TOP_AXIBUS_SEL, 24),
+	GATE_TOP2(CLK_TOP_UART2, CLK_TOP_RG_UART2, 25),
+	GATE_TOP2(CLK_TOP_GCPU_B, CLK_TOP_AXIBUS_SEL, 27),
+	GATE_TOP2_I(CLK_TOP_MSDC0_B, CLK_TOP_MSDC0, 28),
+	GATE_TOP2_I(CLK_TOP_MSDC1_B, CLK_TOP_MSDC1, 29),
+	GATE_TOP2_I(CLK_TOP_MSDC2_B, CLK_TOP_MSDC2, 30),
+	GATE_TOP2(CLK_TOP_USB_B, CLK_TOP_USB_SEL, 31),
+	/* TOP3 */
+	GATE_TOP3(CLK_TOP_APLL12_DIV0, CLK_TOP_APLL12_CK_DIV0, 0),
+	GATE_TOP3(CLK_TOP_APLL12_DIV3, CLK_TOP_APLL12_CK_DIV3, 3),
+	GATE_TOP3(CLK_TOP_APLL12_DIV4, CLK_TOP_APLL12_CK_DIV4, 4),
+	GATE_TOP3(CLK_TOP_APLL12_DIV6, CLK_TOP_APLL12_CK_DIV6, 8),
+	/* TOP4 */
+	GATE_TOP4(CLK_TOP_SPINOR, CLK_TOP_SPINOR_SEL, 0),
+	GATE_TOP4(CLK_TOP_MSDC2, CLK_TOP_MSDC2_SEL, 1),
+	GATE_TOP4(CLK_TOP_ETH, CLK_TOP_ETH_SEL, 2),
+	GATE_TOP4(CLK_TOP_AUD1, CLK_TOP_AUD1_SEL, 8),
+	GATE_TOP4(CLK_TOP_AUD2, CLK_TOP_AUD2_SEL, 9),
+	GATE_TOP4(CLK_TOP_I2C, CLK_TOP_I2C_SEL, 12),
+	GATE_TOP4(CLK_TOP_PWM_INFRA, CLK_TOP_PWM_SEL, 13),
+	GATE_TOP4(CLK_TOP_AUD_SPDIF_IN, CLK_TOP_AUD_SPDIFIN_SEL, 14),
+	GATE_TOP4(CLK_TOP_RG_UART2, CLK_TOP_UART2_SEL, 15),
+	GATE_TOP4(CLK_TOP_DBG_AT, CLK_TOP_DBG_ATCLK_SEL, 17),
+	/* TOP5 */
+	GATE_TOP5_I(CLK_TOP_IMGRZ_SYS, CLK_TOP_IMGRZ_SYS_SEL, 0),
+	GATE_TOP5_I(CLK_TOP_PNG_SYS, CLK_TOP_PNG_SYS_SEL, 1),
+	GATE_TOP5_I(CLK_TOP_GRAPH_E, CLK_TOP_GRAPH_ECLK_SEL, 2),
+	GATE_TOP5_I(CLK_TOP_FDBI, CLK_TOP_FDBI_SEL, 3),
+	GATE_TOP5_I(CLK_TOP_FAUDIO, CLK_TOP_FAUDIO_SEL, 4),
+	GATE_TOP5_I(CLK_TOP_FAUD_INTBUS, CLK_TOP_FAUD_INTBUS_SEL, 5),
+	GATE_TOP5_I(CLK_TOP_HAPLL1, CLK_TOP_HAPLL1_SEL, 6),
+	GATE_TOP5_I(CLK_TOP_HAPLL2, CLK_TOP_HAPLL2_SEL, 7),
+	GATE_TOP5_I(CLK_TOP_FA2SYS, CLK_TOP_FA2SYS_SEL, 8),
+	GATE_TOP5_I(CLK_TOP_FA1SYS, CLK_TOP_FA1SYS_SEL, 9),
+	GATE_TOP5_I(CLK_TOP_FASM_L, CLK_TOP_FASM_L_SEL, 10),
+	GATE_TOP5_I(CLK_TOP_FASM_M, CLK_TOP_FASM_M_SEL, 11),
+	GATE_TOP5_I(CLK_TOP_FASM_H, CLK_TOP_FASM_H_SEL, 12),
+	GATE_TOP5_I(CLK_TOP_FECC, CLK_TOP_FECC_CK_SEL, 23),
+	GATE_TOP5_I(CLK_TOP_PE2_MAC, CLK_TOP_PE2_MAC_SEL, 24),
+	GATE_TOP5_I(CLK_TOP_CMSYS, CLK_TOP_CMSYS_SEL, 25),
+	GATE_TOP5_I(CLK_TOP_GCPU, CLK_TOP_GCPU_SEL, 26),
+	GATE_TOP5(CLK_TOP_SPIS, CLK_TOP_SPIS_CK_SEL, 27),
+	/* TOP6 */
+	GATE_TOP6(CLK_TOP_I2C3, CLK_TOP_AHB_INFRA_D2, 0),
+	GATE_TOP6(CLK_TOP_SPI_SLV_B, CLK_TOP_SPIS_CK_SEL, 1),
+	GATE_TOP6(CLK_TOP_SPI_SLV_BUS, CLK_TOP_AXIBUS_SEL, 2),
+	GATE_TOP6(CLK_TOP_PCIE_MAC_BUS, CLK_TOP_AXIBUS_SEL, 3),
+	GATE_TOP6(CLK_TOP_CMSYS_BUS, CLK_TOP_AXIBUS_SEL, 4),
+	GATE_TOP6(CLK_TOP_ECC_B, CLK_TOP_AXIBUS_SEL, 5),
+	GATE_TOP6(CLK_TOP_PCIE_PHY_BUS, CLK_TOP_CLK26M, 6),
+	GATE_TOP6(CLK_TOP_PCIE_AUX, CLK_TOP_CLK26M, 7),
+	/* TOP7 */
+	GATE_TOP7(CLK_TOP_DISP_DPI, CLK_TOP_DISP_DPI_CK_SEL, 0),
+};
+
+static const struct mtk_clk_tree mt8518_clk_tree = {
+	.xtal_rate = 26 * MHZ,
+	.xtal2_rate = 26 * MHZ,
+	.fdivs_offs = CLK_TOP_DMPLL,
+	.muxes_offs = CLK_TOP_UART0_SEL,
+	.plls = apmixed_plls,
+	.fclks = top_fixed_clks,
+	.fdivs = top_fixed_divs,
+	.muxes = top_muxes,
+};
+
+static int mt8518_apmixedsys_probe(struct udevice *dev)
+{
+	return mtk_common_clk_init(dev, &mt8518_clk_tree);
+}
+
+static int mt8518_topckgen_probe(struct udevice *dev)
+{
+	return mtk_common_clk_init(dev, &mt8518_clk_tree);
+}
+
+static int mt8518_topckgen_cg_probe(struct udevice *dev)
+{
+	return mtk_common_clk_gate_init(dev, &mt8518_clk_tree, top_clks);
+}
+
+static const struct udevice_id mt8518_apmixed_compat[] = {
+	{ .compatible = "mediatek,mt8518-apmixedsys", },
+	{ }
+};
+
+static const struct udevice_id mt8518_topckgen_compat[] = {
+	{ .compatible = "mediatek,mt8518-topckgen", },
+	{ }
+};
+
+static const struct udevice_id mt8518_topckgen_cg_compat[] = {
+	{ .compatible = "mediatek,mt8518-topckgen-cg", },
+	{ }
+};
+
+U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
+	.name = "mt8518-apmixedsys",
+	.id = UCLASS_CLK,
+	.of_match = mt8518_apmixed_compat,
+	.probe = mt8518_apmixedsys_probe,
+	.priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
+	.ops = &mtk_clk_apmixedsys_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_topckgen) = {
+	.name = "mt8518-topckgen",
+	.id = UCLASS_CLK,
+	.of_match = mt8518_topckgen_compat,
+	.probe = mt8518_topckgen_probe,
+	.priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
+	.ops = &mtk_clk_topckgen_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_topckgen_cg) = {
+	.name = "mt8518-topckgen-cg",
+	.id = UCLASS_CLK,
+	.of_match = mt8518_topckgen_cg_compat,
+	.probe = mt8518_topckgen_cg_probe,
+	.priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+	.ops = &mtk_clk_gate_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/include/dt-bindings/clock/mt8518-clk.h b/include/dt-bindings/clock/mt8518-clk.h
new file mode 100644
index 0000000000..43b7247968
--- /dev/null
+++ b/include/dt-bindings/clock/mt8518-clk.h
@@ -0,0 +1,249 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT8518_H
+#define _DT_BINDINGS_CLK_MT8518_H
+
+/* APMIXEDSYS */
+
+#define CLK_APMIXED_ARMPLL		0
+#define CLK_APMIXED_MAINPLL		1
+#define CLK_APMIXED_UNIVPLL		2
+#define CLK_APMIXED_MMPLL		3
+#define CLK_APMIXED_APLL1		4
+#define CLK_APMIXED_APLL2		5
+#define CLK_APMIXED_TVDPLL		6
+#define CLK_APMIXED_NR_CLK		7
+
+/* TOPCKGEN */
+
+#define CLK_TOP_CLK_NULL		0
+#define CLK_TOP_FQ_TRNG_OUT0		1
+#define CLK_TOP_FQ_TRNG_OUT1		2
+#define CLK_TOP_CLK32K			3
+#define CLK_TOP_DMPLL			4
+#define CLK_TOP_MAINPLL_D4		5
+#define CLK_TOP_MAINPLL_D8		6
+#define CLK_TOP_MAINPLL_D16		7
+#define CLK_TOP_MAINPLL_D11		8
+#define CLK_TOP_MAINPLL_D22		9
+#define CLK_TOP_MAINPLL_D3		10
+#define CLK_TOP_MAINPLL_D6		11
+#define CLK_TOP_MAINPLL_D12		12
+#define CLK_TOP_MAINPLL_D5		13
+#define CLK_TOP_MAINPLL_D10		14
+#define CLK_TOP_MAINPLL_D20		15
+#define CLK_TOP_MAINPLL_D40		16
+#define CLK_TOP_MAINPLL_D7		17
+#define CLK_TOP_MAINPLL_D14		18
+#define CLK_TOP_UNIVPLL_D2		19
+#define CLK_TOP_UNIVPLL_D4		20
+#define CLK_TOP_UNIVPLL_D8		21
+#define CLK_TOP_UNIVPLL_D16		22
+#define CLK_TOP_UNIVPLL_D3		23
+#define CLK_TOP_UNIVPLL_D6		24
+#define CLK_TOP_UNIVPLL_D12		25
+#define CLK_TOP_UNIVPLL_D24		26
+#define CLK_TOP_UNIVPLL_D5		27
+#define CLK_TOP_UNIVPLL_D20		28
+#define CLK_TOP_UNIVPLL_D10		29
+#define CLK_TOP_MMPLL_D2		30
+#define CLK_TOP_USB20_48M		31
+#define CLK_TOP_APLL1			32
+#define CLK_TOP_APLL1_D4		33
+#define CLK_TOP_APLL2			34
+#define CLK_TOP_APLL2_D2		35
+#define CLK_TOP_APLL2_D3		36
+#define CLK_TOP_APLL2_D4		37
+#define CLK_TOP_APLL2_D8		38
+#define CLK_TOP_CLK26M			39
+#define CLK_TOP_CLK26M_D2		40
+#define CLK_TOP_CLK26M_D4		41
+#define CLK_TOP_CLK26M_D8		42
+#define CLK_TOP_CLK26M_D793		43
+#define CLK_TOP_TVDPLL			44
+#define CLK_TOP_TVDPLL_D2		45
+#define CLK_TOP_TVDPLL_D4		46
+#define CLK_TOP_TVDPLL_D8		47
+#define CLK_TOP_TVDPLL_D16		48
+#define CLK_TOP_USB20_CLK480M		49
+#define CLK_TOP_RG_APLL1_D2		50
+#define CLK_TOP_RG_APLL1_D4		51
+#define CLK_TOP_RG_APLL1_D8		52
+#define CLK_TOP_RG_APLL1_D16		53
+#define CLK_TOP_RG_APLL1_D3		54
+#define CLK_TOP_RG_APLL2_D2		55
+#define CLK_TOP_RG_APLL2_D4		56
+#define CLK_TOP_RG_APLL2_D8		57
+#define CLK_TOP_RG_APLL2_D16		58
+#define CLK_TOP_RG_APLL2_D3		59
+#define CLK_TOP_NFI1X_INFRA_BCLK	60
+#define CLK_TOP_AHB_INFRA_D2		61
+#define CLK_TOP_UART0_SEL		62
+#define CLK_TOP_EMI1X_SEL		63
+#define CLK_TOP_EMI_DDRPHY_SEL		64
+#define CLK_TOP_MSDC1_SEL		65
+#define CLK_TOP_PWM_MM_SEL		66
+#define CLK_TOP_UART1_SEL		67
+#define CLK_TOP_SPM_52M_SEL		68
+#define CLK_TOP_PMICSPI_SEL		69
+#define CLK_TOP_NFI2X_SEL		70
+#define CLK_TOP_DDRPHYCFG_SEL		71
+#define CLK_TOP_SMI_SEL			72
+#define CLK_TOP_USB_SEL			73
+#define CLK_TOP_SPINOR_SEL		74
+#define CLK_TOP_ETH_SEL			75
+#define CLK_TOP_AUD1_SEL		76
+#define CLK_TOP_AUD2_SEL		77
+#define CLK_TOP_I2C_SEL			78
+#define CLK_TOP_AUD_I2S0_M_SEL		79
+#define CLK_TOP_AUD_I2S3_M_SEL		80
+#define CLK_TOP_AUD_I2S4_M_SEL		81
+#define CLK_TOP_AUD_I2S6_M_SEL		82
+#define CLK_TOP_PWM_SEL			83
+#define CLK_TOP_AUD_SPDIFIN_SEL		84
+#define CLK_TOP_UART2_SEL		85
+#define CLK_TOP_DBG_ATCLK_SEL		86
+#define CLK_TOP_PNG_SYS_SEL		87
+#define CLK_TOP_SEJ_13M_SEL		88
+#define CLK_TOP_IMGRZ_SYS_SEL		89
+#define CLK_TOP_GRAPH_ECLK_SEL		90
+#define CLK_TOP_FDBI_SEL		91
+#define CLK_TOP_FAUDIO_SEL		92
+#define CLK_TOP_FA2SYS_SEL		93
+#define CLK_TOP_FA1SYS_SEL		94
+#define CLK_TOP_FASM_M_SEL		95
+#define CLK_TOP_FASM_H_SEL		96
+#define CLK_TOP_FASM_L_SEL		97
+#define CLK_TOP_FECC_CK_SEL		98
+#define CLK_TOP_PE2_MAC_SEL		99
+#define CLK_TOP_CMSYS_SEL		100
+#define CLK_TOP_GCPU_SEL		101
+#define CLK_TOP_SPIS_CK_SEL		102
+#define CLK_TOP_APLL1_REF_SEL		103
+#define CLK_TOP_APLL2_REF_SEL		104
+#define CLK_TOP_INT_32K_SEL		105
+#define CLK_TOP_APLL1_SRC_SEL		106
+#define CLK_TOP_APLL2_SRC_SEL		107
+#define CLK_TOP_FAUD_INTBUS_SEL		108
+#define CLK_TOP_AXIBUS_SEL		109
+#define CLK_TOP_HAPLL1_SEL		110
+#define CLK_TOP_HAPLL2_SEL		111
+#define CLK_TOP_SPINFI_SEL		112
+#define CLK_TOP_MSDC0_SEL		113
+#define CLK_TOP_MSDC0_CLK50_SEL		114
+#define CLK_TOP_MSDC2_SEL		115
+#define CLK_TOP_MSDC2_CLK50_SEL		116
+#define CLK_TOP_DISP_DPI_CK_SEL		117
+#define CLK_TOP_SPI1_SEL		118
+#define CLK_TOP_SPI2_SEL		119
+#define CLK_TOP_SPI3_SEL		120
+#define CLK_TOP_APLL12_CK_DIV0		121
+#define CLK_TOP_APLL12_CK_DIV3		122
+#define CLK_TOP_APLL12_CK_DIV4		123
+#define CLK_TOP_APLL12_CK_DIV6		124
+
+/* TOPCKGEN Gates */
+#define CLK_TOP_PWM_MM			0
+#define CLK_TOP_SMI			1
+#define CLK_TOP_SPI2			2
+#define CLK_TOP_SPI3			3
+#define CLK_TOP_SPINFI			4
+#define CLK_TOP_26M_DEBUG		5
+#define CLK_TOP_USB_48M_DEBUG		6
+#define CLK_TOP_52M_DEBUG		7
+#define CLK_TOP_32K_DEBUG		8
+#define CLK_TOP_THERM			9
+#define CLK_TOP_APDMA			10
+#define CLK_TOP_I2C0			11
+#define CLK_TOP_I2C1			12
+#define CLK_TOP_AUXADC1			13
+#define CLK_TOP_NFI			14
+#define CLK_TOP_NFIECC			15
+#define CLK_TOP_DEBUGSYS		16
+#define CLK_TOP_PWM			17
+#define CLK_TOP_UART0			18
+#define CLK_TOP_UART1			19
+#define CLK_TOP_USB			20
+#define CLK_TOP_FLASHIF_26M		21
+#define CLK_TOP_AUXADC2			22
+#define CLK_TOP_I2C2			23
+#define CLK_TOP_MSDC0			24
+#define CLK_TOP_MSDC1			25
+#define CLK_TOP_NFI2X			26
+#define CLK_TOP_MEMSLP_DLYER		27
+#define CLK_TOP_SPI			28
+#define CLK_TOP_APXGPT			29
+#define CLK_TOP_PMICWRAP_MD		30
+#define CLK_TOP_PMICWRAP_CONN		31
+#define CLK_TOP_PMIC_SYSCK		32
+#define CLK_TOP_AUX_ADC			33
+#define CLK_TOP_AUX_TP			34
+#define CLK_TOP_RBIST			35
+#define CLK_TOP_NFI_BUS			36
+#define CLK_TOP_GCE			37
+#define CLK_TOP_TRNG			38
+#define CLK_TOP_PWM_B			39
+#define CLK_TOP_PWM1_FB			40
+#define CLK_TOP_PWM2_FB			41
+#define CLK_TOP_PWM3_FB			42
+#define CLK_TOP_PWM4_FB			43
+#define CLK_TOP_PWM5_FB			44
+#define CLK_TOP_FLASHIF_FREERUN		45
+#define CLK_TOP_CQDMA			46
+#define CLK_TOP_66M_ETH			47
+#define CLK_TOP_133M_ETH		48
+#define CLK_TOP_FLASHIF_AXI		49
+#define CLK_TOP_USBIF			50
+#define CLK_TOP_UART2			51
+#define CLK_TOP_GCPU_B			52
+#define CLK_TOP_MSDC0_B			53
+#define CLK_TOP_MSDC1_B			54
+#define CLK_TOP_MSDC2_B			55
+#define CLK_TOP_USB_B			56
+#define CLK_TOP_SPINOR			57
+#define CLK_TOP_MSDC2			58
+#define CLK_TOP_ETH			59
+#define CLK_TOP_AUD1			60
+#define CLK_TOP_AUD2			61
+#define CLK_TOP_I2C			62
+#define CLK_TOP_PWM_INFRA		63
+#define CLK_TOP_AUD_SPDIF_IN		64
+#define CLK_TOP_RG_UART2		65
+#define CLK_TOP_DBG_AT			66
+#define CLK_TOP_APLL12_DIV0		67
+#define CLK_TOP_APLL12_DIV3		68
+#define CLK_TOP_APLL12_DIV4		69
+#define CLK_TOP_APLL12_DIV6		70
+#define CLK_TOP_IMGRZ_SYS		71
+#define CLK_TOP_PNG_SYS			72
+#define CLK_TOP_GRAPH_E			73
+#define CLK_TOP_FDBI			74
+#define CLK_TOP_FAUDIO			75
+#define CLK_TOP_FAUD_INTBUS		76
+#define CLK_TOP_HAPLL1			77
+#define CLK_TOP_HAPLL2			78
+#define CLK_TOP_FA2SYS			79
+#define CLK_TOP_FA1SYS			80
+#define CLK_TOP_FASM_L			81
+#define CLK_TOP_FASM_M			82
+#define CLK_TOP_FASM_H			83
+#define CLK_TOP_FECC			84
+#define CLK_TOP_PE2_MAC			85
+#define CLK_TOP_CMSYS			86
+#define CLK_TOP_GCPU			87
+#define CLK_TOP_SPIS			88
+#define CLK_TOP_I2C3			89
+#define CLK_TOP_SPI_SLV_B		90
+#define CLK_TOP_SPI_SLV_BUS		91
+#define CLK_TOP_PCIE_MAC_BUS		92
+#define CLK_TOP_CMSYS_BUS		93
+#define CLK_TOP_ECC_B			94
+#define CLK_TOP_PCIE_PHY_BUS		95
+#define CLK_TOP_PCIE_AUX		96
+#define CLK_TOP_DISP_DPI		97
+#define CLK_TOP_NR_CLK			98
+
+#endif /* _DT_BINDINGS_CLK_MT8518_H */
-- 
2.18.0

[U-Boot] [PATCH 3/5] mmc: mtk-sd: add HS200 support

[mingming lee]

add HS200 mode and tune support

Signed-off-by: mingming lee <mingming.lee@mediatek.com>
---
 drivers/mmc/mtk-sd.c | 30 ++++++++++++++++++++++++------
 1 file changed, 24 insertions(+), 6 deletions(-)

diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c
index f555357af2..bede4153b3 100644
--- a/drivers/mmc/mtk-sd.c
+++ b/drivers/mmc/mtk-sd.c
@@ -362,6 +362,8 @@ static u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
 	case MMC_CMD_WRITE_SINGLE_BLOCK:
 	case MMC_CMD_READ_SINGLE_BLOCK:
 	case SD_CMD_APP_SEND_SCR:
+	case MMC_CMD_SEND_TUNING_BLOCK:
+	case MMC_CMD_SEND_TUNING_BLOCK_HS200:
 		dtype = 1;
 		break;
 	case SD_CMD_SWITCH_FUNC: /* same as MMC_CMD_SWITCH */
@@ -467,6 +469,14 @@ static int msdc_start_command(struct msdc_host *host, struct mmc_cmd *cmd,
 	if (!msdc_cmd_is_ready(host))
 		return -EIO;
 
+	if ((readl(&host->base->msdc_fifocs) &
+	    MSDC_FIFOCS_TXCNT_M) >> MSDC_FIFOCS_TXCNT_S ||
+	    (readl(&host->base->msdc_fifocs) &
+	    MSDC_FIFOCS_RXCNT_M) >> MSDC_FIFOCS_RXCNT_S) {
+		pr_err("TX/RX FIFO non-empty before start of IO. Reset\n");
+		msdc_reset_hw(host);
+	}
+
 	msdc_fifo_clr(host);
 
 	host->last_resp_type = cmd->resp_type;
@@ -650,14 +660,22 @@ static int msdc_ops_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 			     struct mmc_data *data)
 {
 	struct msdc_host *host = dev_get_priv(dev);
-	int ret;
+	int cmd_ret, data_ret;
 
-	ret = msdc_start_command(host, cmd, data);
-	if (ret)
-		return ret;
+	cmd_ret = msdc_start_command(host, cmd, data);
+	if (cmd_ret &&
+	    !(cmd_ret == -EIO &&
+	    (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
+	    cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)))
+		return cmd_ret;
 
-	if (data)
-		return msdc_start_data(host, data);
+	if (data) {
+		data_ret = msdc_start_data(host, data);
+		if (cmd_ret)
+			return cmd_ret;
+		else
+			return data_ret;
+	}
 
 	return 0;
 }
-- 
2.18.0

[U-Boot] [PATCH 4/5] pinctrl: add driver for MT8518

[mingming lee]

Add Pinctrl driver for MediaTek MT8518 SoC.

Signed-off-by: mingming lee <mingming.lee@mediatek.com>
---
 arch/arm/dts/mt8518.dtsi                  |   9 +
 drivers/pinctrl/mediatek/Kconfig          |   4 +
 drivers/pinctrl/mediatek/Makefile         |   1 +
 drivers/pinctrl/mediatek/pinctrl-mt8518.c | 411 ++++++++++++++++++++++
 4 files changed, 425 insertions(+)
 create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8518.c

diff --git a/arch/arm/dts/mt8518.dtsi b/arch/arm/dts/mt8518.dtsi
index 39d001884f..d924944c2a 100644
--- a/arch/arm/dts/mt8518.dtsi
+++ b/arch/arm/dts/mt8518.dtsi
@@ -151,6 +151,15 @@
 		status = "disabled";
 	};
 
+	pinctrl: pinctrl at 10005000 {
+		compatible = "mediatek,mt8518-pinctrl";
+		reg = <0x10005000 0x1000>;
+		gpio: gpio-controller {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+	};
+
 	mmc0: mmc at 11120000 {
 		compatible = "mediatek,mt8516-mmc";
 		reg = <0x11120000 0x1000>;
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index 9930ca1faf..22ee62362b 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -16,4 +16,8 @@ config PINCTRL_MT8516
 	bool "MT8516 SoC pinctrl driver"
 	select PINCTRL_MTK
 
+config PINCTRL_MT8518
+        bool "MT8518 SoC pinctrl driver"
+	select PINCTRL_MTK
+
 endif
diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile
index c4f29088d2..0ab7b1595b 100644
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o
 obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
 obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
 obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o
+obj-$(CONFIG_PINCTRL_MT8518) += pinctrl-mt8518.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8518.c b/drivers/pinctrl/mediatek/pinctrl-mt8518.c
new file mode 100644
index 0000000000..8d2cd948f6
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8518.c
@@ -0,0 +1,411 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Mingming Lee <mingming.lee@mediatek.com>
+ */
+
+#include <dm.h>
+
+#include "pinctrl-mtk-common.h"
+
+#define PIN_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits)	\
+	PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit,	\
+		       _x_bits, 16, false)
+
+static const struct mtk_pin_field_calc mt8518_pin_mode_range[] = {
+	PIN_FIELD_CALC(0, 119, 0x300, 0x10, 0, 3, 15, false),
+};
+
+static const struct mtk_pin_field_calc mt8518_pin_dir_range[] = {
+	PIN_FIELD(0, 119, 0x0, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8518_pin_di_range[] = {
+	PIN_FIELD(0, 119, 0x200, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8518_pin_do_range[] = {
+	PIN_FIELD(0, 119, 0x100, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8518_pin_ies_range[] = {
+	PIN_FIELD(0, 2, 0x900, 0x10, 0, 1),
+	PIN_FIELD(3, 3, 0x920, 0x10, 9, 1),
+	PIN_FIELD(4, 4, 0x920, 0x10, 8, 1),
+	PIN_FIELD(5, 5, 0x920, 0x10, 7, 1),
+	PIN_FIELD(6, 6, 0x920, 0x10, 6, 1),
+	PIN_FIELD(7, 7, 0x920, 0x10, 10, 1),
+	PIN_FIELD(8, 8, 0x920, 0x10, 1, 1),
+	PIN_FIELD(9, 9, 0x920, 0x10, 0, 1),
+	PIN_FIELD(10, 10, 0x920, 0x10, 5, 1),
+	PIN_FIELD(11, 11, 0x920, 0x10, 4, 1),
+	PIN_FIELD(12, 12, 0x920, 0x10, 3, 1),
+	PIN_FIELD(13, 13, 0x920, 0x10, 2, 1),
+	PIN_FIELD(14, 14, 0x900, 0x10, 1, 1),
+	PIN_FIELD(15, 15, 0x900, 0x10, 2, 1),
+	PIN_FIELD(16, 16, 0x900, 0x10, 3, 1),
+	PIN_FIELD(17, 20, 0x900, 0x10, 4, 1),
+	PIN_FIELD(21, 22, 0x900, 0x10, 5, 1),
+	PIN_FIELD(23, 27, 0x910, 0x10, 15, 1),
+	PIN_FIELD(28, 28, 0x900, 0x10, 6, 1),
+	PIN_FIELD(29, 29, 0x930, 0x10, 2, 1),
+	PIN_FIELD(30, 30, 0x930, 0x10, 1, 1),
+	PIN_FIELD(31, 31, 0x930, 0x10, 6, 1),
+	PIN_FIELD(32, 32, 0x930, 0x10, 5, 1),
+	PIN_FIELD(33, 33, 0x930, 0x10, 4, 1),
+	PIN_FIELD(34, 35, 0x930, 0x10, 3, 1),
+	PIN_FIELD(36, 39, 0x900, 0x10, 7, 1),
+	PIN_FIELD(40, 41, 0x900, 0x10, 8, 1),
+	PIN_FIELD(42, 44, 0x900, 0x10, 9, 1),
+	PIN_FIELD(45, 47, 0x900, 0x10, 10, 1),
+	PIN_FIELD(48, 51, 0x900, 0x10, 11, 1),
+	PIN_FIELD(52, 55, 0x900, 0x10, 12, 1),
+	PIN_FIELD(56, 56, 0x900, 0x10, 13, 1),
+	PIN_FIELD(57, 57, 0x900, 0x10, 14, 1),
+	PIN_FIELD(58, 58, 0x900, 0x10, 15, 1),
+	PIN_FIELD(59, 60, 0x910, 0x10, 0, 1),
+
+	PIN_FIELD(61, 61, 0x910, 0x10, 1, 1),
+	PIN_FIELD(62, 62, 0x910, 0x10, 2, 1),
+	PIN_FIELD(63, 69, 0x910, 0x10, 3, 1),
+	PIN_FIELD(70, 70, 0x910, 0x10, 4, 1),
+	PIN_FIELD(71, 76, 0x910, 0x10, 5, 1),
+	PIN_FIELD(77, 80, 0x910, 0x10, 6, 1),
+	PIN_FIELD(81, 87, 0x910, 0x10, 7, 1),
+	PIN_FIELD(88, 97, 0x910, 0x10, 8, 1),
+	PIN_FIELD(98, 103, 0x910, 0x10, 9, 1),
+	PIN_FIELD(104, 107, 0x910, 0x10, 10, 1),
+	PIN_FIELD(108, 109, 0x910, 0x10, 11, 1),
+	PIN_FIELD(110, 111, 0x910, 0x10, 12, 1),
+	PIN_FIELD(112, 113, 0x910, 0x10, 13, 1),
+	PIN_FIELD(114, 114, 0x920, 0x10, 12, 1),
+	PIN_FIELD(115, 115, 0x920, 0x10, 11, 1),
+	PIN_FIELD(116, 116, 0x930, 0x10, 0, 1),
+	PIN_FIELD(117, 117, 0x920, 0x10, 15, 1),
+	PIN_FIELD(118, 118, 0x920, 0x10, 14, 1),
+	PIN_FIELD(119, 119, 0x920, 0x10, 13, 1),
+};
+
+static const struct mtk_pin_field_calc mt8518_pin_smt_range[] = {
+	PIN_FIELD(0, 2, 0xA00, 0x10, 0, 1),
+	PIN_FIELD(3, 3, 0xA20, 0x10, 9, 1),
+	PIN_FIELD(4, 4, 0xA20, 0x10, 8, 1),
+	PIN_FIELD(5, 5, 0xA20, 0x10, 7, 1),
+	PIN_FIELD(6, 6, 0xA20, 0x10, 6, 1),
+	PIN_FIELD(7, 7, 0xA20, 0x10, 10, 1),
+	PIN_FIELD(8, 8, 0xA20, 0x10, 1, 1),
+	PIN_FIELD(9, 9, 0xA20, 0x10, 0, 1),
+	PIN_FIELD(10, 10, 0xA20, 0x10, 5, 1),
+	PIN_FIELD(11, 11, 0xA20, 0x10, 4, 1),
+	PIN_FIELD(12, 12, 0xA20, 0x10, 3, 1),
+	PIN_FIELD(13, 13, 0xA20, 0x10, 2, 1),
+	PIN_FIELD(14, 14, 0xA00, 0x10, 1, 1),
+	PIN_FIELD(15, 15, 0xA00, 0x10, 2, 1),
+	PIN_FIELD(16, 16, 0xA00, 0x10, 3, 1),
+	PIN_FIELD(17, 20, 0xA00, 0x10, 4, 1),
+	PIN_FIELD(21, 22, 0xA00, 0x10, 5, 1),
+	PIN_FIELD(23, 27, 0xA10, 0x10, 15, 1),
+	PIN_FIELD(28, 28, 0xA00, 0x10, 6, 1),
+	PIN_FIELD(29, 29, 0xA30, 0x10, 2, 1),
+	PIN_FIELD(30, 30, 0xA30, 0x10, 1, 1),
+	PIN_FIELD(31, 31, 0xA30, 0x10, 6, 1),
+	PIN_FIELD(32, 32, 0xA30, 0x10, 5, 1),
+	PIN_FIELD(33, 33, 0xA30, 0x10, 4, 1),
+	PIN_FIELD(34, 35, 0xA30, 0x10, 3, 1),
+	PIN_FIELD(36, 39, 0xA00, 0x10, 7, 1),
+	PIN_FIELD(40, 41, 0xA00, 0x10, 8, 1),
+	PIN_FIELD(42, 44, 0xA00, 0x10, 9, 1),
+	PIN_FIELD(45, 47, 0xA00, 0x10, 10, 1),
+	PIN_FIELD(48, 51, 0xA00, 0x10, 11, 1),
+	PIN_FIELD(52, 55, 0xA00, 0x10, 12, 1),
+	PIN_FIELD(56, 56, 0xA00, 0x10, 13, 1),
+	PIN_FIELD(57, 57, 0xA00, 0x10, 14, 1),
+	PIN_FIELD(58, 58, 0xA00, 0x10, 15, 1),
+	PIN_FIELD(59, 60, 0xA10, 0x10, 0, 1),
+
+	PIN_FIELD(61, 61, 0xA10, 0x10, 1, 1),
+	PIN_FIELD(62, 62, 0xA10, 0x10, 2, 1),
+	PIN_FIELD(63, 69, 0xA10, 0x10, 3, 1),
+	PIN_FIELD(70, 70, 0xA10, 0x10, 4, 1),
+	PIN_FIELD(71, 76, 0xA10, 0x10, 5, 1),
+	PIN_FIELD(77, 80, 0xA10, 0x10, 6, 1),
+	PIN_FIELD(81, 87, 0xA10, 0x10, 7, 1),
+	PIN_FIELD(88, 97, 0xA10, 0x10, 8, 1),
+	PIN_FIELD(98, 103, 0xA10, 0x10, 9, 1),
+	PIN_FIELD(104, 107, 0xA10, 0x10, 10, 1),
+	PIN_FIELD(108, 109, 0xA10, 0x10, 11, 1),
+	PIN_FIELD(110, 111, 0xA10, 0x10, 12, 1),
+	PIN_FIELD(112, 113, 0xA10, 0x10, 13, 1),
+	PIN_FIELD(114, 114, 0xA20, 0x10, 12, 1),
+	PIN_FIELD(115, 115, 0xA20, 0x10, 11, 1),
+	PIN_FIELD(116, 116, 0xA30, 0x10, 0, 1),
+	PIN_FIELD(117, 117, 0xA20, 0x10, 15, 1),
+	PIN_FIELD(118, 118, 0xA20, 0x10, 14, 1),
+	PIN_FIELD(119, 119, 0xA20, 0x10, 13, 1),
+};
+
+static const struct mtk_pin_field_calc mt8518_pin_pullen_range[] = {
+	PIN_FIELD(14, 15, 0x500, 0x10, 14, 1),
+	PIN_FIELD(16, 28, 0x510, 0x10, 0, 1),
+	PIN_FIELD(36, 47, 0x520, 0x10, 4, 1),
+	PIN_FIELD(48, 63, 0x530, 0x10, 0, 1),
+	PIN_FIELD(64, 79, 0x540, 0x10, 0, 1),
+	PIN_FIELD(80, 95, 0x550, 0x10, 0, 1),
+	PIN_FIELD(96, 111, 0x560, 0x10, 0, 1),
+	PIN_FIELD(112, 113, 0x570, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8518_pin_pullsel_range[] = {
+	PIN_FIELD(14, 15, 0x600, 0x10, 14, 1),
+	PIN_FIELD(16, 28, 0x610, 0x10, 0, 1),
+	PIN_FIELD(36, 47, 0x620, 0x10, 4, 1),
+	PIN_FIELD(48, 63, 0x630, 0x10, 0, 1),
+	PIN_FIELD(64, 79, 0x640, 0x10, 0, 1),
+	PIN_FIELD(80, 95, 0x650, 0x10, 0, 1),
+	PIN_FIELD(96, 111, 0x660, 0x10, 0, 1),
+	PIN_FIELD(112, 113, 0x670, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8518_pin_drv_range[] = {
+	PIN_FIELD(0, 2, 0xd70, 0x10, 8, 4),
+	PIN_FIELD(3, 6, 0xd70, 0x10, 0, 4),
+	PIN_FIELD(7, 7, 0xd70, 0x10, 4, 4),
+	PIN_FIELD(8, 8, 0xd60, 0x10, 8, 4),
+	PIN_FIELD(9, 9, 0xd60, 0x10, 12, 4),
+	PIN_FIELD(10, 13, 0xd70, 0x10, 0, 4),
+	PIN_FIELD(14, 14, 0xd50, 0x10, 8, 4),
+	PIN_FIELD(15, 15, 0xd20, 0x10, 4, 4),
+	PIN_FIELD(16, 16, 0xd50, 0x10, 8, 4),
+	PIN_FIELD(17, 20, 0xd20, 0x10, 12, 4),
+	PIN_FIELD(23, 27, 0xd30, 0x10, 8, 4),
+	PIN_FIELD(28, 28, 0xd10, 0x10, 0, 4),
+	PIN_FIELD(29, 29, 0xd40, 0x10, 12, 4),
+	PIN_FIELD(30, 30, 0xd50, 0x10, 0, 4),
+	PIN_FIELD(31, 35, 0xd50, 0x10, 4, 4),
+	PIN_FIELD(36, 41, 0xd00, 0x10, 0, 4),
+	PIN_FIELD(42, 47, 0xd00, 0x10, 4, 4),
+	PIN_FIELD(48, 51, 0xd00, 0x10, 8, 4),
+	PIN_FIELD(52, 55, 0xd10, 0x10, 12, 4),
+	PIN_FIELD(56, 56, 0xdb0, 0x10, 4, 4),
+	PIN_FIELD(57, 58, 0xd00, 0x10, 8, 4),
+	PIN_FIELD(59, 62, 0xd00, 0x10, 12, 4),
+	PIN_FIELD(63, 68, 0xd90, 0x10, 12, 4),
+	PIN_FIELD(69, 69, 0xda0, 0x10, 0, 4),
+	PIN_FIELD(70, 70, 0xda0, 0x10, 12, 4),
+	PIN_FIELD(71, 73, 0xd80, 0x10, 12, 4),
+	PIN_FIELD(74, 76, 0xd90, 0x10, 0, 4),
+	PIN_FIELD(77, 80, 0xd20, 0x10, 0, 4),
+	PIN_FIELD(81, 87, 0xd80, 0x10, 8, 4),
+	PIN_FIELD(88, 97, 0xd30, 0x10, 0, 4),
+	PIN_FIELD(98, 103, 0xd10, 0x10, 4, 4),
+	PIN_FIELD(104, 105, 0xd40, 0x10, 8, 4),
+	PIN_FIELD(106, 107, 0xd10, 0x10, 8, 4),
+	PIN_FIELD(114, 114, 0xd50, 0x10, 12, 4),
+	PIN_FIELD(115, 115, 0xd60, 0x10, 0, 4),
+	PIN_FIELD(116, 119, 0xd60, 0x10, 4, 4),
+};
+
+static const struct mtk_pin_reg_calc mt8518_reg_cals[] = {
+	[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8518_pin_mode_range),
+	[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8518_pin_dir_range),
+	[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8518_pin_di_range),
+	[PINCTRL_PIN_REG_DO] = MTK_RANGE(mt8518_pin_do_range),
+	[PINCTRL_PIN_REG_IES] = MTK_RANGE(mt8518_pin_ies_range),
+	[PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt8518_pin_smt_range),
+	[PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt8518_pin_pullsel_range),
+	[PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt8518_pin_pullen_range),
+	[PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8518_pin_drv_range),
+};
+
+static const struct mtk_pin_desc mt8518_pins[] = {
+	MTK_PIN(0, "NFI_NCEB0", DRV_GRP4),
+	MTK_PIN(1, "NFI_NREB", DRV_GRP4),
+	MTK_PIN(2, "NFI_NRNB", DRV_GRP4),
+	MTK_PIN(3, "MSDC0_DAT7", DRV_GRP4),
+	MTK_PIN(4, "MSDC0_DAT6", DRV_GRP4),
+	MTK_PIN(5, "MSDC0_DAT5", DRV_GRP4),
+	MTK_PIN(6, "MSDC0_DAT4", DRV_GRP4),
+	MTK_PIN(7, "MSDC0_RSTB", DRV_GRP4),
+	MTK_PIN(8, "MSDC0_CMD", DRV_GRP4),
+	MTK_PIN(9, "MSDC0_CLK", DRV_GRP4),
+	MTK_PIN(10, "MSDC0_DAT3", DRV_GRP4),
+	MTK_PIN(11, "MSDC0_DAT2", DRV_GRP4),
+	MTK_PIN(12, "MSDC0_DAT1", DRV_GRP4),
+	MTK_PIN(13, "MSDC0_DAT0", DRV_GRP4),
+	MTK_PIN(14, "RTC32K_CK", DRV_GRP2),
+	MTK_PIN(15, "WATCHDOG", DRV_GRP2),
+	MTK_PIN(16, "SUSPEND", DRV_GRP2),
+	MTK_PIN(17, "JTMS", DRV_GRP2),
+	MTK_PIN(18, "JTCK", DRV_GRP2),
+	MTK_PIN(19, "JTDI", DRV_GRP2),
+	MTK_PIN(20, "JTDO", DRV_GRP2),
+	MTK_PIN(21, "SDA3", DRV_GRP2),
+	MTK_PIN(22, "SCL3", DRV_GRP2),
+	MTK_PIN(23, "PWRAP_SPI_CLK", DRV_GRP2),
+	MTK_PIN(24, "PWRAP_SPI_CSN", DRV_GRP2),
+	MTK_PIN(25, "PWRAP_SPI_MOSI", DRV_GRP2),
+	MTK_PIN(26, "PWRAP_SPI_MISO", DRV_GRP2),
+	MTK_PIN(27, "PWRAP_INT", DRV_GRP2),
+	MTK_PIN(28, "EINT22", DRV_GRP2),
+	MTK_PIN(29, "MSDC2_CMD", DRV_GRP4),
+	MTK_PIN(30, "MSDC2_CLK", DRV_GRP4),
+	MTK_PIN(31, "MSDC2_DAT0", DRV_GRP4),
+	MTK_PIN(32, "MSDC2_DAT1", DRV_GRP4),
+	MTK_PIN(33, "MSDC2_DAT2", DRV_GRP4),
+	MTK_PIN(34, "MSDC2_DAT3", DRV_GRP4),
+	MTK_PIN(35, "MSDC2_DS", DRV_GRP4),
+	MTK_PIN(36, "EINT0", DRV_GRP0),
+	MTK_PIN(37, "EINT1", DRV_GRP0),
+	MTK_PIN(38, "EINT2", DRV_GRP0),
+	MTK_PIN(39, "EINT3", DRV_GRP0),
+	MTK_PIN(40, "EINT4", DRV_GRP0),
+	MTK_PIN(41, "EINT5", DRV_GRP0),
+	MTK_PIN(42, "EINT6", DRV_GRP0),
+	MTK_PIN(43, "EINT7", DRV_GRP0),
+	MTK_PIN(44, "EINT8", DRV_GRP0),
+	MTK_PIN(45, "EINT9", DRV_GRP0),
+	MTK_PIN(46, "EINT10", DRV_GRP0),
+	MTK_PIN(47, "EINT11", DRV_GRP0),
+	MTK_PIN(48, "EINT12", DRV_GRP0),
+	MTK_PIN(49, "EINT13", DRV_GRP0),
+	MTK_PIN(50, "EINT14", DRV_GRP0),
+	MTK_PIN(51, "EINT15", DRV_GRP0),
+	MTK_PIN(52, "URXD1", DRV_GRP0),
+	MTK_PIN(53, "UTXD1", DRV_GRP0),
+	MTK_PIN(54, "URTS1", DRV_GRP0),
+	MTK_PIN(55, "UCTS1", DRV_GRP0),
+	MTK_PIN(56, "IR", DRV_GRP0),
+	MTK_PIN(57, "EINT16", DRV_GRP0),
+	MTK_PIN(58, "EINT17", DRV_GRP0),
+	MTK_PIN(59, "EINT18", DRV_GRP0),
+	MTK_PIN(60, "EINT19", DRV_GRP0),
+	MTK_PIN(61, "EINT20", DRV_GRP0),
+	MTK_PIN(62, "EINT21", DRV_GRP0),
+	MTK_PIN(63, "I2SO_MCLK", DRV_GRP0),
+	MTK_PIN(64, "I2SO_BCK", DRV_GRP0),
+	MTK_PIN(65, "I2SO_LRCK", DRV_GRP0),
+	MTK_PIN(66, "I2SO_D0", DRV_GRP0),
+	MTK_PIN(67, "I2SO_D1", DRV_GRP0),
+	MTK_PIN(68, "I2SO_D2", DRV_GRP0),
+	MTK_PIN(69, "I2SO_D3", DRV_GRP0),
+	MTK_PIN(70, "SPDIF_IN0", DRV_GRP0),
+	MTK_PIN(71, "DMIC_CLK0", DRV_GRP0),
+	MTK_PIN(72, "DMIC_CLK1", DRV_GRP0),
+	MTK_PIN(73, "DMIC_DAT0", DRV_GRP0),
+	MTK_PIN(74, "DMIC_DAT1", DRV_GRP0),
+	MTK_PIN(75, "DMIC_DAT2", DRV_GRP0),
+	MTK_PIN(76, "DMIC_DAT3", DRV_GRP0),
+	MTK_PIN(77, "TDM_MCLK", DRV_GRP0),
+	MTK_PIN(78, "TDM_BCK", DRV_GRP0),
+	MTK_PIN(79, "TDM_LRCK", DRV_GRP0),
+	MTK_PIN(80, "TDM_DI", DRV_GRP0),
+	MTK_PIN(81, "I2SIN_D0", DRV_GRP0),
+	MTK_PIN(82, "I2SIN_D1", DRV_GRP0),
+	MTK_PIN(83, "I2SIN_D2", DRV_GRP0),
+	MTK_PIN(84, "I2SIN_D3", DRV_GRP0),
+	MTK_PIN(85, "I2SIN_MCLK", DRV_GRP0),
+	MTK_PIN(86, "I2SIN_BCK", DRV_GRP0),
+	MTK_PIN(87, "I2SIN_LRCK", DRV_GRP0),
+	MTK_PIN(88, "SPI1_CS", DRV_GRP0),
+	MTK_PIN(89, "SPI1_CK", DRV_GRP0),
+	MTK_PIN(90, "SPI1_MI", DRV_GRP0),
+	MTK_PIN(91, "SPI1_MO", DRV_GRP0),
+	MTK_PIN(92, "SPI2_CS", DRV_GRP0),
+	MTK_PIN(93, "SPI2_CK", DRV_GRP0),
+	MTK_PIN(94, "SPI2_MI0", DRV_GRP0),
+	MTK_PIN(95, "SPI2_MI1", DRV_GRP0),
+	MTK_PIN(96, "SPI2_MI2", DRV_GRP0),
+	MTK_PIN(97, "SPI2_MI3", DRV_GRP0),
+	MTK_PIN(98, "SW_RESET_DSP", DRV_GRP0),
+	MTK_PIN(99, "GPIO1", DRV_GRP0),
+	MTK_PIN(100, "GPIO2", DRV_GRP0),
+	MTK_PIN(101, "GPIO3", DRV_GRP0),
+	MTK_PIN(102, "GPIO4", DRV_GRP0),
+	MTK_PIN(103, "RTC32K_DSP", DRV_GRP0),
+	MTK_PIN(104, "URXD0", DRV_GRP2),
+	MTK_PIN(105, "UTXD0", DRV_GRP2),
+	MTK_PIN(106, "URXD2", DRV_GRP2),
+	MTK_PIN(107, "UTXD2", DRV_GRP2),
+	MTK_PIN(108, "SDA1", DRV_GRP4),
+	MTK_PIN(109, "SCL1", DRV_GRP4),
+	MTK_PIN(110, "SDA0", DRV_GRP4),
+	MTK_PIN(111, "SCL0", DRV_GRP4),
+	MTK_PIN(112, "SDA2", DRV_GRP4),
+	MTK_PIN(113, "SCL2", DRV_GRP4),
+	MTK_PIN(114, "MSDC1_CMD", DRV_GRP4),
+	MTK_PIN(115, "MSDC1_CLK", DRV_GRP4),
+	MTK_PIN(116, "MSDC1_DAT0", DRV_GRP4),
+	MTK_PIN(117, "MSDC1_DAT1", DRV_GRP4),
+	MTK_PIN(118, "MSDC1_DAT2", DRV_GRP4),
+	MTK_PIN(119, "MSDC1_DAT3", DRV_GRP4),
+};
+
+/* List all groups consisting of these pins dedicated to the enablement of
+ * certain hardware block and the corresponding mode for all of the pins.
+ * The hardware probably has multiple combinations of these pinouts.
+ */
+
+/* UART */
+static int mt8518_uart0_0_rxd_txd_pins[]		= { 104, 105, };
+static int mt8518_uart0_0_rxd_txd_funcs[]		= {  1,  1, };
+static int mt8518_uart1_0_rxd_txd_pins[]		= { 52, 53, };
+static int mt8518_uart1_0_rxd_txd_funcs[]		= {  1,  1, };
+static int mt8518_uart2_0_rxd_txd_pins[]		= { 106, 107, };
+static int mt8518_uart2_0_rxd_txd_funcs[]		= {  1,  1, };
+
+/* Joint those groups owning the same capability in user point of view which
+ * allows that people tend to use through the device tree.
+ */
+static const char *const mt8518_uart_groups[] = { "uart0_0_rxd_txd",
+						"uart1_0_rxd_txd",
+						"uart2_0_rxd_txd", };
+
+/* MMC0 */
+static int mt8518_msdc0_pins[] = { 3, 4, 5, 6, 7, 8, 9, 10, 11,
+				   12, 13, };
+static int mt8518_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
+
+static const struct mtk_group_desc mt8518_groups[] = {
+	PINCTRL_PIN_GROUP("uart0_0_rxd_txd", mt8518_uart0_0_rxd_txd),
+	PINCTRL_PIN_GROUP("uart1_0_rxd_txd", mt8518_uart1_0_rxd_txd),
+	PINCTRL_PIN_GROUP("uart2_0_rxd_txd", mt8518_uart2_0_rxd_txd),
+
+	PINCTRL_PIN_GROUP("msdc0", mt8518_msdc0),
+};
+
+static const char *const mt8518_msdc_groups[] = { "msdc0" };
+
+static const struct mtk_function_desc mt8518_functions[] = {
+	{"uart", mt8518_uart_groups, ARRAY_SIZE(mt8518_uart_groups)},
+	{"msdc", mt8518_msdc_groups, ARRAY_SIZE(mt8518_msdc_groups)},
+};
+
+static struct mtk_pinctrl_soc mt8518_data = {
+	.name = "mt8518_pinctrl",
+	.reg_cal = mt8518_reg_cals,
+	.pins = mt8518_pins,
+	.npins = ARRAY_SIZE(mt8518_pins),
+	.grps = mt8518_groups,
+	.ngrps = ARRAY_SIZE(mt8518_groups),
+	.funcs = mt8518_functions,
+	.nfuncs = ARRAY_SIZE(mt8518_functions),
+};
+
+static int mtk_pinctrl_mt8518_probe(struct udevice *dev)
+{
+	return mtk_pinctrl_common_probe(dev, &mt8518_data);
+}
+
+static const struct udevice_id mt8518_pctrl_match[] = {
+	{ .compatible = "mediatek,mt8518-pinctrl" },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(mt8518_pinctrl) = {
+	.name = "mt8518_pinctrl",
+	.id = UCLASS_PINCTRL,
+	.of_match = mt8518_pctrl_match,
+	.ops = &mtk_pinctrl_ops,
+	.probe = mtk_pinctrl_mt8518_probe,
+	.priv_auto_alloc_size = sizeof(struct mtk_pinctrl_priv),
+};
-- 
2.18.0

[U-Boot] [PATCH 5/5] ARM: MediaTek: add basic support for MT8518 boards

[mingming lee]

This adds a general board file based on MT8518 SoCs from MediaTek.

Apart from the generic parts (cpu) we add some low level init codes
and initialize the early clocks.

This commit is adding the basic boot support for the MT8518 eMMC board.

Signed-off-by: mingming lee <mingming.lee@mediatek.com>
---
 arch/arm/dts/Makefile              |   3 +-
 arch/arm/dts/mt8518-ap1-emmc.dts   | 104 +++++++++++++++++++++++++++++
 arch/arm/mach-mediatek/Kconfig     |   1 +
 board/mediatek/mt8518/Kconfig      |  14 ++++
 board/mediatek/mt8518/MAINTAINERS  |   6 ++
 board/mediatek/mt8518/Makefile     |   3 +
 board/mediatek/mt8518/mt8518_ap1.c |  27 ++++++++
 configs/mt8518_ap1_emmc_defconfig  |  54 +++++++++++++++
 include/configs/mt8518.h           |  73 ++++++++++++++++++++
 9 files changed, 284 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/mt8518-ap1-emmc.dts
 create mode 100644 board/mediatek/mt8518/Kconfig
 create mode 100644 board/mediatek/mt8518/MAINTAINERS
 create mode 100644 board/mediatek/mt8518/Makefile
 create mode 100644 board/mediatek/mt8518/mt8518_ap1.c
 create mode 100644 configs/mt8518_ap1_emmc_defconfig
 create mode 100644 include/configs/mt8518.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index aac1b83d49..54ca31c995 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -788,7 +788,8 @@ dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \
 dtb-$(CONFIG_ARCH_MEDIATEK) += \
 	mt7623n-bananapi-bpi-r2.dtb \
 	mt7629-rfb.dtb \
-	mt8516-pumpkin.dtb
+	mt8516-pumpkin.dtb \
+	mt8518-ap1-emmc.dtb
 
 dtb-$(CONFIG_TARGET_GE_BX50V3) += imx6q-bx50v3.dtb
 dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb
diff --git a/arch/arm/dts/mt8518-ap1-emmc.dts b/arch/arm/dts/mt8518-ap1-emmc.dts
new file mode 100644
index 0000000000..a542d65f59
--- /dev/null
+++ b/arch/arm/dts/mt8518-ap1-emmc.dts
@@ -0,0 +1,104 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Mingming Lee <mingming.lee@mediatek.com>
+ *
+ */
+
+/dts-v1/;
+
+#include <config.h>
+#include "mt8518.dtsi"
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	model = "MT8518 AP1 EMMC";
+
+	chosen {
+		stdout-path = &uart0;
+		tick-timer = &timer0;
+	};
+
+	memory at 40000000 {
+		device_type = "memory";
+		reg = <0x40000000 0x10000000>;
+	};
+
+	reg_1p8v: regulator-1p8v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-1.8V";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	reg_3p3v: regulator-3p3v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+};
+
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins_default>;
+	bus-width = <8>;
+	max-frequency = <200000000>;
+	cap-mmc-highspeed;
+	mmc-hs200-1_8v;
+	cap-mmc-hw-reset;
+	vmmc-supply = <&reg_3p3v>;
+	vqmmc-supply = <&reg_1p8v>;
+	non-removable;
+	status = "okay";
+};
+
+&pinctrl {
+	mmc0_pins_default: mmc0default {
+		mux {
+			function = "msdc";
+			groups =  "msdc0";
+		};
+
+		conf-cmd-data {
+			pins = "MSDC0_CMD", "MSDC0_DAT0", "MSDC0_DAT1",
+			       "MSDC0_DAT2", "MSDC0_DAT3", "MSDC0_DAT4",
+			       "MSDC0_DAT5", "MSDC0_DAT6", "MSDC0_DAT7";
+			input-enable;
+			bias-pull-up;
+		};
+
+		conf-clk {
+			pins = "MSDC0_CLK";
+			bias-pull-down;
+		};
+
+		conf-rst {
+			pins = "MSDC0_RSTB";
+			bias-pull-up;
+		};
+	};
+
+		uart0_pins: uart0 {
+			mux {
+				function = "uart";
+				groups = "uart0_0_rxd_txd";
+			};
+		};
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins>;
+	status = "okay";
+};
+
+&watchdog {
+	status = "okay";
+};
diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
index 8e343c3182..a5808bd343 100644
--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -52,5 +52,6 @@ endchoice
 source "board/mediatek/mt7623/Kconfig"
 source "board/mediatek/mt7629/Kconfig"
 source "board/mediatek/pumpkin/Kconfig"
+source "board/mediatek/mt8518/Kconfig"
 
 endif
diff --git a/board/mediatek/mt8518/Kconfig b/board/mediatek/mt8518/Kconfig
new file mode 100644
index 0000000000..1971c4d8c3
--- /dev/null
+++ b/board/mediatek/mt8518/Kconfig
@@ -0,0 +1,14 @@
+if TARGET_MT8518
+
+config SYS_BOARD
+	default "mt8518"
+
+config SYS_CONFIG_NAME
+	default "mt8518"
+
+
+config MTK_BROM_HEADER_INFO
+	string
+	default "media=nor"
+
+endif
diff --git a/board/mediatek/mt8518/MAINTAINERS b/board/mediatek/mt8518/MAINTAINERS
new file mode 100644
index 0000000000..c9151947ad
--- /dev/null
+++ b/board/mediatek/mt8518/MAINTAINERS
@@ -0,0 +1,6 @@
+MT8518
+M:	Mingming lee <mingming.lee@mediatek.com>
+S:	Maintained
+F:	board/mediatek/mt8518
+F:	include/configs/mt8518.h
+F:	configs/mt8518_ap1_emmc_defconfig
diff --git a/board/mediatek/mt8518/Makefile b/board/mediatek/mt8518/Makefile
new file mode 100644
index 0000000000..0884b32c56
--- /dev/null
+++ b/board/mediatek/mt8518/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier:	GPL-2.0
+
+obj-y += mt8518_ap1.o
diff --git a/board/mediatek/mt8518/mt8518_ap1.c b/board/mediatek/mt8518/mt8518_ap1.c
new file mode 100644
index 0000000000..3d46350514
--- /dev/null
+++ b/board/mediatek/mt8518/mt8518_ap1.c
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ */
+
+#include <common.h>
+#include <dm.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	printf("gd->fdt_blob is %p\n", gd->fdt_blob);
+	return 0;
+}
+
+int board_late_init(void)
+{
+	/*to load environment variable from persistent store*/
+	gd->env_valid = 1;
+	env_relocate();
+
+	return 0;
+}
diff --git a/configs/mt8518_ap1_emmc_defconfig b/configs/mt8518_ap1_emmc_defconfig
new file mode 100644
index 0000000000..2cacd9cfaa
--- /dev/null
+++ b/configs/mt8518_ap1_emmc_defconfig
@@ -0,0 +1,54 @@
+CONFIG_ARM=y
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_ARCH_MEDIATEK=y
+CONFIG_SYS_TEXT_BASE=0x44E00000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_TARGET_MT8518=y
+CONFIG_SYS_PROMPT="MT8518> "
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEBUG_UART_BASE=0x11005000
+CONFIG_DEBUG_UART_CLOCK=26000000
+# CONFIG_PSCI_RESET is not set
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FDT_DEBUG=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_LZMA=y
+CONFIG_LZ4=y
+CONFIG_LZO=y
+CONFIG_GZIP=y
+CONFIG_BZIP2=y
+CONFIG_CMD_BOOTMENU=y
+CONFIG_MENU_SHOW=y
+CONFIG_DEFAULT_FDT_FILE="mt8518-ap1-emmc"
+CONFIG_DEFAULT_DEVICE_TREE="mt8518-ap1-emmc"
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MT8518=y
+CONFIG_RAM=y
+CONFIG_BAUDRATE=921600
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_DM=y
+CONFIG_DM_DEMO=y
+CONFIG_DM_RESET=y
+CONFIG_DM_DEBUG=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART_MTK=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_MTK_SERIAL=y
+#CONFIG_WDT=y
+#CONFIG_WDT_MTK=y
+CONFIG_CLK=y
+CONFIG_TIMER=y
+CONFIG_MTK_TIMER=y
+CONFIG_CMD_MMC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_MTK=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_LOG=y
+CONFIG_LOGLEVEL=7
diff --git a/include/configs/mt8518.h b/include/configs/mt8518.h
new file mode 100644
index 0000000000..afb8d041c0
--- /dev/null
+++ b/include/configs/mt8518.h
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Configuration for MediaTek MT8518 SoC
+ *
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Mingming Lee <mingming.lee@mediatek.com>
+ */
+
+#ifndef __MT8518_H
+#define __MT8518_H
+
+#include <linux/sizes.h>
+
+#define CONFIG_ENV_SIZE				SZ_4K
+
+/* Machine ID */
+#define CONFIG_MACH_TYPE			8518
+#define CONFIG_SYS_NONCACHED_MEMORY		BIT(20)
+
+#define CONFIG_CPU_ARMV8
+
+#define COUNTER_FREQUENCY			13000000
+
+/* DRAM definition */
+#define CONFIG_SYS_SDRAM_BASE			0x40000000
+#define CONFIG_SYS_SDRAM_SIZE			0x20000000
+
+#define CONFIG_SYS_LOAD_ADDR			0x41000000
+#define CONFIG_LOADADDR				CONFIG_SYS_LOAD_ADDR
+
+#define CONFIG_SYS_MALLOC_LEN			SZ_32M
+#define CONFIG_SYS_BOOTM_LEN			SZ_64M
+
+/* Uboot definition */
+#define CONFIG_SYS_UBOOT_START			CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_INIT_SP_ADDR			(CONFIG_SYS_TEXT_BASE + \
+						SZ_2M - \
+						GENERATED_GBL_DATA_SIZE)
+
+/* ENV Setting */
+#if defined(CONFIG_MMC_MTK)
+#define CONFIG_SYS_MMC_ENV_DEV			0
+#define CONFIG_ENV_OFFSET			0x1B00000
+#define CONFIG_ENV_OVERWRITE
+
+/* MMC offset in block unit,and block size is 0x200 */
+#define ENV_BOOT_READ_IMAGE \
+	"boot_rd_img=mmc dev 0" \
+	";mmc read ${loadaddr} 0x800 0x8000" \
+	";iminfo ${loadaddr}\0"
+#endif
+
+/* Console configuration */
+#define ENV_DEVICE_SETTINGS \
+	"stdin=serial\0" \
+	"stdout=serial\0" \
+	"stderr=serial\0"
+
+#define ENV_BOOT_CMD \
+	"mtk_boot=run boot_rd_img;bootm;\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"fdt_high=0x6c000000\0" \
+	ENV_DEVICE_SETTINGS \
+	ENV_BOOT_READ_IMAGE \
+	ENV_BOOT_CMD \
+	"bootcmd=run mtk_boot;\0" \
+
+#if defined(CONFIG_MMC_MTK)
+#define CONFIG_SYS_MMC_ENV_DEV			0
+#endif
+
+#endif
-- 
2.18.0

[U-Boot] [PATCH 5/5] ARM: MediaTek: add basic support for MT8518 boards

[Tom Rini]

On Wed, Sep 11, 2019 at 07:14:59PM +0800, mingming lee wrote:

> This adds a general board file based on MT8518 SoCs from MediaTek.
> 
> Apart from the generic parts (cpu) we add some low level init codes
> and initialize the early clocks.
> 
> This commit is adding the basic boot support for the MT8518 eMMC board.
> 
> Signed-off-by: mingming lee <mingming.lee@mediatek.com>

OK, there's a few problems here:

[snip]
> +int board_init(void)
> +{
> +	/* address of boot parameters */
> +	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
> +
> +	printf("gd->fdt_blob is %p\n", gd->fdt_blob);

Please remove this (and audit the series for other) bring-up debug
printfs that we shouldn't need anymore.

> +	return 0;
> +}
> +
> +int board_late_init(void)
> +{
> +	/*to load environment variable from persistent store*/
> +	gd->env_valid = 1;
> +	env_relocate();
> +
> +	return 0;
> +}

Er, do you really need this?

[snip]
> +/* Machine ID */
> +#define CONFIG_MACH_TYPE			8518
> +#define CONFIG_SYS_NONCACHED_MEMORY		BIT(20)

CONFIG_MACH_TYPE is not relevant to aarch64 platforms (it's for
pre-device tree boards) and 'BIT(20)' isn't a valid value for
CONFIG_SYS_NONCACHED_MEMORY (and leads to a warning a build).

Thanks!

-- 
Tom
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[U-Boot] [PATCH 5/5] ARM: MediaTek: add basic support for MT8518 boards

[Mingming Lee]

On Sat, 2019-10-12 at 01:28 +0800, Tom Rini wrote:
> On Wed, Sep 11, 2019 at 07:14:59PM +0800, mingming lee wrote:
> 
> > This adds a general board file based on MT8518 SoCs from MediaTek.
> > 
> > Apart from the generic parts (cpu) we add some low level init codes
> > and initialize the early clocks.
> > 
> > This commit is adding the basic boot support for the MT8518 eMMC board.
> > 
> > Signed-off-by: mingming lee <mingming.lee@mediatek.com>
> 
> OK, there's a few problems here:
> 
> [snip]
> > +int board_init(void)
> > +{
> > +	/* address of boot parameters */
> > +	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
> > +
> > +	printf("gd->fdt_blob is %p\n", gd->fdt_blob);
> 
> Please remove this (and audit the series for other) bring-up debug
> printfs that we shouldn't need anymore.
> 
> > +	return 0;
> > +}
> > +
> > +int board_late_init(void)
> > +{
> > +	/*to load environment variable from persistent store*/
> > +	gd->env_valid = 1;
> > +	env_relocate();
> > +
> > +	return 0;
> > +}
> 
> Er, do you really need this?
> 
> [snip]
> > +/* Machine ID */
> > +#define CONFIG_MACH_TYPE			8518
> > +#define CONFIG_SYS_NONCACHED_MEMORY		BIT(20)
> 
> CONFIG_MACH_TYPE is not relevant to aarch64 platforms (it's for
> pre-device tree boards) and 'BIT(20)' isn't a valid value for
> CONFIG_SYS_NONCACHED_MEMORY (and leads to a warning a build).
> 
> Thanks!
> 

Thank you for your advice.I would modify those issues in the next
Version.
For the debug info using API printf,I would modify it to the API
debug() 
For the API board_late_init and define CONFIG_MACH_TYPE,I would delete
it.
For BIT(20), I used to use SZ_1M,it also have warning.I think I would
modify it to 0x100000.